LCOV - code coverage report
Current view: top level - lib/CodeGen/SelectionDAG - FunctionLoweringInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 270 274 98.5 %
Date: 2017-09-14 15:23:50 Functions: 15 15 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This implements routines for translating functions from LLVM IR into
      11             : // Machine IR.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "llvm/CodeGen/FunctionLoweringInfo.h"
      16             : #include "llvm/CodeGen/Analysis.h"
      17             : #include "llvm/CodeGen/MachineFrameInfo.h"
      18             : #include "llvm/CodeGen/MachineFunction.h"
      19             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      20             : #include "llvm/CodeGen/MachineModuleInfo.h"
      21             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      22             : #include "llvm/CodeGen/WinEHFuncInfo.h"
      23             : #include "llvm/IR/DataLayout.h"
      24             : #include "llvm/IR/DebugInfo.h"
      25             : #include "llvm/IR/DerivedTypes.h"
      26             : #include "llvm/IR/Function.h"
      27             : #include "llvm/IR/Instructions.h"
      28             : #include "llvm/IR/IntrinsicInst.h"
      29             : #include "llvm/IR/LLVMContext.h"
      30             : #include "llvm/IR/Module.h"
      31             : #include "llvm/Support/Debug.h"
      32             : #include "llvm/Support/ErrorHandling.h"
      33             : #include "llvm/Support/MathExtras.h"
      34             : #include "llvm/Support/raw_ostream.h"
      35             : #include "llvm/Target/TargetFrameLowering.h"
      36             : #include "llvm/Target/TargetInstrInfo.h"
      37             : #include "llvm/Target/TargetLowering.h"
      38             : #include "llvm/Target/TargetOptions.h"
      39             : #include "llvm/Target/TargetRegisterInfo.h"
      40             : #include "llvm/Target/TargetSubtargetInfo.h"
      41             : #include <algorithm>
      42             : using namespace llvm;
      43             : 
      44             : #define DEBUG_TYPE "function-lowering-info"
      45             : 
      46             : /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
      47             : /// PHI nodes or outside of the basic block that defines it, or used by a
      48             : /// switch or atomic instruction, which may expand to multiple basic blocks.
      49     2007390 : static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
      50     4014780 :   if (I->use_empty()) return false;
      51     2377158 :   if (isa<PHINode>(I)) return true;
      52     1149497 :   const BasicBlock *BB = I->getParent();
      53     5874511 :   for (const User *U : I->users())
      54     2522058 :     if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
      55             :       return true;
      56             : 
      57             :   return false;
      58             : }
      59             : 
      60     2007390 : static ISD::NodeType getPreferredExtendForValue(const Value *V) {
      61             :   // For the users of the source value being used for compare instruction, if
      62             :   // the number of signed predicate is greater than unsigned predicate, we
      63             :   // prefer to use SIGN_EXTEND.
      64             :   //
      65             :   // With this optimization, we would be able to reduce some redundant sign or
      66             :   // zero extension instruction, and eventually more machine CSE opportunities
      67             :   // can be exposed.
      68     2007390 :   ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
      69     2007390 :   unsigned NumOfSigned = 0, NumOfUnsigned = 0;
      70     6941060 :   for (const User *U : V->users()) {
      71       49051 :     if (const auto *CI = dyn_cast<CmpInst>(U)) {
      72       49051 :       NumOfSigned += CI->isSigned();
      73       49051 :       NumOfUnsigned += CI->isUnsigned();
      74             :     }
      75             :   }
      76     2007390 :   if (NumOfSigned > NumOfUnsigned)
      77        5807 :     ExtendKind = ISD::SIGN_EXTEND;
      78             : 
      79     2007390 :   return ExtendKind;
      80             : }
      81             : 
      82      142331 : void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
      83             :                                SelectionDAG *DAG) {
      84      142331 :   Fn = &fn;
      85      142331 :   MF = &mf;
      86      142331 :   TLI = MF->getSubtarget().getTargetLowering();
      87      142331 :   RegInfo = &MF->getRegInfo();
      88      142331 :   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
      89      142331 :   unsigned StackAlign = TFI->getStackAlignment();
      90             : 
      91             :   // Check whether the function can return without sret-demotion.
      92      142418 :   SmallVector<ISD::OutputArg, 4> Outs;
      93      284662 :   GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
      94             :                 mf.getDataLayout());
      95      569324 :   CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
      96      426993 :                                        Fn->isVarArg(), Outs, Fn->getContext());
      97             : 
      98             :   // If this personality uses funclets, we need to do a bit more work.
      99      142416 :   DenseMap<const AllocaInst *, TinyPtrVector<int *>> CatchObjects;
     100      142329 :   EHPersonality Personality = classifyEHPersonality(
     101      426987 :       Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr);
     102          87 :   if (isFuncletEHPersonality(Personality)) {
     103             :     // Calculate state numbers if we haven't already.
     104          87 :     WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
     105          87 :     if (Personality == EHPersonality::MSVC_CXX)
     106          56 :       calculateWinCXXEHStateNumbers(&fn, EHInfo);
     107          31 :     else if (isAsynchronousEHPersonality(Personality))
     108          24 :       calculateSEHStateNumbers(&fn, EHInfo);
     109           7 :     else if (Personality == EHPersonality::CoreCLR)
     110           7 :       calculateClrEHStateNumbers(&fn, EHInfo);
     111             : 
     112             :     // Map all BB references in the WinEH data to MBBs.
     113         319 :     for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
     114         239 :       for (WinEHHandlerType &H : TBME.HandlerArray) {
     115          65 :         if (const AllocaInst *AI = H.CatchObj.Alloca)
     116          40 :           CatchObjects.insert({AI, {}}).first->second.push_back(
     117             :               &H.CatchObj.FrameIndex);
     118             :         else
     119          57 :           H.CatchObj.FrameIndex = INT_MAX;
     120             :       }
     121             :     }
     122             :   }
     123             : 
     124             :   // Initialize the mapping of values to registers.  This is only set up for
     125             :   // instruction values that are used outside of the block that defines
     126             :   // them.
     127      706817 :   for (const BasicBlock &BB : *Fn) {
     128     2846880 :     for (const Instruction &I : BB) {
     129     2007390 :       if (const AllocaInst *AI = dyn_cast<AllocaInst>(&I)) {
     130       28554 :         Type *Ty = AI->getAllocatedType();
     131             :         unsigned Align =
     132       57108 :           std::max((unsigned)MF->getDataLayout().getPrefTypeAlignment(Ty),
     133      114216 :                    AI->getAlignment());
     134             : 
     135             :         // Static allocas can be folded into the initial stack frame
     136             :         // adjustment. For targets that don't realign the stack, don't
     137             :         // do this if there is an extra alignment requirement.
     138       56692 :         if (AI->isStaticAlloca() &&
     139       28408 :             (TFI->isStackRealignable() || (Align <= StackAlign))) {
     140       84396 :           const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
     141       28132 :           uint64_t TySize = MF->getDataLayout().getTypeAllocSize(Ty);
     142             : 
     143       28132 :           TySize *= CUI->getZExtValue();   // Get total allocated size.
     144       28132 :           if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
     145       28132 :           int FrameIndex = INT_MAX;
     146       28132 :           auto Iter = CatchObjects.find(AI);
     147       56264 :           if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) {
     148           5 :             FrameIndex = MF->getFrameInfo().CreateFixedObject(
     149             :                 TySize, 0, /*Immutable=*/false, /*isAliased=*/true);
     150           5 :             MF->getFrameInfo().setObjectAlignment(FrameIndex, Align);
     151             :           } else {
     152       28127 :             FrameIndex =
     153       28127 :                 MF->getFrameInfo().CreateStackObject(TySize, Align, false, AI);
     154             :           }
     155             : 
     156       56264 :           StaticAllocaMap[AI] = FrameIndex;
     157             :           // Update the catch handler information.
     158       56264 :           if (Iter != CatchObjects.end()) {
     159          29 :             for (int *CatchObjPtr : Iter->second)
     160           8 :               *CatchObjPtr = FrameIndex;
     161             :           }
     162             :         } else {
     163             :           // FIXME: Overaligned static allocas should be grouped into
     164             :           // a single dynamic allocation instead of using a separate
     165             :           // stack allocation for each one.
     166         422 :           if (Align <= StackAlign)
     167         348 :             Align = 0;
     168             :           // Inform the Frame Information that we have variable-sized objects.
     169         422 :           MF->getFrameInfo().CreateVariableSizedObject(Align ? Align : 1, AI);
     170             :         }
     171             :       }
     172             : 
     173             :       // Look for inline asm that clobbers the SP register.
     174     3707978 :       if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
     175      333433 :         ImmutableCallSite CS(&I);
     176      666866 :         if (isa<InlineAsm>(CS.getCalledValue())) {
     177        8965 :           unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
     178        8965 :           const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
     179             :           std::vector<TargetLowering::AsmOperandInfo> Ops =
     180       17930 :               TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI, CS);
     181       91295 :           for (TargetLowering::AsmOperandInfo &Op : Ops) {
     182       55435 :             if (Op.Type == InlineAsm::isClobber) {
     183             :               // Clobbers don't have SDValue operands, hence SDValue().
     184       48883 :               TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
     185             :               std::pair<unsigned, const TargetRegisterClass *> PhysReg =
     186       48883 :                   TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
     187       97766 :                                                     Op.ConstraintVT);
     188       48883 :               if (PhysReg.first == SP)
     189          81 :                 MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
     190             :             }
     191             :           }
     192             :         }
     193             :       }
     194             : 
     195             :       // Look for calls to the @llvm.va_start intrinsic. We can omit some
     196             :       // prologue boilerplate for variadic functions that don't examine their
     197             :       // arguments.
     198      140959 :       if (const auto *II = dyn_cast<IntrinsicInst>(&I)) {
     199      140959 :         if (II->getIntrinsicID() == Intrinsic::vastart)
     200         202 :           MF->getFrameInfo().setHasVAStart(true);
     201             :       }
     202             : 
     203             :       // If we have a musttail call in a variadic function, we need to ensure we
     204             :       // forward implicit register parameters.
     205      306802 :       if (const auto *CI = dyn_cast<CallInst>(&I)) {
     206      306865 :         if (CI->isMustTailCall() && Fn->isVarArg())
     207          26 :           MF->getFrameInfo().setHasMustTailInVarArgFunc(true);
     208             :       }
     209             : 
     210             :       // Mark values used outside their block as exported, by allocating
     211             :       // a virtual register for them.
     212     2007390 :       if (isUsedOutsideOfDefiningBlock(&I))
     213      154573 :         if (!isa<AllocaInst>(I) || !StaticAllocaMap.count(cast<AllocaInst>(&I)))
     214      115761 :           InitializeRegForValue(&I);
     215             : 
     216             :       // Decide the preferred extend type for a value.
     217     4014780 :       PreferredExtendType[&I] = getPreferredExtendForValue(&I);
     218             :     }
     219             :   }
     220             : 
     221             :   // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
     222             :   // also creates the initial PHI MachineInstrs, though none of the input
     223             :   // operands are populated.
     224      706817 :   for (const BasicBlock &BB : *Fn) {
     225             :     // Don't create MachineBasicBlocks for imaginary EH pad blocks. These blocks
     226             :     // are really data, and no instructions can live here.
     227      279830 :     if (BB.isEHPad()) {
     228       21986 :       const Instruction *PadInst = BB.getFirstNonPHI();
     229             :       // If this is a non-landingpad EH pad, mark this function as using
     230             :       // funclets.
     231             :       // FIXME: SEH catchpads do not create funclets, so we could avoid setting
     232             :       // this in such cases in order to improve frame layout.
     233       43972 :       if (!isa<LandingPadInst>(PadInst)) {
     234         476 :         MF->setHasEHFunclets(true);
     235         238 :         MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
     236             :       }
     237       43972 :       if (isa<CatchSwitchInst>(PadInst)) {
     238             :         assert(&*BB.begin() == PadInst &&
     239             :                "WinEHPrepare failed to remove PHIs from imaginary BBs");
     240          96 :         continue;
     241             :       }
     242             :       if (isa<FuncletPadInst>(PadInst))
     243             :         assert(&*BB.begin() == PadInst && "WinEHPrepare failed to demote PHIs");
     244             :     }
     245             : 
     246      279734 :     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(&BB);
     247      559468 :     MBBMap[&BB] = MBB;
     248      559468 :     MF->push_back(MBB);
     249             : 
     250             :     // Transfer the address-taken flag. This is necessary because there could
     251             :     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
     252             :     // the first one should be marked.
     253      279734 :     if (BB.hasAddressTaken())
     254         177 :       MBB->setHasAddressTaken();
     255             : 
     256             :     // Mark landing pad blocks.
     257      279734 :     if (BB.isEHPad())
     258             :       MBB->setIsEHPad();
     259             : 
     260             :     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
     261             :     // appropriate.
     262      279734 :     for (BasicBlock::const_iterator I = BB.begin();
     263       40450 :          const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
     264       82270 :       if (PN->use_empty()) continue;
     265             : 
     266             :       // Skip empty types
     267       39082 :       if (PN->getType()->isEmptyTy())
     268           2 :         continue;
     269             : 
     270      117240 :       DebugLoc DL = PN->getDebugLoc();
     271       78160 :       unsigned PHIReg = ValueMap[PN];
     272             :       assert(PHIReg && "PHI node does not have an assigned virtual register!");
     273             : 
     274       78160 :       SmallVector<EVT, 4> ValueVTs;
     275       39080 :       ComputeValueVTs(*TLI, MF->getDataLayout(), PN->getType(), ValueVTs);
     276      156808 :       for (EVT VT : ValueVTs) {
     277       39568 :         unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
     278       39568 :         const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
     279       79936 :         for (unsigned i = 0; i != NumRegisters; ++i)
     280       80736 :           BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
     281       39568 :         PHIReg += NumRegisters;
     282             :       }
     283             :     }
     284             :   }
     285             : 
     286      142329 :   if (!isFuncletEHPersonality(Personality))
     287      142242 :     return;
     288             : 
     289          87 :   WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
     290             : 
     291             :   // Map all BB references in the WinEH data to MBBs.
     292         319 :   for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
     293         239 :     for (WinEHHandlerType &H : TBME.HandlerArray) {
     294         130 :       if (H.Handler)
     295         260 :         H.Handler = MBBMap[H.Handler.get<const BasicBlock *>()];
     296             :     }
     297             :   }
     298         399 :   for (CxxUnwindMapEntry &UME : EHInfo.CxxUnwindMap)
     299         276 :     if (UME.Cleanup)
     300          88 :       UME.Cleanup = MBBMap[UME.Cleanup.get<const BasicBlock *>()];
     301         297 :   for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap) {
     302          72 :     const BasicBlock *BB = UME.Handler.get<const BasicBlock *>();
     303         108 :     UME.Handler = MBBMap[BB];
     304             :   }
     305         280 :   for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap) {
     306          38 :     const BasicBlock *BB = CME.Handler.get<const BasicBlock *>();
     307          57 :     CME.Handler = MBBMap[BB];
     308             :   }
     309             : }
     310             : 
     311             : /// clear - Clear out all the function-specific state. This returns this
     312             : /// FunctionLoweringInfo to an empty state, ready to be used for a
     313             : /// different function.
     314      142254 : void FunctionLoweringInfo::clear() {
     315      142254 :   MBBMap.clear();
     316      142254 :   ValueMap.clear();
     317      142254 :   StaticAllocaMap.clear();
     318      284508 :   LiveOutRegInfo.clear();
     319      142254 :   VisitedBBs.clear();
     320      284508 :   ArgDbgValues.clear();
     321      142254 :   ByValArgFrameIndexMap.clear();
     322      142254 :   RegFixups.clear();
     323      284508 :   StatepointStackSlots.clear();
     324      142254 :   StatepointSpillMaps.clear();
     325      142254 :   PreferredExtendType.clear();
     326      142254 : }
     327             : 
     328             : /// CreateReg - Allocate a single virtual register for the given type.
     329      162229 : unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
     330      486687 :   return RegInfo->createVirtualRegister(
     331      486687 :       MF->getSubtarget().getTargetLowering()->getRegClassFor(VT));
     332             : }
     333             : 
     334             : /// CreateRegs - Allocate the appropriate number of virtual registers of
     335             : /// the correctly promoted or expanded types.  Assign these registers
     336             : /// consecutive vreg numbers and return the first assigned number.
     337             : ///
     338             : /// In the case that the given value has struct or array type, this function
     339             : /// will assign registers for each member or element.
     340             : ///
     341      154991 : unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
     342      154991 :   const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
     343             : 
     344      309982 :   SmallVector<EVT, 4> ValueVTs;
     345      154991 :   ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
     346             : 
     347      154991 :   unsigned FirstReg = 0;
     348      466507 :   for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
     349      313050 :     EVT ValueVT = ValueVTs[Value];
     350      156525 :     MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
     351             : 
     352      156525 :     unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
     353      318535 :     for (unsigned i = 0; i != NumRegs; ++i) {
     354      162010 :       unsigned R = CreateReg(RegisterVT);
     355      162010 :       if (!FirstReg) FirstReg = R;
     356             :     }
     357             :   }
     358      309982 :   return FirstReg;
     359             : }
     360             : 
     361             : /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
     362             : /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
     363             : /// the register's LiveOutInfo is for a smaller bit width, it is extended to
     364             : /// the larger bit width by zero extension. The bit width must be no smaller
     365             : /// than the LiveOutInfo's existing bit width.
     366             : const FunctionLoweringInfo::LiveOutInfo *
     367       25492 : FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
     368       50984 :   if (!LiveOutRegInfo.inBounds(Reg))
     369             :     return nullptr;
     370             : 
     371       50480 :   LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
     372       25240 :   if (!LOI->IsValid)
     373             :     return nullptr;
     374             : 
     375       48936 :   if (BitWidth > LOI->Known.getBitWidth()) {
     376       15504 :     LOI->NumSignBits = 1;
     377       15504 :     LOI->Known = LOI->Known.zextOrTrunc(BitWidth);
     378             :   }
     379             : 
     380             :   return LOI;
     381             : }
     382             : 
     383             : /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
     384             : /// register based on the LiveOutInfo of its operands.
     385       32107 : void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
     386       32107 :   Type *Ty = PN->getType();
     387       47273 :   if (!Ty->isIntegerTy() || Ty->isVectorTy())
     388       19526 :     return;
     389             : 
     390       27747 :   SmallVector<EVT, 1> ValueVTs;
     391       15166 :   ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
     392             :   assert(ValueVTs.size() == 1 &&
     393             :          "PHIs with non-vector integer types should have a single VT.");
     394       15166 :   EVT IntVT = ValueVTs[0];
     395             : 
     396       15166 :   if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
     397             :     return;
     398       30132 :   IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
     399       15066 :   unsigned BitWidth = IntVT.getSizeInBits();
     400             : 
     401       30132 :   unsigned DestReg = ValueMap[PN];
     402       15066 :   if (!TargetRegisterInfo::isVirtualRegister(DestReg))
     403             :     return;
     404       13733 :   LiveOutRegInfo.grow(DestReg);
     405       27466 :   LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
     406             : 
     407       13733 :   Value *V = PN->getIncomingValue(0);
     408       41141 :   if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
     409          60 :     DestLOI.NumSignBits = 1;
     410          60 :     DestLOI.Known = KnownBits(BitWidth);
     411          60 :     return;
     412             :   }
     413             : 
     414       15432 :   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
     415        3518 :     APInt Val = CI->getValue().zextOrTrunc(BitWidth);
     416        1759 :     DestLOI.NumSignBits = Val.getNumSignBits();
     417        8795 :     DestLOI.Known.Zero = ~Val;
     418        1759 :     DestLOI.Known.One = Val;
     419             :   } else {
     420             :     assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
     421             :                                 "CopyToReg node was created.");
     422       23828 :     unsigned SrcReg = ValueMap[V];
     423       11914 :     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
     424           0 :       DestLOI.IsValid = false;
     425           0 :       return;
     426             :     }
     427       11914 :     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
     428       11914 :     if (!SrcLOI) {
     429         538 :       DestLOI.IsValid = false;
     430         538 :       return;
     431             :     }
     432       11376 :     DestLOI = *SrcLOI;
     433             :   }
     434             : 
     435             :   assert(DestLOI.Known.Zero.getBitWidth() == BitWidth &&
     436             :          DestLOI.Known.One.getBitWidth() == BitWidth &&
     437             :          "Masks should have the same bit width as the type.");
     438             : 
     439       41244 :   for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
     440       15528 :     Value *V = PN->getIncomingValue(i);
     441       46516 :     if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
     442          68 :       DestLOI.NumSignBits = 1;
     443          68 :       DestLOI.Known = KnownBits(BitWidth);
     444          68 :       return;
     445             :     }
     446             : 
     447       17342 :     if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
     448        3764 :       APInt Val = CI->getValue().zextOrTrunc(BitWidth);
     449        3764 :       DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
     450        9410 :       DestLOI.Known.Zero &= ~Val;
     451        3764 :       DestLOI.Known.One &= Val;
     452             :       continue;
     453             :     }
     454             : 
     455             :     assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
     456             :                                 "its CopyToReg node was created.");
     457       27156 :     unsigned SrcReg = ValueMap[V];
     458       13578 :     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
     459           0 :       DestLOI.IsValid = false;
     460           0 :       return;
     461             :     }
     462       13578 :     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
     463       13578 :     if (!SrcLOI) {
     464         486 :       DestLOI.IsValid = false;
     465         486 :       return;
     466             :     }
     467       26184 :     DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
     468       26184 :     DestLOI.Known.Zero &= SrcLOI->Known.Zero;
     469       13092 :     DestLOI.Known.One &= SrcLOI->Known.One;
     470             :   }
     471             : }
     472             : 
     473             : /// setArgumentFrameIndex - Record frame index for the byval
     474             : /// argument. This overrides previous frame index entry for this argument,
     475             : /// if any.
     476        1258 : void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
     477             :                                                  int FI) {
     478        2516 :   ByValArgFrameIndexMap[A] = FI;
     479        1258 : }
     480             : 
     481             : /// getArgumentFrameIndex - Get frame index for the byval argument.
     482             : /// If the argument does not have any assigned frame index then 0 is
     483             : /// returned.
     484        1084 : int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
     485        1084 :   auto I = ByValArgFrameIndexMap.find(A);
     486        3252 :   if (I != ByValArgFrameIndexMap.end())
     487          49 :     return I->second;
     488             :   DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
     489             :   return INT_MAX;
     490             : }
     491             : 
     492          12 : unsigned FunctionLoweringInfo::getCatchPadExceptionPointerVReg(
     493             :     const Value *CPI, const TargetRegisterClass *RC) {
     494          12 :   MachineRegisterInfo &MRI = MF->getRegInfo();
     495          36 :   auto I = CatchPadExceptionPointers.insert({CPI, 0});
     496          12 :   unsigned &VReg = I.first->second;
     497          12 :   if (I.second)
     498           6 :     VReg = MRI.createVirtualRegister(RC);
     499             :   assert(VReg && "null vreg in exception pointer table!");
     500          12 :   return VReg;
     501             : }
     502             : 
     503             : unsigned
     504         503 : FunctionLoweringInfo::getOrCreateSwiftErrorVReg(const MachineBasicBlock *MBB,
     505             :                                                 const Value *Val) {
     506        1006 :   auto Key = std::make_pair(MBB, Val);
     507         503 :   auto It = SwiftErrorVRegDefMap.find(Key);
     508             :   // If this is the first use of this swifterror value in this basic block,
     509             :   // create a new virtual register.
     510             :   // After we processed all basic blocks we will satisfy this "upwards exposed
     511             :   // use" by inserting a copy or phi at the beginning of this block.
     512        1509 :   if (It == SwiftErrorVRegDefMap.end()) {
     513          45 :     auto &DL = MF->getDataLayout();
     514          90 :     const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
     515          45 :     auto VReg = MF->getRegInfo().createVirtualRegister(RC);
     516          90 :     SwiftErrorVRegDefMap[Key] = VReg;
     517          90 :     SwiftErrorVRegUpwardsUse[Key] = VReg;
     518          45 :     return VReg;
     519         458 :   } else return It->second;
     520             : }
     521             : 
     522         500 : void FunctionLoweringInfo::setCurrentSwiftErrorVReg(
     523             :     const MachineBasicBlock *MBB, const Value *Val, unsigned VReg) {
     524        1000 :   SwiftErrorVRegDefMap[std::make_pair(MBB, Val)] = VReg;
     525         500 : }
     526             : 
     527             : std::pair<unsigned, bool>
     528         298 : FunctionLoweringInfo::getOrCreateSwiftErrorVRegDefAt(const Instruction *I) {
     529         298 :   auto Key = PointerIntPair<const Instruction *, 1, bool>(I, true);
     530         298 :   auto It = SwiftErrorVRegDefUses.find(Key);
     531         894 :   if (It == SwiftErrorVRegDefUses.end()) {
     532         216 :     auto &DL = MF->getDataLayout();
     533         432 :     const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
     534         216 :     unsigned VReg =  MF->getRegInfo().createVirtualRegister(RC);
     535         432 :     SwiftErrorVRegDefUses[Key] = VReg;
     536         216 :     return std::make_pair(VReg, true);
     537             :   }
     538          82 :   return std::make_pair(It->second, false);
     539             : }
     540             : 
     541             : std::pair<unsigned, bool>
     542         377 : FunctionLoweringInfo::getOrCreateSwiftErrorVRegUseAt(const Instruction *I, const MachineBasicBlock *MBB, const Value *Val) {
     543         377 :   auto Key = PointerIntPair<const Instruction *, 1, bool>(I, false);
     544         377 :   auto It = SwiftErrorVRegDefUses.find(Key);
     545        1131 :   if (It == SwiftErrorVRegDefUses.end()) {
     546         271 :     unsigned VReg = getOrCreateSwiftErrorVReg(MBB, Val);
     547         542 :     SwiftErrorVRegDefUses[Key] = VReg;
     548         271 :     return std::make_pair(VReg, true);
     549             :   }
     550         106 :   return std::make_pair(It->second, false);
     551             : }

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