LCOV - code coverage report
Current view: top level - lib/CodeGen/SelectionDAG - InstrEmitter.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 419 445 94.2 %
Date: 2018-06-17 00:07:59 Functions: 16 17 94.1 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This implements the Emit routines for the SelectionDAG class, which creates
      11             : // MachineInstrs based on the decisions of the SelectionDAG instruction
      12             : // selection.
      13             : //
      14             : //===----------------------------------------------------------------------===//
      15             : 
      16             : #include "InstrEmitter.h"
      17             : #include "SDNodeDbgValue.h"
      18             : #include "llvm/ADT/Statistic.h"
      19             : #include "llvm/CodeGen/MachineConstantPool.h"
      20             : #include "llvm/CodeGen/MachineFunction.h"
      21             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      22             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      23             : #include "llvm/CodeGen/StackMaps.h"
      24             : #include "llvm/CodeGen/TargetInstrInfo.h"
      25             : #include "llvm/CodeGen/TargetLowering.h"
      26             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      27             : #include "llvm/IR/DataLayout.h"
      28             : #include "llvm/IR/DebugInfo.h"
      29             : #include "llvm/Support/Debug.h"
      30             : #include "llvm/Support/ErrorHandling.h"
      31             : #include "llvm/Support/MathExtras.h"
      32             : using namespace llvm;
      33             : 
      34             : #define DEBUG_TYPE "instr-emitter"
      35             : 
      36             : /// MinRCSize - Smallest register class we allow when constraining virtual
      37             : /// registers.  If satisfying all register class constraints would require
      38             : /// using a smaller register class, emit a COPY to a new virtual register
      39             : /// instead.
      40             : const unsigned MinRCSize = 4;
      41             : 
      42             : /// CountResults - The results of target nodes have register or immediate
      43             : /// operands first, then an optional chain, and optional glue operands (which do
      44             : /// not go into the resulting MachineInstr).
      45     5611399 : unsigned InstrEmitter::CountResults(SDNode *Node) {
      46     5611399 :   unsigned N = Node->getNumValues();
      47     8327117 :   while (N && Node->getValueType(N - 1) == MVT::Glue)
      48             :     --N;
      49    11217070 :   if (N && Node->getValueType(N - 1) == MVT::Other)
      50             :     --N;    // Skip over chain result.
      51     5611399 :   return N;
      52             : }
      53             : 
      54             : /// countOperands - The inputs to target nodes have any actual inputs first,
      55             : /// followed by an optional chain operand, then an optional glue operand.
      56             : /// Compute the number of actual operands that will go into the resulting
      57             : /// MachineInstr.
      58             : ///
      59             : /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
      60             : /// the chain and glue. These operands may be implicit on the machine instr.
      61     2868727 : static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
      62             :                               unsigned &NumImpUses) {
      63     2868727 :   unsigned N = Node->getNumOperands();
      64     7618759 :   while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
      65             :     --N;
      66     8444347 :   if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
      67             :     --N; // Ignore chain if it exists.
      68             : 
      69             :   // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
      70     2868727 :   NumImpUses = N - NumExpUses;
      71     3521081 :   for (unsigned I = N; I > NumExpUses; --I) {
      72     1312294 :     if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
      73      180202 :       continue;
      74             :     if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
      75      949398 :       if (TargetRegisterInfo::isPhysicalRegister(RN->getReg()))
      76      472152 :         continue;
      77        3793 :     NumImpUses = N - I;
      78        3793 :     break;
      79             :   }
      80             : 
      81     2868727 :   return N;
      82             : }
      83             : 
      84             : /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
      85             : /// implicit physical register output.
      86      705200 : void InstrEmitter::
      87             : EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
      88             :                 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
      89             :   unsigned VRBase = 0;
      90      705200 :   if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
      91             :     // Just use the input register directly!
      92             :     SDValue Op(Node, ResNo);
      93      470775 :     if (IsClone)
      94           0 :       VRBaseMap.erase(Op);
      95      470775 :     bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
      96             :     (void)isNew; // Silence compiler warning.
      97             :     assert(isNew && "Node emitted out of order - early");
      98             :     return;
      99             :   }
     100             : 
     101             :   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
     102             :   // the CopyToReg'd destination register instead of creating a new vreg.
     103             :   bool MatchReg = true;
     104             :   const TargetRegisterClass *UseRC = nullptr;
     105             :   MVT VT = Node->getSimpleValueType(ResNo);
     106             : 
     107             :   // Stick to the preferred register classes for legal types.
     108      234425 :   if (TLI->isTypeLegal(VT))
     109      234425 :     UseRC = TLI->getRegClassFor(VT);
     110             : 
     111      234425 :   if (!IsClone && !IsCloned)
     112      516219 :     for (SDNode *User : Node->uses()) {
     113             :       bool Match = true;
     114      467029 :       if (User->getOpcode() == ISD::CopyToReg &&
     115      464992 :           User->getOperand(2).getNode() == Node &&
     116      126547 :           User->getOperand(2).getResNo() == ResNo) {
     117      125223 :         unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
     118      125223 :         if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
     119             :           VRBase = DestReg;
     120             :           Match = false;
     121      109388 :         } else if (DestReg != SrcReg)
     122             :           Match = false;
     123             :       } else {
     124     2470932 :         for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
     125     2044488 :           SDValue Op = User->getOperand(i);
     126     1937715 :           if (Op.getNode() != Node || Op.getResNo() != ResNo)
     127      915471 :             continue;
     128             :           MVT VT = Node->getSimpleValueType(Op.getResNo());
     129      213546 :           if (VT == MVT::Other || VT == MVT::Glue)
     130           0 :             continue;
     131             :           Match = false;
     132      106773 :           if (User->isMachineOpcode()) {
     133      213536 :             const MCInstrDesc &II = TII->get(User->getMachineOpcode());
     134             :             const TargetRegisterClass *RC = nullptr;
     135      320304 :             if (i+II.getNumDefs() < II.getNumOperands()) {
     136      213348 :               RC = TRI->getAllocatableClass(
     137      106674 :                 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
     138             :             }
     139      106768 :             if (!UseRC)
     140             :               UseRC = RC;
     141      106768 :             else if (RC) {
     142             :               const TargetRegisterClass *ComRC =
     143      105368 :                 TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy);
     144             :               // If multiple uses expect disjoint register classes, we emit
     145             :               // copies in AddRegisterOperand.
     146      105368 :               if (ComRC)
     147             :                 UseRC = ComRC;
     148             :             }
     149             :           }
     150             :         }
     151             :       }
     152             :       MatchReg &= Match;
     153      338445 :       if (VRBase)
     154             :         break;
     155             :     }
     156             : 
     157             :   const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
     158      234425 :   SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
     159             : 
     160             :   // Figure out the register class to create for the destreg.
     161      234425 :   if (VRBase) {
     162       15835 :     DstRC = MRI->getRegClass(VRBase);
     163      218590 :   } else if (UseRC) {
     164             :     assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
     165             :            "Incompatible phys register def and uses!");
     166             :     DstRC = UseRC;
     167             :   } else {
     168           0 :     DstRC = TLI->getRegClassFor(VT);
     169             :   }
     170             : 
     171             :   // If all uses are reading from the src physical register and copying the
     172             :   // register is either impossible or very expensive, then don't create a copy.
     173      389036 :   if (MatchReg && SrcRC->getCopyCost() < 0) {
     174             :     VRBase = SrcReg;
     175             :   } else {
     176             :     // Create the reg, emit the copy.
     177      195370 :     VRBase = MRI->createVirtualRegister(DstRC);
     178      293055 :     BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
     179      195370 :             VRBase).addReg(SrcReg);
     180             :   }
     181             : 
     182             :   SDValue Op(Node, ResNo);
     183      234425 :   if (IsClone)
     184       20433 :     VRBaseMap.erase(Op);
     185      234425 :   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
     186             :   (void)isNew; // Silence compiler warning.
     187             :   assert(isNew && "Node emitted out of order - early");
     188             : }
     189             : 
     190             : /// getDstOfCopyToRegUse - If the only use of the specified result number of
     191             : /// node is a CopyToReg, return its destination register. Return 0 otherwise.
     192       41755 : unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
     193             :                                                 unsigned ResNo) const {
     194             :   if (!Node->hasOneUse())
     195             :     return 0;
     196             : 
     197             :   SDNode *User = *Node->use_begin();
     198       20096 :   if (User->getOpcode() == ISD::CopyToReg &&
     199       20096 :       User->getOperand(2).getNode() == Node &&
     200        1141 :       User->getOperand(2).getResNo() == ResNo) {
     201        1141 :     unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
     202        1141 :     if (TargetRegisterInfo::isVirtualRegister(Reg))
     203             :       return Reg;
     204             :   }
     205             :   return 0;
     206             : }
     207             : 
     208     1966817 : void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
     209             :                                        MachineInstrBuilder &MIB,
     210             :                                        const MCInstrDesc &II,
     211             :                                        bool IsClone, bool IsCloned,
     212             :                                        DenseMap<SDValue, unsigned> &VRBaseMap) {
     213             :   assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
     214             :          "IMPLICIT_DEF should have been handled as a special case elsewhere!");
     215             : 
     216     1966817 :   unsigned NumResults = CountResults(Node);
     217     8068666 :   for (unsigned i = 0; i < II.getNumDefs(); ++i) {
     218             :     // If the specific node value is only used by a CopyToReg and the dest reg
     219             :     // is a vreg in the same register class, use the CopyToReg'd destination
     220             :     // register instead of creating a new vreg.
     221             :     unsigned VRBase = 0;
     222             :     const TargetRegisterClass *RC =
     223     1378344 :       TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
     224             :     // Always let the value type influence the used register class. The
     225             :     // constraints on the instruction may be too lax to represent the value
     226             :     // type correctly. For example, a 64-bit float (X86::FR64) can't live in
     227             :     // the 32-bit float super-class (X86::FR32).
     228     1378344 :     if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
     229             :       const TargetRegisterClass *VTRC =
     230     1371187 :         TLI->getRegClassFor(Node->getSimpleValueType(i));
     231     1371187 :       if (RC)
     232     1366055 :         VTRC = TRI->getCommonSubClass(RC, VTRC);
     233     1371187 :       if (VTRC)
     234             :         RC = VTRC;
     235             :     }
     236             : 
     237     1378344 :     if (II.OpInfo[i].isOptionalDef()) {
     238             :       // Optional def must be a physical register.
     239        5094 :       VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
     240             :       assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
     241        2547 :       MIB.addReg(VRBase, RegState::Define);
     242             :     }
     243             : 
     244        2547 :     if (!VRBase && !IsClone && !IsCloned)
     245     3292008 :       for (SDNode *User : Node->uses()) {
     246     2420138 :         if (User->getOpcode() == ISD::CopyToReg &&
     247     2417393 :             User->getOperand(2).getNode() == Node &&
     248      421323 :             User->getOperand(2).getResNo() == i) {
     249      396659 :           unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
     250      396659 :           if (TargetRegisterInfo::isVirtualRegister(Reg)) {
     251       70990 :             const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
     252       70990 :             if (RegRC == RC) {
     253             :               VRBase = Reg;
     254       66647 :               MIB.addReg(VRBase, RegState::Define);
     255       66647 :               break;
     256             :             }
     257             :           }
     258             :         }
     259             :       }
     260             : 
     261             :     // Create the result registers for this node and add the result regs to
     262             :     // the machine instruction.
     263     1378344 :     if (VRBase == 0) {
     264             :       assert(RC && "Isn't a register operand!");
     265     2618300 :       VRBase = MRI->createVirtualRegister(RC);
     266     1309150 :       MIB.addReg(VRBase, RegState::Define);
     267             :     }
     268             : 
     269             :     // If this def corresponds to a result of the SDNode insert the VRBase into
     270             :     // the lookup map.
     271     1378344 :     if (i < NumResults) {
     272             :       SDValue Op(Node, i);
     273     1375797 :       if (IsClone)
     274        6611 :         VRBaseMap.erase(Op);
     275     1375797 :       bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
     276             :       (void)isNew; // Silence compiler warning.
     277             :       assert(isNew && "Node emitted out of order - early");
     278             :     }
     279             :   }
     280     1966817 : }
     281             : 
     282             : /// getVR - Return the virtual register corresponding to the specified result
     283             : /// of the specified node.
     284     3112631 : unsigned InstrEmitter::getVR(SDValue Op,
     285             :                              DenseMap<SDValue, unsigned> &VRBaseMap) {
     286     6225262 :   if (Op.isMachineOpcode() &&
     287             :       Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
     288             :     // Add an IMPLICIT_DEF instruction before every use.
     289       41755 :     unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
     290             :     // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
     291             :     // does not include operand register class info.
     292       41755 :     if (!VReg) {
     293             :       const TargetRegisterClass *RC =
     294       82492 :         TLI->getRegClassFor(Op.getSimpleValueType());
     295       82492 :       VReg = MRI->createVirtualRegister(RC);
     296             :     }
     297       41755 :     BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
     298       83510 :             TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
     299       41755 :     return VReg;
     300             :   }
     301             : 
     302     3070876 :   DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
     303             :   assert(I != VRBaseMap.end() && "Node emitted out of order - late");
     304     3070876 :   return I->second;
     305             : }
     306             : 
     307             : 
     308             : /// AddRegisterOperand - Add the specified register as an operand to the
     309             : /// specified machine instr. Insert register copies if the register is
     310             : /// not in the required register class.
     311             : void
     312     2084562 : InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
     313             :                                  SDValue Op,
     314             :                                  unsigned IIOpNum,
     315             :                                  const MCInstrDesc *II,
     316             :                                  DenseMap<SDValue, unsigned> &VRBaseMap,
     317             :                                  bool IsDebug, bool IsClone, bool IsCloned) {
     318             :   assert(Op.getValueType() != MVT::Other &&
     319             :          Op.getValueType() != MVT::Glue &&
     320             :          "Chain and glue operands should occur at end of operand list!");
     321             :   // Get/emit the operand.
     322     2084562 :   unsigned VReg = getVR(Op, VRBaseMap);
     323             : 
     324     2084562 :   const MCInstrDesc &MCID = MIB->getDesc();
     325     6101071 :   bool isOptDef = IIOpNum < MCID.getNumOperands() &&
     326     1931947 :     MCID.OpInfo[IIOpNum].isOptionalDef();
     327             : 
     328             :   // If the instruction requires a register in a different class, create
     329             :   // a new virtual register and copy the value into it, but first attempt to
     330             :   // shrink VReg's register class within reason.  For example, if VReg == GR32
     331             :   // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
     332     2084562 :   if (II) {
     333             :     const TargetRegisterClass *OpRC = nullptr;
     334     3987238 :     if (IIOpNum < II->getNumOperands())
     335     1843889 :       OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
     336             : 
     337     1843889 :     if (OpRC) {
     338             :       const TargetRegisterClass *ConstrainedRC
     339     1838608 :         = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
     340     1838608 :       if (!ConstrainedRC) {
     341       60418 :         OpRC = TRI->getAllocatableClass(OpRC);
     342             :         assert(OpRC && "Constraints cannot be fulfilled for allocation");
     343      120836 :         unsigned NewVReg = MRI->createVirtualRegister(OpRC);
     344      120836 :         BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
     345      120836 :                 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
     346             :         VReg = NewVReg;
     347             :       } else {
     348             :         assert(ConstrainedRC->isAllocatable() &&
     349             :            "Constraining an allocatable VReg produced an unallocatable class?");
     350             :       }
     351             :     }
     352             :   }
     353             : 
     354             :   // If this value has only one use, that use is a kill. This is a
     355             :   // conservative approximation. InstrEmitter does trivial coalescing
     356             :   // with CopyFromReg nodes, so don't emit kill flags for them.
     357             :   // Avoid kill flags on Schedule cloned nodes, since there will be
     358             :   // multiple uses.
     359             :   // Tied operands are never killed, so we need to check that. And that
     360             :   // means we need to determine the index of the operand.
     361     3390142 :   bool isKill = Op.hasOneUse() &&
     362     2291258 :                 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
     363     3066398 :                 !IsDebug &&
     364             :                 !(IsClone || IsCloned);
     365             :   if (isKill) {
     366      976596 :     unsigned Idx = MIB->getNumOperands();
     367     1162214 :     while (Idx > 0 &&
     368     2226285 :            MIB->getOperand(Idx-1).isReg() &&
     369             :            MIB->getOperand(Idx-1).isImplicit())
     370             :       --Idx;
     371      976596 :     bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
     372             :     if (isTied)
     373             :       isKill = false;
     374             :   }
     375             : 
     376     4169124 :   MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
     377     2084562 :              getDebugRegState(IsDebug));
     378     2084562 : }
     379             : 
     380             : /// AddOperand - Add the specified operand to the specified machine instr.  II
     381             : /// specifies the instruction information for the node, and IIOpNum is the
     382             : /// operand number (in the II) that we are adding.
     383    10554568 : void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
     384             :                               SDValue Op,
     385             :                               unsigned IIOpNum,
     386             :                               const MCInstrDesc *II,
     387             :                               DenseMap<SDValue, unsigned> &VRBaseMap,
     388             :                               bool IsDebug, bool IsClone, bool IsCloned) {
     389    10554568 :   if (Op.isMachineOpcode()) {
     390     1521368 :     AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
     391             :                        IsDebug, IsClone, IsCloned);
     392             :   } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
     393     4075559 :     MIB.addImm(C->getSExtValue());
     394             :   } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
     395         158 :     MIB.addFPImm(F->getConstantFPValue());
     396             :   } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
     397     3053725 :     unsigned VReg = R->getReg();
     398             :     MVT OpVT = Op.getSimpleValueType();
     399             :     const TargetRegisterClass *OpRC =
     400     6107363 :         TLI->isTypeLegal(OpVT) ? TLI->getRegClassFor(OpVT) : nullptr;
     401             :     const TargetRegisterClass *IIRC =
     402     3053725 :         II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
     403             :            : nullptr;
     404             : 
     405     4885474 :     if (OpRC && IIRC && OpRC != IIRC &&
     406             :         TargetRegisterInfo::isVirtualRegister(VReg)) {
     407        2820 :       unsigned NewVReg = MRI->createVirtualRegister(IIRC);
     408        2820 :       BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
     409        2820 :                TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
     410             :       VReg = NewVReg;
     411             :     }
     412             :     // Turn additional physreg operands into implicit uses on non-variadic
     413             :     // instructions. This is used by call and return instructions passing
     414             :     // arguments in registers.
     415     6568516 :     bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
     416     3053725 :     MIB.addReg(VReg, getImplRegState(Imp));
     417             :   } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
     418      180221 :     MIB.addRegMask(RM->getRegMask());
     419             :   } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
     420             :     MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
     421      762418 :                          TGA->getTargetFlags());
     422             :   } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
     423      163872 :     MIB.addMBB(BBNode->getBasicBlock());
     424             :   } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
     425      196919 :     MIB.addFrameIndex(FI->getIndex());
     426             :   } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
     427         361 :     MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
     428             :   } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
     429       25444 :     int Offset = CP->getOffset();
     430       25444 :     unsigned Align = CP->getAlignment();
     431       25444 :     Type *Type = CP->getType();
     432             :     // MachineConstantPool wants an explicit alignment.
     433       25444 :     if (Align == 0) {
     434           0 :       Align = MF->getDataLayout().getPrefTypeAlignment(Type);
     435           0 :       if (Align == 0) {
     436             :         // Alignment of vector types.  FIXME!
     437           0 :         Align = MF->getDataLayout().getTypeAllocSize(Type);
     438             :       }
     439             :     }
     440             : 
     441             :     unsigned Idx;
     442       25444 :     MachineConstantPool *MCP = MF->getConstantPool();
     443       25444 :     if (CP->isMachineConstantPoolEntry())
     444         260 :       Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
     445             :     else
     446       25184 :       Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
     447       25444 :     MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
     448             :   } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
     449       11135 :     MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
     450             :   } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
     451          57 :     MIB.addSym(SymNode->getMCSymbol());
     452             :   } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
     453             :     MIB.addBlockAddress(BA->getBlockAddress(),
     454             :                         BA->getOffset(),
     455         137 :                         BA->getTargetFlags());
     456             :   } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
     457           0 :     MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
     458             :   } else {
     459             :     assert(Op.getValueType() != MVT::Other &&
     460             :            Op.getValueType() != MVT::Glue &&
     461             :            "Chain and glue operands should occur at end of operand list!");
     462      563194 :     AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
     463             :                        IsDebug, IsClone, IsCloned);
     464             :   }
     465    10554568 : }
     466             : 
     467      134015 : unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
     468             :                                           MVT VT, const DebugLoc &DL) {
     469      134015 :   const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
     470      134015 :   const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
     471             : 
     472             :   // RC is a sub-class of VRC that supports SubIdx.  Try to constrain VReg
     473             :   // within reason.
     474      134015 :   if (RC && RC != VRC)
     475        1934 :     RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
     476             : 
     477             :   // VReg has been adjusted.  It can be used with SubIdx operands now.
     478      134015 :   if (RC)
     479             :     return VReg;
     480             : 
     481             :   // VReg couldn't be reasonably constrained.  Emit a COPY to a new virtual
     482             :   // register instead.
     483           0 :   RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
     484             :   assert(RC && "No legal register class for VT supports that SubIdx");
     485           0 :   unsigned NewReg = MRI->createVirtualRegister(RC);
     486           0 :   BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
     487           0 :     .addReg(VReg);
     488           0 :   return NewReg;
     489             : }
     490             : 
     491             : /// EmitSubregNode - Generate machine code for subreg nodes.
     492             : ///
     493      196441 : void InstrEmitter::EmitSubregNode(SDNode *Node,
     494             :                                   DenseMap<SDValue, unsigned> &VRBaseMap,
     495             :                                   bool IsClone, bool IsCloned) {
     496             :   unsigned VRBase = 0;
     497      196441 :   unsigned Opc = Node->getMachineOpcode();
     498             : 
     499             :   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
     500             :   // the CopyToReg'd destination register instead of creating a new vreg.
     501      399598 :   for (SDNode *User : Node->uses()) {
     502      278310 :     if (User->getOpcode() == ISD::CopyToReg &&
     503       54304 :         User->getOperand(2).getNode() == Node) {
     504       54299 :       unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
     505       54299 :       if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
     506             :         VRBase = DestReg;
     507             :         break;
     508             :       }
     509             :     }
     510             :   }
     511             : 
     512      196441 :   if (Opc == TargetOpcode::EXTRACT_SUBREG) {
     513             :     // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub.  There are no
     514             :     // constraints on the %dst register, COPY can target all legal register
     515             :     // classes.
     516      402099 :     unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
     517             :     const TargetRegisterClass *TRC =
     518      268066 :       TLI->getRegClassFor(Node->getSimpleValueType(0));
     519             : 
     520             :     unsigned Reg;
     521             :     MachineInstr *DefMI;
     522      134033 :     RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
     523           0 :     if (R && TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
     524             :       Reg = R->getReg();
     525             :       DefMI = nullptr;
     526             :     } else {
     527      134033 :       Reg = getVR(Node->getOperand(0), VRBaseMap);
     528      134033 :       DefMI = MRI->getVRegDef(Reg);
     529             :     }
     530             : 
     531             :     unsigned SrcReg, DstReg, DefSubIdx;
     532      111537 :     if (DefMI &&
     533      111587 :         TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
     534      134101 :         SubIdx == DefSubIdx &&
     535          18 :         TRC == MRI->getRegClass(SrcReg)) {
     536             :       // Optimize these:
     537             :       // r1025 = s/zext r1024, 4
     538             :       // r1026 = extract_subreg r1025, 4
     539             :       // to a copy
     540             :       // r1026 = copy r1024
     541          18 :       VRBase = MRI->createVirtualRegister(TRC);
     542          36 :       BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
     543          36 :               TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
     544          18 :       MRI->clearKillFlags(SrcReg);
     545             :     } else {
     546             :       // Reg may not support a SubIdx sub-register, and we may need to
     547             :       // constrain its register class or issue a COPY to a compatible register
     548             :       // class.
     549      134015 :       if (TargetRegisterInfo::isVirtualRegister(Reg))
     550      134015 :         Reg = ConstrainForSubReg(Reg, SubIdx,
     551      134015 :                                  Node->getOperand(0).getSimpleValueType(),
     552             :                                  Node->getDebugLoc());
     553             : 
     554             :       // Create the destreg if it is missing.
     555      134015 :       if (VRBase == 0)
     556      232662 :         VRBase = MRI->createVirtualRegister(TRC);
     557             : 
     558             :       // Create the extract_subreg machine instruction.
     559             :       MachineInstrBuilder CopyMI =
     560      134015 :           BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
     561      268030 :                   TII->get(TargetOpcode::COPY), VRBase);
     562      134015 :       if (TargetRegisterInfo::isVirtualRegister(Reg))
     563      134015 :         CopyMI.addReg(Reg, 0, SubIdx);
     564             :       else
     565           0 :         CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
     566             :     }
     567      124816 :   } else if (Opc == TargetOpcode::INSERT_SUBREG ||
     568       62408 :              Opc == TargetOpcode::SUBREG_TO_REG) {
     569       62408 :     SDValue N0 = Node->getOperand(0);
     570       62408 :     SDValue N1 = Node->getOperand(1);
     571       62408 :     SDValue N2 = Node->getOperand(2);
     572      124816 :     unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
     573             : 
     574             :     // Figure out the register class to create for the destreg.  It should be
     575             :     // the largest legal register class supporting SubIdx sub-registers.
     576             :     // RegisterCoalescer will constrain it further if it decides to eliminate
     577             :     // the INSERT_SUBREG instruction.
     578             :     //
     579             :     //   %dst = INSERT_SUBREG %src, %sub, SubIdx
     580             :     //
     581             :     // is lowered by TwoAddressInstructionPass to:
     582             :     //
     583             :     //   %dst = COPY %src
     584             :     //   %dst:SubIdx = COPY %sub
     585             :     //
     586             :     // There is no constraint on the %src register class.
     587             :     //
     588      124816 :     const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0));
     589       62408 :     SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
     590             :     assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
     591             : 
     592       68738 :     if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
     593      118494 :       VRBase = MRI->createVirtualRegister(SRC);
     594             : 
     595             :     // Create the insert_subreg or subreg_to_reg machine instruction.
     596             :     MachineInstrBuilder MIB =
     597      124816 :       BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
     598             : 
     599             :     // If creating a subreg_to_reg, then the first input operand
     600             :     // is an implicit value immediate, otherwise it's a register
     601       62408 :     if (Opc == TargetOpcode::SUBREG_TO_REG) {
     602             :       const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
     603       73516 :       MIB.addImm(SD->getZExtValue());
     604             :     } else
     605       25650 :       AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
     606             :                  IsClone, IsCloned);
     607             :     // Add the subregister being inserted
     608       62408 :     AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
     609             :                IsClone, IsCloned);
     610       62408 :     MIB.addImm(SubIdx);
     611       62408 :     MBB->insert(InsertPos, MIB);
     612             :   } else
     613           0 :     llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
     614             : 
     615             :   SDValue Op(Node, 0);
     616      196441 :   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
     617             :   (void)isNew; // Silence compiler warning.
     618             :   assert(isNew && "Node emitted out of order - early");
     619      196441 : }
     620             : 
     621             : /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
     622             : /// COPY_TO_REGCLASS is just a normal copy, except that the destination
     623             : /// register is constrained to be in a particular register class.
     624             : ///
     625             : void
     626       38413 : InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
     627             :                                      DenseMap<SDValue, unsigned> &VRBaseMap) {
     628       76826 :   unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
     629             : 
     630             :   // Create the new VReg in the destination class and emit a copy.
     631       76826 :   unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
     632             :   const TargetRegisterClass *DstRC =
     633       76826 :     TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
     634       76826 :   unsigned NewVReg = MRI->createVirtualRegister(DstRC);
     635      115239 :   BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
     636       76826 :     NewVReg).addReg(VReg);
     637             : 
     638             :   SDValue Op(Node, 0);
     639       38413 :   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
     640             :   (void)isNew; // Silence compiler warning.
     641             :   assert(isNew && "Node emitted out of order - early");
     642       38413 : }
     643             : 
     644             : /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
     645             : ///
     646       45992 : void InstrEmitter::EmitRegSequence(SDNode *Node,
     647             :                                   DenseMap<SDValue, unsigned> &VRBaseMap,
     648             :                                   bool IsClone, bool IsCloned) {
     649       91984 :   unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
     650       45992 :   const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
     651       91984 :   unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
     652       45992 :   const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
     653       45992 :   MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
     654       45992 :   unsigned NumOps = Node->getNumOperands();
     655             :   assert((NumOps & 1) == 1 &&
     656             :          "REG_SEQUENCE must have an odd number of operands!");
     657      598036 :   for (unsigned i = 1; i != NumOps; ++i) {
     658      552044 :     SDValue Op = Node->getOperand(i);
     659      276022 :     if ((i & 1) == 0) {
     660      138011 :       RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
     661             :       // Skip physical registers as they don't have a vreg to get and we'll
     662             :       // insert copies for them in TwoAddressInstructionPass anyway.
     663        2590 :       if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
     664      273432 :         unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
     665      136716 :         unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
     666      136716 :         const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
     667             :         const TargetRegisterClass *SRC =
     668      136716 :         TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
     669      136716 :         if (SRC && SRC != RC) {
     670        3669 :           MRI->setRegClass(NewVReg, SRC);
     671             :           RC = SRC;
     672             :         }
     673             :       }
     674             :     }
     675      276022 :     AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
     676             :                IsClone, IsCloned);
     677             :   }
     678             : 
     679       45992 :   MBB->insert(InsertPos, MIB);
     680             :   SDValue Op(Node, 0);
     681       45992 :   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
     682             :   (void)isNew; // Silence compiler warning.
     683             :   assert(isNew && "Node emitted out of order - early");
     684       45992 : }
     685             : 
     686             : /// EmitDbgValue - Generate machine instruction for a dbg_value node.
     687             : ///
     688             : MachineInstr *
     689       24878 : InstrEmitter::EmitDbgValue(SDDbgValue *SD,
     690             :                            DenseMap<SDValue, unsigned> &VRBaseMap) {
     691       24878 :   MDNode *Var = SD->getVariable();
     692       24878 :   MDNode *Expr = SD->getExpression();
     693             :   DebugLoc DL = SD->getDebugLoc();
     694             :   assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
     695             :          "Expected inlined-at fields to agree");
     696             : 
     697       24878 :   if (SD->getKind() == SDDbgValue::FRAMEIX) {
     698             :     // Stack address; this needs to be lowered in target-dependent fashion.
     699             :     // EmitTargetCodeForFrameDebugValue is responsible for allocation.
     700        2296 :     return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
     701        1148 :         .addFrameIndex(SD->getFrameIx())
     702             :         .addImm(0)
     703             :         .addMetadata(Var)
     704             :         .addMetadata(Expr);
     705             :   }
     706             :   // Otherwise, we're going to create an instruction here.
     707       23730 :   const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
     708       47460 :   MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
     709       23730 :   if (SD->getKind() == SDDbgValue::SDNODE) {
     710       10651 :     SDNode *Node = SD->getSDNode();
     711       10651 :     SDValue Op = SDValue(Node, SD->getResNo());
     712             :     // It's possible we replaced this SDNode with other(s) and therefore
     713             :     // didn't generate code for it.  It's better to catch these cases where
     714             :     // they happen and transfer the debug info, but trying to guarantee that
     715             :     // in all cases would be very fragile; this is a safeguard for any
     716             :     // that were missed.
     717       10651 :     DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
     718       10651 :     if (I==VRBaseMap.end())
     719           4 :       MIB.addReg(0U);       // undef
     720             :     else
     721       10647 :       AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
     722             :                  /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
     723       13079 :   } else if (SD->getKind() == SDDbgValue::VREG) {
     724        3805 :     MIB.addReg(SD->getVReg(), RegState::Debug);
     725        9274 :   } else if (SD->getKind() == SDDbgValue::CONST) {
     726        9274 :     const Value *V = SD->getConst();
     727             :     if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
     728        1543 :       if (CI->getBitWidth() > 64)
     729             :         MIB.addCImm(CI);
     730             :       else
     731             :         MIB.addImm(CI->getSExtValue());
     732             :     } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
     733             :       MIB.addFPImm(CF);
     734             :     } else {
     735             :       // Could be an Undef.  In any case insert an Undef so we can see what we
     736             :       // dropped.
     737        7710 :       MIB.addReg(0U);
     738             :     }
     739             :   } else {
     740             :     // Insert an Undef so we can see what we dropped.
     741           0 :     MIB.addReg(0U);
     742             :   }
     743             : 
     744             :   // Indirect addressing is indicated by an Imm as the second parameter.
     745       23730 :   if (SD->isIndirect())
     746             :     MIB.addImm(0U);
     747             :   else
     748       23715 :     MIB.addReg(0U, RegState::Debug);
     749             : 
     750             :   MIB.addMetadata(Var);
     751             :   MIB.addMetadata(Expr);
     752             : 
     753       23730 :   return &*MIB;
     754             : }
     755             : 
     756             : MachineInstr *
     757           0 : InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
     758           0 :   MDNode *Label = SD->getLabel();
     759             :   DebugLoc DL = SD->getDebugLoc();
     760             :   assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
     761             :          "Expected inlined-at fields to agree");
     762             : 
     763           0 :   const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
     764           0 :   MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
     765             :   MIB.addMetadata(Label);
     766             : 
     767           0 :   return &*MIB;
     768             : }
     769             : 
     770             : /// EmitMachineNode - Generate machine code for a target-specific node and
     771             : /// needed dependencies.
     772             : ///
     773     3174750 : void InstrEmitter::
     774             : EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
     775             :                 DenseMap<SDValue, unsigned> &VRBaseMap) {
     776     3174750 :   unsigned Opc = Node->getMachineOpcode();
     777             : 
     778             :   // Handle subreg insert/extract specially
     779     6349500 :   if (Opc == TargetOpcode::EXTRACT_SUBREG ||
     780     3174750 :       Opc == TargetOpcode::INSERT_SUBREG ||
     781     3174750 :       Opc == TargetOpcode::SUBREG_TO_REG) {
     782      196441 :     EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
     783      196441 :     return;
     784             :   }
     785             : 
     786             :   // Handle COPY_TO_REGCLASS specially.
     787     2978309 :   if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
     788       38413 :     EmitCopyToRegClassNode(Node, VRBaseMap);
     789       38413 :     return;
     790             :   }
     791             : 
     792             :   // Handle REG_SEQUENCE specially.
     793     2939896 :   if (Opc == TargetOpcode::REG_SEQUENCE) {
     794       45992 :     EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
     795       45992 :     return;
     796             :   }
     797             : 
     798     2893904 :   if (Opc == TargetOpcode::IMPLICIT_DEF)
     799             :     // We want a unique VR for each IMPLICIT_DEF use.
     800             :     return;
     801             : 
     802     2868727 :   const MCInstrDesc &II = TII->get(Opc);
     803     2868727 :   unsigned NumResults = CountResults(Node);
     804     2868727 :   unsigned NumDefs = II.getNumDefs();
     805             :   const MCPhysReg *ScratchRegs = nullptr;
     806             : 
     807             :   // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
     808     2868727 :   if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
     809             :     // Stackmaps do not have arguments and do not preserve their calling
     810             :     // convention. However, to simplify runtime support, they clobber the same
     811             :     // scratch registers as AnyRegCC.
     812             :     unsigned CC = CallingConv::AnyReg;
     813         286 :     if (Opc == TargetOpcode::PATCHPOINT) {
     814         146 :       CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
     815             :       NumDefs = NumResults;
     816             :     }
     817         286 :     ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
     818             :   }
     819             : 
     820     2868727 :   unsigned NumImpUses = 0;
     821             :   unsigned NodeOperands =
     822     5737454 :     countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
     823     2868727 :   bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
     824             : #ifndef NDEBUG
     825             :   unsigned NumMIOperands = NodeOperands + NumResults;
     826             :   if (II.isVariadic())
     827             :     assert(NumMIOperands >= II.getNumOperands() &&
     828             :            "Too few operands for a variadic node!");
     829             :   else
     830             :     assert(NumMIOperands >= II.getNumOperands() &&
     831             :            NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
     832             :                             NumImpUses &&
     833             :            "#operands for dag node doesn't match .td file!");
     834             : #endif
     835             : 
     836             :   // Create the new machine instruction.
     837     5737454 :   MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
     838             : 
     839             :   // Add result register values for things that are defined by this
     840             :   // instruction.
     841     2868727 :   if (NumResults) {
     842     1966817 :     CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
     843             : 
     844             :     // Transfer any IR flags from the SDNode to the MachineInstr
     845     1966817 :     MachineInstr *MI = MIB.getInstr();
     846     1966817 :     const SDNodeFlags Flags = Node->getFlags();
     847     1966817 :     if (Flags.hasNoSignedZeros())
     848             :       MI->setFlag(MachineInstr::MIFlag::FmNsz);
     849             : 
     850     1966817 :     if (Flags.hasAllowReciprocal())
     851             :       MI->setFlag(MachineInstr::MIFlag::FmArcp);
     852             : 
     853     1966817 :     if (Flags.hasNoNaNs())
     854             :       MI->setFlag(MachineInstr::MIFlag::FmNoNans);
     855             : 
     856     1966817 :     if (Flags.hasNoInfs())
     857             :       MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
     858             : 
     859     1966817 :     if (Flags.hasAllowContract())
     860             :       MI->setFlag(MachineInstr::MIFlag::FmContract);
     861             : 
     862     1966817 :     if (Flags.hasApproximateFuncs())
     863             :       MI->setFlag(MachineInstr::MIFlag::FmAfn);
     864             : 
     865     1966817 :     if (Flags.hasAllowReassociation())
     866             :       MI->setFlag(MachineInstr::MIFlag::FmReassoc);
     867             :   }
     868             : 
     869             :   // Emit all of the actual operands of this instruction, adding them to the
     870             :   // instruction as appropriate.
     871             :   bool HasOptPRefs = NumDefs > NumResults;
     872             :   assert((!HasOptPRefs || !HasPhysRegOuts) &&
     873             :          "Unable to cope with optional defs and phys regs defs!");
     874     2868727 :   unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
     875    23182447 :   for (unsigned i = NumSkip; i != NodeOperands; ++i)
     876    20313720 :     AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
     877             :                VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
     878             : 
     879             :   // Add scratch registers as implicit def and early clobber
     880     2868727 :   if (ScratchRegs)
     881        1406 :     for (unsigned i = 0; ScratchRegs[i]; ++i)
     882         560 :       MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
     883         560 :                                  RegState::EarlyClobber);
     884             : 
     885             :   // Transfer all of the memory reference descriptions of this instruction.
     886             :   MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
     887     2868727 :                  cast<MachineSDNode>(Node)->memoperands_end());
     888             : 
     889             :   // Insert the instruction into position in the block. This needs to
     890             :   // happen before any custom inserter hook is called so that the
     891             :   // hook knows where in the block to insert the replacement code.
     892     2868727 :   MBB->insert(InsertPos, MIB);
     893             : 
     894             :   // The MachineInstr may also define physregs instead of virtregs.  These
     895             :   // physreg values can reach other instructions in different ways:
     896             :   //
     897             :   // 1. When there is a use of a Node value beyond the explicitly defined
     898             :   //    virtual registers, we emit a CopyFromReg for one of the implicitly
     899             :   //    defined physregs.  This only happens when HasPhysRegOuts is true.
     900             :   //
     901             :   // 2. A CopyFromReg reading a physreg may be glued to this instruction.
     902             :   //
     903             :   // 3. A glued instruction may implicitly use a physreg.
     904             :   //
     905             :   // 4. A glued instruction may use a RegisterSDNode operand.
     906             :   //
     907             :   // Collect all the used physreg defs, and make sure that any unused physreg
     908             :   // defs are marked as dead.
     909             :   SmallVector<unsigned, 8> UsedRegs;
     910             : 
     911             :   // Additional results must be physical register defs.
     912     2868727 :   if (HasPhysRegOuts) {
     913     2268591 :     for (unsigned i = NumDefs; i < NumResults; ++i) {
     914      756373 :       unsigned Reg = II.getImplicitDefs()[i - NumDefs];
     915      756373 :       if (!Node->hasAnyUseOfValue(i))
     916      619502 :         continue;
     917             :       // This implicitly defined physreg has a use.
     918      136871 :       UsedRegs.push_back(Reg);
     919      136871 :       EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
     920             :     }
     921             :   }
     922             : 
     923             :   // Scan the glue chain for any used physregs.
     924     5737454 :   if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
     925      928896 :     for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
     926      794942 :       if (F->getOpcode() == ISD::CopyFromReg) {
     927      203084 :         UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
     928      101542 :         continue;
     929      245158 :       } else if (F->getOpcode() == ISD::CopyToReg) {
     930             :         // Skip CopyToReg nodes that are internal to the glue chain.
     931        1262 :         continue;
     932             :       }
     933             :       // Collect declared implicit uses.
     934      487792 :       const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
     935      243896 :       UsedRegs.append(MCID.getImplicitUses(),
     936      487792 :                       MCID.getImplicitUses() + MCID.getNumImplicitUses());
     937             :       // In addition to declared implicit uses, we must also check for
     938             :       // direct RegisterSDNode operands.
     939     2638284 :       for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
     940     1075246 :         if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
     941       30166 :           unsigned Reg = R->getReg();
     942       30166 :           if (TargetRegisterInfo::isPhysicalRegister(Reg))
     943       11861 :             UsedRegs.push_back(Reg);
     944             :         }
     945             :     }
     946             :   }
     947             : 
     948             :   // Finally mark unused registers as dead.
     949     2868727 :   if (!UsedRegs.empty() || II.getImplicitDefs())
     950     1923730 :     MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
     951             : 
     952             :   // Run post-isel target hook to adjust this instruction if needed.
     953     5737454 :   if (II.hasPostISelHook())
     954       33576 :     TLI->AdjustInstrPostInstrSelection(*MIB, Node);
     955             : }
     956             : 
     957             : /// EmitSpecialNode - Generate machine code for a target-independent node and
     958             : /// needed dependencies.
     959     1725180 : void InstrEmitter::
     960             : EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
     961             :                 DenseMap<SDValue, unsigned> &VRBaseMap) {
     962     3450360 :   switch (Node->getOpcode()) {
     963           0 :   default:
     964             : #ifndef NDEBUG
     965             :     Node->dump();
     966             : #endif
     967           0 :     llvm_unreachable("This target-independent node should have been selected!");
     968           0 :   case ISD::EntryToken:
     969           0 :     llvm_unreachable("EntryToken should have been excluded from the schedule!");
     970             :   case ISD::MERGE_VALUES:
     971             :   case ISD::TokenFactor: // fall thru
     972             :     break;
     973      784695 :   case ISD::CopyToReg: {
     974             :     unsigned SrcReg;
     975      784695 :     SDValue SrcVal = Node->getOperand(2);
     976             :     if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
     977       65788 :       SrcReg = R->getReg();
     978             :     else
     979      718907 :       SrcReg = getVR(SrcVal, VRBaseMap);
     980             : 
     981     1569390 :     unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
     982      784695 :     if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
     983             :       break;
     984             : 
     985     1675515 :     BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
     986     1117010 :             DestReg).addReg(SrcReg);
     987      558505 :     break;
     988             :   }
     989      568329 :   case ISD::CopyFromReg: {
     990     1136658 :     unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
     991      568329 :     EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
     992      568329 :     break;
     993             :   }
     994       85359 :   case ISD::EH_LABEL:
     995             :   case ISD::ANNOTATION_LABEL: {
     996             :     unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
     997       85359 :                        ? TargetOpcode::EH_LABEL
     998             :                        : TargetOpcode::ANNOTATION_LABEL;
     999       85359 :     MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
    1000      170718 :     BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
    1001       85359 :             TII->get(Opc)).addSym(S);
    1002       85359 :     break;
    1003             :   }
    1004             : 
    1005       42790 :   case ISD::LIFETIME_START:
    1006             :   case ISD::LIFETIME_END: {
    1007       42790 :     unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
    1008             :     TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
    1009             : 
    1010       42790 :     FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
    1011      128370 :     BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
    1012       42790 :     .addFrameIndex(FI->getIndex());
    1013       42790 :     break;
    1014             :   }
    1015             : 
    1016       16384 :   case ISD::INLINEASM: {
    1017       16384 :     unsigned NumOps = Node->getNumOperands();
    1018       32768 :     if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
    1019             :       --NumOps;  // Ignore the glue operand.
    1020             : 
    1021             :     // Create the inline asm machine instruction.
    1022       16384 :     MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(),
    1023       32768 :                                       TII->get(TargetOpcode::INLINEASM));
    1024             : 
    1025             :     // Add the asm string as an external symbol operand.
    1026       16384 :     SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
    1027       16384 :     const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
    1028             :     MIB.addExternalSymbol(AsmStr);
    1029             : 
    1030             :     // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
    1031             :     // bits.
    1032             :     int64_t ExtraInfo =
    1033             :       cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
    1034       49152 :                           getZExtValue();
    1035             :     MIB.addImm(ExtraInfo);
    1036             : 
    1037             :     // Remember to operand index of the group flags.
    1038             :     SmallVector<unsigned, 8> GroupIdx;
    1039             : 
    1040             :     // Remember registers that are part of early-clobber defs.
    1041             :     SmallVector<unsigned, 8> ECRegs;
    1042             : 
    1043             :     // Add all of the operand registers to the instruction.
    1044       79808 :     for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
    1045             :       unsigned Flags =
    1046      190272 :         cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
    1047             :       const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
    1048             : 
    1049       63424 :       GroupIdx.push_back(MIB->getNumOperands());
    1050       63424 :       MIB.addImm(Flags);
    1051       63424 :       ++i;  // Skip the ID value.
    1052             : 
    1053             :       switch (InlineAsm::getKind(Flags)) {
    1054           0 :       default: llvm_unreachable("Bad flags!");
    1055             :         case InlineAsm::Kind_RegDef:
    1056       11117 :         for (unsigned j = 0; j != NumVals; ++j, ++i) {
    1057        7424 :           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
    1058             :           // FIXME: Add dead flags for physical and virtual registers defined.
    1059             :           // For now, mark physical register defs as implicit to help fast
    1060             :           // regalloc. This makes inline asm look a lot like calls.
    1061        3712 :           MIB.addReg(Reg, RegState::Define |
    1062        3712 :                   getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
    1063        3693 :         }
    1064             :         break;
    1065             :       case InlineAsm::Kind_RegDefEarlyClobber:
    1066             :       case InlineAsm::Kind_Clobber:
    1067      145965 :         for (unsigned j = 0; j != NumVals; ++j, ++i) {
    1068       97310 :           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
    1069       48655 :           MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
    1070       48655 :                   getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
    1071       48655 :           ECRegs.push_back(Reg);
    1072       48655 :         }
    1073             :         break;
    1074             :       case InlineAsm::Kind_RegUse:  // Use of register.
    1075             :       case InlineAsm::Kind_Imm:  // Immediate.
    1076             :       case InlineAsm::Kind_Mem:  // Addressing mode.
    1077             :         // The addressing mode has been selected, just add all of the
    1078             :         // operands to the machine instruction.
    1079       57038 :         for (unsigned j = 0; j != NumVals; ++j, ++i)
    1080       45962 :           AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
    1081       11076 :                      /*IsDebug=*/false, IsClone, IsCloned);
    1082             : 
    1083             :         // Manually set isTied bits.
    1084       11076 :         if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
    1085             :           unsigned DefGroup = 0;
    1086             :           if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
    1087         518 :             unsigned DefIdx = GroupIdx[DefGroup] + 1;
    1088         259 :             unsigned UseIdx = GroupIdx.back() + 1;
    1089         787 :             for (unsigned j = 0; j != NumVals; ++j)
    1090         264 :               MIB->tieOperands(DefIdx + j, UseIdx + j);
    1091             :           }
    1092             :         }
    1093             :         break;
    1094             :       }
    1095             :     }
    1096             : 
    1097             :     // GCC inline assembly allows input operands to also be early-clobber
    1098             :     // output operands (so long as the operand is written only after it's
    1099             :     // used), but this does not match the semantics of our early-clobber flag.
    1100             :     // If an early-clobber operand register is also an input operand register,
    1101             :     // then remove the early-clobber flag.
    1102      113694 :     for (unsigned Reg : ECRegs) {
    1103       97310 :       if (MIB->readsRegister(Reg, TRI)) {
    1104          42 :         MachineOperand *MO = MIB->findRegisterDefOperand(Reg, false, TRI);
    1105             :         assert(MO && "No def operand for clobbered register?");
    1106             :         MO->setIsEarlyClobber(false);
    1107             :       }
    1108             :     }
    1109             : 
    1110             :     // Get the mdnode from the asm if it exists and add it to the instruction.
    1111       16384 :     SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
    1112       16384 :     const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
    1113       16384 :     if (MD)
    1114             :       MIB.addMetadata(MD);
    1115             : 
    1116       16384 :     MBB->insert(InsertPos, MIB);
    1117             :     break;
    1118             :   }
    1119             :   }
    1120     1725180 : }
    1121             : 
    1122             : /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
    1123             : /// at the given position in the given block.
    1124      364532 : InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
    1125      364532 :                            MachineBasicBlock::iterator insertpos)
    1126      729064 :     : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
    1127      364532 :       TII(MF->getSubtarget().getInstrInfo()),
    1128      364532 :       TRI(MF->getSubtarget().getRegisterInfo()),
    1129      364532 :       TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
    1130     1822660 :       InsertPos(insertpos) {}

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