LCOV - code coverage report
Current view: top level - lib/CodeGen/SelectionDAG - InstrEmitter.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 480 500 96.0 %
Date: 2017-09-14 15:23:50 Functions: 16 16 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This implements the Emit routines for the SelectionDAG class, which creates
      11             : // MachineInstrs based on the decisions of the SelectionDAG instruction
      12             : // selection.
      13             : //
      14             : //===----------------------------------------------------------------------===//
      15             : 
      16             : #include "InstrEmitter.h"
      17             : #include "SDNodeDbgValue.h"
      18             : #include "llvm/ADT/Statistic.h"
      19             : #include "llvm/CodeGen/MachineConstantPool.h"
      20             : #include "llvm/CodeGen/MachineFunction.h"
      21             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      22             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      23             : #include "llvm/CodeGen/StackMaps.h"
      24             : #include "llvm/IR/DataLayout.h"
      25             : #include "llvm/IR/DebugInfo.h"
      26             : #include "llvm/Support/Debug.h"
      27             : #include "llvm/Support/ErrorHandling.h"
      28             : #include "llvm/Support/MathExtras.h"
      29             : #include "llvm/Target/TargetInstrInfo.h"
      30             : #include "llvm/Target/TargetLowering.h"
      31             : #include "llvm/Target/TargetSubtargetInfo.h"
      32             : using namespace llvm;
      33             : 
      34             : #define DEBUG_TYPE "instr-emitter"
      35             : 
      36             : /// MinRCSize - Smallest register class we allow when constraining virtual
      37             : /// registers.  If satisfying all register class constraints would require
      38             : /// using a smaller register class, emit a COPY to a new virtual register
      39             : /// instead.
      40             : const unsigned MinRCSize = 4;
      41             : 
      42             : /// CountResults - The results of target nodes have register or immediate
      43             : /// operands first, then an optional chain, and optional glue operands (which do
      44             : /// not go into the resulting MachineInstr).
      45     5265617 : unsigned InstrEmitter::CountResults(SDNode *Node) {
      46    10531234 :   unsigned N = Node->getNumValues();
      47    21570519 :   while (N && Node->getValueType(N - 1) == MVT::Glue)
      48     1444923 :     --N;
      49    15790827 :   if (N && Node->getValueType(N - 1) == MVT::Other)
      50     3131441 :     --N;    // Skip over chain result.
      51     5265617 :   return N;
      52             : }
      53             : 
      54             : /// countOperands - The inputs to target nodes have any actual inputs first,
      55             : /// followed by an optional chain operand, then an optional glue operand.
      56             : /// Compute the number of actual operands that will go into the resulting
      57             : /// MachineInstr.
      58             : ///
      59             : /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
      60             : /// the chain and glue. These operands may be implicit on the machine instr.
      61     2693017 : static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
      62             :                               unsigned &NumImpUses) {
      63     5386034 :   unsigned N = Node->getNumOperands();
      64    13711551 :   while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
      65      629686 :     --N;
      66    10563121 :   if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
      67     1704354 :     --N; // Ignore chain if it exists.
      68             : 
      69             :   // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
      70     2693017 :   NumImpUses = N - NumExpUses;
      71     2693017 :   for (unsigned I = N; I > NumExpUses; --I) {
      72     1985589 :     if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
      73      187904 :       continue;
      74     1421173 :     if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
      75      946510 :       if (TargetRegisterInfo::isPhysicalRegister(RN->getReg()))
      76      471143 :         continue;
      77        2816 :     NumImpUses = N - I;
      78        2816 :     break;
      79             :   }
      80             : 
      81     2693017 :   return N;
      82             : }
      83             : 
      84             : /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
      85             : /// implicit physical register output.
      86      556607 : void InstrEmitter::
      87             : EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
      88             :                 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
      89      556607 :   unsigned VRBase = 0;
      90     1113214 :   if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
      91             :     // Just use the input register directly!
      92      338587 :     SDValue Op(Node, ResNo);
      93      338587 :     if (IsClone)
      94           0 :       VRBaseMap.erase(Op);
      95     1015761 :     bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
      96             :     (void)isNew; // Silence compiler warning.
      97             :     assert(isNew && "Node emitted out of order - early");
      98             :     return;
      99             :   }
     100             : 
     101             :   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
     102             :   // the CopyToReg'd destination register instead of creating a new vreg.
     103      218020 :   bool MatchReg = true;
     104      218020 :   const TargetRegisterClass *UseRC = nullptr;
     105      218020 :   MVT VT = Node->getSimpleValueType(ResNo);
     106             : 
     107             :   // Stick to the preferred register classes for legal types.
     108      436040 :   if (TLI->isTypeLegal(VT))
     109      218020 :     UseRC = TLI->getRegClassFor(VT);
     110             : 
     111      218020 :   if (!IsClone && !IsCloned)
     112     1244667 :     for (SDNode *User : Node->uses()) {
     113      357599 :       bool Match = true;
     114      106938 :       if (User->getOpcode() == ISD::CopyToReg &&
     115      569792 :           User->getOperand(2).getNode() == Node &&
     116      210510 :           User->getOperand(2).getResNo() == ResNo) {
     117      312867 :         unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
     118      104289 :         if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
     119             :           VRBase = DestReg;
     120             :           Match = false;
     121       94199 :         } else if (DestReg != SrcReg)
     122        2278 :           Match = false;
     123             :       } else {
     124     3556490 :         for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
     125     2796560 :           SDValue Op = User->getOperand(i);
     126     2631660 :           if (Op.getNode() != Node || Op.getResNo() != ResNo)
     127     2466760 :             continue;
     128      329800 :           MVT VT = Node->getSimpleValueType(Op.getResNo());
     129      329800 :           if (VT == MVT::Other || VT == MVT::Glue)
     130           0 :             continue;
     131      164900 :           Match = false;
     132      164900 :           if (User->isMachineOpcode()) {
     133      494685 :             const MCInstrDesc &II = TII->get(User->getMachineOpcode());
     134      164895 :             const TargetRegisterClass *RC = nullptr;
     135      329790 :             if (i+II.getNumDefs() < II.getNumOperands()) {
     136      329678 :               RC = TRI->getAllocatableClass(
     137      164839 :                 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
     138             :             }
     139      164895 :             if (!UseRC)
     140             :               UseRC = RC;
     141      164895 :             else if (RC) {
     142             :               const TargetRegisterClass *ComRC =
     143      163692 :                 TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy);
     144             :               // If multiple uses expect disjoint register classes, we emit
     145             :               // copies in AddRegisterOperand.
     146      163692 :               if (ComRC)
     147      163538 :                 UseRC = ComRC;
     148             :             }
     149             :           }
     150             :         }
     151             :       }
     152      357599 :       MatchReg &= Match;
     153      357599 :       if (VRBase)
     154             :         break;
     155             :     }
     156             : 
     157      218020 :   const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
     158      218020 :   SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
     159             : 
     160             :   // Figure out the register class to create for the destreg.
     161      218020 :   if (VRBase) {
     162       20180 :     DstRC = MRI->getRegClass(VRBase);
     163      207930 :   } else if (UseRC) {
     164             :     assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
     165             :            "Incompatible phys register def and uses!");
     166             :     DstRC = UseRC;
     167             :   } else {
     168           0 :     DstRC = TLI->getRegClassFor(VT);
     169             :   }
     170             : 
     171             :   // If all uses are reading from the src physical register and copying the
     172             :   // register is either impossible or very expensive, then don't create a copy.
     173      353124 :   if (MatchReg && SrcRC->getCopyCost() < 0) {
     174             :     VRBase = SrcReg;
     175             :   } else {
     176             :     // Create the reg, emit the copy.
     177       94032 :     VRBase = MRI->createVirtualRegister(DstRC);
     178      282096 :     BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
     179      376128 :             VRBase).addReg(SrcReg);
     180             :   }
     181             : 
     182      218020 :   SDValue Op(Node, ResNo);
     183      218020 :   if (IsClone)
     184       19106 :     VRBaseMap.erase(Op);
     185      654060 :   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
     186             :   (void)isNew; // Silence compiler warning.
     187             :   assert(isNew && "Node emitted out of order - early");
     188             : }
     189             : 
     190             : /// getDstOfCopyToRegUse - If the only use of the specified result number of
     191             : /// node is a CopyToReg, return its destination register. Return 0 otherwise.
     192       30951 : unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
     193             :                                                 unsigned ResNo) const {
     194       15016 :   if (!Node->hasOneUse())
     195             :     return 0;
     196             : 
     197       45048 :   SDNode *User = *Node->use_begin();
     198         909 :   if (User->getOpcode() == ISD::CopyToReg &&
     199       16834 :       User->getOperand(2).getNode() == Node &&
     200        1818 :       User->getOperand(2).getResNo() == ResNo) {
     201        2727 :     unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
     202         909 :     if (TargetRegisterInfo::isVirtualRegister(Reg))
     203             :       return Reg;
     204             :   }
     205             :   return 0;
     206             : }
     207             : 
     208     1826044 : void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
     209             :                                        MachineInstrBuilder &MIB,
     210             :                                        const MCInstrDesc &II,
     211             :                                        bool IsClone, bool IsCloned,
     212             :                                        DenseMap<SDValue, unsigned> &VRBaseMap) {
     213             :   assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
     214             :          "IMPLICIT_DEF should have been handled as a special case elsewhere!");
     215             : 
     216     1826044 :   unsigned NumResults = CountResults(Node);
     217     6133308 :   for (unsigned i = 0; i < II.getNumDefs(); ++i) {
     218             :     // If the specific node value is only used by a CopyToReg and the dest reg
     219             :     // is a vreg in the same register class, use the CopyToReg'd destination
     220             :     // register instead of creating a new vreg.
     221     1240610 :     unsigned VRBase = 0;
     222             :     const TargetRegisterClass *RC =
     223     1240610 :       TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
     224             :     // Always let the value type influence the used register class. The
     225             :     // constraints on the instruction may be too lax to represent the value
     226             :     // type correctly. For example, a 64-bit float (X86::FR64) can't live in
     227             :     // the 32-bit float super-class (X86::FR32).
     228     4951770 :     if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
     229             :       const TargetRegisterClass *VTRC =
     230     2468328 :         TLI->getRegClassFor(Node->getSimpleValueType(i));
     231     1234164 :       if (RC)
     232     1231836 :         VTRC = TRI->getCommonSubClass(RC, VTRC);
     233     1234164 :       if (VTRC)
     234     1188844 :         RC = VTRC;
     235             :     }
     236             : 
     237     1240610 :     if (II.OpInfo[i].isOptionalDef()) {
     238             :       // Optional def must be a physical register.
     239        6336 :       VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
     240             :       assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
     241        2112 :       MIB.addReg(VRBase, RegState::Define);
     242             :     }
     243             : 
     244        2112 :     if (!VRBase && !IsClone && !IsCloned)
     245     7259164 :       for (SDNode *User : Node->uses()) {
     246      416473 :         if (User->getOpcode() == ISD::CopyToReg &&
     247     2644190 :             User->getOperand(2).getNode() == Node &&
     248      822780 :             User->getOperand(2).getResNo() == i) {
     249     1165611 :           unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
     250      388537 :           if (TargetRegisterInfo::isVirtualRegister(Reg)) {
     251      111752 :             const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
     252       55876 :             if (RegRC == RC) {
     253       51919 :               VRBase = Reg;
     254       51919 :               MIB.addReg(VRBase, RegState::Define);
     255       51919 :               break;
     256             :             }
     257             :           }
     258             :         }
     259             :       }
     260             : 
     261             :     // Create the result registers for this node and add the result regs to
     262             :     // the machine instruction.
     263     1240610 :     if (VRBase == 0) {
     264             :       assert(RC && "Isn't a register operand!");
     265     1186579 :       VRBase = MRI->createVirtualRegister(RC);
     266     1186579 :       MIB.addReg(VRBase, RegState::Define);
     267             :     }
     268             : 
     269             :     // If this def corresponds to a result of the SDNode insert the VRBase into
     270             :     // the lookup map.
     271     1240610 :     if (i < NumResults) {
     272     1238498 :       SDValue Op(Node, i);
     273     1238498 :       if (IsClone)
     274        6184 :         VRBaseMap.erase(Op);
     275     3715494 :       bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
     276             :       (void)isNew; // Silence compiler warning.
     277             :       assert(isNew && "Node emitted out of order - early");
     278             :     }
     279             :   }
     280     1826044 : }
     281             : 
     282             : /// getVR - Return the virtual register corresponding to the specified result
     283             : /// of the specified node.
     284     2813019 : unsigned InstrEmitter::getVR(SDValue Op,
     285             :                              DenseMap<SDValue, unsigned> &VRBaseMap) {
     286     7812927 :   if (Op.isMachineOpcode() &&
     287     2186889 :       Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
     288             :     // Add an IMPLICIT_DEF instruction before every use.
     289       30951 :     unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
     290             :     // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
     291             :     // does not include operand register class info.
     292       30951 :     if (!VReg) {
     293             :       const TargetRegisterClass *RC =
     294       61102 :         TLI->getRegClassFor(Op.getSimpleValueType());
     295       30551 :       VReg = MRI->createVirtualRegister(RC);
     296             :     }
     297       30951 :     BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
     298       61902 :             TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
     299       30951 :     return VReg;
     300             :   }
     301             : 
     302     2782068 :   DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
     303             :   assert(I != VRBaseMap.end() && "Node emitted out of order - late");
     304     2782068 :   return I->second;
     305             : }
     306             : 
     307             : 
     308             : /// AddRegisterOperand - Add the specified register as an operand to the
     309             : /// specified machine instr. Insert register copies if the register is
     310             : /// not in the required register class.
     311             : void
     312     1877456 : InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
     313             :                                  SDValue Op,
     314             :                                  unsigned IIOpNum,
     315             :                                  const MCInstrDesc *II,
     316             :                                  DenseMap<SDValue, unsigned> &VRBaseMap,
     317             :                                  bool IsDebug, bool IsClone, bool IsCloned) {
     318             :   assert(Op.getValueType() != MVT::Other &&
     319             :          Op.getValueType() != MVT::Glue &&
     320             :          "Chain and glue operands should occur at end of operand list!");
     321             :   // Get/emit the operand.
     322     1877456 :   unsigned VReg = getVR(Op, VRBaseMap);
     323             : 
     324     1877456 :   const MCInstrDesc &MCID = MIB->getDesc();
     325     3606054 :   bool isOptDef = IIOpNum < MCID.getNumOperands() &&
     326     3606054 :     MCID.OpInfo[IIOpNum].isOptionalDef();
     327             : 
     328             :   // If the instruction requires a register in a different class, create
     329             :   // a new virtual register and copy the value into it, but first attempt to
     330             :   // shrink VReg's register class within reason.  For example, if VReg == GR32
     331             :   // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
     332     1877456 :   if (II) {
     333     1817486 :     const TargetRegisterClass *OpRC = nullptr;
     334     3634972 :     if (IIOpNum < II->getNumOperands())
     335     1668853 :       OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
     336             : 
     337     1668853 :     if (OpRC) {
     338             :       const TargetRegisterClass *ConstrainedRC
     339     1666376 :         = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
     340     1666376 :       if (!ConstrainedRC) {
     341       48645 :         OpRC = TRI->getAllocatableClass(OpRC);
     342             :         assert(OpRC && "Constraints cannot be fulfilled for allocation");
     343       48645 :         unsigned NewVReg = MRI->createVirtualRegister(OpRC);
     344       97290 :         BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
     345      194580 :                 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
     346       48645 :         VReg = NewVReg;
     347             :       } else {
     348             :         assert(ConstrainedRC->isAllocatable() &&
     349             :            "Constraining an allocatable VReg produced an unallocatable class?");
     350             :       }
     351             :     }
     352             :   }
     353             : 
     354             :   // If this value has only one use, that use is a kill. This is a
     355             :   // conservative approximation. InstrEmitter does trivial coalescing
     356             :   // with CopyFromReg nodes, so don't emit kill flags for them.
     357             :   // Avoid kill flags on Schedule cloned nodes, since there will be
     358             :   // multiple uses.
     359             :   // Tied operands are never killed, so we need to check that. And that
     360             :   // means we need to determine the index of the operand.
     361     3015315 :   bool isKill = Op.hasOneUse() &&
     362     2041645 :                 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
     363     2778661 :                 !IsDebug &&
     364      885065 :                 !(IsClone || IsCloned);
     365             :   if (isKill) {
     366      885065 :     unsigned Idx = MIB->getNumOperands();
     367     1055821 :     while (Idx > 0 &&
     368     4140808 :            MIB->getOperand(Idx-1).isReg() &&
     369     1826008 :            MIB->getOperand(Idx-1).isImplicit())
     370             :       --Idx;
     371     1015288 :     bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
     372             :     if (isTied)
     373      130223 :       isKill = false;
     374             :   }
     375             : 
     376     5632368 :   MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
     377     1877456 :              getDebugRegState(IsDebug));
     378     1877456 : }
     379             : 
     380             : /// AddOperand - Add the specified operand to the specified machine instr.  II
     381             : /// specifies the instruction information for the node, and IIOpNum is the
     382             : /// operand number (in the II) that we are adding.
     383    10202432 : void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
     384             :                               SDValue Op,
     385             :                               unsigned IIOpNum,
     386             :                               const MCInstrDesc *II,
     387             :                               DenseMap<SDValue, unsigned> &VRBaseMap,
     388             :                               bool IsDebug, bool IsClone, bool IsCloned) {
     389    20404864 :   if (Op.isMachineOpcode()) {
     390     1371269 :     AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
     391             :                        IsDebug, IsClone, IsCloned);
     392     4032137 :   } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
     393     4032137 :     MIB.addImm(C->getSExtValue());
     394         116 :   } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
     395         116 :     MIB.addFPImm(F->getConstantFPValue());
     396     3028465 :   } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
     397             :     // Turn additional physreg operands into implicit uses on non-variadic
     398             :     // instructions. This is used by call and return instructions passing
     399             :     // arguments in registers.
     400     6526515 :     bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
     401     3028465 :     MIB.addReg(R->getReg(), getImplRegState(Imp));
     402      187918 :   } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
     403      187918 :     MIB.addRegMask(RM->getRegMask());
     404      767426 :   } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
     405             :     MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
     406      767426 :                          TGA->getTargetFlags());
     407      134721 :   } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
     408      134721 :     MIB.addMBB(BBNode->getBasicBlock());
     409      143988 :   } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
     410      143988 :     MIB.addFrameIndex(FI->getIndex());
     411         285 :   } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
     412         285 :     MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
     413       20185 :   } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
     414       20185 :     int Offset = CP->getOffset();
     415       20185 :     unsigned Align = CP->getAlignment();
     416       20185 :     Type *Type = CP->getType();
     417             :     // MachineConstantPool wants an explicit alignment.
     418       20185 :     if (Align == 0) {
     419           0 :       Align = MF->getDataLayout().getPrefTypeAlignment(Type);
     420           0 :       if (Align == 0) {
     421             :         // Alignment of vector types.  FIXME!
     422           0 :         Align = MF->getDataLayout().getTypeAllocSize(Type);
     423             :       }
     424             :     }
     425             : 
     426             :     unsigned Idx;
     427       20185 :     MachineConstantPool *MCP = MF->getConstantPool();
     428       20185 :     if (CP->isMachineConstantPoolEntry())
     429         340 :       Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
     430             :     else
     431       19845 :       Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
     432       20185 :     MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
     433        9555 :   } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
     434        9555 :     MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
     435          52 :   } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
     436          52 :     MIB.addSym(SymNode->getMCSymbol());
     437         128 :   } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
     438             :     MIB.addBlockAddress(BA->getBlockAddress(),
     439             :                         BA->getOffset(),
     440         128 :                         BA->getTargetFlags());
     441           0 :   } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
     442           0 :     MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
     443             :   } else {
     444             :     assert(Op.getValueType() != MVT::Other &&
     445             :            Op.getValueType() != MVT::Glue &&
     446             :            "Chain and glue operands should occur at end of operand list!");
     447      506187 :     AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
     448             :                        IsDebug, IsClone, IsCloned);
     449             :   }
     450    10202432 : }
     451             : 
     452      128785 : unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
     453             :                                           MVT VT, const DebugLoc &DL) {
     454      257570 :   const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
     455      128785 :   const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
     456             : 
     457             :   // RC is a sub-class of VRC that supports SubIdx.  Try to constrain VReg
     458             :   // within reason.
     459      128785 :   if (RC && RC != VRC)
     460        1535 :     RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
     461             : 
     462             :   // VReg has been adjusted.  It can be used with SubIdx operands now.
     463      128785 :   if (RC)
     464             :     return VReg;
     465             : 
     466             :   // VReg couldn't be reasonably constrained.  Emit a COPY to a new virtual
     467             :   // register instead.
     468           0 :   RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
     469             :   assert(RC && "No legal register class for VT supports that SubIdx");
     470           0 :   unsigned NewReg = MRI->createVirtualRegister(RC);
     471           0 :   BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
     472           0 :     .addReg(VReg);
     473           0 :   return NewReg;
     474             : }
     475             : 
     476             : /// EmitSubregNode - Generate machine code for subreg nodes.
     477             : ///
     478      171016 : void InstrEmitter::EmitSubregNode(SDNode *Node,
     479             :                                   DenseMap<SDValue, unsigned> &VRBaseMap,
     480             :                                   bool IsClone, bool IsCloned) {
     481      171016 :   unsigned VRBase = 0;
     482      342032 :   unsigned Opc = Node->getMachineOpcode();
     483             : 
     484             :   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
     485             :   // the CopyToReg'd destination register instead of creating a new vreg.
     486      912041 :   for (SDNode *User : Node->uses()) {
     487      235310 :     if (User->getOpcode() == ISD::CopyToReg &&
     488       58966 :         User->getOperand(2).getNode() == Node) {
     489       88437 :       unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
     490       29479 :       if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
     491             :         VRBase = DestReg;
     492             :         break;
     493             :       }
     494             :     }
     495             :   }
     496             : 
     497      171016 :   if (Opc == TargetOpcode::EXTRACT_SUBREG) {
     498             :     // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub.  There are no
     499             :     // constraints on the %dst register, COPY can target all legal register
     500             :     // classes.
     501      515272 :     unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
     502             :     const TargetRegisterClass *TRC =
     503      257636 :       TLI->getRegClassFor(Node->getSimpleValueType(0));
     504             : 
     505             :     unsigned Reg;
     506             :     MachineInstr *DefMI;
     507      257653 :     RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
     508          34 :     if (R && TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
     509             :       Reg = R->getReg();
     510             :       DefMI = nullptr;
     511             :     } else {
     512      257602 :       Reg = getVR(Node->getOperand(0), VRBaseMap);
     513      128801 :       DefMI = MRI->getVRegDef(Reg);
     514             :     }
     515             : 
     516             :     unsigned SrcReg, DstReg, DefSubIdx;
     517      112047 :     if (DefMI &&
     518      112087 :         TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
     519      128857 :         SubIdx == DefSubIdx &&
     520          32 :         TRC == MRI->getRegClass(SrcReg)) {
     521             :       // Optimize these:
     522             :       // r1025 = s/zext r1024, 4
     523             :       // r1026 = extract_subreg r1025, 4
     524             :       // to a copy
     525             :       // r1026 = copy r1024
     526          16 :       VRBase = MRI->createVirtualRegister(TRC);
     527          32 :       BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
     528          64 :               TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
     529          16 :       MRI->clearKillFlags(SrcReg);
     530             :     } else {
     531             :       // Reg may not support a SubIdx sub-register, and we may need to
     532             :       // constrain its register class or issue a COPY to a compatible register
     533             :       // class.
     534      128802 :       if (TargetRegisterInfo::isVirtualRegister(Reg))
     535      257570 :         Reg = ConstrainForSubReg(Reg, SubIdx,
     536      257570 :                                  Node->getOperand(0).getSimpleValueType(),
     537             :                                  Node->getDebugLoc());
     538             : 
     539             :       // Create the destreg if it is missing.
     540      128802 :       if (VRBase == 0)
     541      118725 :         VRBase = MRI->createVirtualRegister(TRC);
     542             : 
     543             :       // Create the extract_subreg machine instruction.
     544             :       MachineInstrBuilder CopyMI =
     545      128802 :           BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
     546      515208 :                   TII->get(TargetOpcode::COPY), VRBase);
     547      128802 :       if (TargetRegisterInfo::isVirtualRegister(Reg))
     548      128785 :         CopyMI.addReg(Reg, 0, SubIdx);
     549             :       else
     550          17 :         CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
     551             :     }
     552       84396 :   } else if (Opc == TargetOpcode::INSERT_SUBREG ||
     553       42198 :              Opc == TargetOpcode::SUBREG_TO_REG) {
     554       84396 :     SDValue N0 = Node->getOperand(0);
     555       84396 :     SDValue N1 = Node->getOperand(1);
     556       84396 :     SDValue N2 = Node->getOperand(2);
     557       84396 :     unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
     558             : 
     559             :     // Figure out the register class to create for the destreg.  It should be
     560             :     // the largest legal register class supporting SubIdx sub-registers.
     561             :     // RegisterCoalescer will constrain it further if it decides to eliminate
     562             :     // the INSERT_SUBREG instruction.
     563             :     //
     564             :     //   %dst = INSERT_SUBREG %src, %sub, SubIdx
     565             :     //
     566             :     // is lowered by TwoAddressInstructionPass to:
     567             :     //
     568             :     //   %dst = COPY %src
     569             :     //   %dst:SubIdx = COPY %sub
     570             :     //
     571             :     // There is no constraint on the %src register class.
     572             :     //
     573       84396 :     const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0));
     574       42198 :     SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
     575             :     assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
     576             : 
     577       47366 :     if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
     578       39618 :       VRBase = MRI->createVirtualRegister(SRC);
     579             : 
     580             :     // Create the insert_subreg or subreg_to_reg machine instruction.
     581             :     MachineInstrBuilder MIB =
     582      126594 :       BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
     583             : 
     584             :     // If creating a subreg_to_reg, then the first input operand
     585             :     // is an implicit value immediate, otherwise it's a register
     586       42198 :     if (Opc == TargetOpcode::SUBREG_TO_REG) {
     587       24651 :       const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
     588       24651 :       MIB.addImm(SD->getZExtValue());
     589             :     } else
     590       17547 :       AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
     591             :                  IsClone, IsCloned);
     592             :     // Add the subregister being inserted
     593       42198 :     AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
     594             :                IsClone, IsCloned);
     595       84396 :     MIB.addImm(SubIdx);
     596       84396 :     MBB->insert(InsertPos, MIB);
     597             :   } else
     598           0 :     llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
     599             : 
     600      171016 :   SDValue Op(Node, 0);
     601      513048 :   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
     602             :   (void)isNew; // Silence compiler warning.
     603             :   assert(isNew && "Node emitted out of order - early");
     604      171016 : }
     605             : 
     606             : /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
     607             : /// COPY_TO_REGCLASS is just a normal copy, except that the destination
     608             : /// register is constrained to be in a particular register class.
     609             : ///
     610             : void
     611       34334 : InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
     612             :                                      DenseMap<SDValue, unsigned> &VRBaseMap) {
     613       68668 :   unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
     614             : 
     615             :   // Create the new VReg in the destination class and emit a copy.
     616      137336 :   unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
     617             :   const TargetRegisterClass *DstRC =
     618       68668 :     TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
     619       34334 :   unsigned NewVReg = MRI->createVirtualRegister(DstRC);
     620      103002 :   BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
     621      137336 :     NewVReg).addReg(VReg);
     622             : 
     623       34334 :   SDValue Op(Node, 0);
     624      103002 :   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
     625             :   (void)isNew; // Silence compiler warning.
     626             :   assert(isNew && "Node emitted out of order - early");
     627       34334 : }
     628             : 
     629             : /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
     630             : ///
     631       48550 : void InstrEmitter::EmitRegSequence(SDNode *Node,
     632             :                                   DenseMap<SDValue, unsigned> &VRBaseMap,
     633             :                                   bool IsClone, bool IsCloned) {
     634      194200 :   unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
     635       97100 :   const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
     636       48550 :   unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
     637       97100 :   const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
     638       97100 :   MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
     639       97100 :   unsigned NumOps = Node->getNumOperands();
     640             :   assert((NumOps & 1) == 1 &&
     641             :          "REG_SEQUENCE must have an odd number of operands!");
     642      326632 :   for (unsigned i = 1; i != NumOps; ++i) {
     643      556164 :     SDValue Op = Node->getOperand(i);
     644      278082 :     if ((i & 1) == 0) {
     645      279357 :       RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
     646             :       // Skip physical registers as they don't have a vreg to get and we'll
     647             :       // insert copies for them in TwoAddressInstructionPass anyway.
     648        2550 :       if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
     649      275532 :         unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
     650      275532 :         unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
     651      275532 :         const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
     652             :         const TargetRegisterClass *SRC =
     653      137766 :         TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
     654      137766 :         if (SRC && SRC != RC) {
     655        2900 :           MRI->setRegClass(NewVReg, SRC);
     656        2900 :           RC = SRC;
     657             :         }
     658             :       }
     659             :     }
     660      278082 :     AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
     661             :                IsClone, IsCloned);
     662             :   }
     663             : 
     664       97100 :   MBB->insert(InsertPos, MIB);
     665       48550 :   SDValue Op(Node, 0);
     666      145650 :   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
     667             :   (void)isNew; // Silence compiler warning.
     668             :   assert(isNew && "Node emitted out of order - early");
     669       48550 : }
     670             : 
     671             : /// EmitDbgValue - Generate machine instruction for a dbg_value node.
     672             : ///
     673             : MachineInstr *
     674       16075 : InstrEmitter::EmitDbgValue(SDDbgValue *SD,
     675             :                            DenseMap<SDValue, unsigned> &VRBaseMap) {
     676       16075 :   MDNode *Var = SD->getVariable();
     677       16075 :   MDNode *Expr = SD->getExpression();
     678       32150 :   DebugLoc DL = SD->getDebugLoc();
     679             :   assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
     680             :          "Expected inlined-at fields to agree");
     681             : 
     682       16075 :   if (SD->getKind() == SDDbgValue::FRAMEIX) {
     683             :     // Stack address; this needs to be lowered in target-dependent fashion.
     684             :     // EmitTargetCodeForFrameDebugValue is responsible for allocation.
     685        1752 :     return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
     686        1168 :         .addFrameIndex(SD->getFrameIx())
     687         584 :         .addImm(0)
     688         584 :         .addMetadata(Var)
     689         584 :         .addMetadata(Expr);
     690             :   }
     691             :   // Otherwise, we're going to create an instruction here.
     692       30982 :   const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
     693       30982 :   MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
     694       15491 :   if (SD->getKind() == SDDbgValue::SDNODE) {
     695        9613 :     SDNode *Node = SD->getSDNode();
     696       19226 :     SDValue Op = SDValue(Node, SD->getResNo());
     697             :     // It's possible we replaced this SDNode with other(s) and therefore
     698             :     // didn't generate code for it.  It's better to catch these cases where
     699             :     // they happen and transfer the debug info, but trying to guarantee that
     700             :     // in all cases would be very fragile; this is a safeguard for any
     701             :     // that were missed.
     702        9613 :     DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
     703       19226 :     if (I==VRBaseMap.end())
     704           4 :       MIB.addReg(0U);       // undef
     705             :     else
     706        9609 :       AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
     707             :                  /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
     708        5878 :   } else if (SD->getKind() == SDDbgValue::CONST) {
     709        5878 :     const Value *V = SD->getConst();
     710        1483 :     if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
     711        1483 :       if (CI->getBitWidth() > 64)
     712             :         MIB.addCImm(CI);
     713             :       else
     714        1482 :         MIB.addImm(CI->getSExtValue());
     715          17 :     } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
     716             :       MIB.addFPImm(CF);
     717             :     } else {
     718             :       // Could be an Undef.  In any case insert an Undef so we can see what we
     719             :       // dropped.
     720        4378 :       MIB.addReg(0U);
     721             :     }
     722             :   } else {
     723             :     // Insert an Undef so we can see what we dropped.
     724           0 :     MIB.addReg(0U);
     725             :   }
     726             : 
     727             :   // Indirect addressing is indicated by an Imm as the second parameter.
     728       15491 :   if (SD->isIndirect())
     729             :     MIB.addImm(0U);
     730             :   else
     731       15478 :     MIB.addReg(0U, RegState::Debug);
     732             : 
     733       15491 :   MIB.addMetadata(Var);
     734       15491 :   MIB.addMetadata(Expr);
     735             : 
     736       15491 :   return &*MIB;
     737             : }
     738             : 
     739             : /// EmitMachineNode - Generate machine code for a target-specific node and
     740             : /// needed dependencies.
     741             : ///
     742     2965846 : void InstrEmitter::
     743             : EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
     744             :                 DenseMap<SDValue, unsigned> &VRBaseMap) {
     745     5931692 :   unsigned Opc = Node->getMachineOpcode();
     746             : 
     747             :   // Handle subreg insert/extract specially
     748     5931692 :   if (Opc == TargetOpcode::EXTRACT_SUBREG ||
     749     2965846 :       Opc == TargetOpcode::INSERT_SUBREG ||
     750     2965846 :       Opc == TargetOpcode::SUBREG_TO_REG) {
     751      171016 :     EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
     752      171016 :     return;
     753             :   }
     754             : 
     755             :   // Handle COPY_TO_REGCLASS specially.
     756     2794830 :   if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
     757       34334 :     EmitCopyToRegClassNode(Node, VRBaseMap);
     758       34334 :     return;
     759             :   }
     760             : 
     761             :   // Handle REG_SEQUENCE specially.
     762     2760496 :   if (Opc == TargetOpcode::REG_SEQUENCE) {
     763       48550 :     EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
     764       48550 :     return;
     765             :   }
     766             : 
     767     2711946 :   if (Opc == TargetOpcode::IMPLICIT_DEF)
     768             :     // We want a unique VR for each IMPLICIT_DEF use.
     769             :     return;
     770             : 
     771     5386034 :   const MCInstrDesc &II = TII->get(Opc);
     772     2693017 :   unsigned NumResults = CountResults(Node);
     773     2693017 :   unsigned NumDefs = II.getNumDefs();
     774     2693017 :   const MCPhysReg *ScratchRegs = nullptr;
     775             : 
     776             :   // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
     777     2693017 :   if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
     778             :     // Stackmaps do not have arguments and do not preserve their calling
     779             :     // convention. However, to simplify runtime support, they clobber the same
     780             :     // scratch registers as AnyRegCC.
     781         228 :     unsigned CC = CallingConv::AnyReg;
     782         228 :     if (Opc == TargetOpcode::PATCHPOINT) {
     783         116 :       CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
     784         116 :       NumDefs = NumResults;
     785             :     }
     786         228 :     ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
     787             :   }
     788             : 
     789     2693017 :   unsigned NumImpUses = 0;
     790             :   unsigned NodeOperands =
     791     2693017 :     countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
     792     2693017 :   bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
     793             : #ifndef NDEBUG
     794             :   unsigned NumMIOperands = NodeOperands + NumResults;
     795             :   if (II.isVariadic())
     796             :     assert(NumMIOperands >= II.getNumOperands() &&
     797             :            "Too few operands for a variadic node!");
     798             :   else
     799             :     assert(NumMIOperands >= II.getNumOperands() &&
     800             :            NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
     801             :                             NumImpUses &&
     802             :            "#operands for dag node doesn't match .td file!");
     803             : #endif
     804             : 
     805             :   // Create the new machine instruction.
     806     5386034 :   MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
     807             : 
     808             :   // Add result register values for things that are defined by this
     809             :   // instruction.
     810     2693017 :   if (NumResults)
     811     1826044 :     CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
     812             : 
     813             :   // Emit all of the actual operands of this instruction, adding them to the
     814             :   // instruction as appropriate.
     815     2693017 :   bool HasOptPRefs = NumDefs > NumResults;
     816             :   assert((!HasOptPRefs || !HasPhysRegOuts) &&
     817             :          "Unable to cope with optional defs and phys regs defs!");
     818     2693017 :   unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
     819    12543915 :   for (unsigned i = NumSkip; i != NodeOperands; ++i)
     820    19701796 :     AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
     821             :                VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
     822             : 
     823             :   // Add scratch registers as implicit def and early clobber
     824     2693017 :   if (ScratchRegs)
     825        1004 :     for (unsigned i = 0; ScratchRegs[i]; ++i)
     826         388 :       MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
     827         388 :                                  RegState::EarlyClobber);
     828             : 
     829             :   // Transfer all of the memory reference descriptions of this instruction.
     830     2693017 :   MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
     831     5386034 :                  cast<MachineSDNode>(Node)->memoperands_end());
     832             : 
     833             :   // Insert the instruction into position in the block. This needs to
     834             :   // happen before any custom inserter hook is called so that the
     835             :   // hook knows where in the block to insert the replacement code.
     836     5386034 :   MBB->insert(InsertPos, MIB);
     837             : 
     838             :   // The MachineInstr may also define physregs instead of virtregs.  These
     839             :   // physreg values can reach other instructions in different ways:
     840             :   //
     841             :   // 1. When there is a use of a Node value beyond the explicitly defined
     842             :   //    virtual registers, we emit a CopyFromReg for one of the implicitly
     843             :   //    defined physregs.  This only happens when HasPhysRegOuts is true.
     844             :   //
     845             :   // 2. A CopyFromReg reading a physreg may be glued to this instruction.
     846             :   //
     847             :   // 3. A glued instruction may implicitly use a physreg.
     848             :   //
     849             :   // 4. A glued instruction may use a RegisterSDNode operand.
     850             :   //
     851             :   // Collect all the used physreg defs, and make sure that any unused physreg
     852             :   // defs are marked as dead.
     853     5386034 :   SmallVector<unsigned, 8> UsedRegs;
     854             : 
     855             :   // Additional results must be physical register defs.
     856     2693017 :   if (HasPhysRegOuts) {
     857     2167825 :     for (unsigned i = NumDefs; i < NumResults; ++i) {
     858      722684 :       unsigned Reg = II.getImplicitDefs()[i - NumDefs];
     859      722684 :       if (!Node->hasAnyUseOfValue(i))
     860      598795 :         continue;
     861             :       // This implicitly defined physreg has a use.
     862      123889 :       UsedRegs.push_back(Reg);
     863      123889 :       EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
     864             :     }
     865             :   }
     866             : 
     867             :   // Scan the glue chain for any used physregs.
     868    10156989 :   if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
     869      932066 :     for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
     870      694876 :       if (F->getOpcode() == ISD::CopyFromReg) {
     871      182706 :         UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
     872       60902 :         continue;
     873      256085 :       } else if (F->getOpcode() == ISD::CopyToReg) {
     874             :         // Skip CopyToReg nodes that are internal to the glue chain.
     875         303 :         continue;
     876             :       }
     877             :       // Collect declared implicit uses.
     878      767346 :       const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
     879      255782 :       UsedRegs.append(MCID.getImplicitUses(),
     880      255782 :                       MCID.getImplicitUses() + MCID.getNumImplicitUses());
     881             :       // In addition to declared implicit uses, we must also check for
     882             :       // direct RegisterSDNode operands.
     883     1636782 :       for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
     884     2278682 :         if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
     885       28246 :           unsigned Reg = R->getReg();
     886       56492 :           if (TargetRegisterInfo::isPhysicalRegister(Reg))
     887       12754 :             UsedRegs.push_back(Reg);
     888             :         }
     889             :     }
     890             :   }
     891             : 
     892             :   // Finally mark unused registers as dead.
     893     2693017 :   if (!UsedRegs.empty() || II.getImplicitDefs())
     894     1883634 :     MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
     895             : 
     896             :   // Run post-isel target hook to adjust this instruction if needed.
     897     2693017 :   if (II.hasPostISelHook())
     898       30463 :     TLI->AdjustInstrPostInstrSelection(*MIB, Node);
     899             : }
     900             : 
     901             : /// EmitSpecialNode - Generate machine code for a target-independent node and
     902             : /// needed dependencies.
     903     1470625 : void InstrEmitter::
     904             : EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
     905             :                 DenseMap<SDValue, unsigned> &VRBaseMap) {
     906     2941250 :   switch (Node->getOpcode()) {
     907           0 :   default:
     908             : #ifndef NDEBUG
     909             :     Node->dump();
     910             : #endif
     911           0 :     llvm_unreachable("This target-independent node should have been selected!");
     912           0 :   case ISD::EntryToken:
     913           0 :     llvm_unreachable("EntryToken should have been excluded from the schedule!");
     914             :   case ISD::MERGE_VALUES:
     915             :   case ISD::TokenFactor: // fall thru
     916             :     break;
     917      717313 :   case ISD::CopyToReg: {
     918             :     unsigned SrcReg;
     919     1434626 :     SDValue SrcVal = Node->getOperand(2);
     920       82651 :     if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
     921       82651 :       SrcReg = R->getReg();
     922             :     else
     923      634662 :       SrcReg = getVR(SrcVal, VRBaseMap);
     924             : 
     925     2151939 :     unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
     926      717313 :     if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
     927             :       break;
     928             : 
     929     1581660 :     BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
     930     2108880 :             DestReg).addReg(SrcReg);
     931      527220 :     break;
     932             :   }
     933      432718 :   case ISD::CopyFromReg: {
     934     1298154 :     unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
     935      432718 :     EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
     936      432718 :     break;
     937             :   }
     938       53141 :   case ISD::EH_LABEL:
     939             :   case ISD::ANNOTATION_LABEL: {
     940       53141 :     unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
     941       53141 :                        ? TargetOpcode::EH_LABEL
     942       53141 :                        : TargetOpcode::ANNOTATION_LABEL;
     943       53141 :     MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
     944      106282 :     BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
     945      212564 :             TII->get(Opc)).addSym(S);
     946       53141 :     break;
     947             :   }
     948             : 
     949       40599 :   case ISD::LIFETIME_START:
     950             :   case ISD::LIFETIME_END: {
     951       40599 :     unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
     952       40599 :     TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
     953             : 
     954      121797 :     FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
     955      162396 :     BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
     956       81198 :     .addFrameIndex(FI->getIndex());
     957       40599 :     break;
     958             :   }
     959             : 
     960        8860 :   case ISD::INLINEASM: {
     961       17720 :     unsigned NumOps = Node->getNumOperands();
     962       28130 :     if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
     963        1550 :       --NumOps;  // Ignore the glue operand.
     964             : 
     965             :     // Create the inline asm machine instruction.
     966        8860 :     MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(),
     967       35440 :                                       TII->get(TargetOpcode::INLINEASM));
     968             : 
     969             :     // Add the asm string as an external symbol operand.
     970       17720 :     SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
     971        8860 :     const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
     972        8860 :     MIB.addExternalSymbol(AsmStr);
     973             : 
     974             :     // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
     975             :     // bits.
     976             :     int64_t ExtraInfo =
     977             :       cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
     978       35440 :                           getZExtValue();
     979        8860 :     MIB.addImm(ExtraInfo);
     980             : 
     981             :     // Remember to operand index of the group flags.
     982       17720 :     SmallVector<unsigned, 8> GroupIdx;
     983             : 
     984             :     // Remember registers that are part of early-clobber defs.
     985       17720 :     SmallVector<unsigned, 8> ECRegs;
     986             : 
     987             :     // Add all of the operand registers to the instruction.
     988       70058 :     for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
     989             :       unsigned Flags =
     990      209352 :         cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
     991       52338 :       const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
     992             : 
     993       52338 :       GroupIdx.push_back(MIB->getNumOperands());
     994      104676 :       MIB.addImm(Flags);
     995       52338 :       ++i;  // Skip the ID value.
     996             : 
     997       52338 :       switch (InlineAsm::getKind(Flags)) {
     998           0 :       default: llvm_unreachable("Bad flags!");
     999             :         case InlineAsm::Kind_RegDef:
    1000        9583 :         for (unsigned j = 0; j != NumVals; ++j, ++i) {
    1001        9597 :           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
    1002             :           // FIXME: Add dead flags for physical and virtual registers defined.
    1003             :           // For now, mark physical register defs as implicit to help fast
    1004             :           // regalloc. This makes inline asm look a lot like calls.
    1005        3199 :           MIB.addReg(Reg, RegState::Define |
    1006        6398 :                   getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
    1007        3185 :         }
    1008             :         break;
    1009             :       case InlineAsm::Kind_RegDefEarlyClobber:
    1010             :       case InlineAsm::Kind_Clobber:
    1011      138339 :         for (unsigned j = 0; j != NumVals; ++j, ++i) {
    1012      138339 :           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
    1013       46113 :           MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
    1014      138339 :                   getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
    1015       46113 :           ECRegs.push_back(Reg);
    1016       46113 :         }
    1017             :         break;
    1018             :       case InlineAsm::Kind_RegUse:  // Use of register.
    1019             :       case InlineAsm::Kind_Imm:  // Immediate.
    1020             :       case InlineAsm::Kind_Mem:  // Addressing mode.
    1021             :         // The addressing mode has been selected, just add all of the
    1022             :         // operands to the machine instruction.
    1023       11236 :         for (unsigned j = 0; j != NumVals; ++j, ++i)
    1024        8196 :           AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
    1025        3040 :                      /*IsDebug=*/false, IsClone, IsCloned);
    1026             : 
    1027             :         // Manually set isTied bits.
    1028        3040 :         if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
    1029        2308 :           unsigned DefGroup = 0;
    1030         180 :           if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
    1031         360 :             unsigned DefIdx = GroupIdx[DefGroup] + 1;
    1032         360 :             unsigned UseIdx = GroupIdx.back() + 1;
    1033         365 :             for (unsigned j = 0; j != NumVals; ++j)
    1034         185 :               MIB->tieOperands(DefIdx + j, UseIdx + j);
    1035             :           }
    1036             :         }
    1037             :         break;
    1038             :       }
    1039             :     }
    1040             : 
    1041             :     // GCC inline assembly allows input operands to also be early-clobber
    1042             :     // output operands (so long as the operand is written only after it's
    1043             :     // used), but this does not match the semantics of our early-clobber flag.
    1044             :     // If an early-clobber operand register is also an input operand register,
    1045             :     // then remove the early-clobber flag.
    1046       72693 :     for (unsigned Reg : ECRegs) {
    1047       92226 :       if (MIB->readsRegister(Reg, TRI)) {
    1048          84 :         MachineOperand *MO = MIB->findRegisterDefOperand(Reg, false, TRI);
    1049             :         assert(MO && "No def operand for clobbered register?");
    1050             :         MO->setIsEarlyClobber(false);
    1051             :       }
    1052             :     }
    1053             : 
    1054             :     // Get the mdnode from the asm if it exists and add it to the instruction.
    1055       17720 :     SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
    1056        8860 :     const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
    1057        8860 :     if (MD)
    1058             :       MIB.addMetadata(MD);
    1059             : 
    1060       17720 :     MBB->insert(InsertPos, MIB);
    1061             :     break;
    1062             :   }
    1063             :   }
    1064     1470625 : }
    1065             : 
    1066             : /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
    1067             : /// at the given position in the given block.
    1068      280008 : InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
    1069      280008 :                            MachineBasicBlock::iterator insertpos)
    1070      560016 :     : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
    1071      280008 :       TII(MF->getSubtarget().getInstrInfo()),
    1072      280008 :       TRI(MF->getSubtarget().getRegisterInfo()),
    1073      280008 :       TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
    1074     1400040 :       InsertPos(insertpos) {}

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