LCOV - code coverage report
Current view: top level - lib/CodeGen/SelectionDAG - LegalizeVectorOps.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 503 531 94.7 %
Date: 2017-09-14 15:23:50 Functions: 26 26 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements the SelectionDAG::LegalizeVectors method.
      11             : //
      12             : // The vector legalizer looks for vector operations which might need to be
      13             : // scalarized and legalizes them. This is a separate step from Legalize because
      14             : // scalarizing can introduce illegal types.  For example, suppose we have an
      15             : // ISD::SDIV of type v2i64 on x86-32.  The type is legal (for example, addition
      16             : // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
      17             : // operation, which introduces nodes with the illegal type i64 which must be
      18             : // expanded.  Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
      19             : // the operation must be unrolled, which introduces nodes with the illegal
      20             : // type i8 which must be promoted.
      21             : //
      22             : // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
      23             : // or operations that happen to take a vector which are custom-lowered;
      24             : // the legalization for such operations never produces nodes
      25             : // with illegal types, so it's okay to put off legalizing them until
      26             : // SelectionDAG::Legalize runs.
      27             : //
      28             : //===----------------------------------------------------------------------===//
      29             : 
      30             : #include "llvm/CodeGen/SelectionDAG.h"
      31             : #include "llvm/Target/TargetLowering.h"
      32             : using namespace llvm;
      33             : 
      34             : namespace {
      35      560140 : class VectorLegalizer {
      36             :   SelectionDAG& DAG;
      37             :   const TargetLowering &TLI;
      38             :   bool Changed; // Keep track of whether anything changed
      39             : 
      40             :   /// For nodes that are of legal width, and that have more than one use, this
      41             :   /// map indicates what regularized operand to use.  This allows us to avoid
      42             :   /// legalizing the same thing more than once.
      43             :   SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
      44             : 
      45             :   /// \brief Adds a node to the translation cache.
      46     4097217 :   void AddLegalizedOperand(SDValue From, SDValue To) {
      47    12291651 :     LegalizedNodes.insert(std::make_pair(From, To));
      48             :     // If someone requests legalization of the new node, return itself.
      49       48167 :     if (From != To)
      50      144501 :       LegalizedNodes.insert(std::make_pair(To, To));
      51     4097217 :   }
      52             : 
      53             :   /// \brief Legalizes the given node.
      54             :   SDValue LegalizeOp(SDValue Op);
      55             : 
      56             :   /// \brief Assuming the node is legal, "legalize" the results.
      57             :   SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
      58             : 
      59             :   /// \brief Implements unrolling a VSETCC.
      60             :   SDValue UnrollVSETCC(SDValue Op);
      61             : 
      62             :   /// \brief Implement expand-based legalization of vector operations.
      63             :   ///
      64             :   /// This is just a high-level routine to dispatch to specific code paths for
      65             :   /// operations to legalize them.
      66             :   SDValue Expand(SDValue Op);
      67             : 
      68             :   /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if
      69             :   /// FSUB isn't legal.
      70             :   ///
      71             :   /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
      72             :   /// SINT_TO_FLOAT and SHR on vectors isn't legal.
      73             :   SDValue ExpandUINT_TO_FLOAT(SDValue Op);
      74             : 
      75             :   /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
      76             :   SDValue ExpandSEXTINREG(SDValue Op);
      77             : 
      78             :   /// \brief Implement expansion for ANY_EXTEND_VECTOR_INREG.
      79             :   ///
      80             :   /// Shuffles the low lanes of the operand into place and bitcasts to the proper
      81             :   /// type. The contents of the bits in the extended part of each element are
      82             :   /// undef.
      83             :   SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
      84             : 
      85             :   /// \brief Implement expansion for SIGN_EXTEND_VECTOR_INREG.
      86             :   ///
      87             :   /// Shuffles the low lanes of the operand into place, bitcasts to the proper
      88             :   /// type, then shifts left and arithmetic shifts right to introduce a sign
      89             :   /// extension.
      90             :   SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
      91             : 
      92             :   /// \brief Implement expansion for ZERO_EXTEND_VECTOR_INREG.
      93             :   ///
      94             :   /// Shuffles the low lanes of the operand into place and blends zeros into
      95             :   /// the remaining lanes, finally bitcasting to the proper type.
      96             :   SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
      97             : 
      98             :   /// \brief Expand bswap of vectors into a shuffle if legal.
      99             :   SDValue ExpandBSWAP(SDValue Op);
     100             : 
     101             :   /// \brief Implement vselect in terms of XOR, AND, OR when blend is not
     102             :   /// supported by the target.
     103             :   SDValue ExpandVSELECT(SDValue Op);
     104             :   SDValue ExpandSELECT(SDValue Op);
     105             :   SDValue ExpandLoad(SDValue Op);
     106             :   SDValue ExpandStore(SDValue Op);
     107             :   SDValue ExpandFNEG(SDValue Op);
     108             :   SDValue ExpandFSUB(SDValue Op);
     109             :   SDValue ExpandBITREVERSE(SDValue Op);
     110             :   SDValue ExpandCTLZ(SDValue Op);
     111             :   SDValue ExpandCTTZ_ZERO_UNDEF(SDValue Op);
     112             : 
     113             :   /// \brief Implements vector promotion.
     114             :   ///
     115             :   /// This is essentially just bitcasting the operands to a different type and
     116             :   /// bitcasting the result back to the original type.
     117             :   SDValue Promote(SDValue Op);
     118             : 
     119             :   /// \brief Implements [SU]INT_TO_FP vector promotion.
     120             :   ///
     121             :   /// This is a [zs]ext of the input operand to the next size up.
     122             :   SDValue PromoteINT_TO_FP(SDValue Op);
     123             : 
     124             :   /// \brief Implements FP_TO_[SU]INT vector promotion of the result type.
     125             :   ///
     126             :   /// It is promoted to the next size up integer type.  The result is then
     127             :   /// truncated back to the original type.
     128             :   SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
     129             : 
     130             : public:
     131             :   /// \brief Begin legalizer the vector operations in the DAG.
     132             :   bool Run();
     133      280070 :   VectorLegalizer(SelectionDAG& dag) :
     134      560140 :       DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
     135             : };
     136             : 
     137      280070 : bool VectorLegalizer::Run() {
     138             :   // Before we start legalizing vector nodes, check if there are any vectors.
     139      280070 :   bool HasVectors = false;
     140      560140 :   for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
     141     6554953 :        E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
     142             :     // Check if the values of the nodes contain vectors. We don't need to check
     143             :     // the operands because we are going to check their values at some point.
     144    24840625 :     for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
     145    13208619 :          J != E; ++J)
     146     7392616 :       HasVectors |= J->isVector();
     147             : 
     148             :     // If we found a vector node we can start the legalization.
     149     5816003 :     if (HasVectors)
     150             :       break;
     151             :   }
     152             : 
     153             :   // If this basic block has no vectors then no need to legalize vectors.
     154      280070 :   if (!HasVectors)
     155             :     return false;
     156             : 
     157             :   // The legalize process is inherently a bottom-up recursive process (users
     158             :   // legalize their uses before themselves).  Given infinite stack space, we
     159             :   // could just start legalizing on the root and traverse the whole graph.  In
     160             :   // practice however, this causes us to run out of stack space on large basic
     161             :   // blocks.  To avoid this problem, compute an ordering of the nodes where each
     162             :   // node is only legalized after all of its operands are legalized.
     163      101260 :   DAG.AssignTopologicalOrder();
     164      202520 :   for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
     165     3518013 :        E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
     166     6428466 :     LegalizeOp(SDValue(&*I, 0));
     167             : 
     168             :   // Finally, it's possible the root changed.  Get the new root.
     169      101260 :   SDValue OldRoot = DAG.getRoot();
     170             :   assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
     171      202520 :   DAG.setRoot(LegalizedNodes[OldRoot]);
     172             : 
     173      101260 :   LegalizedNodes.clear();
     174             : 
     175             :   // Remove dead nodes now.
     176      101260 :   DAG.RemoveDeadNodes();
     177             : 
     178      101260 :   return Changed;
     179             : }
     180             : 
     181     3227153 : SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
     182             :   // Generic legalization: just pass the operand through.
     183    10389000 :   for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
     184    11804082 :     AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
     185     6454306 :   return Result.getValue(Op.getResNo());
     186             : }
     187             : 
     188     9231328 : SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
     189             :   // Note that LegalizeOp may be reentered even from single-use nodes, which
     190             :   // means that we always must cache transformed nodes.
     191     9231328 :   DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
     192    27693984 :   if (I != LegalizedNodes.end()) return I->second;
     193             : 
     194     3389333 :   SDNode* Node = Op.getNode();
     195             : 
     196             :   // Legalize the operands
     197     3389333 :   SmallVector<SDValue, 8> Ops;
     198    18719626 :   for (const SDValue &Op : Node->op_values())
     199     5970480 :     Ops.push_back(LegalizeOp(Op));
     200             : 
     201    10167999 :   SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
     202             : 
     203     3389333 :   bool HasVectorValue = false;
     204     6778666 :   if (Op.getOpcode() == ISD::LOAD) {
     205      443532 :     LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
     206      221766 :     ISD::LoadExtType ExtType = LD->getExtensionType();
     207      661137 :     if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
     208       12473 :       switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
     209             :                                    LD->getMemoryVT())) {
     210           0 :       default: llvm_unreachable("This action is not supported yet!");
     211        1102 :       case TargetLowering::Legal:
     212        1102 :         return TranslateLegalizeResults(Op, Result);
     213        1358 :       case TargetLowering::Custom:
     214        1358 :         if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
     215        1358 :           if (Lowered == Result)
     216           0 :             return TranslateLegalizeResults(Op, Lowered);
     217        1358 :           Changed = true;
     218        1358 :           if (Lowered->getNumValues() != Op->getNumValues()) {
     219             :             // This expanded to something other than the load. Assume the
     220             :             // lowering code took care of any chain values, and just handle the
     221             :             // returned value.
     222             :             assert(Result.getValue(1).use_empty() &&
     223             :                    "There are still live users of the old chain!");
     224        1358 :             return LegalizeOp(Lowered);
     225             :           }
     226           0 :           return TranslateLegalizeResults(Op, Lowered);
     227           0 :         }
     228             :         LLVM_FALLTHROUGH;
     229             :       case TargetLowering::Expand:
     230        1701 :         Changed = true;
     231        1701 :         return LegalizeOp(ExpandLoad(Op));
     232             :       }
     233     6335134 :   } else if (Op.getOpcode() == ISD::STORE) {
     234      518982 :     StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
     235      259491 :     EVT StVT = ST->getMemoryVT();
     236      518982 :     MVT ValVT = ST->getValue().getSimpleValueType();
     237      381524 :     if (StVT.isVector() && ST->isTruncatingStore())
     238        4503 :       switch (TLI.getTruncStoreAction(ValVT, StVT)) {
     239           0 :       default: llvm_unreachable("This action is not supported yet!");
     240         242 :       case TargetLowering::Legal:
     241        1747 :         return TranslateLegalizeResults(Op, Result);
     242        1054 :       case TargetLowering::Custom: {
     243        1054 :         SDValue Lowered = TLI.LowerOperation(Result, DAG);
     244        1054 :         Changed = Lowered != Result;
     245        1054 :         return TranslateLegalizeResults(Op, Lowered);
     246             :       }
     247         209 :       case TargetLowering::Expand:
     248         209 :         Changed = true;
     249         209 :         return LegalizeOp(ExpandStore(Op));
     250             :       }
     251     8724072 :   } else if (Op.getOpcode() == ISD::MSCATTER || Op.getOpcode() == ISD::MSTORE)
     252             :     HasVectorValue = true;
     253             : 
     254    10857518 :   for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
     255     7473851 :        J != E;
     256             :        ++J)
     257     4090184 :     HasVectorValue |= J->isVector();
     258     3383667 :   if (!HasVectorValue)
     259     2628020 :     return TranslateLegalizeResults(Op, Result);
     260             : 
     261      755647 :   EVT QueryType;
     262     1511294 :   switch (Op.getOpcode()) {
     263      596735 :   default:
     264      596735 :     return TranslateLegalizeResults(Op, Result);
     265      156909 :   case ISD::ADD:
     266             :   case ISD::SUB:
     267             :   case ISD::MUL:
     268             :   case ISD::SDIV:
     269             :   case ISD::UDIV:
     270             :   case ISD::SREM:
     271             :   case ISD::UREM:
     272             :   case ISD::SDIVREM:
     273             :   case ISD::UDIVREM:
     274             :   case ISD::FADD:
     275             :   case ISD::FSUB:
     276             :   case ISD::FMUL:
     277             :   case ISD::FDIV:
     278             :   case ISD::FREM:
     279             :   case ISD::AND:
     280             :   case ISD::OR:
     281             :   case ISD::XOR:
     282             :   case ISD::SHL:
     283             :   case ISD::SRA:
     284             :   case ISD::SRL:
     285             :   case ISD::ROTL:
     286             :   case ISD::ROTR:
     287             :   case ISD::BSWAP:
     288             :   case ISD::BITREVERSE:
     289             :   case ISD::CTLZ:
     290             :   case ISD::CTTZ:
     291             :   case ISD::CTLZ_ZERO_UNDEF:
     292             :   case ISD::CTTZ_ZERO_UNDEF:
     293             :   case ISD::CTPOP:
     294             :   case ISD::SELECT:
     295             :   case ISD::VSELECT:
     296             :   case ISD::SELECT_CC:
     297             :   case ISD::SETCC:
     298             :   case ISD::ZERO_EXTEND:
     299             :   case ISD::ANY_EXTEND:
     300             :   case ISD::TRUNCATE:
     301             :   case ISD::SIGN_EXTEND:
     302             :   case ISD::FP_TO_SINT:
     303             :   case ISD::FP_TO_UINT:
     304             :   case ISD::FNEG:
     305             :   case ISD::FABS:
     306             :   case ISD::FMINNUM:
     307             :   case ISD::FMAXNUM:
     308             :   case ISD::FMINNAN:
     309             :   case ISD::FMAXNAN:
     310             :   case ISD::FCOPYSIGN:
     311             :   case ISD::FSQRT:
     312             :   case ISD::FSIN:
     313             :   case ISD::FCOS:
     314             :   case ISD::FPOWI:
     315             :   case ISD::FPOW:
     316             :   case ISD::FLOG:
     317             :   case ISD::FLOG2:
     318             :   case ISD::FLOG10:
     319             :   case ISD::FEXP:
     320             :   case ISD::FEXP2:
     321             :   case ISD::FCEIL:
     322             :   case ISD::FTRUNC:
     323             :   case ISD::FRINT:
     324             :   case ISD::FNEARBYINT:
     325             :   case ISD::FROUND:
     326             :   case ISD::FFLOOR:
     327             :   case ISD::FP_ROUND:
     328             :   case ISD::FP_EXTEND:
     329             :   case ISD::FMA:
     330             :   case ISD::SIGN_EXTEND_INREG:
     331             :   case ISD::ANY_EXTEND_VECTOR_INREG:
     332             :   case ISD::SIGN_EXTEND_VECTOR_INREG:
     333             :   case ISD::ZERO_EXTEND_VECTOR_INREG:
     334             :   case ISD::SMIN:
     335             :   case ISD::SMAX:
     336             :   case ISD::UMIN:
     337             :   case ISD::UMAX:
     338             :   case ISD::SMUL_LOHI:
     339             :   case ISD::UMUL_LOHI:
     340      313818 :     QueryType = Node->getValueType(0);
     341      156909 :     break;
     342           0 :   case ISD::FP_ROUND_INREG:
     343           0 :     QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
     344           0 :     break;
     345        1731 :   case ISD::SINT_TO_FP:
     346             :   case ISD::UINT_TO_FP:
     347        5193 :     QueryType = Node->getOperand(0).getValueType();
     348        1731 :     break;
     349         156 :   case ISD::MSCATTER:
     350         468 :     QueryType = cast<MaskedScatterSDNode>(Node)->getValue().getValueType();
     351         156 :     break;
     352         116 :   case ISD::MSTORE:
     353         348 :     QueryType = cast<MaskedStoreSDNode>(Node)->getValue().getValueType();
     354         116 :     break;
     355             :   }
     356             : 
     357      476736 :   switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
     358           0 :   default: llvm_unreachable("This action is not supported yet!");
     359       10249 :   case TargetLowering::Promote:
     360       10249 :     Result = Promote(Op);
     361       10249 :     Changed = true;
     362       10249 :     break;
     363             :   case TargetLowering::Legal:
     364             :     break;
     365       34134 :   case TargetLowering::Custom: {
     366       34134 :     if (SDValue Tmp1 = TLI.LowerOperation(Op, DAG)) {
     367       33114 :       Result = Tmp1;
     368       33114 :       break;
     369             :     }
     370             :     LLVM_FALLTHROUGH;
     371             :   }
     372             :   case TargetLowering::Expand:
     373        6286 :     Result = Expand(Op);
     374             :   }
     375             : 
     376             :   // Make sure that the generated code is itself legal.
     377       43347 :   if (Result != Op) {
     378       43347 :     Result = LegalizeOp(Result);
     379       43347 :     Changed = true;
     380             :   }
     381             : 
     382             :   // Note that LegalizeOp may be reentered even from single-use nodes, which
     383             :   // means that we always must cache transformed nodes.
     384      158912 :   AddLegalizedOperand(Op, Result);
     385      158912 :   return Result;
     386             : }
     387             : 
     388       10249 : SDValue VectorLegalizer::Promote(SDValue Op) {
     389             :   // For a few operations there is a specific concept for promotion based on
     390             :   // the operand's type.
     391       20498 :   switch (Op.getOpcode()) {
     392          20 :   case ISD::SINT_TO_FP:
     393             :   case ISD::UINT_TO_FP:
     394             :     // "Promote" the operation by extending the operand.
     395          20 :     return PromoteINT_TO_FP(Op);
     396          19 :   case ISD::FP_TO_UINT:
     397             :   case ISD::FP_TO_SINT:
     398             :     // Promote the operation by extending the operand.
     399          19 :     return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
     400             :   }
     401             : 
     402             :   // There are currently two cases of vector promotion:
     403             :   // 1) Bitcasting a vector of integers to a different type to a vector of the
     404             :   //    same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64.
     405             :   // 2) Extending a vector of floats to a vector of the same number of larger
     406             :   //    floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
     407       10210 :   MVT VT = Op.getSimpleValueType();
     408             :   assert(Op.getNode()->getNumValues() == 1 &&
     409             :          "Can't promote a vector with multiple results!");
     410       20420 :   MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
     411       20420 :   SDLoc dl(Op);
     412       40840 :   SmallVector<SDValue, 4> Operands(Op.getNumOperands());
     413             : 
     414       61416 :   for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
     415       81992 :     if (Op.getOperand(j).getValueType().isVector())
     416       40722 :       if (Op.getOperand(j)
     417       40722 :               .getValueType()
     418       40722 :               .getVectorElementType()
     419       20546 :               .isFloatingPoint() &&
     420       41204 :           NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
     421         345 :         Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
     422             :       else
     423      101460 :         Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
     424             :     else
     425         411 :       Operands[j] = Op.getOperand(j);
     426             :   }
     427             : 
     428       51050 :   Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags());
     429       20478 :   if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
     430       40706 :       (VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
     431       10318 :        NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
     432         192 :     return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
     433             :   else
     434       30438 :     return DAG.getNode(ISD::BITCAST, dl, VT, Op);
     435             : }
     436             : 
     437          20 : SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
     438             :   // INT_TO_FP operations may require the input operand be promoted even
     439             :   // when the type is otherwise legal.
     440          60 :   EVT VT = Op.getOperand(0).getValueType();
     441             :   assert(Op.getNode()->getNumValues() == 1 &&
     442             :          "Can't promote a vector with multiple results!");
     443             : 
     444             :   // Normal getTypeToPromoteTo() doesn't work here, as that will promote
     445             :   // by widening the vector w/ the same element width and twice the number
     446             :   // of elements. We want the other way around, the same number of elements,
     447             :   // each twice the width.
     448             :   //
     449             :   // Increase the bitwidth of the element to the next pow-of-two
     450             :   // (which is greater than 8 bits).
     451             : 
     452          20 :   EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext());
     453             :   assert(NVT.isSimple() && "Promoting to a non-simple vector type!");
     454          40 :   SDLoc dl(Op);
     455          80 :   SmallVector<SDValue, 4> Operands(Op.getNumOperands());
     456             : 
     457          40 :   unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
     458          20 :     ISD::SIGN_EXTEND;
     459          80 :   for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
     460          80 :     if (Op.getOperand(j).getValueType().isVector())
     461          80 :       Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
     462             :     else
     463           0 :       Operands[j] = Op.getOperand(j);
     464             :   }
     465             : 
     466         120 :   return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
     467             : }
     468             : 
     469             : // For FP_TO_INT we promote the result type to a vector type with wider
     470             : // elements and then truncate the result.  This is different from the default
     471             : // PromoteVector which uses bitcast to promote thus assumning that the
     472             : // promoted vector type has the same overall size.
     473          19 : SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
     474             :   assert(Op.getNode()->getNumValues() == 1 &&
     475             :          "Can't promote a vector with multiple results!");
     476          38 :   EVT VT = Op.getValueType();
     477             : 
     478          19 :   EVT NewVT;
     479             :   unsigned NewOpc;
     480             :   while (1) {
     481          19 :     NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
     482             :     assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
     483          19 :     if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
     484             :       NewOpc = ISD::FP_TO_SINT;
     485             :       break;
     486             :     }
     487           0 :     if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
     488             :       NewOpc = ISD::FP_TO_UINT;
     489             :       break;
     490             :     }
     491             :   }
     492             : 
     493          38 :   SDLoc loc(Op);
     494          95 :   SDValue promoted  = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
     495          95 :   return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
     496             : }
     497             : 
     498             : 
     499        1701 : SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
     500        3402 :   LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
     501             : 
     502        1701 :   EVT SrcVT = LD->getMemoryVT();
     503        1701 :   EVT SrcEltVT = SrcVT.getScalarType();
     504        1701 :   unsigned NumElem = SrcVT.getVectorNumElements();
     505             : 
     506             : 
     507        1701 :   SDValue NewChain;
     508        1701 :   SDValue Value;
     509        3402 :   if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
     510        1210 :     SDLoc dl(Op);
     511             : 
     512        1210 :     SmallVector<SDValue, 8> Vals;
     513        1210 :     SmallVector<SDValue, 8> LoadChains;
     514             : 
     515        1210 :     EVT DstEltVT = LD->getValueType(0).getScalarType();
     516        1210 :     SDValue Chain = LD->getChain();
     517         605 :     SDValue BasePTR = LD->getBasePtr();
     518         605 :     ISD::LoadExtType ExtType = LD->getExtensionType();
     519             : 
     520             :     // When elements in a vector is not byte-addressable, we cannot directly
     521             :     // load each element by advancing pointer, which could only address bytes.
     522             :     // Instead, we load all significant words, mask bits off, and concatenate
     523             :     // them to form each element. Finally, they are extended to destination
     524             :     // scalar type to build the destination vector.
     525        2420 :     EVT WideVT = TLI.getPointerTy(DAG.getDataLayout());
     526             : 
     527             :     assert(WideVT.isRound() &&
     528             :            "Could not handle the sophisticated case when the widest integer is"
     529             :            " not power of 2.");
     530             :     assert(WideVT.bitsGE(SrcEltVT) &&
     531             :            "Type is not legalized?");
     532             : 
     533         605 :     unsigned WideBytes = WideVT.getStoreSize();
     534         605 :     unsigned Offset = 0;
     535         605 :     unsigned RemainingBytes = SrcVT.getStoreSize();
     536         605 :     SmallVector<SDValue, 8> LoadVals;
     537             : 
     538        1214 :     while (RemainingBytes > 0) {
     539         609 :       SDValue ScalarLoad;
     540         609 :       unsigned LoadBytes = WideBytes;
     541             : 
     542         609 :       if (RemainingBytes >= LoadBytes) {
     543          13 :         ScalarLoad =
     544          39 :             DAG.getLoad(WideVT, dl, Chain, BasePTR,
     545          13 :                         LD->getPointerInfo().getWithOffset(Offset),
     546          39 :                         MinAlign(LD->getAlignment(), Offset),
     547          78 :                         LD->getMemOperand()->getFlags(), LD->getAAInfo());
     548             :       } else {
     549         596 :         EVT LoadVT = WideVT;
     550        1862 :         while (RemainingBytes < LoadBytes) {
     551        1266 :           LoadBytes >>= 1; // Reduce the load size by half.
     552        1266 :           LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
     553             :         }
     554         596 :         ScalarLoad =
     555        1788 :             DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
     556         596 :                            LD->getPointerInfo().getWithOffset(Offset), LoadVT,
     557        1788 :                            MinAlign(LD->getAlignment(), Offset),
     558        3576 :                            LD->getMemOperand()->getFlags(), LD->getAAInfo());
     559             :       }
     560             : 
     561         609 :       RemainingBytes -= LoadBytes;
     562         609 :       Offset += LoadBytes;
     563        1218 :       BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
     564             :                             DAG.getConstant(LoadBytes, dl,
     565        1827 :                                             BasePTR.getValueType()));
     566             : 
     567        1218 :       LoadVals.push_back(ScalarLoad.getValue(0));
     568        1218 :       LoadChains.push_back(ScalarLoad.getValue(1));
     569             :     }
     570             : 
     571             :     // Extract bits, pack and extend/trunc them into destination type.
     572         605 :     unsigned SrcEltBits = SrcEltVT.getSizeInBits();
     573         605 :     SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, dl, WideVT);
     574             : 
     575         605 :     unsigned BitOffset = 0;
     576         605 :     unsigned WideIdx = 0;
     577         605 :     unsigned WideBits = WideVT.getSizeInBits();
     578             : 
     579        4851 :     for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
     580        4246 :       SDValue Lo, Hi, ShAmt;
     581             : 
     582        4246 :       if (BitOffset < WideBits) {
     583        8492 :         ShAmt = DAG.getConstant(
     584        8492 :             BitOffset, dl, TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
     585       12738 :         Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
     586        8492 :         Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
     587             :       }
     588             : 
     589        4246 :       BitOffset += SrcEltBits;
     590        4246 :       if (BitOffset >= WideBits) {
     591          13 :         WideIdx++;
     592          13 :         BitOffset -= WideBits;
     593          13 :         if (BitOffset > 0) {
     594           0 :           ShAmt = DAG.getConstant(
     595           0 :               SrcEltBits - BitOffset, dl,
     596           0 :               TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
     597           0 :           Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
     598           0 :           Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
     599             :         }
     600             :       }
     601             : 
     602        4246 :       if (Hi.getNode())
     603           0 :         Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
     604             : 
     605        4246 :       switch (ExtType) {
     606           0 :       default: llvm_unreachable("Unknown extended-load op!");
     607        1878 :       case ISD::EXTLOAD:
     608        1878 :         Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
     609             :         break;
     610         968 :       case ISD::ZEXTLOAD:
     611         968 :         Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
     612             :         break;
     613        1400 :       case ISD::SEXTLOAD:
     614        1400 :         ShAmt =
     615        5600 :             DAG.getConstant(WideBits - SrcEltBits, dl,
     616        4200 :                             TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
     617        2800 :         Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
     618        2800 :         Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
     619        1400 :         Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
     620             :         break;
     621             :       }
     622        4246 :       Vals.push_back(Lo);
     623             :     }
     624             : 
     625        2420 :     NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
     626        1815 :     Value = DAG.getBuildVector(Op.getNode()->getValueType(0), dl, Vals);
     627             :   } else {
     628        1096 :     SDValue Scalarized = TLI.scalarizeVectorLoad(LD, DAG);
     629             : 
     630        2192 :     NewChain = Scalarized.getValue(1);
     631        2192 :     Value = Scalarized.getValue(0);
     632             :   }
     633             : 
     634        3402 :   AddLegalizedOperand(Op.getValue(0), Value);
     635        3402 :   AddLegalizedOperand(Op.getValue(1), NewChain);
     636             : 
     637        1701 :   return (Op.getResNo() ? NewChain : Value);
     638             : }
     639             : 
     640         209 : SDValue VectorLegalizer::ExpandStore(SDValue Op) {
     641         418 :   StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
     642             : 
     643         209 :   EVT StVT = ST->getMemoryVT();
     644         209 :   EVT MemSclVT = StVT.getScalarType();
     645         209 :   unsigned ScalarSize = MemSclVT.getSizeInBits();
     646             : 
     647             :   // Round odd types to the next pow of two.
     648           0 :   if (!isPowerOf2_32(ScalarSize)) {
     649             :     // FIXME: This is completely broken and inconsistent with ExpandLoad
     650             :     // handling.
     651             : 
     652             :     // For sub-byte element sizes, this ends up with 0 stride between elements,
     653             :     // so the same element just gets re-written to the same location. There seem
     654             :     // to be tests explicitly testing for this broken behavior though.  tests
     655             :     // for this broken behavior.
     656             : 
     657           0 :     LLVMContext &Ctx = *DAG.getContext();
     658             : 
     659             :     EVT NewMemVT
     660             :       = EVT::getVectorVT(Ctx,
     661           0 :                          MemSclVT.getIntegerVT(Ctx, NextPowerOf2(ScalarSize)),
     662           0 :                          StVT.getVectorNumElements());
     663             : 
     664           0 :     SDValue NewVectorStore = DAG.getTruncStore(
     665           0 :         ST->getChain(), SDLoc(Op), ST->getValue(), ST->getBasePtr(),
     666           0 :         ST->getPointerInfo(), NewMemVT, ST->getAlignment(),
     667           0 :         ST->getMemOperand()->getFlags(), ST->getAAInfo());
     668           0 :     ST = cast<StoreSDNode>(NewVectorStore.getNode());
     669             :   }
     670             : 
     671         209 :   SDValue TF = TLI.scalarizeVectorStore(ST, DAG);
     672         209 :   AddLegalizedOperand(Op, TF);
     673         209 :   return TF;
     674             : }
     675             : 
     676        6286 : SDValue VectorLegalizer::Expand(SDValue Op) {
     677       12572 :   switch (Op->getOpcode()) {
     678         689 :   case ISD::SIGN_EXTEND_INREG:
     679         689 :     return ExpandSEXTINREG(Op);
     680         234 :   case ISD::ANY_EXTEND_VECTOR_INREG:
     681         234 :     return ExpandANY_EXTEND_VECTOR_INREG(Op);
     682          12 :   case ISD::SIGN_EXTEND_VECTOR_INREG:
     683          12 :     return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
     684         683 :   case ISD::ZERO_EXTEND_VECTOR_INREG:
     685         683 :     return ExpandZERO_EXTEND_VECTOR_INREG(Op);
     686          49 :   case ISD::BSWAP:
     687          49 :     return ExpandBSWAP(Op);
     688        1031 :   case ISD::VSELECT:
     689        1031 :     return ExpandVSELECT(Op);
     690          90 :   case ISD::SELECT:
     691          90 :     return ExpandSELECT(Op);
     692         130 :   case ISD::UINT_TO_FP:
     693         130 :     return ExpandUINT_TO_FLOAT(Op);
     694          34 :   case ISD::FNEG:
     695          34 :     return ExpandFNEG(Op);
     696          33 :   case ISD::FSUB:
     697          33 :     return ExpandFSUB(Op);
     698         142 :   case ISD::SETCC:
     699         142 :     return UnrollVSETCC(Op);
     700         129 :   case ISD::BITREVERSE:
     701         129 :     return ExpandBITREVERSE(Op);
     702         138 :   case ISD::CTLZ:
     703             :   case ISD::CTLZ_ZERO_UNDEF:
     704         138 :     return ExpandCTLZ(Op);
     705          83 :   case ISD::CTTZ_ZERO_UNDEF:
     706          83 :     return ExpandCTTZ_ZERO_UNDEF(Op);
     707        2809 :   default:
     708        2809 :     return DAG.UnrollVectorOp(Op.getNode());
     709             :   }
     710             : }
     711             : 
     712          90 : SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
     713             :   // Lower a select instruction where the condition is a scalar and the
     714             :   // operands are vectors. Lower this select to VSELECT and implement it
     715             :   // using XOR AND OR. The selector bit is broadcasted.
     716         180 :   EVT VT = Op.getValueType();
     717         180 :   SDLoc DL(Op);
     718             : 
     719         180 :   SDValue Mask = Op.getOperand(0);
     720         180 :   SDValue Op1 = Op.getOperand(1);
     721         180 :   SDValue Op2 = Op.getOperand(2);
     722             : 
     723             :   assert(VT.isVector() && !Mask.getValueType().isVector()
     724             :          && Op1.getValueType() == Op2.getValueType() && "Invalid type");
     725             : 
     726             :   // If we can't even use the basic vector operations of
     727             :   // AND,OR,XOR, we will have to scalarize the op.
     728             :   // Notice that the operation may be 'promoted' which means that it is
     729             :   // 'bitcasted' to another type which is handled.
     730             :   // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
     731         187 :   if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
     732          21 :       TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
     733         111 :       TLI.getOperationAction(ISD::OR,  VT) == TargetLowering::Expand ||
     734          14 :       TLI.getOperationAction(ISD::BUILD_VECTOR,  VT) == TargetLowering::Expand)
     735          83 :     return DAG.UnrollVectorOp(Op.getNode());
     736             : 
     737             :   // Generate a mask operand.
     738           7 :   EVT MaskTy = VT.changeVectorElementTypeToInteger();
     739             : 
     740             :   // What is the size of each element in the vector mask.
     741           7 :   EVT BitTy = MaskTy.getScalarType();
     742             : 
     743          14 :   Mask = DAG.getSelect(DL, BitTy, Mask,
     744          14 :           DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL,
     745             :                           BitTy),
     746          14 :           DAG.getConstant(0, DL, BitTy));
     747             : 
     748             :   // Broadcast the mask so that the entire vector is all-one or all zero.
     749           7 :   Mask = DAG.getSplatBuildVector(MaskTy, DL, Mask);
     750             : 
     751             :   // Bitcast the operands to be the same type as the mask.
     752             :   // This is needed when we select between FP types because
     753             :   // the mask is a vector of integers.
     754          14 :   Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
     755          14 :   Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
     756             : 
     757           7 :   SDValue AllOnes = DAG.getConstant(
     758          14 :             APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy);
     759          14 :   SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
     760             : 
     761          14 :   Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
     762          14 :   Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
     763          14 :   SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
     764          21 :   return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
     765             : }
     766             : 
     767         689 : SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
     768        1378 :   EVT VT = Op.getValueType();
     769             : 
     770             :   // Make sure that the SRA and SHL instructions are available.
     771        2044 :   if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
     772        1332 :       TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
     773          23 :     return DAG.UnrollVectorOp(Op.getNode());
     774             : 
     775         666 :   SDLoc DL(Op);
     776        1998 :   EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
     777             : 
     778         666 :   unsigned BW = VT.getScalarSizeInBits();
     779         666 :   unsigned OrigBW = OrigTy.getScalarSizeInBits();
     780         666 :   SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT);
     781             : 
     782        1332 :   Op = Op.getOperand(0);
     783        1332 :   Op =   DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
     784        1332 :   return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
     785             : }
     786             : 
     787             : // Generically expand a vector anyext in register to a shuffle of the relevant
     788             : // lanes into the appropriate locations, with other lanes left undef.
     789         234 : SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
     790         468 :   SDLoc DL(Op);
     791         468 :   EVT VT = Op.getValueType();
     792         234 :   int NumElements = VT.getVectorNumElements();
     793         468 :   SDValue Src = Op.getOperand(0);
     794         468 :   EVT SrcVT = Src.getValueType();
     795         234 :   int NumSrcElements = SrcVT.getVectorNumElements();
     796             : 
     797             :   // Build a base mask of undef shuffles.
     798         468 :   SmallVector<int, 16> ShuffleMask;
     799         234 :   ShuffleMask.resize(NumSrcElements, -1);
     800             : 
     801             :   // Place the extended lanes into the correct locations.
     802         234 :   int ExtLaneScale = NumSrcElements / NumElements;
     803         468 :   int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
     804        1082 :   for (int i = 0; i < NumElements; ++i)
     805        1696 :     ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
     806             : 
     807         234 :   return DAG.getNode(
     808             :       ISD::BITCAST, DL, VT,
     809         702 :       DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
     810             : }
     811             : 
     812          12 : SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
     813          24 :   SDLoc DL(Op);
     814          24 :   EVT VT = Op.getValueType();
     815          24 :   SDValue Src = Op.getOperand(0);
     816          24 :   EVT SrcVT = Src.getValueType();
     817             : 
     818             :   // First build an any-extend node which can be legalized above when we
     819             :   // recurse through it.
     820          12 :   Op = DAG.getAnyExtendVectorInReg(Src, DL, VT);
     821             : 
     822             :   // Now we need sign extend. Do this by shifting the elements. Even if these
     823             :   // aren't legal operations, they have a better chance of being legalized
     824             :   // without full scalarization than the sign extension does.
     825          12 :   unsigned EltWidth = VT.getScalarSizeInBits();
     826          12 :   unsigned SrcEltWidth = SrcVT.getScalarSizeInBits();
     827          12 :   SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT);
     828          12 :   return DAG.getNode(ISD::SRA, DL, VT,
     829          12 :                      DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
     830          36 :                      ShiftAmount);
     831             : }
     832             : 
     833             : // Generically expand a vector zext in register to a shuffle of the relevant
     834             : // lanes into the appropriate locations, a blend of zero into the high bits,
     835             : // and a bitcast to the wider element type.
     836         683 : SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
     837        1366 :   SDLoc DL(Op);
     838        1366 :   EVT VT = Op.getValueType();
     839         683 :   int NumElements = VT.getVectorNumElements();
     840        1366 :   SDValue Src = Op.getOperand(0);
     841        1366 :   EVT SrcVT = Src.getValueType();
     842         683 :   int NumSrcElements = SrcVT.getVectorNumElements();
     843             : 
     844             :   // Build up a zero vector to blend into this one.
     845         683 :   SDValue Zero = DAG.getConstant(0, DL, SrcVT);
     846             : 
     847             :   // Shuffle the incoming lanes into the correct position, and pull all other
     848             :   // lanes from the zero vector.
     849        1366 :   SmallVector<int, 16> ShuffleMask;
     850         683 :   ShuffleMask.reserve(NumSrcElements);
     851       11187 :   for (int i = 0; i < NumSrcElements; ++i)
     852       10504 :     ShuffleMask.push_back(i);
     853             : 
     854         683 :   int ExtLaneScale = NumSrcElements / NumElements;
     855        1366 :   int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
     856        3855 :   for (int i = 0; i < NumElements; ++i)
     857        6344 :     ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
     858             : 
     859         683 :   return DAG.getNode(ISD::BITCAST, DL, VT,
     860        2049 :                      DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
     861             : }
     862             : 
     863         141 : static void createBSWAPShuffleMask(EVT VT, SmallVectorImpl<int> &ShuffleMask) {
     864         141 :   int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
     865         983 :   for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
     866        3866 :     for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
     867        3024 :       ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
     868         141 : }
     869             : 
     870          49 : SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
     871          98 :   EVT VT = Op.getValueType();
     872             : 
     873             :   // Generate a byte wise shuffle mask for the BSWAP.
     874          98 :   SmallVector<int, 16> ShuffleMask;
     875          49 :   createBSWAPShuffleMask(VT, ShuffleMask);
     876          98 :   EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
     877             : 
     878             :   // Only emit a shuffle if the mask is legal.
     879          98 :   if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
     880          12 :     return DAG.UnrollVectorOp(Op.getNode());
     881             : 
     882          37 :   SDLoc DL(Op);
     883         111 :   Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
     884          74 :   Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT), ShuffleMask);
     885          74 :   return DAG.getNode(ISD::BITCAST, DL, VT, Op);
     886             : }
     887             : 
     888         129 : SDValue VectorLegalizer::ExpandBITREVERSE(SDValue Op) {
     889         258 :   EVT VT = Op.getValueType();
     890             : 
     891             :   // If we have the scalar operation, it's probably cheaper to unroll it.
     892         129 :   if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType()))
     893           7 :     return DAG.UnrollVectorOp(Op.getNode());
     894             : 
     895             :   // If the vector element width is a whole number of bytes, test if its legal
     896             :   // to BSWAP shuffle the bytes and then perform the BITREVERSE on the byte
     897             :   // vector. This greatly reduces the number of bit shifts necessary.
     898         122 :   unsigned ScalarSizeInBits = VT.getScalarSizeInBits();
     899         122 :   if (ScalarSizeInBits > 8 && (ScalarSizeInBits % 8) == 0) {
     900         100 :     SmallVector<int, 16> BSWAPMask;
     901          92 :     createBSWAPShuffleMask(VT, BSWAPMask);
     902             : 
     903         184 :     EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, BSWAPMask.size());
     904         276 :     if (TLI.isShuffleMaskLegal(BSWAPMask, ByteVT) &&
     905          84 :         (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, ByteVT) ||
     906          22 :          (TLI.isOperationLegalOrCustom(ISD::SHL, ByteVT) &&
     907          44 :           TLI.isOperationLegalOrCustom(ISD::SRL, ByteVT) &&
     908          44 :           TLI.isOperationLegalOrCustomOrPromote(ISD::AND, ByteVT) &&
     909          22 :           TLI.isOperationLegalOrCustomOrPromote(ISD::OR, ByteVT)))) {
     910         168 :       SDLoc DL(Op);
     911         252 :       Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
     912         168 :       Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
     913         168 :                                 BSWAPMask);
     914         168 :       Op = DAG.getNode(ISD::BITREVERSE, DL, ByteVT, Op);
     915         168 :       return DAG.getNode(ISD::BITCAST, DL, VT, Op);
     916             :     }
     917             :   }
     918             : 
     919             :   // If we have the appropriate vector bit operations, it is better to use them
     920             :   // than unrolling and expanding each component.
     921          38 :   if (!TLI.isOperationLegalOrCustom(ISD::SHL, VT) ||
     922          64 :       !TLI.isOperationLegalOrCustom(ISD::SRL, VT) ||
     923          64 :       !TLI.isOperationLegalOrCustomOrPromote(ISD::AND, VT) ||
     924          32 :       !TLI.isOperationLegalOrCustomOrPromote(ISD::OR, VT))
     925           6 :     return DAG.UnrollVectorOp(Op.getNode());
     926             : 
     927             :   // Let LegalizeDAG handle this later.
     928          32 :   return Op;
     929             : }
     930             : 
     931        1031 : SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
     932             :   // Implement VSELECT in terms of XOR, AND, OR
     933             :   // on platforms which do not support blend natively.
     934        2062 :   SDLoc DL(Op);
     935             : 
     936        2062 :   SDValue Mask = Op.getOperand(0);
     937        2062 :   SDValue Op1 = Op.getOperand(1);
     938        2062 :   SDValue Op2 = Op.getOperand(2);
     939             : 
     940        2062 :   EVT VT = Mask.getValueType();
     941             : 
     942             :   // If we can't even use the basic vector operations of
     943             :   // AND,OR,XOR, we will have to scalarize the op.
     944             :   // Notice that the operation may be 'promoted' which means that it is
     945             :   // 'bitcasted' to another type which is handled.
     946             :   // This operation also isn't safe with AND, OR, XOR when the boolean
     947             :   // type is 0/1 as we need an all ones vector constant to mask with.
     948             :   // FIXME: Sign extend 1 to all ones if thats legal on the target.
     949        3078 :   if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
     950        3048 :       TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
     951        4079 :       TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
     952        2032 :       TLI.getBooleanContents(Op1.getValueType()) !=
     953             :           TargetLowering::ZeroOrNegativeOneBooleanContent)
     954          15 :     return DAG.UnrollVectorOp(Op.getNode());
     955             : 
     956             :   // If the mask and the type are different sizes, unroll the vector op. This
     957             :   // can occur when getSetCCResultType returns something that is different in
     958             :   // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
     959        1016 :   if (VT.getSizeInBits() != Op1.getValueSizeInBits())
     960           0 :     return DAG.UnrollVectorOp(Op.getNode());
     961             : 
     962             :   // Bitcast the operands to be the same type as the mask.
     963             :   // This is needed when we select between FP types because
     964             :   // the mask is a vector of integers.
     965        2032 :   Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
     966        2032 :   Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
     967             : 
     968        1016 :   SDValue AllOnes = DAG.getConstant(
     969        2032 :     APInt::getAllOnesValue(VT.getScalarSizeInBits()), DL, VT);
     970        2032 :   SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
     971             : 
     972        2032 :   Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
     973        2032 :   Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
     974        2032 :   SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
     975        3048 :   return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
     976             : }
     977             : 
     978         130 : SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
     979         390 :   EVT VT = Op.getOperand(0).getValueType();
     980         260 :   SDLoc DL(Op);
     981             : 
     982             :   // Make sure that the SINT_TO_FP and SRL instructions are available.
     983         281 :   if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
     984          42 :       TLI.getOperationAction(ISD::SRL,        VT) == TargetLowering::Expand)
     985         109 :     return DAG.UnrollVectorOp(Op.getNode());
     986             : 
     987          21 :   unsigned BW = VT.getScalarSizeInBits();
     988             :   assert((BW == 64 || BW == 32) &&
     989             :          "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
     990             : 
     991          21 :   SDValue HalfWord = DAG.getConstant(BW / 2, DL, VT);
     992             : 
     993             :   // Constants to clear the upper part of the word.
     994             :   // Notice that we can also use SHL+SHR, but using a constant is slightly
     995             :   // faster on x86.
     996          42 :   uint64_t HWMask = (BW == 64) ? 0x00000000FFFFFFFF : 0x0000FFFF;
     997          21 :   SDValue HalfWordMask = DAG.getConstant(HWMask, DL, VT);
     998             : 
     999             :   // Two to the power of half-word-size.
    1000          42 :   SDValue TWOHW = DAG.getConstantFP(1 << (BW / 2), DL, Op.getValueType());
    1001             : 
    1002             :   // Clear upper part of LO, lower HI
    1003          63 :   SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
    1004          63 :   SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
    1005             : 
    1006             :   // Convert hi and lo to floats
    1007             :   // Convert the hi part back to the upper values
    1008             :   // TODO: Can any fast-math-flags be set on these nodes?
    1009          63 :   SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
    1010          63 :           fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
    1011          63 :   SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
    1012             : 
    1013             :   // Add the two halves
    1014          63 :   return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
    1015             : }
    1016             : 
    1017          34 : SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
    1018          68 :   if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
    1019           8 :     SDLoc DL(Op);
    1020           8 :     SDValue Zero = DAG.getConstantFP(-0.0, DL, Op.getValueType());
    1021             :     // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB.
    1022           4 :     return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
    1023          12 :                        Zero, Op.getOperand(0));
    1024             :   }
    1025          30 :   return DAG.UnrollVectorOp(Op.getNode());
    1026             : }
    1027             : 
    1028          33 : SDValue VectorLegalizer::ExpandFSUB(SDValue Op) {
    1029             :   // For floating-point values, (a-b) is the same as a+(-b). If FNEG is legal,
    1030             :   // we can defer this to operation legalization where it will be lowered as
    1031             :   // a+(-b).
    1032          66 :   EVT VT = Op.getValueType();
    1033          33 :   if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
    1034           3 :       TLI.isOperationLegalOrCustom(ISD::FADD, VT))
    1035           3 :     return Op; // Defer to LegalizeDAG
    1036             : 
    1037          30 :   return DAG.UnrollVectorOp(Op.getNode());
    1038             : }
    1039             : 
    1040         138 : SDValue VectorLegalizer::ExpandCTLZ(SDValue Op) {
    1041         276 :   EVT VT = Op.getValueType();
    1042         138 :   unsigned NumBitsPerElt = VT.getScalarSizeInBits();
    1043             : 
    1044             :   // If the non-ZERO_UNDEF version is supported we can use that instead.
    1045         276 :   if (Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF &&
    1046         111 :       TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) {
    1047         176 :     SDLoc DL(Op);
    1048         352 :     return DAG.getNode(ISD::CTLZ, DL, Op.getValueType(), Op.getOperand(0));
    1049             :   }
    1050             : 
    1051             :   // If CTPOP is available we can lower with a CTPOP based method:
    1052             :   // u16 ctlz(u16 x) {
    1053             :   //   x |= (x >> 1);
    1054             :   //   x |= (x >> 2);
    1055             :   //   x |= (x >> 4);
    1056             :   //   x |= (x >> 8);
    1057             :   //   return ctpop(~x);
    1058             :   // }
    1059             :   // Ref: "Hacker's Delight" by Henry Warren
    1060          50 :   if (isPowerOf2_32(NumBitsPerElt) &&
    1061          50 :       TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
    1062          60 :       TLI.isOperationLegalOrCustom(ISD::SRL, VT) &&
    1063          60 :       TLI.isOperationLegalOrCustomOrPromote(ISD::OR, VT) &&
    1064          30 :       TLI.isOperationLegalOrCustomOrPromote(ISD::XOR, VT)) {
    1065          60 :     SDLoc DL(Op);
    1066          60 :     SDValue Res = Op.getOperand(0);
    1067          60 :     EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
    1068             : 
    1069         172 :     for (unsigned i = 1; i != NumBitsPerElt; i *= 2)
    1070         284 :       Res = DAG.getNode(
    1071             :           ISD::OR, DL, VT, Res,
    1072         426 :           DAG.getNode(ISD::SRL, DL, VT, Res, DAG.getConstant(i, DL, ShiftTy)));
    1073             : 
    1074          30 :     Res = DAG.getNOT(DL, Res, VT);
    1075          60 :     return DAG.getNode(ISD::CTPOP, DL, VT, Res);
    1076             :   }
    1077             : 
    1078             :   // Otherwise go ahead and unroll.
    1079          20 :   return DAG.UnrollVectorOp(Op.getNode());
    1080             : }
    1081             : 
    1082          83 : SDValue VectorLegalizer::ExpandCTTZ_ZERO_UNDEF(SDValue Op) {
    1083             :   // If the non-ZERO_UNDEF version is supported we can use that instead.
    1084         166 :   if (TLI.isOperationLegalOrCustom(ISD::CTTZ, Op.getValueType())) {
    1085         154 :     SDLoc DL(Op);
    1086         308 :     return DAG.getNode(ISD::CTTZ, DL, Op.getValueType(), Op.getOperand(0));
    1087             :   }
    1088             : 
    1089             :   // Otherwise go ahead and unroll.
    1090           6 :   return DAG.UnrollVectorOp(Op.getNode());
    1091             : }
    1092             : 
    1093         142 : SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
    1094         284 :   EVT VT = Op.getValueType();
    1095         142 :   unsigned NumElems = VT.getVectorNumElements();
    1096         142 :   EVT EltVT = VT.getVectorElementType();
    1097         568 :   SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
    1098         284 :   EVT TmpEltVT = LHS.getValueType().getVectorElementType();
    1099         284 :   SDLoc dl(Op);
    1100         426 :   SmallVector<SDValue, 8> Ops(NumElems);
    1101        1054 :   for (unsigned i = 0; i < NumElems; ++i) {
    1102         912 :     SDValue LHSElem = DAG.getNode(
    1103             :         ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
    1104        2736 :         DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
    1105         912 :     SDValue RHSElem = DAG.getNode(
    1106             :         ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
    1107        2736 :         DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
    1108        2736 :     Ops[i] = DAG.getNode(ISD::SETCC, dl,
    1109         912 :                          TLI.getSetCCResultType(DAG.getDataLayout(),
    1110         912 :                                                 *DAG.getContext(), TmpEltVT),
    1111        2736 :                          LHSElem, RHSElem, CC);
    1112        3648 :     Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
    1113         912 :                            DAG.getConstant(APInt::getAllOnesValue
    1114        1824 :                                            (EltVT.getSizeInBits()), dl, EltVT),
    1115        1824 :                            DAG.getConstant(0, dl, EltVT));
    1116             :   }
    1117         426 :   return DAG.getBuildVector(VT, dl, Ops);
    1118             : }
    1119             : 
    1120             : }
    1121             : 
    1122      280070 : bool SelectionDAG::LegalizeVectors() {
    1123      560140 :   return VectorLegalizer(*this).Run();
    1124             : }

Generated by: LCOV version 1.13