LCOV - code coverage report
Current view: top level - lib/CodeGen/SelectionDAG - ScheduleDAGFast.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 230 285 80.7 %
Date: 2018-06-17 00:07:59 Functions: 23 23 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===----- ScheduleDAGFast.cpp - Fast poor list scheduler -----------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This implements a fast scheduler.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "InstrEmitter.h"
      15             : #include "ScheduleDAGSDNodes.h"
      16             : #include "SDNodeDbgValue.h"
      17             : #include "llvm/ADT/STLExtras.h"
      18             : #include "llvm/ADT/SmallSet.h"
      19             : #include "llvm/ADT/Statistic.h"
      20             : #include "llvm/CodeGen/SchedulerRegistry.h"
      21             : #include "llvm/CodeGen/SelectionDAGISel.h"
      22             : #include "llvm/CodeGen/TargetInstrInfo.h"
      23             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      24             : #include "llvm/IR/DataLayout.h"
      25             : #include "llvm/IR/InlineAsm.h"
      26             : #include "llvm/Support/Debug.h"
      27             : #include "llvm/Support/ErrorHandling.h"
      28             : #include "llvm/Support/raw_ostream.h"
      29             : using namespace llvm;
      30             : 
      31             : #define DEBUG_TYPE "pre-RA-sched"
      32             : 
      33             : STATISTIC(NumUnfolds,    "Number of nodes unfolded");
      34             : STATISTIC(NumDups,       "Number of duplicated nodes");
      35             : STATISTIC(NumPRCopies,   "Number of physical copies");
      36             : 
      37             : static RegisterScheduler
      38      101169 :   fastDAGScheduler("fast", "Fast suboptimal list scheduling",
      39             :                    createFastDAGScheduler);
      40             : static RegisterScheduler
      41      101169 :   linearizeDAGScheduler("linearize", "Linearize DAG, no scheduling",
      42             :                         createDAGLinearizer);
      43             : 
      44             : 
      45             : namespace {
      46             :   /// FastPriorityQueue - A degenerate priority queue that considers
      47             :   /// all nodes to have the same priority.
      48             :   ///
      49          34 :   struct FastPriorityQueue {
      50             :     SmallVector<SUnit *, 16> Queue;
      51             : 
      52         450 :     bool empty() const { return Queue.empty(); }
      53             : 
      54             :     void push(SUnit *U) {
      55         202 :       Queue.push_back(U);
      56             :     }
      57             : 
      58             :     SUnit *pop() {
      59         215 :       if (empty()) return nullptr;
      60         202 :       SUnit *V = Queue.back();
      61             :       Queue.pop_back();
      62             :       return V;
      63             :     }
      64             :   };
      65             : 
      66             : //===----------------------------------------------------------------------===//
      67             : /// ScheduleDAGFast - The actual "fast" list scheduler implementation.
      68             : ///
      69         102 : class ScheduleDAGFast : public ScheduleDAGSDNodes {
      70             : private:
      71             :   /// AvailableQueue - The priority queue to use for the available SUnits.
      72             :   FastPriorityQueue AvailableQueue;
      73             : 
      74             :   /// LiveRegDefs - A set of physical registers and their definition
      75             :   /// that are "live". These nodes must be scheduled before any other nodes that
      76             :   /// modifies the registers can be scheduled.
      77             :   unsigned NumLiveRegs;
      78             :   std::vector<SUnit*> LiveRegDefs;
      79             :   std::vector<unsigned> LiveRegCycles;
      80             : 
      81             : public:
      82             :   ScheduleDAGFast(MachineFunction &mf)
      83          34 :     : ScheduleDAGSDNodes(mf) {}
      84             : 
      85             :   void Schedule() override;
      86             : 
      87             :   /// AddPred - adds a predecessor edge to SUnit SU.
      88             :   /// This returns true if this is a new predecessor.
      89             :   void AddPred(SUnit *SU, const SDep &D) {
      90          73 :     SU->addPred(D);
      91             :   }
      92             : 
      93             :   /// RemovePred - removes a predecessor edge from SUnit SU.
      94             :   /// This returns true if an edge was removed.
      95             :   void RemovePred(SUnit *SU, const SDep &D) {
      96          23 :     SU->removePred(D);
      97             :   }
      98             : 
      99             : private:
     100             :   void ReleasePred(SUnit *SU, SDep *PredEdge);
     101             :   void ReleasePredecessors(SUnit *SU, unsigned CurCycle);
     102             :   void ScheduleNodeBottomUp(SUnit*, unsigned);
     103             :   SUnit *CopyAndMoveSuccessors(SUnit*);
     104             :   void InsertCopiesAndMoveSuccs(SUnit*, unsigned,
     105             :                                 const TargetRegisterClass*,
     106             :                                 const TargetRegisterClass*,
     107             :                                 SmallVectorImpl<SUnit*>&);
     108             :   bool DelayForLiveRegsBottomUp(SUnit*, SmallVectorImpl<unsigned>&);
     109             :   void ListScheduleBottomUp();
     110             : 
     111             :   /// forceUnitLatencies - The fast scheduler doesn't care about real latencies.
     112         204 :   bool forceUnitLatencies() const override { return true; }
     113             : };
     114             : }  // end anonymous namespace
     115             : 
     116             : 
     117             : /// Schedule - Schedule the DAG using list scheduling.
     118          34 : void ScheduleDAGFast::Schedule() {
     119             :   LLVM_DEBUG(dbgs() << "********** List Scheduling **********\n");
     120             : 
     121          34 :   NumLiveRegs = 0;
     122          34 :   LiveRegDefs.resize(TRI->getNumRegs(), nullptr);
     123          34 :   LiveRegCycles.resize(TRI->getNumRegs(), 0);
     124             : 
     125             :   // Build the scheduling graph.
     126          34 :   BuildSchedGraph(nullptr);
     127             : 
     128             :   LLVM_DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) SUnits[su]
     129             :                  .dumpAll(this));
     130             : 
     131             :   // Execute the actual scheduling loop.
     132          34 :   ListScheduleBottomUp();
     133          34 : }
     134             : 
     135             : //===----------------------------------------------------------------------===//
     136             : //  Bottom-Up Scheduling
     137             : //===----------------------------------------------------------------------===//
     138             : 
     139             : /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
     140             : /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
     141         226 : void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) {
     142             :   SUnit *PredSU = PredEdge->getSUnit();
     143             : 
     144             : #ifndef NDEBUG
     145             :   if (PredSU->NumSuccsLeft == 0) {
     146             :     dbgs() << "*** Scheduling failed! ***\n";
     147             :     PredSU->dump(this);
     148             :     dbgs() << " has been released too many times!\n";
     149             :     llvm_unreachable(nullptr);
     150             :   }
     151             : #endif
     152         226 :   --PredSU->NumSuccsLeft;
     153             : 
     154             :   // If all the node's successors are scheduled, this node is ready
     155             :   // to be scheduled. Ignore the special EntrySU node.
     156         226 :   if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
     157         171 :     PredSU->isAvailable = true;
     158             :     AvailableQueue.push(PredSU);
     159             :   }
     160         226 : }
     161             : 
     162         235 : void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigned CurCycle) {
     163             :   // Bottom up: release predecessors
     164         687 :   for (SDep &Pred : SU->Preds) {
     165         226 :     ReleasePred(SU, &Pred);
     166             :     if (Pred.isAssignedRegDep()) {
     167             :       // This is a physical register dependency and it's impossible or
     168             :       // expensive to copy the register. Make sure nothing that can
     169             :       // clobber the register is scheduled between the predecessor and
     170             :       // this node.
     171          60 :       if (!LiveRegDefs[Pred.getReg()]) {
     172          30 :         ++NumLiveRegs;
     173          60 :         LiveRegDefs[Pred.getReg()] = Pred.getSUnit();
     174          60 :         LiveRegCycles[Pred.getReg()] = CurCycle;
     175             :       }
     176             :     }
     177             :   }
     178         235 : }
     179             : 
     180             : /// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
     181             : /// count of its predecessors. If a predecessor pending count is zero, add it to
     182             : /// the Available queue.
     183         201 : void ScheduleDAGFast::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
     184             :   LLVM_DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
     185             :   LLVM_DEBUG(SU->dump(this));
     186             : 
     187             :   assert(CurCycle >= SU->getHeight() && "Node scheduled below its height!");
     188         201 :   SU->setHeightToAtLeast(CurCycle);
     189         201 :   Sequence.push_back(SU);
     190             : 
     191         201 :   ReleasePredecessors(SU, CurCycle);
     192             : 
     193             :   // Release all the implicit physical register defs that are live.
     194         898 :   for (SDep &Succ : SU->Succs) {
     195             :     if (Succ.isAssignedRegDep()) {
     196         144 :       if (LiveRegCycles[Succ.getReg()] == Succ.getSUnit()->getHeight()) {
     197             :         assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
     198             :         assert(LiveRegDefs[Succ.getReg()] == SU &&
     199             :                "Physical register dependency violated?");
     200          30 :         --NumLiveRegs;
     201          60 :         LiveRegDefs[Succ.getReg()] = nullptr;
     202          60 :         LiveRegCycles[Succ.getReg()] = 0;
     203             :       }
     204             :     }
     205             :   }
     206             : 
     207         201 :   SU->isScheduled = true;
     208         201 : }
     209             : 
     210             : /// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
     211             : /// successors to the newly created node.
     212          13 : SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) {
     213          13 :   if (SU->getNode()->getGluedNode())
     214             :     return nullptr;
     215             : 
     216             :   SDNode *N = SU->getNode();
     217             :   if (!N)
     218             :     return nullptr;
     219             : 
     220             :   SUnit *NewSU;
     221             :   bool TryUnfold = false;
     222           6 :   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
     223             :     MVT VT = N->getSimpleValueType(i);
     224           2 :     if (VT == MVT::Glue)
     225             :       return nullptr;
     226           2 :     else if (VT == MVT::Other)
     227             :       TryUnfold = true;
     228             :   }
     229           3 :   for (const SDValue &Op : N->op_values()) {
     230           2 :     MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
     231           2 :     if (VT == MVT::Glue)
     232             :       return nullptr;
     233             :   }
     234             : 
     235           1 :   if (TryUnfold) {
     236             :     SmallVector<SDNode*, 2> NewNodes;
     237           0 :     if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
     238             :       return nullptr;
     239             : 
     240             :     LLVM_DEBUG(dbgs() << "Unfolding SU # " << SU->NodeNum << "\n");
     241             :     assert(NewNodes.size() == 2 && "Expected a load folding node!");
     242             : 
     243           0 :     N = NewNodes[1];
     244           0 :     SDNode *LoadNode = NewNodes[0];
     245           0 :     unsigned NumVals = N->getNumValues();
     246           0 :     unsigned OldNumVals = SU->getNode()->getNumValues();
     247           0 :     for (unsigned i = 0; i != NumVals; ++i)
     248           0 :       DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i));
     249           0 :     DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals-1),
     250             :                                    SDValue(LoadNode, 1));
     251             : 
     252           0 :     SUnit *NewSU = newSUnit(N);
     253             :     assert(N->getNodeId() == -1 && "Node already inserted!");
     254           0 :     N->setNodeId(NewSU->NodeNum);
     255             : 
     256           0 :     const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
     257           0 :     for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
     258             :       if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
     259           0 :         NewSU->isTwoAddress = true;
     260           0 :         break;
     261             :       }
     262             :     }
     263           0 :     if (MCID.isCommutable())
     264           0 :       NewSU->isCommutable = true;
     265             : 
     266             :     // LoadNode may already exist. This can happen when there is another
     267             :     // load from the same location and producing the same type of value
     268             :     // but it has different alignment or volatileness.
     269             :     bool isNewLoad = true;
     270             :     SUnit *LoadSU;
     271           0 :     if (LoadNode->getNodeId() != -1) {
     272           0 :       LoadSU = &SUnits[LoadNode->getNodeId()];
     273             :       isNewLoad = false;
     274             :     } else {
     275           0 :       LoadSU = newSUnit(LoadNode);
     276           0 :       LoadNode->setNodeId(LoadSU->NodeNum);
     277             :     }
     278             : 
     279             :     SDep ChainPred;
     280             :     SmallVector<SDep, 4> ChainSuccs;
     281             :     SmallVector<SDep, 4> LoadPreds;
     282             :     SmallVector<SDep, 4> NodePreds;
     283             :     SmallVector<SDep, 4> NodeSuccs;
     284           0 :     for (SDep &Pred : SU->Preds) {
     285           0 :       if (Pred.isCtrl())
     286           0 :         ChainPred = Pred;
     287           0 :       else if (Pred.getSUnit()->getNode() &&
     288           0 :                Pred.getSUnit()->getNode()->isOperandOf(LoadNode))
     289           0 :         LoadPreds.push_back(Pred);
     290             :       else
     291           0 :         NodePreds.push_back(Pred);
     292             :     }
     293           0 :     for (SDep &Succ : SU->Succs) {
     294           0 :       if (Succ.isCtrl())
     295           0 :         ChainSuccs.push_back(Succ);
     296             :       else
     297           0 :         NodeSuccs.push_back(Succ);
     298             :     }
     299             : 
     300           0 :     if (ChainPred.getSUnit()) {
     301             :       RemovePred(SU, ChainPred);
     302           0 :       if (isNewLoad)
     303             :         AddPred(LoadSU, ChainPred);
     304             :     }
     305           0 :     for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) {
     306           0 :       const SDep &Pred = LoadPreds[i];
     307             :       RemovePred(SU, Pred);
     308           0 :       if (isNewLoad) {
     309             :         AddPred(LoadSU, Pred);
     310             :       }
     311             :     }
     312           0 :     for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) {
     313           0 :       const SDep &Pred = NodePreds[i];
     314             :       RemovePred(SU, Pred);
     315             :       AddPred(NewSU, Pred);
     316             :     }
     317           0 :     for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) {
     318           0 :       SDep D = NodeSuccs[i];
     319             :       SUnit *SuccDep = D.getSUnit();
     320             :       D.setSUnit(SU);
     321             :       RemovePred(SuccDep, D);
     322             :       D.setSUnit(NewSU);
     323             :       AddPred(SuccDep, D);
     324             :     }
     325           0 :     for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) {
     326           0 :       SDep D = ChainSuccs[i];
     327             :       SUnit *SuccDep = D.getSUnit();
     328             :       D.setSUnit(SU);
     329             :       RemovePred(SuccDep, D);
     330           0 :       if (isNewLoad) {
     331             :         D.setSUnit(LoadSU);
     332             :         AddPred(SuccDep, D);
     333             :       }
     334             :     }
     335           0 :     if (isNewLoad) {
     336             :       SDep D(LoadSU, SDep::Barrier);
     337           0 :       D.setLatency(LoadSU->Latency);
     338             :       AddPred(NewSU, D);
     339             :     }
     340             : 
     341             :     ++NumUnfolds;
     342             : 
     343           0 :     if (NewSU->NumSuccsLeft == 0) {
     344           0 :       NewSU->isAvailable = true;
     345             :       return NewSU;
     346             :     }
     347             :     SU = NewSU;
     348             :   }
     349             : 
     350             :   LLVM_DEBUG(dbgs() << "Duplicating SU # " << SU->NodeNum << "\n");
     351           1 :   NewSU = Clone(SU);
     352             : 
     353             :   // New SUnit has the exact same predecessors.
     354           3 :   for (SDep &Pred : SU->Preds)
     355             :     if (!Pred.isArtificial())
     356             :       AddPred(NewSU, Pred);
     357             : 
     358             :   // Only copy scheduled successors. Cut them from old node's successor
     359             :   // list and move them over.
     360             :   SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
     361           5 :   for (SDep &Succ : SU->Succs) {
     362           0 :     if (Succ.isArtificial())
     363             :       continue;
     364             :     SUnit *SuccSU = Succ.getSUnit();
     365           2 :     if (SuccSU->isScheduled) {
     366           1 :       SDep D = Succ;
     367             :       D.setSUnit(NewSU);
     368             :       AddPred(SuccSU, D);
     369             :       D.setSUnit(SU);
     370           1 :       DelDeps.push_back(std::make_pair(SuccSU, D));
     371             :     }
     372             :   }
     373           2 :   for (unsigned i = 0, e = DelDeps.size(); i != e; ++i)
     374           2 :     RemovePred(DelDeps[i].first, DelDeps[i].second);
     375             : 
     376             :   ++NumDups;
     377             :   return NewSU;
     378             : }
     379             : 
     380             : /// InsertCopiesAndMoveSuccs - Insert register copies and move all
     381             : /// scheduled successors of the given SUnit to the last copy.
     382          12 : void ScheduleDAGFast::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
     383             :                                               const TargetRegisterClass *DestRC,
     384             :                                               const TargetRegisterClass *SrcRC,
     385             :                                               SmallVectorImpl<SUnit*> &Copies) {
     386          12 :   SUnit *CopyFromSU = newSUnit(static_cast<SDNode *>(nullptr));
     387          12 :   CopyFromSU->CopySrcRC = SrcRC;
     388          12 :   CopyFromSU->CopyDstRC = DestRC;
     389             : 
     390          12 :   SUnit *CopyToSU = newSUnit(static_cast<SDNode *>(nullptr));
     391          12 :   CopyToSU->CopySrcRC = DestRC;
     392          12 :   CopyToSU->CopyDstRC = SrcRC;
     393             : 
     394             :   // Only copy scheduled successors. Cut them from old node's successor
     395             :   // list and move them over.
     396             :   SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
     397          88 :   for (SDep &Succ : SU->Succs) {
     398           0 :     if (Succ.isArtificial())
     399             :       continue;
     400             :     SUnit *SuccSU = Succ.getSUnit();
     401          38 :     if (SuccSU->isScheduled) {
     402          22 :       SDep D = Succ;
     403          22 :       D.setSUnit(CopyToSU);
     404             :       AddPred(SuccSU, D);
     405          22 :       DelDeps.push_back(std::make_pair(SuccSU, Succ));
     406             :     }
     407             :   }
     408          34 :   for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
     409          44 :     RemovePred(DelDeps[i].first, DelDeps[i].second);
     410             :   }
     411             :   SDep FromDep(SU, SDep::Data, Reg);
     412          12 :   FromDep.setLatency(SU->Latency);
     413          12 :   AddPred(CopyFromSU, FromDep);
     414          12 :   SDep ToDep(CopyFromSU, SDep::Data, 0);
     415          12 :   ToDep.setLatency(CopyFromSU->Latency);
     416          12 :   AddPred(CopyToSU, ToDep);
     417             : 
     418          12 :   Copies.push_back(CopyFromSU);
     419          12 :   Copies.push_back(CopyToSU);
     420             : 
     421             :   ++NumPRCopies;
     422          12 : }
     423             : 
     424             : /// getPhysicalRegisterVT - Returns the ValueType of the physical register
     425             : /// definition of the specified node.
     426             : /// FIXME: Move to SelectionDAG?
     427          13 : static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
     428             :                                  const TargetInstrInfo *TII) {
     429             :   unsigned NumRes;
     430          26 :   if (N->getOpcode() == ISD::CopyFromReg) {
     431             :     // CopyFromReg has: "chain, Val, glue" so operand 1 gives the type.
     432             :     NumRes = 1;
     433             :   } else {
     434           1 :     const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
     435             :     assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
     436           1 :     NumRes = MCID.getNumDefs();
     437           1 :     for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
     438           1 :       if (Reg == *ImpDef)
     439             :         break;
     440           0 :       ++NumRes;
     441             :     }
     442             :   }
     443          13 :   return N->getSimpleValueType(NumRes);
     444             : }
     445             : 
     446             : /// CheckForLiveRegDef - Return true and update live register vector if the
     447             : /// specified register def of the specified SUnit clobbers any "live" registers.
     448          65 : static bool CheckForLiveRegDef(SUnit *SU, unsigned Reg,
     449             :                                std::vector<SUnit*> &LiveRegDefs,
     450             :                                SmallSet<unsigned, 4> &RegAdded,
     451             :                                SmallVectorImpl<unsigned> &LRegs,
     452             :                                const TargetRegisterInfo *TRI) {
     453             :   bool Added = false;
     454         604 :   for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
     455         474 :     if (LiveRegDefs[*AI] && LiveRegDefs[*AI] != SU) {
     456          14 :       if (RegAdded.insert(*AI).second) {
     457          28 :         LRegs.push_back(*AI);
     458             :         Added = true;
     459             :       }
     460             :     }
     461             :   }
     462          65 :   return Added;
     463             : }
     464             : 
     465             : /// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay
     466             : /// scheduling of the given node to satisfy live physical register dependencies.
     467             : /// If the specific node is the last one that's available to schedule, do
     468             : /// whatever is necessary (i.e. backtracking or cloning) to make it possible.
     469         202 : bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
     470             :                                               SmallVectorImpl<unsigned> &LRegs){
     471         202 :   if (NumLiveRegs == 0)
     472             :     return false;
     473             : 
     474          39 :   SmallSet<unsigned, 4> RegAdded;
     475             :   // If this node would clobber any "live" register, then it's not ready.
     476         169 :   for (SDep &Pred : SU->Preds) {
     477             :     if (Pred.isAssignedRegDep()) {
     478           0 :       CheckForLiveRegDef(Pred.getSUnit(), Pred.getReg(), LiveRegDefs,
     479             :                          RegAdded, LRegs, TRI);
     480             :     }
     481             :   }
     482             : 
     483          39 :   for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) {
     484         176 :     if (Node->getOpcode() == ISD::INLINEASM) {
     485             :       // Inline asm can clobber physical defs.
     486           2 :       unsigned NumOps = Node->getNumOperands();
     487           4 :       if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
     488             :         --NumOps;  // Ignore the glue operand.
     489             : 
     490           8 :       for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
     491             :         unsigned Flags =
     492          18 :           cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
     493             :         unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
     494             : 
     495           6 :         ++i; // Skip the ID value.
     496           4 :         if (InlineAsm::isRegDefKind(Flags) ||
     497          10 :             InlineAsm::isRegDefEarlyClobberKind(Flags) ||
     498             :             InlineAsm::isClobberKind(Flags)) {
     499             :           // Check for def of register or earlyclobber register.
     500          12 :           for (; NumVals; --NumVals, ++i) {
     501           8 :             unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
     502           4 :             if (TargetRegisterInfo::isPhysicalRegister(Reg))
     503           2 :               CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
     504             :           }
     505             :         } else
     506           2 :           i += NumVals;
     507             :       }
     508           2 :       continue;
     509             :     }
     510          86 :     if (!Node->isMachineOpcode())
     511          48 :       continue;
     512          76 :     const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
     513          38 :     if (!MCID.ImplicitDefs)
     514           9 :       continue;
     515         155 :     for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) {
     516          63 :       CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
     517             :     }
     518             :   }
     519          39 :   return !LRegs.empty();
     520             : }
     521             : 
     522             : 
     523             : /// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
     524             : /// schedulers.
     525          34 : void ScheduleDAGFast::ListScheduleBottomUp() {
     526             :   unsigned CurCycle = 0;
     527             : 
     528             :   // Release any predecessors of the special Exit node.
     529          34 :   ReleasePredecessors(&ExitSU, CurCycle);
     530             : 
     531             :   // Add root to Available queue.
     532          34 :   if (!SUnits.empty()) {
     533          30 :     SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()];
     534             :     assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
     535          30 :     RootSU->isAvailable = true;
     536             :     AvailableQueue.push(RootSU);
     537             :   }
     538             : 
     539             :   // While Available queue is not empty, grab the node with the highest
     540             :   // priority. If it is not ready put it back.  Schedule the node.
     541             :   SmallVector<SUnit*, 4> NotReady;
     542             :   DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMap;
     543          68 :   Sequence.reserve(SUnits.size());
     544         436 :   while (!AvailableQueue.empty()) {
     545             :     bool Delayed = false;
     546         201 :     LRegsMap.clear();
     547         201 :     SUnit *CurSU = AvailableQueue.pop();
     548         215 :     while (CurSU) {
     549             :       SmallVector<unsigned, 4> LRegs;
     550         202 :       if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
     551             :         break;
     552             :       Delayed = true;
     553          42 :       LRegsMap.insert(std::make_pair(CurSU, LRegs));
     554             : 
     555          14 :       CurSU->isPending = true;  // This SU is not in AvailableQueue right now.
     556          14 :       NotReady.push_back(CurSU);
     557          14 :       CurSU = AvailableQueue.pop();
     558             :     }
     559             : 
     560             :     // All candidates are delayed due to live physical reg dependencies.
     561             :     // Try code duplication or inserting cross class copies
     562             :     // to resolve it.
     563         201 :     if (Delayed && !CurSU) {
     564             :       if (!CurSU) {
     565             :         // Try duplicating the nodes that produces these
     566             :         // "expensive to copy" values to break the dependency. In case even
     567             :         // that doesn't work, insert cross class copies.
     568          13 :         SUnit *TrySU = NotReady[0];
     569             :         SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU];
     570             :         assert(LRegs.size() == 1 && "Can't handle this yet!");
     571          13 :         unsigned Reg = LRegs[0];
     572          26 :         SUnit *LRDef = LiveRegDefs[Reg];
     573          13 :         MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
     574             :         const TargetRegisterClass *RC =
     575          13 :           TRI->getMinimalPhysRegClass(Reg, VT);
     576          13 :         const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
     577             : 
     578             :         // If cross copy register class is the same as RC, then it must be
     579             :         // possible copy the value directly. Do not try duplicate the def.
     580             :         // If cross copy register class is not the same as RC, then it's
     581             :         // possible to copy the value but it require cross register class copies
     582             :         // and it is expensive.
     583             :         // If cross copy register class is null, then it's not possible to copy
     584             :         // the value at all.
     585             :         SUnit *NewDef = nullptr;
     586          13 :         if (DestRC != RC) {
     587          13 :           NewDef = CopyAndMoveSuccessors(LRDef);
     588          13 :           if (!DestRC && !NewDef)
     589           0 :             report_fatal_error("Can't handle live physical "
     590             :                                "register dependency!");
     591             :         }
     592          13 :         if (!NewDef) {
     593             :           // Issue copies, these can be expensive cross register class copies.
     594             :           SmallVector<SUnit*, 2> Copies;
     595          12 :           InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
     596             :           LLVM_DEBUG(dbgs() << "Adding an edge from SU # " << TrySU->NodeNum
     597             :                             << " to SU #" << Copies.front()->NodeNum << "\n");
     598          36 :           AddPred(TrySU, SDep(Copies.front(), SDep::Artificial));
     599          12 :           NewDef = Copies.back();
     600             :         }
     601             : 
     602             :         LLVM_DEBUG(dbgs() << "Adding an edge from SU # " << NewDef->NodeNum
     603             :                           << " to SU #" << TrySU->NodeNum << "\n");
     604          26 :         LiveRegDefs[Reg] = NewDef;
     605          26 :         AddPred(NewDef, SDep(TrySU, SDep::Artificial));
     606          13 :         TrySU->isAvailable = false;
     607          13 :         CurSU = NewDef;
     608             :       }
     609             : 
     610          13 :       if (!CurSU) {
     611           0 :         llvm_unreachable("Unable to resolve live physical register dependencies!");
     612             :       }
     613             :     }
     614             : 
     615             :     // Add the nodes that aren't ready back onto the available list.
     616         215 :     for (unsigned i = 0, e = NotReady.size(); i != e; ++i) {
     617          28 :       NotReady[i]->isPending = false;
     618             :       // May no longer be available due to backtracking.
     619          14 :       if (NotReady[i]->isAvailable)
     620             :         AvailableQueue.push(NotReady[i]);
     621             :     }
     622             :     NotReady.clear();
     623             : 
     624         201 :     if (CurSU)
     625         201 :       ScheduleNodeBottomUp(CurSU, CurCycle);
     626         201 :     ++CurCycle;
     627             :   }
     628             : 
     629             :   // Reverse the order since it is bottom up.
     630             :   std::reverse(Sequence.begin(), Sequence.end());
     631             : 
     632             : #ifndef NDEBUG
     633             :   VerifyScheduledSequence(/*isBottomUp=*/true);
     634             : #endif
     635          34 : }
     636             : 
     637             : 
     638             : namespace {
     639             : //===----------------------------------------------------------------------===//
     640             : // ScheduleDAGLinearize - No scheduling scheduler, it simply linearize the
     641             : // DAG in topological order.
     642             : // IMPORTANT: this may not work for targets with phyreg dependency.
     643             : //
     644          42 : class ScheduleDAGLinearize : public ScheduleDAGSDNodes {
     645             : public:
     646          42 :   ScheduleDAGLinearize(MachineFunction &mf) : ScheduleDAGSDNodes(mf) {}
     647             : 
     648             :   void Schedule() override;
     649             : 
     650             :   MachineBasicBlock *
     651             :     EmitSchedule(MachineBasicBlock::iterator &InsertPos) override;
     652             : 
     653             : private:
     654             :   std::vector<SDNode*> Sequence;
     655             :   DenseMap<SDNode*, SDNode*> GluedMap;  // Cache glue to its user
     656             : 
     657             :   void ScheduleNode(SDNode *N);
     658             : };
     659             : } // end anonymous namespace
     660             : 
     661         610 : void ScheduleDAGLinearize::ScheduleNode(SDNode *N) {
     662         610 :   if (N->getNodeId() != 0)
     663           0 :     llvm_unreachable(nullptr);
     664             : 
     665         973 :   if (!N->isMachineOpcode() &&
     666         349 :       (N->getOpcode() == ISD::EntryToken || isPassiveNode(N)))
     667             :     // These nodes do not need to be translated into MIs.
     668             :     return;
     669             : 
     670             :   LLVM_DEBUG(dbgs() << "\n*** Scheduling: ");
     671             :   LLVM_DEBUG(N->dump(DAG));
     672         400 :   Sequence.push_back(N);
     673             : 
     674         400 :   unsigned NumOps = N->getNumOperands();
     675         400 :   if (unsigned NumLeft = NumOps) {
     676             :     SDNode *GluedOpN = nullptr;
     677             :     do {
     678        1150 :       const SDValue &Op = N->getOperand(NumLeft-1);
     679        1150 :       SDNode *OpN = Op.getNode();
     680             : 
     681        1211 :       if (NumLeft == NumOps && Op.getValueType() == MVT::Glue) {
     682             :         // Schedule glue operand right above N.
     683             :         GluedOpN = OpN;
     684             :         assert(OpN->getNodeId() != 0 && "Glue operand not ready?");
     685             :         OpN->setNodeId(0);
     686          61 :         ScheduleNode(OpN);
     687         129 :         continue;
     688             :       }
     689             : 
     690        1096 :       if (OpN == GluedOpN)
     691             :         // Glue operand is already scheduled.
     692           7 :         continue;
     693             : 
     694        1082 :       DenseMap<SDNode*, SDNode*>::iterator DI = GluedMap.find(OpN);
     695        1082 :       if (DI != GluedMap.end() && DI->second != N)
     696             :         // Users of glues are counted against the glued users.
     697             :         OpN = DI->second;
     698             : 
     699        1082 :       unsigned Degree = OpN->getNodeId();
     700             :       assert(Degree > 0 && "Predecessor over-released!");
     701        1082 :       OpN->setNodeId(--Degree);
     702        1082 :       if (Degree == 0)
     703         535 :         ScheduleNode(OpN);
     704        1150 :     } while (--NumLeft);
     705             :   }
     706             : }
     707             : 
     708             : /// findGluedUser - Find the representative use of a glue value by walking
     709             : /// the use chain.
     710             : static SDNode *findGluedUser(SDNode *N) {
     711         122 :   while (SDNode *Glued = N->getGluedUser())
     712             :     N = Glued;
     713             :   return N;
     714             : }
     715             : 
     716          14 : void ScheduleDAGLinearize::Schedule() {
     717             :   LLVM_DEBUG(dbgs() << "********** DAG Linearization **********\n");
     718             : 
     719             :   SmallVector<SDNode*, 8> Glues;
     720             :   unsigned DAGSize = 0;
     721         640 :   for (SDNode &Node : DAG->allnodes()) {
     722         612 :     SDNode *N = &Node;
     723             : 
     724             :     // Use node id to record degree.
     725             :     unsigned Degree = N->use_size();
     726         612 :     N->setNodeId(Degree);
     727         612 :     unsigned NumVals = N->getNumValues();
     728         673 :     if (NumVals && N->getValueType(NumVals-1) == MVT::Glue &&
     729          61 :         N->hasAnyUseOfValue(NumVals-1)) {
     730          61 :       SDNode *User = findGluedUser(N);
     731             :       if (User) {
     732          61 :         Glues.push_back(N);
     733         122 :         GluedMap.insert(std::make_pair(N, User));
     734             :       }
     735             :     }
     736             : 
     737         977 :     if (N->isMachineOpcode() ||
     738         351 :         (N->getOpcode() != ISD::EntryToken && !isPassiveNode(N)))
     739         400 :       ++DAGSize;
     740             :   }
     741             : 
     742          75 :   for (unsigned i = 0, e = Glues.size(); i != e; ++i) {
     743         122 :     SDNode *Glue = Glues[i];
     744         122 :     SDNode *GUser = GluedMap[Glue];
     745          61 :     unsigned Degree = Glue->getNodeId();
     746          61 :     unsigned UDegree = GUser->getNodeId();
     747             : 
     748             :     // Glue user must be scheduled together with the glue operand. So other
     749             :     // users of the glue operand must be treated as its users.
     750             :     SDNode *ImmGUser = Glue->getGluedUser();
     751         129 :     for (const SDNode *U : Glue->uses())
     752          68 :       if (U == ImmGUser)
     753          68 :         --Degree;
     754          61 :     GUser->setNodeId(UDegree + Degree);
     755             :     Glue->setNodeId(1);
     756             :   }
     757             : 
     758          14 :   Sequence.reserve(DAGSize);
     759          14 :   ScheduleNode(DAG->getRoot().getNode());
     760          14 : }
     761             : 
     762             : MachineBasicBlock*
     763          14 : ScheduleDAGLinearize::EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
     764          14 :   InstrEmitter Emitter(BB, InsertPos);
     765             :   DenseMap<SDValue, unsigned> VRBaseMap;
     766             : 
     767             :   LLVM_DEBUG({ dbgs() << "\n*** Final schedule ***\n"; });
     768             : 
     769          28 :   unsigned NumNodes = Sequence.size();
     770          14 :   MachineBasicBlock *BB = Emitter.getBlock();
     771         814 :   for (unsigned i = 0; i != NumNodes; ++i) {
     772         800 :     SDNode *N = Sequence[NumNodes-i-1];
     773             :     LLVM_DEBUG(N->dump(DAG));
     774         400 :     Emitter.EmitNode(N, false, false, VRBaseMap);
     775             : 
     776             :     // Emit any debug values associated with the node.
     777         400 :     if (N->getHasDebugValue()) {
     778             :       MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
     779           6 :       for (auto DV : DAG->GetDbgValues(N)) {
     780           2 :         if (DV->isInvalidated())
     781           0 :           continue;
     782           2 :         if (auto *DbgMI = Emitter.EmitDbgValue(DV, VRBaseMap))
     783             :           BB->insert(InsertPos, DbgMI);
     784             :         DV->setIsInvalidated();
     785             :       }
     786             :     }
     787             :   }
     788             : 
     789             :   LLVM_DEBUG(dbgs() << '\n');
     790             : 
     791          14 :   InsertPos = Emitter.getInsertPos();
     792          28 :   return Emitter.getBlock();
     793             : }
     794             : 
     795             : //===----------------------------------------------------------------------===//
     796             : //                         Public Constructor Functions
     797             : //===----------------------------------------------------------------------===//
     798             : 
     799             : llvm::ScheduleDAGSDNodes *
     800          34 : llvm::createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
     801          68 :   return new ScheduleDAGFast(*IS->MF);
     802             : }
     803             : 
     804             : llvm::ScheduleDAGSDNodes *
     805          14 : llvm::createDAGLinearizer(SelectionDAGISel *IS, CodeGenOpt::Level) {
     806          14 :   return new ScheduleDAGLinearize(*IS->MF);
     807      303507 : }

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