LCOV - code coverage report
Current view: top level - lib/CodeGen/SelectionDAG - ScheduleDAGSDNodes.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 433 441 98.2 %
Date: 2017-09-14 15:23:50 Functions: 25 27 92.6 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This implements the ScheduleDAG class, which is a base class used by
      11             : // scheduling implementation classes.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "ScheduleDAGSDNodes.h"
      16             : #include "InstrEmitter.h"
      17             : #include "SDNodeDbgValue.h"
      18             : #include "llvm/ADT/DenseMap.h"
      19             : #include "llvm/ADT/SmallPtrSet.h"
      20             : #include "llvm/ADT/SmallSet.h"
      21             : #include "llvm/ADT/SmallVector.h"
      22             : #include "llvm/ADT/Statistic.h"
      23             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      24             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      25             : #include "llvm/CodeGen/SelectionDAG.h"
      26             : #include "llvm/MC/MCInstrItineraries.h"
      27             : #include "llvm/Support/CommandLine.h"
      28             : #include "llvm/Support/Debug.h"
      29             : #include "llvm/Support/raw_ostream.h"
      30             : #include "llvm/Target/TargetInstrInfo.h"
      31             : #include "llvm/Target/TargetLowering.h"
      32             : #include "llvm/Target/TargetRegisterInfo.h"
      33             : #include "llvm/Target/TargetSubtargetInfo.h"
      34             : using namespace llvm;
      35             : 
      36             : #define DEBUG_TYPE "pre-RA-sched"
      37             : 
      38             : STATISTIC(LoadsClustered, "Number of loads clustered together");
      39             : 
      40             : // This allows the latency-based scheduler to notice high latency instructions
      41             : // without a target itinerary. The choice of number here has more to do with
      42             : // balancing scheduler heuristics than with the actual machine latency.
      43       72306 : static cl::opt<int> HighLatencyCycles(
      44      216918 :   "sched-high-latency-cycles", cl::Hidden, cl::init(10),
      45      216918 :   cl::desc("Roughly estimate the number of cycles that 'long latency'"
      46       72306 :            "instructions take for targets with no itinerary"));
      47             : 
      48      280008 : ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
      49             :     : ScheduleDAG(mf), BB(nullptr), DAG(nullptr),
      50      560016 :       InstrItins(mf.getSubtarget().getInstrItineraryData()) {}
      51             : 
      52             : /// Run - perform scheduling.
      53             : ///
      54      280008 : void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb) {
      55      280008 :   BB = bb;
      56      280008 :   DAG = dag;
      57             : 
      58             :   // Clear the scheduler's SUnit DAG.
      59      280008 :   ScheduleDAG::clearDAG();
      60      560016 :   Sequence.clear();
      61             : 
      62             :   // Invoke the target's selection of scheduler.
      63      280008 :   Schedule();
      64      280008 : }
      65             : 
      66             : /// NewSUnit - Creates a new SUnit and return a ptr to it.
      67             : ///
      68     3575904 : SUnit *ScheduleDAGSDNodes::newSUnit(SDNode *N) {
      69             : #ifndef NDEBUG
      70             :   const SUnit *Addr = nullptr;
      71             :   if (!SUnits.empty())
      72             :     Addr = &SUnits[0];
      73             : #endif
      74     7151808 :   SUnits.emplace_back(N, (unsigned)SUnits.size());
      75             :   assert((Addr == nullptr || Addr == &SUnits[0]) &&
      76             :          "SUnits std::vector reallocated on the fly!");
      77    10727712 :   SUnits.back().OrigNode = &SUnits.back();
      78     7151808 :   SUnit *SU = &SUnits.back();
      79     3575904 :   const TargetLowering &TLI = DAG->getTargetLoweringInfo();
      80     7151590 :   if (!N ||
      81     6291996 :       (N->isMachineOpcode() &&
      82     2716310 :        N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
      83       19146 :     SU->SchedulingPref = Sched::None;
      84             :   else
      85     3556758 :     SU->SchedulingPref = TLI.getSchedulingPreference(N);
      86     3575904 :   return SU;
      87             : }
      88             : 
      89       19106 : SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
      90       19106 :   SUnit *SU = newSUnit(Old->getNode());
      91       19106 :   SU->OrigNode = Old->OrigNode;
      92       19106 :   SU->Latency = Old->Latency;
      93       19106 :   SU->isVRegCycle = Old->isVRegCycle;
      94       19106 :   SU->isCall = Old->isCall;
      95       19106 :   SU->isCallOp = Old->isCallOp;
      96       19106 :   SU->isTwoAddress = Old->isTwoAddress;
      97       19106 :   SU->isCommutable = Old->isCommutable;
      98       19106 :   SU->hasPhysRegDefs = Old->hasPhysRegDefs;
      99       19106 :   SU->hasPhysRegClobbers = Old->hasPhysRegClobbers;
     100       19106 :   SU->isScheduleHigh = Old->isScheduleHigh;
     101       19106 :   SU->isScheduleLow = Old->isScheduleLow;
     102       19106 :   SU->SchedulingPref = Old->SchedulingPref;
     103       19106 :   Old->isCloned = true;
     104       19106 :   return SU;
     105             : }
     106             : 
     107             : /// CheckForPhysRegDependency - Check if the dependency between def and use of
     108             : /// a specified operand is a physical register dependency. If so, returns the
     109             : /// register and the cost of copying the register.
     110     4552435 : static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
     111             :                                       const TargetRegisterInfo *TRI,
     112             :                                       const TargetInstrInfo *TII,
     113             :                                       unsigned &PhysReg, int &Cost) {
     114     4552435 :   if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
     115             :     return;
     116             : 
     117     1903782 :   unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
     118      634594 :   if (TargetRegisterInfo::isVirtualRegister(Reg))
     119             :     return;
     120             : 
     121     1034418 :   unsigned ResNo = User->getOperand(2).getResNo();
     122     1075395 :   if (Def->getOpcode() == ISD::CopyFromReg &&
     123      122931 :       cast<RegisterSDNode>(Def->getOperand(1))->getReg() == Reg) {
     124        4531 :     PhysReg = Reg;
     125      512678 :   } else if (Def->isMachineOpcode()) {
     126     1428696 :     const MCInstrDesc &II = TII->get(Def->getMachineOpcode());
     127      600793 :     if (ResNo >= II.getNumDefs() &&
     128      124561 :         II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg)
     129      124550 :       PhysReg = Reg;
     130             :   }
     131             : 
     132      517209 :   if (PhysReg != 0) {
     133             :     const TargetRegisterClass *RC =
     134      129081 :         TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo));
     135      258162 :     Cost = RC->getCopyCost();
     136             :   }
     137             : }
     138             : 
     139             : // Helper for AddGlue to clone node operands.
     140       50676 : static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef<EVT> VTs,
     141             :                                 SDValue ExtraOper = SDValue()) {
     142      202704 :   SmallVector<SDValue, 8> Ops(N->op_begin(), N->op_end());
     143       50676 :   if (ExtraOper.getNode())
     144       21751 :     Ops.push_back(ExtraOper);
     145             : 
     146       50676 :   SDVTList VTList = DAG->getVTList(VTs);
     147       50676 :   MachineSDNode::mmo_iterator Begin = nullptr, End = nullptr;
     148       50676 :   MachineSDNode *MN = dyn_cast<MachineSDNode>(N);
     149             : 
     150             :   // Store memory references.
     151             :   if (MN) {
     152       50676 :     Begin = MN->memoperands_begin();
     153       50676 :     End = MN->memoperands_end();
     154             :   }
     155             : 
     156      101352 :   DAG->MorphNodeTo(N, N->getOpcode(), VTList, Ops);
     157             : 
     158             :   // Reset the memory references
     159       50676 :   if (MN)
     160       50676 :     MN->setMemRefs(Begin, End);
     161       50676 : }
     162             : 
     163       89743 : static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) {
     164       89743 :   SDNode *GlueDestNode = Glue.getNode();
     165             : 
     166             :   // Don't add glue from a node to itself.
     167       89743 :   if (GlueDestNode == N) return false;
     168             : 
     169             :   // Don't add a glue operand to something that already uses glue.
     170       89742 :   if (GlueDestNode &&
     171       87120 :       N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
     172             :     return false;
     173             :   }
     174             :   // Don't add glue to something that already has a glue value.
     175      358944 :   if (N->getValueType(N->getNumValues() - 1) == MVT::Glue) return false;
     176             : 
     177      151965 :   SmallVector<EVT, 4> VTs(N->value_begin(), N->value_end());
     178       50655 :   if (AddGlue)
     179       21772 :     VTs.push_back(MVT::Glue);
     180             : 
     181       50655 :   CloneNodeWithValues(N, DAG, VTs, Glue);
     182             : 
     183       50655 :   return true;
     184             : }
     185             : 
     186             : // Cleanup after unsuccessful AddGlue. Use the standard method of morphing the
     187             : // node even though simply shrinking the value list is sufficient.
     188          21 : static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) {
     189             :   assert((N->getValueType(N->getNumValues() - 1) == MVT::Glue &&
     190             :           !N->hasAnyUseOfValue(N->getNumValues() - 1)) &&
     191             :          "expected an unused glue value");
     192             : 
     193          42 :   CloneNodeWithValues(N, DAG,
     194          42 :                       makeArrayRef(N->value_begin(), N->getNumValues() - 1));
     195          21 : }
     196             : 
     197             : /// ClusterNeighboringLoads - Force nearby loads together by "gluing" them.
     198             : /// This function finds loads of the same base and different offsets. If the
     199             : /// offsets are not far apart (target specific), it add MVT::Glue inputs and
     200             : /// outputs to ensure they are scheduled together and in order. This
     201             : /// optimization may benefit some targets by improving cache locality.
     202      465411 : void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
     203      465411 :   SDNode *Chain = nullptr;
     204      930822 :   unsigned NumOps = Node->getNumOperands();
     205     1477020 :   if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
     206      769248 :     Chain = Node->getOperand(NumOps-1).getNode();
     207      465411 :   if (!Chain)
     208      436507 :     return;
     209             : 
     210             :   // Look for other loads of the same chain. Find loads that are loading from
     211             :   // the same base pointer and different offsets.
     212      413528 :   SmallPtrSet<SDNode*, 16> Visited;
     213      413528 :   SmallVector<int64_t, 4> Offsets;
     214      413528 :   DenseMap<long long, SDNode*> O2SMap;  // Map from offset to SDNode.
     215      384624 :   bool Cluster = false;
     216      384624 :   SDNode *Base = Node;
     217             :   // This algorithm requires a reasonably low use count before finding a match
     218             :   // to avoid uselessly blowing up compile time in large blocks.
     219      384624 :   unsigned UseCount = 0;
     220     3022276 :   for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end();
     221     3022276 :        I != E && UseCount < 100; ++I, ++UseCount) {
     222     2637652 :     SDNode *User = *I;
     223     3031145 :     if (User == Node || !Visited.insert(User).second)
     224     2701852 :       continue;
     225             :     int64_t Offset1, Offset2;
     226     4488370 :     if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
     227      329345 :         Offset1 == Offset2)
     228             :       // FIXME: Should be ok if they addresses are identical. But earlier
     229             :       // optimizations really should have eliminated one of the loads.
     230     1914866 :       continue;
     231     1317172 :     if (O2SMap.insert(std::make_pair(Offset1, Base)).second)
     232       29642 :       Offsets.push_back(Offset1);
     233     1317172 :     O2SMap.insert(std::make_pair(Offset2, User));
     234      329293 :     Offsets.push_back(Offset2);
     235      329293 :     if (Offset2 < Offset1)
     236       45407 :       Base = User;
     237      329293 :     Cluster = true;
     238             :     // Reset UseCount to allow more matches.
     239      329293 :     UseCount = 0;
     240             :   }
     241             : 
     242      384624 :   if (!Cluster)
     243      355720 :     return;
     244             : 
     245             :   // Sort them in increasing order.
     246       88926 :   std::sort(Offsets.begin(), Offsets.end());
     247             : 
     248             :   // Check if the loads are close enough.
     249       58546 :   SmallVector<SDNode*, 4> Loads;
     250       29642 :   unsigned NumLoads = 0;
     251       29642 :   int64_t BaseOff = Offsets[0];
     252       59284 :   SDNode *BaseLoad = O2SMap[BaseOff];
     253       29642 :   Loads.push_back(BaseLoad);
     254      120123 :   for (unsigned i = 1, e = Offsets.size(); i != e; ++i) {
     255      133640 :     int64_t Offset = Offsets[i];
     256      133640 :     SDNode *Load = O2SMap[Offset];
     257       66820 :     if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads))
     258             :       break; // Stop right here. Ignore loads that are further away.
     259       60839 :     Loads.push_back(Load);
     260       60839 :     ++NumLoads;
     261             :   }
     262             : 
     263       29642 :   if (NumLoads == 0)
     264             :     return;
     265             : 
     266             :   // Cluster loads by adding MVT::Glue outputs and inputs. This also
     267             :   // ensure they are scheduled in order of increasing addresses.
     268       28904 :   SDNode *Lead = Loads[0];
     269       28904 :   SDValue InGlue = SDValue(nullptr, 0);
     270       28904 :   if (AddGlue(Lead, InGlue, true, DAG))
     271       28396 :     InGlue = SDValue(Lead, Lead->getNumValues() - 1);
     272      118647 :   for (unsigned I = 1, E = Loads.size(); I != E; ++I) {
     273       60839 :     bool OutGlue = I < E - 1;
     274      121678 :     SDNode *Load = Loads[I];
     275             : 
     276             :     // If AddGlue fails, we could leave an unsused glue value. This should not
     277             :     // cause any
     278       60839 :     if (AddGlue(Load, InGlue, OutGlue, DAG)) {
     279       36457 :       if (OutGlue)
     280       15148 :         InGlue = SDValue(Load, Load->getNumValues() - 1);
     281             : 
     282             :       ++LoadsClustered;
     283             :     }
     284       24382 :     else if (!OutGlue && InGlue.getNode())
     285          21 :       RemoveUnusedGlue(InGlue.getNode(), DAG);
     286             :   }
     287             : }
     288             : 
     289             : /// ClusterNodes - Cluster certain nodes which should be scheduled together.
     290             : ///
     291      279998 : void ScheduleDAGSDNodes::ClusterNodes() {
     292     8773940 :   for (SDNode &NI : DAG->allnodes()) {
     293     8213944 :     SDNode *Node = &NI;
     294    13484964 :     if (!Node || !Node->isMachineOpcode())
     295     5271020 :       continue;
     296             : 
     297     5885848 :     unsigned Opc = Node->getMachineOpcode();
     298     5885848 :     const MCInstrDesc &MCID = TII->get(Opc);
     299     2942924 :     if (MCID.mayLoad())
     300             :       // Cluster loads from "near" addresses into combined SUnits.
     301      465411 :       ClusterNeighboringLoads(Node);
     302             :   }
     303      279998 : }
     304             : 
     305      279998 : void ScheduleDAGSDNodes::BuildSchedUnits() {
     306             :   // During scheduling, the NodeId field of SDNode is used to map SDNodes
     307             :   // to their associated SUnits by holding SUnits table indices. A value
     308             :   // of -1 means the SDNode does not yet have an associated SUnit.
     309      279998 :   unsigned NumNodes = 0;
     310     8773940 :   for (SDNode &NI : DAG->allnodes()) {
     311    16427888 :     NI.setNodeId(-1);
     312     8213944 :     ++NumNodes;
     313             :   }
     314             : 
     315             :   // Reserve entries in the vector for each of the SUnits we are creating.  This
     316             :   // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
     317             :   // invalidated.
     318             :   // FIXME: Multiply by 2 because we may clone nodes during scheduling.
     319             :   // This is a temporary workaround.
     320      279998 :   SUnits.reserve(NumNodes * 2);
     321             : 
     322             :   // Add all nodes in depth first order.
     323      559996 :   SmallVector<SDNode*, 64> Worklist;
     324      559996 :   SmallPtrSet<SDNode*, 32> Visited;
     325      279998 :   Worklist.push_back(DAG->getRoot().getNode());
     326      279998 :   Visited.insert(DAG->getRoot().getNode());
     327             : 
     328      279998 :   SmallVector<SUnit*, 8> CallSUnits;
     329     8476930 :   while (!Worklist.empty()) {
     330     8196932 :     SDNode *NI = Worklist.pop_back_val();
     331             : 
     332             :     // Add all operands to the worklist unless they've already been added.
     333    50749340 :     for (const SDValue &Op : NI->op_values())
     334    17177738 :       if (Visited.insert(Op.getNode()).second)
     335     7916934 :         Worklist.push_back(Op.getNode());
     336             : 
     337     8196932 :     if (isPassiveNode(NI))  // Leaf node, e.g. a TargetImmediate.
     338     8438898 :       continue;
     339             : 
     340             :     // If this node has already been processed, stop now.
     341     4410784 :     if (NI->getNodeId() != -1) continue;
     342             : 
     343     3544182 :     SUnit *NodeSUnit = newSUnit(NI);
     344             : 
     345             :     // See if anything is glued to this node, if so, add them to glued
     346             :     // nodes.  Nodes can have at most one glue input and one glue output.  Glue
     347             :     // is required to be the last operand and result of a node.
     348             : 
     349             :     // Scan up to find glued preds.
     350     3544182 :     SDNode *N = NI;
     351     8800862 :     while (N->getNumOperands() &&
     352    13005471 :            N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
     353     1712498 :       N = N->getOperand(N->getNumOperands()-1).getNode();
     354             :       assert(N->getNodeId() == -1 && "Node already inserted!");
     355     1712498 :       N->setNodeId(NodeSUnit->NodeNum);
     356     1604539 :       if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
     357      186230 :         NodeSUnit->isCall = true;
     358             :     }
     359             : 
     360             :     // Scan down to find any glued succs.
     361             :     N = NI;
     362    13823898 :     while (N->getValueType(N->getNumValues()-1) == MVT::Glue) {
     363     1213785 :       SDValue GlueVal(N, N->getNumValues()-1);
     364             : 
     365             :       // There are either zero or one users of the Glue result.
     366      404595 :       bool HasGlueUse = false;
     367      404595 :       for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
     368     1001199 :            UI != E; ++UI)
     369      606957 :         if (GlueVal.isOperandOf(*UI)) {
     370       10353 :           HasGlueUse = true;
     371             :           assert(N->getNodeId() == -1 && "Node already inserted!");
     372       20706 :           N->setNodeId(NodeSUnit->NodeNum);
     373       10353 :           N = *UI;
     374       28539 :           if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
     375           0 :             NodeSUnit->isCall = true;
     376             :           break;
     377             :         }
     378      404595 :       if (!HasGlueUse) break;
     379             :     }
     380             : 
     381     3544182 :     if (NodeSUnit->isCall)
     382      186230 :       CallSUnits.push_back(NodeSUnit);
     383             : 
     384             :     // Schedule zero-latency TokenFactor below any nodes that may increase the
     385             :     // schedule height. Otherwise, ancestors of the TokenFactor may appear to
     386             :     // have false stalls.
     387     3544182 :     if (NI->getOpcode() == ISD::TokenFactor)
     388      217978 :       NodeSUnit->isScheduleLow = true;
     389             : 
     390             :     // If there are glue operands involved, N is now the bottom-most node
     391             :     // of the sequence of nodes that are glued together.
     392             :     // Update the SUnit.
     393     7088364 :     NodeSUnit->setNode(N);
     394             :     assert(N->getNodeId() == -1 && "Node already inserted!");
     395     7088364 :     N->setNodeId(NodeSUnit->NodeNum);
     396             : 
     397             :     // Compute NumRegDefsLeft. This must be done before AddSchedEdges.
     398     3544182 :     InitNumRegDefsLeft(NodeSUnit);
     399             : 
     400             :     // Assign the Latency field of NodeSUnit using target-provided information.
     401     3544182 :     computeLatency(NodeSUnit);
     402             :   }
     403             : 
     404             :   // Find all call operands.
     405      466228 :   while (!CallSUnits.empty()) {
     406      186230 :     SUnit *SU = CallSUnits.pop_back_val();
     407      186230 :     for (const SDNode *SUNode = SU->getNode(); SUNode;
     408             :          SUNode = SUNode->getGluedNode()) {
     409      764240 :       if (SUNode->getOpcode() != ISD::CopyToReg)
     410      402958 :         continue;
     411      722564 :       SDNode *SrcN = SUNode->getOperand(2).getNode();
     412      361282 :       if (isPassiveNode(SrcN)) continue;   // Not scheduled.
     413      557658 :       SUnit *SrcSU = &SUnits[SrcN->getNodeId()];
     414      278829 :       SrcSU->isCallOp = true;
     415             :     }
     416             :   }
     417      279998 : }
     418             : 
     419      279998 : void ScheduleDAGSDNodes::AddSchedEdges() {
     420      279998 :   const TargetSubtargetInfo &ST = MF.getSubtarget();
     421             : 
     422             :   // Check to see if the scheduler cares about latencies.
     423      279998 :   bool UnitLatencies = forceUnitLatencies();
     424             : 
     425             :   // Pass 2: add the preds, succs, etc.
     426     4104178 :   for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
     427     7088364 :     SUnit *SU = &SUnits[su];
     428     3544182 :     SDNode *MainNode = SU->getNode();
     429             : 
     430     3544182 :     if (MainNode->isMachineOpcode()) {
     431     2681794 :       unsigned Opc = MainNode->getMachineOpcode();
     432     5363588 :       const MCInstrDesc &MCID = TII->get(Opc);
     433    25790490 :       for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
     434    10638245 :         if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
     435      212397 :           SU->isTwoAddress = true;
     436      212397 :           break;
     437             :         }
     438             :       }
     439     2681794 :       if (MCID.isCommutable())
     440      111518 :         SU->isCommutable = true;
     441             :     }
     442             : 
     443             :     // Find all predecessors and successors of the group.
     444     4410784 :     for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) {
     445     7351082 :       if (N->isMachineOpcode() &&
     446     8820894 :           TII->get(N->getMachineOpcode()).getImplicitDefs()) {
     447      746556 :         SU->hasPhysRegClobbers = true;
     448      746556 :         unsigned NumUsed = InstrEmitter::CountResults(N);
     449     1345483 :         while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1))
     450             :           --NumUsed;    // Skip over unused values at the end.
     451     2986224 :         if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
     452      104729 :           SU->hasPhysRegDefs = true;
     453             :       }
     454             : 
     455    25999306 :       for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
     456    34355476 :         SDNode *OpN = N->getOperand(i).getNode();
     457    29803041 :         if (isPassiveNode(OpN)) continue;   // Not scheduled.
     458    12415762 :         SUnit *OpSU = &SUnits[OpN->getNodeId()];
     459             :         assert(OpSU && "Node has no SUnit!");
     460     6207881 :         if (OpSU == SU) continue;           // In the same group.
     461             : 
     462    13657305 :         EVT OpVT = N->getOperand(i).getValueType();
     463             :         assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
     464     9104870 :         bool isChain = OpVT == MVT::Other;
     465             : 
     466     4552435 :         unsigned PhysReg = 0;
     467     4552435 :         int Cost = 1;
     468             :         // Determine if this is a physical register dependency.
     469     4552435 :         CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
     470             :         assert((PhysReg == 0 || !isChain) &&
     471             :                "Chain dependence via physreg data?");
     472             :         // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
     473             :         // emits a copy from the physical register to a virtual register unless
     474             :         // it requires a cross class copy (cost < 0). That means we are only
     475             :         // treating "expensive to copy" register dependency as physical register
     476             :         // dependency. This may change in the future though.
     477     4552435 :         if (Cost >= 0 && !StressSched)
     478     4427392 :           PhysReg = 0;
     479             : 
     480             :         // If this is a ctrl dep, latency is 1.
     481     4552435 :         unsigned OpLatency = isChain ? 1 : OpSU->Latency;
     482             :         // Special-case TokenFactor chains as zero-latency.
     483     4552435 :         if(isChain && OpN->getOpcode() == ISD::TokenFactor)
     484             :           OpLatency = 0;
     485             : 
     486             :         SDep Dep = isChain ? SDep(OpSU, SDep::Barrier)
     487     7181385 :           : SDep(OpSU, SDep::Data, PhysReg);
     488     9104870 :         Dep.setLatency(OpLatency);
     489     4552435 :         if (!isChain && !UnitLatencies) {
     490      171684 :           computeOperandLatency(OpN, N, i, Dep);
     491      171684 :           ST.adjustSchedDependency(OpSU, SU, Dep);
     492             :         }
     493             : 
     494     4651160 :         if (!SU->addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) {
     495             :           // Multiple register uses are combined in the same SUnit. For example,
     496             :           // we could have a set of glued nodes with all their defs consumed by
     497             :           // another set of glued nodes. Register pressure tracking sees this as
     498             :           // a single use, so to keep pressure balanced we reduce the defs.
     499             :           //
     500             :           // We can't tell (without more book-keeping) if this results from
     501             :           // glued nodes or duplicate operands. As long as we don't reduce
     502             :           // NumRegDefsLeft to zero, we handle the common cases well.
     503       14817 :           --OpSU->NumRegDefsLeft;
     504             :         }
     505             :       }
     506             :     }
     507             :   }
     508      279998 : }
     509             : 
     510             : /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
     511             : /// are input.  This SUnit graph is similar to the SelectionDAG, but
     512             : /// excludes nodes that aren't interesting to scheduling, and represents
     513             : /// glued together nodes with a single SUnit.
     514      279998 : void ScheduleDAGSDNodes::BuildSchedGraph(AliasAnalysis *AA) {
     515             :   // Cluster certain nodes which should be scheduled together.
     516      279998 :   ClusterNodes();
     517             :   // Populate the SUnits array.
     518      279998 :   BuildSchedUnits();
     519             :   // Compute all the scheduling dependencies between nodes.
     520      279998 :   AddSchedEdges();
     521      279998 : }
     522             : 
     523             : // Initialize NumNodeDefs for the current Node's opcode.
     524     5359391 : void ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() {
     525             :   // Check for phys reg copy.
     526     5359391 :   if (!Node)
     527     1816350 :     return;
     528             : 
     529     5359391 :   if (!Node->isMachineOpcode()) {
     530     3592646 :     if (Node->getOpcode() == ISD::CopyFromReg)
     531      672219 :       NodeNumDefs = 1;
     532             :     else
     533     1124104 :       NodeNumDefs = 0;
     534             :     return;
     535             :   }
     536     7126136 :   unsigned POpc = Node->getMachineOpcode();
     537     3563068 :   if (POpc == TargetOpcode::IMPLICIT_DEF) {
     538             :     // No register need be allocated for this.
     539       19936 :     NodeNumDefs = 0;
     540       19936 :     return;
     541             :   }
     542     3543132 :   if (POpc == TargetOpcode::PATCHPOINT &&
     543         292 :       Node->getValueType(0) == MVT::Other) {
     544             :     // PATCHPOINT is defined to have one result, but it might really have none
     545             :     // if we're not using CallingConv::AnyReg. Don't mistake the chain for a
     546             :     // real definition.
     547          91 :     NodeNumDefs = 0;
     548          91 :     return;
     549             :   }
     550    10629123 :   unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
     551             :   // Some instructions define regs that are not represented in the selection DAG
     552             :   // (e.g. unused flags). See tMOVi8. Make sure we don't access past NumValues.
     553    10629123 :   NodeNumDefs = std::min(Node->getNumValues(), NRegDefs);
     554     3543041 :   DefIdx = 0;
     555             : }
     556             : 
     557             : // Construct a RegDefIter for this SUnit and find the first valid value.
     558     4324198 : ScheduleDAGSDNodes::RegDefIter::RegDefIter(const SUnit *SU,
     559     4324198 :                                            const ScheduleDAGSDNodes *SD)
     560     8648396 :   : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
     561     4324198 :   InitNodeNumDefs();
     562     4324198 :   Advance();
     563     4324198 : }
     564             : 
     565             : // Advance to the next valid value defined by the SUnit.
     566     6776029 : void ScheduleDAGSDNodes::RegDefIter::Advance() {
     567     8846415 :   for (;Node;) { // Visit all glued nodes.
     568     7876690 :     for (;DefIdx < NodeNumDefs; ++DefIdx) {
     569     2642305 :       if (!Node->hasAnyUseOfValue(DefIdx))
     570             :         continue;
     571     5219142 :       ValueType = Node->getSimpleValueType(DefIdx);
     572     2609571 :       ++DefIdx;
     573     2609571 :       return; // Found a normal regdef.
     574             :     }
     575    10403302 :     Node = Node->getGluedNode();
     576     5201651 :     if (!Node) {
     577             :       return; // No values left to visit.
     578             :     }
     579     1035193 :     InitNodeNumDefs();
     580             :   }
     581             : }
     582             : 
     583     3556580 : void ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) {
     584             :   assert(SU->NumRegDefsLeft == 0 && "expect a new node");
     585     5440386 :   for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) {
     586             :     assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected");
     587     1883806 :     ++SU->NumRegDefsLeft;
     588             :   }
     589     3556580 : }
     590             : 
     591     3556580 : void ScheduleDAGSDNodes::computeLatency(SUnit *SU) {
     592     3556580 :   SDNode *N = SU->getNode();
     593             : 
     594             :   // TokenFactor operands are considered zero latency, and some schedulers
     595             :   // (e.g. Top-Down list) may rely on the fact that operand latency is nonzero
     596             :   // whenever node latency is nonzero.
     597     3556580 :   if (N && N->getOpcode() == ISD::TokenFactor) {
     598      217978 :     SU->Latency = 0;
     599      217978 :     return;
     600             :   }
     601             : 
     602             :   // Check to see if the scheduler cares about latencies.
     603     3338602 :   if (forceUnitLatencies()) {
     604     3136488 :     SU->Latency = 1;
     605     3136488 :     return;
     606             :   }
     607             : 
     608      202114 :   if (!InstrItins || InstrItins->isEmpty()) {
     609      213335 :     if (N && N->isMachineOpcode() &&
     610      188524 :         TII->isHighLatencyDef(N->getMachineOpcode()))
     611           0 :       SU->Latency = HighLatencyCycles;
     612             :     else
     613      119073 :       SU->Latency = 1;
     614             :     return;
     615             :   }
     616             : 
     617             :   // Compute the latency for the node.  We use the sum of the latencies for
     618             :   // all nodes glued together into this SUnit.
     619       83041 :   SU->Latency = 0;
     620      192088 :   for (SDNode *N = SU->getNode(); N; N = N->getGluedNode())
     621      109047 :     if (N->isMachineOpcode())
     622       69899 :       SU->Latency += TII->getInstrLatency(InstrItins, N);
     623             : }
     624             : 
     625      171684 : void ScheduleDAGSDNodes::computeOperandLatency(SDNode *Def, SDNode *Use,
     626             :                                                unsigned OpIdx, SDep& dep) const{
     627             :   // Check to see if the scheduler cares about latencies.
     628      171684 :   if (forceUnitLatencies())
     629             :     return;
     630             : 
     631      171684 :   if (dep.getKind() != SDep::Data)
     632             :     return;
     633             : 
     634      343368 :   unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
     635      171684 :   if (Use->isMachineOpcode())
     636             :     // Adjust the use operand index by num of defs.
     637      527332 :     OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
     638      171684 :   int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
     639      178002 :   if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg &&
     640       12636 :       !BB->succ_empty()) {
     641         804 :     unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
     642         268 :     if (TargetRegisterInfo::isVirtualRegister(Reg))
     643             :       // This copy is a liveout value. It is likely coalesced, so reduce the
     644             :       // latency so not to penalize the def.
     645             :       // FIXME: need target specific adjustment here?
     646          87 :       Latency = (Latency > 1) ? Latency - 1 : 1;
     647             :   }
     648      171684 :   if (Latency >= 0)
     649       54965 :     dep.setLatency(Latency);
     650             : }
     651             : 
     652           0 : void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
     653             :   // Cannot completely remove virtual function even in release mode.
     654             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
     655             :   if (!SU->getNode()) {
     656             :     dbgs() << "PHYS REG COPY\n";
     657             :     return;
     658             :   }
     659             : 
     660             :   SU->getNode()->dump(DAG);
     661             :   dbgs() << "\n";
     662             :   SmallVector<SDNode *, 4> GluedNodes;
     663             :   for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
     664             :     GluedNodes.push_back(N);
     665             :   while (!GluedNodes.empty()) {
     666             :     dbgs() << "    ";
     667             :     GluedNodes.back()->dump(DAG);
     668             :     dbgs() << "\n";
     669             :     GluedNodes.pop_back();
     670             :   }
     671             : #endif
     672           0 : }
     673             : 
     674             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
     675             : void ScheduleDAGSDNodes::dumpSchedule() const {
     676             :   for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
     677             :     if (SUnit *SU = Sequence[i])
     678             :       SU->dump(this);
     679             :     else
     680             :       dbgs() << "**** NOOP ****\n";
     681             :   }
     682             : }
     683             : #endif
     684             : 
     685             : #ifndef NDEBUG
     686             : /// VerifyScheduledSequence - Verify that all SUnits were scheduled and that
     687             : /// their state is consistent with the nodes listed in Sequence.
     688             : ///
     689             : void ScheduleDAGSDNodes::VerifyScheduledSequence(bool isBottomUp) {
     690             :   unsigned ScheduledNodes = ScheduleDAG::VerifyScheduledDAG(isBottomUp);
     691             :   unsigned Noops = 0;
     692             :   for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
     693             :     if (!Sequence[i])
     694             :       ++Noops;
     695             :   assert(Sequence.size() - Noops == ScheduledNodes &&
     696             :          "The number of nodes scheduled doesn't match the expected number!");
     697             : }
     698             : #endif // NDEBUG
     699             : 
     700             : /// ProcessSDDbgValues - Process SDDbgValues associated with this node.
     701             : static void
     702       44634 : ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
     703             :                    SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
     704             :                    DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) {
     705       89268 :   if (!N->getHasDebugValue())
     706             :     return;
     707             : 
     708             :   // Opportunistically insert immediate dbg_value uses, i.e. those with the same
     709             :   // source order number as N.
     710        4027 :   MachineBasicBlock *BB = Emitter.getBlock();
     711        4027 :   MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
     712        8054 :   ArrayRef<SDDbgValue*> DVs = DAG->GetDbgValues(N);
     713       12592 :   for (unsigned i = 0, e = DVs.size(); i != e; ++i) {
     714       17130 :     if (DVs[i]->isInvalidated())
     715           0 :       continue;
     716        8565 :     unsigned DVOrder = DVs[i]->getOrder();
     717        8565 :     if (!Order || DVOrder == Order) {
     718        7776 :       MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap);
     719        7776 :       if (DbgMI) {
     720       15552 :         Orders.push_back(std::make_pair(DVOrder, DbgMI));
     721        7776 :         BB->insert(InsertPos, DbgMI);
     722             :       }
     723        7776 :       DVs[i]->setIsInvalidated();
     724             :     }
     725             :   }
     726             : }
     727             : 
     728             : // ProcessSourceNode - Process nodes with source order numbers. These are added
     729             : // to a vector which EmitSchedule uses to determine how to insert dbg_value
     730             : // instructions in the right order.
     731             : static void
     732       47787 : ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
     733             :                   DenseMap<SDValue, unsigned> &VRBaseMap,
     734             :                   SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
     735             :                   SmallSet<unsigned, 8> &Seen) {
     736       47787 :   unsigned Order = N->getIROrder();
     737       47787 :   if (!Order || !Seen.insert(Order).second) {
     738             :     // Process any valid SDDbgValues even if node does not have any order
     739             :     // assigned.
     740       27329 :     ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
     741       57811 :     return;
     742             :   }
     743             : 
     744       20458 :   MachineBasicBlock *BB = Emitter.getBlock();
     745       76535 :   if (Emitter.getInsertPos() == BB->begin() || BB->back().isPHI() ||
     746             :       // Fast-isel may have inserted some instructions, in which case the
     747             :       // BB->back().isPHI() test will not fire when we want it to.
     748       69220 :       std::prev(Emitter.getInsertPos())->isPHI()) {
     749             :     // Did not insert any instruction.
     750        6306 :     Orders.push_back(std::make_pair(Order, (MachineInstr*)nullptr));
     751        3153 :     return;
     752             :   }
     753             : 
     754       69220 :   Orders.push_back(std::make_pair(Order, &*std::prev(Emitter.getInsertPos())));
     755       17305 :   ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
     756             : }
     757             : 
     758         218 : void ScheduleDAGSDNodes::
     759             : EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
     760             :                 MachineBasicBlock::iterator InsertPos) {
     761         654 :   for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
     762         218 :        I != E; ++I) {
     763         218 :     if (I->isCtrl()) continue;  // ignore chain preds
     764         218 :     if (I->getSUnit()->CopyDstRC) {
     765             :       // Copy to physical register.
     766         109 :       DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit());
     767             :       assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
     768             :       // Find the destination physical register.
     769         109 :       unsigned Reg = 0;
     770         221 :       for (SUnit::const_succ_iterator II = SU->Succs.begin(),
     771         218 :              EE = SU->Succs.end(); II != EE; ++II) {
     772         112 :         if (II->isCtrl()) continue;  // ignore chain preds
     773         111 :         if (II->getReg()) {
     774             :           Reg = II->getReg();
     775             :           break;
     776             :         }
     777             :       }
     778         545 :       BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
     779         109 :         .addReg(VRI->second);
     780             :     } else {
     781             :       // Copy from physical register.
     782             :       assert(I->getReg() && "Unknown physical register!");
     783         109 :       unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
     784         327 :       bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
     785             :       (void)isNew; // Silence compiler warning.
     786             :       assert(isNew && "Node emitted out of order - early");
     787         545 :       BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
     788         109 :         .addReg(I->getReg());
     789             :     }
     790             :     break;
     791             :   }
     792         218 : }
     793             : 
     794             : /// EmitSchedule - Emit the machine code in scheduled order. Return the new
     795             : /// InsertPos and MachineBasicBlock that contains this insertion
     796             : /// point. ScheduleDAGSDNodes holds a BB pointer for convenience, but this does
     797             : /// not necessarily refer to returned BB. The emitter may split blocks.
     798      279998 : MachineBasicBlock *ScheduleDAGSDNodes::
     799             : EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
     800      279998 :   InstrEmitter Emitter(BB, InsertPos);
     801      559996 :   DenseMap<SDValue, unsigned> VRBaseMap;
     802      559996 :   DenseMap<SUnit*, unsigned> CopyVRBaseMap;
     803      559996 :   SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
     804      559996 :   SmallSet<unsigned, 8> Seen;
     805      559996 :   bool HasDbg = DAG->hasDebugValues();
     806             : 
     807             :   // If this is the first BB, emit byval parameter dbg_value's.
     808      287598 :   if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) {
     809         704 :     SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin();
     810         704 :     SDDbgInfo::DbgIterator PDE = DAG->ByvalParmDbgEnd();
     811         360 :     for (; PDI != PDE; ++PDI) {
     812           4 :       MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap);
     813           4 :       if (DbgMI)
     814           4 :         BB->insert(InsertPos, DbgMI);
     815             :     }
     816             :   }
     817             : 
     818     4129701 :   for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
     819     7139410 :     SUnit *SU = Sequence[i];
     820     3569705 :     if (!SU) {
     821             :       // Null SUnit* is a noop.
     822           0 :       TII->insertNoop(*Emitter.getBlock(), InsertPos);
     823         218 :       continue;
     824             :     }
     825             : 
     826             :     // For pre-regalloc scheduling, create instructions corresponding to the
     827             :     // SDNode and any glued SDNodes and append them to the block.
     828     3569923 :     if (!SU->getNode()) {
     829             :       // Emit a copy.
     830         218 :       EmitPhysRegCopy(SU, CopyVRBaseMap, InsertPos);
     831         218 :       continue;
     832             :     }
     833             : 
     834     7138974 :     SmallVector<SDNode *, 4> GluedNodes;
     835     8872178 :     for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
     836      866602 :       GluedNodes.push_back(N);
     837     4436089 :     while (!GluedNodes.empty()) {
     838     1733204 :       SDNode *N = GluedNodes.back();
     839      866602 :       Emitter.EmitNode(N, SU->OrigNode != SU, SU->isCloned, VRBaseMap);
     840             :       // Remember the source order of the inserted instruction.
     841      866602 :       if (HasDbg)
     842        8218 :         ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
     843             :       GluedNodes.pop_back();
     844             :     }
     845     3569487 :     Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
     846             :                      VRBaseMap);
     847             :     // Remember the source order of the inserted instruction.
     848     3569487 :     if (HasDbg)
     849       39569 :       ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
     850             :                         Seen);
     851             :   }
     852             : 
     853             :   // Insert all the dbg_values which have not already been inserted in source
     854             :   // order sequence.
     855      279998 :   if (HasDbg) {
     856        3800 :     MachineBasicBlock::iterator BBBegin = BB->getFirstNonPHI();
     857             : 
     858             :     // Sort the source order instructions and use the order to insert debug
     859             :     // values.
     860       11400 :     std::sort(Orders.begin(), Orders.end(), less_first());
     861             : 
     862        7600 :     SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
     863        7600 :     SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
     864             :     // Now emit the rest according to source order.
     865        3800 :     unsigned LastOrder = 0;
     866       31181 :     for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
     867       47162 :       unsigned Order = Orders[i].first;
     868       47162 :       MachineInstr *MI = Orders[i].second;
     869             :       // Insert all SDDbgValue's whose order(s) are before "Order".
     870       23581 :       if (!MI)
     871        3151 :         continue;
     872       56671 :       for (; DI != DE &&
     873       75530 :              (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
     874       19747 :         if ((*DI)->isInvalidated())
     875       11840 :           continue;
     876        7907 :         MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap);
     877        7907 :         if (DbgMI) {
     878        7907 :           if (!LastOrder)
     879             :             // Insert to start of the BB (after PHIs).
     880        3245 :             BB->insert(BBBegin, DbgMI);
     881             :           else {
     882             :             // Insert at the instruction, which may be in a different
     883             :             // block, if the block was split by a custom inserter.
     884        4662 :             MachineBasicBlock::iterator Pos = MI;
     885        9324 :             MI->getParent()->insert(Pos, DbgMI);
     886             :           }
     887             :         }
     888             :       }
     889             :       LastOrder = Order;
     890             :     }
     891             :     // Add trailing DbgValue's before the terminator. FIXME: May want to add
     892             :     // some of them before one or more conditional branches?
     893        3800 :     SmallVector<MachineInstr*, 8> DbgMIs;
     894        7664 :     while (DI != DE) {
     895        1932 :       if (!(*DI)->isInvalidated())
     896         388 :         if (MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap))
     897         388 :           DbgMIs.push_back(DbgMI);
     898        1932 :       ++DI;
     899             :     }
     900             : 
     901        3800 :     MachineBasicBlock *InsertBB = Emitter.getBlock();
     902        3800 :     MachineBasicBlock::iterator Pos = InsertBB->getFirstTerminator();
     903       11400 :     InsertBB->insert(Pos, DbgMIs.begin(), DbgMIs.end());
     904             :   }
     905             : 
     906      279998 :   InsertPos = Emitter.getInsertPos();
     907      559996 :   return Emitter.getBlock();
     908             : }
     909             : 
     910             : /// Return the basic block label.
     911           0 : std::string ScheduleDAGSDNodes::getDAGName() const {
     912           0 :   return "sunit-dag." + BB->getFullName();
     913      216918 : }

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