LCOV - code coverage report
Current view: top level - lib/CodeGen - TargetInstrInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 450 498 90.4 %
Date: 2017-09-14 15:23:50 Functions: 45 51 88.2 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements the TargetInstrInfo class.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "llvm/Target/TargetInstrInfo.h"
      15             : #include "llvm/CodeGen/MachineFrameInfo.h"
      16             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      17             : #include "llvm/CodeGen/MachineMemOperand.h"
      18             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      19             : #include "llvm/CodeGen/PseudoSourceValue.h"
      20             : #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
      21             : #include "llvm/CodeGen/StackMaps.h"
      22             : #include "llvm/CodeGen/TargetSchedule.h"
      23             : #include "llvm/IR/DataLayout.h"
      24             : #include "llvm/MC/MCAsmInfo.h"
      25             : #include "llvm/MC/MCInstrItineraries.h"
      26             : #include "llvm/Support/CommandLine.h"
      27             : #include "llvm/Support/ErrorHandling.h"
      28             : #include "llvm/Support/raw_ostream.h"
      29             : #include "llvm/Target/TargetFrameLowering.h"
      30             : #include "llvm/Target/TargetLowering.h"
      31             : #include "llvm/Target/TargetMachine.h"
      32             : #include "llvm/Target/TargetRegisterInfo.h"
      33             : #include <cctype>
      34             : 
      35             : using namespace llvm;
      36             : 
      37       72306 : static cl::opt<bool> DisableHazardRecognizer(
      38      216918 :   "disable-sched-hazard", cl::Hidden, cl::init(false),
      39      289224 :   cl::desc("Disable hazard detection during preRA scheduling"));
      40             : 
      41       28000 : TargetInstrInfo::~TargetInstrInfo() {
      42       28000 : }
      43             : 
      44             : const TargetRegisterClass*
      45    39431152 : TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
      46             :                              const TargetRegisterInfo *TRI,
      47             :                              const MachineFunction &MF) const {
      48    78862304 :   if (OpNum >= MCID.getNumOperands())
      49             :     return nullptr;
      50             : 
      51    39431148 :   short RegClass = MCID.OpInfo[OpNum].RegClass;
      52    39431148 :   if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
      53     1899919 :     return TRI->getPointerRegClass(MF, RegClass);
      54             : 
      55             :   // Instructions like INSERT_SUBREG do not have fixed register classes.
      56    37531229 :   if (RegClass < 0)
      57             :     return nullptr;
      58             : 
      59             :   // Otherwise just look it up normally.
      60    56338946 :   return TRI->getRegClass(RegClass);
      61             : }
      62             : 
      63             : /// insertNoop - Insert a noop into the instruction stream at the specified
      64             : /// point.
      65           0 : void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
      66             :                                  MachineBasicBlock::iterator MI) const {
      67           0 :   llvm_unreachable("Target didn't implement insertNoop!");
      68             : }
      69             : 
      70             : /// Measure the specified inline asm to determine an approximation of its
      71             : /// length.
      72             : /// Comments (which run till the next SeparatorString or newline) do not
      73             : /// count as an instruction.
      74             : /// Any other non-whitespace text is considered an instruction, with
      75             : /// multiple instructions separated by SeparatorString or newlines.
      76             : /// Variable-length instructions are not handled here; this function
      77             : /// may be overloaded in the target code to do that.
      78      201174 : unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
      79             :                                              const MCAsmInfo &MAI) const {
      80             :   // Count the number of instructions in the asm.
      81      201174 :   bool atInsnStart = true;
      82      201174 :   unsigned InstCount = 0;
      83      315106 :   for (; *Str; ++Str) {
      84       56966 :     if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
      85             :                                 strlen(MAI.getSeparatorString())) == 0) {
      86             :       atInsnStart = true;
      87       55792 :     } else if (strncmp(Str, MAI.getCommentString().data(),
      88       55792 :                        MAI.getCommentString().size()) == 0) {
      89             :       // Stop counting as an instruction after a comment until the next
      90             :       // separator.
      91             :       atInsnStart = false;
      92             :     }
      93             : 
      94       55589 :     if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
      95        3217 :       ++InstCount;
      96        3217 :       atInsnStart = false;
      97             :     }
      98             :   }
      99             : 
     100      201174 :   return InstCount * MAI.getMaxInstLength();
     101             : }
     102             : 
     103             : /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
     104             : /// after it, replacing it with an unconditional branch to NewDest.
     105             : void
     106       11749 : TargetInstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
     107             :                                          MachineBasicBlock *NewDest) const {
     108       11749 :   MachineBasicBlock *MBB = Tail->getParent();
     109             : 
     110             :   // Remove all the old successors of MBB from the CFG.
     111       24757 :   while (!MBB->succ_empty())
     112        6504 :     MBB->removeSuccessor(MBB->succ_begin());
     113             : 
     114             :   // Save off the debug loc before erasing the instruction.
     115       35247 :   DebugLoc DL = Tail->getDebugLoc();
     116             : 
     117             :   // Remove all the dead instructions from the end of MBB.
     118       23498 :   MBB->erase(Tail, MBB->end());
     119             : 
     120             :   // If MBB isn't immediately before MBB, insert a branch to it.
     121       35247 :   if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
     122       44420 :     insertBranch(*MBB, NewDest, nullptr, SmallVector<MachineOperand, 0>(), DL);
     123       11749 :   MBB->addSuccessor(NewDest);
     124       11749 : }
     125             : 
     126      336779 : MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
     127             :                                                       bool NewMI, unsigned Idx1,
     128             :                                                       unsigned Idx2) const {
     129      336779 :   const MCInstrDesc &MCID = MI.getDesc();
     130      336779 :   bool HasDef = MCID.getNumDefs();
     131      641325 :   if (HasDef && !MI.getOperand(0).isReg())
     132             :     // No idea how to commute this instruction. Target should implement its own.
     133             :     return nullptr;
     134             : 
     135      336779 :   unsigned CommutableOpIdx1 = Idx1; (void)CommutableOpIdx1;
     136      336779 :   unsigned CommutableOpIdx2 = Idx2; (void)CommutableOpIdx2;
     137             :   assert(findCommutedOpIndices(MI, CommutableOpIdx1, CommutableOpIdx2) &&
     138             :          CommutableOpIdx1 == Idx1 && CommutableOpIdx2 == Idx2 &&
     139             :          "TargetInstrInfo::CommuteInstructionImpl(): not commutable operands.");
     140             :   assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() &&
     141             :          "This only knows how to commute register operands so far");
     142             : 
     143      336779 :   unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
     144      673558 :   unsigned Reg1 = MI.getOperand(Idx1).getReg();
     145      673558 :   unsigned Reg2 = MI.getOperand(Idx2).getReg();
     146      641325 :   unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0;
     147      673558 :   unsigned SubReg1 = MI.getOperand(Idx1).getSubReg();
     148      673558 :   unsigned SubReg2 = MI.getOperand(Idx2).getSubReg();
     149      673558 :   bool Reg1IsKill = MI.getOperand(Idx1).isKill();
     150      673558 :   bool Reg2IsKill = MI.getOperand(Idx2).isKill();
     151      673558 :   bool Reg1IsUndef = MI.getOperand(Idx1).isUndef();
     152      673558 :   bool Reg2IsUndef = MI.getOperand(Idx2).isUndef();
     153      673558 :   bool Reg1IsInternal = MI.getOperand(Idx1).isInternalRead();
     154      673558 :   bool Reg2IsInternal = MI.getOperand(Idx2).isInternalRead();
     155             :   // If destination is tied to either of the commuted source register, then
     156             :   // it must be updated.
     157      336810 :   if (HasDef && Reg0 == Reg1 &&
     158         473 :       MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
     159             :     Reg2IsKill = false;
     160             :     Reg0 = Reg2;
     161             :     SubReg0 = SubReg2;
     162      336748 :   } else if (HasDef && Reg0 == Reg2 &&
     163         578 :              MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
     164             :     Reg1IsKill = false;
     165             :     Reg0 = Reg1;
     166             :     SubReg0 = SubReg1;
     167             :   }
     168             : 
     169      336779 :   MachineInstr *CommutedMI = nullptr;
     170      336779 :   if (NewMI) {
     171             :     // Create a new instruction.
     172           0 :     MachineFunction &MF = *MI.getParent()->getParent();
     173           0 :     CommutedMI = MF.CloneMachineInstr(&MI);
     174             :   } else {
     175             :     CommutedMI = &MI;
     176             :   }
     177             : 
     178      336779 :   if (HasDef) {
     179      304546 :     CommutedMI->getOperand(0).setReg(Reg0);
     180      304546 :     CommutedMI->getOperand(0).setSubReg(SubReg0);
     181             :   }
     182      673558 :   CommutedMI->getOperand(Idx2).setReg(Reg1);
     183      673558 :   CommutedMI->getOperand(Idx1).setReg(Reg2);
     184     1010337 :   CommutedMI->getOperand(Idx2).setSubReg(SubReg1);
     185     1010337 :   CommutedMI->getOperand(Idx1).setSubReg(SubReg2);
     186     1010337 :   CommutedMI->getOperand(Idx2).setIsKill(Reg1IsKill);
     187     1010337 :   CommutedMI->getOperand(Idx1).setIsKill(Reg2IsKill);
     188     1010337 :   CommutedMI->getOperand(Idx2).setIsUndef(Reg1IsUndef);
     189     1010337 :   CommutedMI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
     190     1010337 :   CommutedMI->getOperand(Idx2).setIsInternalRead(Reg1IsInternal);
     191     1010337 :   CommutedMI->getOperand(Idx1).setIsInternalRead(Reg2IsInternal);
     192      336779 :   return CommutedMI;
     193             : }
     194             : 
     195      406112 : MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr &MI, bool NewMI,
     196             :                                                   unsigned OpIdx1,
     197             :                                                   unsigned OpIdx2) const {
     198             :   // If OpIdx1 or OpIdx2 is not specified, then this method is free to choose
     199             :   // any commutable operand, which is done in findCommutedOpIndices() method
     200             :   // called below.
     201      782985 :   if ((OpIdx1 == CommuteAnyOperandIndex || OpIdx2 == CommuteAnyOperandIndex) &&
     202      376873 :       !findCommutedOpIndices(MI, OpIdx1, OpIdx2)) {
     203             :     assert(MI.isCommutable() &&
     204             :            "Precondition violation: MI must be commutable.");
     205             :     return nullptr;
     206             :   }
     207      404691 :   return commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
     208             : }
     209             : 
     210      423072 : bool TargetInstrInfo::fixCommutedOpIndices(unsigned &ResultIdx1,
     211             :                                            unsigned &ResultIdx2,
     212             :                                            unsigned CommutableOpIdx1,
     213             :                                            unsigned CommutableOpIdx2) {
     214      808410 :   if (ResultIdx1 == CommuteAnyOperandIndex &&
     215      385338 :       ResultIdx2 == CommuteAnyOperandIndex) {
     216      385338 :     ResultIdx1 = CommutableOpIdx1;
     217      385338 :     ResultIdx2 = CommutableOpIdx2;
     218       37734 :   } else if (ResultIdx1 == CommuteAnyOperandIndex) {
     219           0 :     if (ResultIdx2 == CommutableOpIdx1)
     220           0 :       ResultIdx1 = CommutableOpIdx2;
     221           0 :     else if (ResultIdx2 == CommutableOpIdx2)
     222           0 :       ResultIdx1 = CommutableOpIdx1;
     223             :     else
     224             :       return false;
     225       37734 :   } else if (ResultIdx2 == CommuteAnyOperandIndex) {
     226        5451 :     if (ResultIdx1 == CommutableOpIdx1)
     227        4376 :       ResultIdx2 = CommutableOpIdx2;
     228        1075 :     else if (ResultIdx1 == CommutableOpIdx2)
     229        1006 :       ResultIdx2 = CommutableOpIdx1;
     230             :     else
     231             :       return false;
     232             :   } else
     233             :     // Check that the result operand indices match the given commutable
     234             :     // operand indices.
     235       32283 :     return (ResultIdx1 == CommutableOpIdx1 && ResultIdx2 == CommutableOpIdx2) ||
     236         176 :            (ResultIdx1 == CommutableOpIdx2 && ResultIdx2 == CommutableOpIdx1);
     237             : 
     238             :   return true;
     239             : }
     240             : 
     241      188922 : bool TargetInstrInfo::findCommutedOpIndices(MachineInstr &MI,
     242             :                                             unsigned &SrcOpIdx1,
     243             :                                             unsigned &SrcOpIdx2) const {
     244             :   assert(!MI.isBundle() &&
     245             :          "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
     246             : 
     247      188922 :   const MCInstrDesc &MCID = MI.getDesc();
     248      188922 :   if (!MCID.isCommutable())
     249             :     return false;
     250             : 
     251             :   // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
     252             :   // is not true, then the target must implement this.
     253      188199 :   unsigned CommutableOpIdx1 = MCID.getNumDefs();
     254      188199 :   unsigned CommutableOpIdx2 = CommutableOpIdx1 + 1;
     255      188199 :   if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
     256             :                             CommutableOpIdx1, CommutableOpIdx2))
     257             :     return false;
     258             : 
     259      936940 :   if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
     260             :     // No idea.
     261             :     return false;
     262             :   return true;
     263             : }
     264             : 
     265     1098776 : bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
     266     1098776 :   if (!MI.isTerminator()) return false;
     267             : 
     268             :   // Conditional branch is a special case.
     269      704127 :   if (MI.isBranch() && !MI.isBarrier())
     270             :     return true;
     271      422630 :   if (!MI.isPredicable())
     272             :     return true;
     273       13183 :   return !isPredicated(MI);
     274             : }
     275             : 
     276           0 : bool TargetInstrInfo::PredicateInstruction(
     277             :     MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
     278           0 :   bool MadeChange = false;
     279             : 
     280             :   assert(!MI.isBundle() &&
     281             :          "TargetInstrInfo::PredicateInstruction() can't handle bundles");
     282             : 
     283           0 :   const MCInstrDesc &MCID = MI.getDesc();
     284           0 :   if (!MI.isPredicable())
     285             :     return false;
     286             : 
     287           0 :   for (unsigned j = 0, i = 0, e = MI.getNumOperands(); i != e; ++i) {
     288           0 :     if (MCID.OpInfo[i].isPredicate()) {
     289           0 :       MachineOperand &MO = MI.getOperand(i);
     290           0 :       if (MO.isReg()) {
     291           0 :         MO.setReg(Pred[j].getReg());
     292           0 :         MadeChange = true;
     293           0 :       } else if (MO.isImm()) {
     294           0 :         MO.setImm(Pred[j].getImm());
     295           0 :         MadeChange = true;
     296           0 :       } else if (MO.isMBB()) {
     297           0 :         MO.setMBB(Pred[j].getMBB());
     298           0 :         MadeChange = true;
     299             :       }
     300           0 :       ++j;
     301             :     }
     302             :   }
     303             :   return MadeChange;
     304             : }
     305             : 
     306     1665211 : bool TargetInstrInfo::hasLoadFromStackSlot(const MachineInstr &MI,
     307             :                                            const MachineMemOperand *&MMO,
     308             :                                            int &FrameIndex) const {
     309     2060263 :   for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
     310     3330422 :                                   oe = MI.memoperands_end();
     311     2060263 :        o != oe; ++o) {
     312      899158 :     if ((*o)->isLoad()) {
     313      231623 :       if (const FixedStackPseudoSourceValue *Value =
     314      356988 :           dyn_cast_or_null<FixedStackPseudoSourceValue>(
     315      231623 :               (*o)->getPseudoValue())) {
     316       54527 :         FrameIndex = Value->getFrameIndex();
     317       54527 :         MMO = *o;
     318       54527 :         return true;
     319             :       }
     320             :     }
     321             :   }
     322             :   return false;
     323             : }
     324             : 
     325     1613531 : bool TargetInstrInfo::hasStoreToStackSlot(const MachineInstr &MI,
     326             :                                           const MachineMemOperand *&MMO,
     327             :                                           int &FrameIndex) const {
     328     1968173 :   for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
     329     3227062 :                                   oe = MI.memoperands_end();
     330     1968173 :        o != oe; ++o) {
     331      794274 :     if ((*o)->isStore()) {
     332      194239 :       if (const FixedStackPseudoSourceValue *Value =
     333      265218 :           dyn_cast_or_null<FixedStackPseudoSourceValue>(
     334      194239 :               (*o)->getPseudoValue())) {
     335       42495 :         FrameIndex = Value->getFrameIndex();
     336       42495 :         MMO = *o;
     337       42495 :         return true;
     338             :       }
     339             :     }
     340             :   }
     341             :   return false;
     342             : }
     343             : 
     344         115 : bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
     345             :                                         unsigned SubIdx, unsigned &Size,
     346             :                                         unsigned &Offset,
     347             :                                         const MachineFunction &MF) const {
     348         115 :   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
     349         115 :   if (!SubIdx) {
     350         226 :     Size = TRI->getSpillSize(*RC);
     351         113 :     Offset = 0;
     352         113 :     return true;
     353             :   }
     354           2 :   unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
     355             :   // Convert bit size to byte size to be consistent with
     356             :   // MCRegisterClass::getSize().
     357           2 :   if (BitSize % 8)
     358             :     return false;
     359             : 
     360           2 :   int BitOffset = TRI->getSubRegIdxOffset(SubIdx);
     361           2 :   if (BitOffset < 0 || BitOffset % 8)
     362             :     return false;
     363             : 
     364           2 :   Size = BitSize /= 8;
     365           2 :   Offset = (unsigned)BitOffset / 8;
     366             : 
     367             :   assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");
     368             : 
     369           2 :   if (!MF.getDataLayout().isLittleEndian()) {
     370           2 :     Offset = TRI->getSpillSize(*RC) - (Offset + Size);
     371             :   }
     372             :   return true;
     373             : }
     374             : 
     375        6096 : void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
     376             :                                     MachineBasicBlock::iterator I,
     377             :                                     unsigned DestReg, unsigned SubIdx,
     378             :                                     const MachineInstr &Orig,
     379             :                                     const TargetRegisterInfo &TRI) const {
     380        6096 :   MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
     381        6096 :   MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
     382        6096 :   MBB.insert(I, MI);
     383        6096 : }
     384             : 
     385      395469 : bool TargetInstrInfo::produceSameValue(const MachineInstr &MI0,
     386             :                                        const MachineInstr &MI1,
     387             :                                        const MachineRegisterInfo *MRI) const {
     388      395469 :   return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
     389             : }
     390             : 
     391        4702 : MachineInstr &TargetInstrInfo::duplicate(MachineBasicBlock &MBB,
     392             :     MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const {
     393             :   assert(!Orig.isNotDuplicable() && "Instruction cannot be duplicated");
     394        4702 :   MachineFunction &MF = *MBB.getParent();
     395        4702 :   return MF.CloneMachineInstrBundle(MBB, InsertBefore, Orig);
     396             : }
     397             : 
     398             : // If the COPY instruction in MI can be folded to a stack operation, return
     399             : // the register class to use.
     400       29187 : static const TargetRegisterClass *canFoldCopy(const MachineInstr &MI,
     401             :                                               unsigned FoldIdx) {
     402             :   assert(MI.isCopy() && "MI must be a COPY instruction");
     403       29187 :   if (MI.getNumOperands() != 2)
     404             :     return nullptr;
     405             :   assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
     406             : 
     407       58374 :   const MachineOperand &FoldOp = MI.getOperand(FoldIdx);
     408       58374 :   const MachineOperand &LiveOp = MI.getOperand(1 - FoldIdx);
     409             : 
     410       58203 :   if (FoldOp.getSubReg() || LiveOp.getSubReg())
     411             :     return nullptr;
     412             : 
     413       28982 :   unsigned FoldReg = FoldOp.getReg();
     414       28982 :   unsigned LiveReg = LiveOp.getReg();
     415             : 
     416             :   assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
     417             :          "Cannot fold physregs");
     418             : 
     419       28982 :   const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
     420       28982 :   const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
     421             : 
     422       57964 :   if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
     423       30258 :     return RC->contains(LiveOp.getReg()) ? RC : nullptr;
     424             : 
     425       27706 :   if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
     426       13755 :     return RC;
     427             : 
     428             :   // FIXME: Allow folding when register classes are memory compatible.
     429             :   return nullptr;
     430             : }
     431             : 
     432           0 : void TargetInstrInfo::getNoop(MCInst &NopInst) const {
     433           0 :   llvm_unreachable("Not implemented");
     434             : }
     435             : 
     436         233 : static MachineInstr *foldPatchpoint(MachineFunction &MF, MachineInstr &MI,
     437             :                                     ArrayRef<unsigned> Ops, int FrameIndex,
     438             :                                     const TargetInstrInfo &TII) {
     439         233 :   unsigned StartIdx = 0;
     440         466 :   switch (MI.getOpcode()) {
     441          31 :   case TargetOpcode::STACKMAP: {
     442             :     // StackMapLiveValues are foldable
     443          31 :     StartIdx = StackMapOpers(&MI).getVarIdx();
     444          31 :     break;
     445             :   }
     446         179 :   case TargetOpcode::PATCHPOINT: {
     447             :     // For PatchPoint, the call args are not foldable (even if reported in the
     448             :     // stackmap e.g. via anyregcc).
     449         358 :     StartIdx = PatchPointOpers(&MI).getVarIdx();
     450         179 :     break;
     451             :   }
     452          23 :   case TargetOpcode::STATEPOINT: {
     453             :     // For statepoints, fold deopt and gc arguments, but not call arguments.
     454          46 :     StartIdx = StatepointOpers(&MI).getVarIdx();
     455          23 :     break;
     456             :   }
     457           0 :   default:
     458           0 :     llvm_unreachable("unexpected stackmap opcode");
     459             :   }
     460             : 
     461             :   // Return false if any operands requested for folding are not foldable (not
     462             :   // part of the stackmap's live values).
     463         581 :   for (unsigned Op : Ops) {
     464         233 :     if (Op < StartIdx)
     465             :       return nullptr;
     466             :   }
     467             : 
     468             :   MachineInstr *NewMI =
     469         345 :       MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
     470         115 :   MachineInstrBuilder MIB(MF, NewMI);
     471             : 
     472             :   // No need to fold return, the meta data, and function arguments
     473         919 :   for (unsigned i = 0; i < StartIdx; ++i)
     474        2412 :     MIB.add(MI.getOperand(i));
     475             : 
     476        4253 :   for (unsigned i = StartIdx; i < MI.getNumOperands(); ++i) {
     477        8276 :     MachineOperand &MO = MI.getOperand(i);
     478        4138 :     if (is_contained(Ops, i)) {
     479             :       unsigned SpillSize;
     480             :       unsigned SpillOffset;
     481             :       // Compute the spill slot size and offset.
     482             :       const TargetRegisterClass *RC =
     483         230 :         MF.getRegInfo().getRegClass(MO.getReg());
     484             :       bool Valid =
     485         230 :           TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);
     486         115 :       if (!Valid)
     487           0 :         report_fatal_error("cannot spill patchpoint subregister operand");
     488         115 :       MIB.addImm(StackMaps::IndirectMemRefOp);
     489         230 :       MIB.addImm(SpillSize);
     490         115 :       MIB.addFrameIndex(FrameIndex);
     491         230 :       MIB.addImm(SpillOffset);
     492             :     }
     493             :     else
     494             :       MIB.add(MO);
     495             :   }
     496         115 :   return NewMI;
     497             : }
     498             : 
     499             : /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
     500             : /// slot into the specified machine instruction for the specified operand(s).
     501             : /// If this is possible, a new instruction is returned with the specified
     502             : /// operand folded, otherwise NULL is returned. The client is responsible for
     503             : /// removing the old instruction and adding the new one in the instruction
     504             : /// stream.
     505       45104 : MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
     506             :                                                  ArrayRef<unsigned> Ops, int FI,
     507             :                                                  LiveIntervals *LIS) const {
     508       45104 :   auto Flags = MachineMemOperand::MONone;
     509       90269 :   for (unsigned i = 0, e = Ops.size(); i != e; ++i)
     510      180660 :     if (MI.getOperand(Ops[i]).isDef())
     511             :       Flags |= MachineMemOperand::MOStore;
     512             :     else
     513             :       Flags |= MachineMemOperand::MOLoad;
     514             : 
     515       45104 :   MachineBasicBlock *MBB = MI.getParent();
     516             :   assert(MBB && "foldMemoryOperand needs an inserted instruction");
     517       45104 :   MachineFunction &MF = *MBB->getParent();
     518             : 
     519             :   // If we're not folding a load into a subreg, the size of the load is the
     520             :   // size of the spill slot. But if we are, we need to figure out what the
     521             :   // actual load size is.
     522       45104 :   int64_t MemSize = 0;
     523       45104 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
     524       45104 :   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
     525             : 
     526       90208 :   if (Flags & MachineMemOperand::MOStore) {
     527       16797 :     MemSize = MFI.getObjectSize(FI);
     528             :   } else {
     529       84973 :     for (unsigned Idx : Ops) {
     530       28359 :       int64_t OpSize = MFI.getObjectSize(FI);
     531             : 
     532       85077 :       if (auto SubReg = MI.getOperand(Idx).getSubReg()) {
     533         347 :         unsigned SubRegSize = TRI->getSubRegIdxSize(SubReg);
     534         347 :         if (SubRegSize > 0 && !(SubRegSize % 8))
     535         347 :           OpSize = SubRegSize / 8;
     536             :       }
     537             : 
     538       28359 :       MemSize = std::max(MemSize, OpSize);
     539             :     }
     540             :   }
     541             : 
     542             :   assert(MemSize && "Did not expect a zero-sized stack slot");
     543             : 
     544       45104 :   MachineInstr *NewMI = nullptr;
     545             : 
     546       90193 :   if (MI.getOpcode() == TargetOpcode::STACKMAP ||
     547       90090 :       MI.getOpcode() == TargetOpcode::PATCHPOINT ||
     548       44986 :       MI.getOpcode() == TargetOpcode::STATEPOINT) {
     549             :     // Fold stackmap/patchpoint.
     550         118 :     NewMI = foldPatchpoint(MF, MI, Ops, FI, *this);
     551         118 :     if (NewMI)
     552          90 :       MBB->insert(MI, NewMI);
     553             :   } else {
     554             :     // Ask the target to do the actual folding.
     555       89972 :     NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, FI, LIS);
     556             :   }
     557             : 
     558       45104 :   if (NewMI) {
     559       16641 :     NewMI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
     560             :     // Add a memory operand, foldMemoryOperandImpl doesn't do that.
     561             :     assert((!(Flags & MachineMemOperand::MOStore) ||
     562             :             NewMI->mayStore()) &&
     563             :            "Folded a def to a non-store!");
     564             :     assert((!(Flags & MachineMemOperand::MOLoad) ||
     565             :             NewMI->mayLoad()) &&
     566             :            "Folded a use to a non-load!");
     567             :     assert(MFI.getObjectOffset(FI) != -1);
     568       16641 :     MachineMemOperand *MMO = MF.getMachineMemOperand(
     569             :         MachinePointerInfo::getFixedStack(MF, FI), Flags, MemSize,
     570        5547 :         MFI.getObjectAlignment(FI));
     571        5547 :     NewMI->addMemOperand(MF, MMO);
     572             : 
     573        5547 :     return NewMI;
     574             :   }
     575             : 
     576             :   // Straight COPY may fold as load/store.
     577       39557 :   if (!MI.isCopy() || Ops.size() != 1)
     578             :     return nullptr;
     579             : 
     580       29187 :   const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
     581       29187 :   if (!RC)
     582             :     return nullptr;
     583             : 
     584       57638 :   const MachineOperand &MO = MI.getOperand(1 - Ops[0]);
     585       28819 :   MachineBasicBlock::iterator Pos = MI;
     586             : 
     587       28819 :   if (Flags == MachineMemOperand::MOStore)
     588       22912 :     storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
     589             :   else
     590       17363 :     loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
     591       57638 :   return &*--Pos;
     592             : }
     593             : 
     594       23473 : bool TargetInstrInfo::hasReassociableOperands(
     595             :     const MachineInstr &Inst, const MachineBasicBlock *MBB) const {
     596       23473 :   const MachineOperand &Op1 = Inst.getOperand(1);
     597       23473 :   const MachineOperand &Op2 = Inst.getOperand(2);
     598       23473 :   const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
     599             : 
     600             :   // We need virtual register definitions for the operands that we will
     601             :   // reassociate.
     602       23473 :   MachineInstr *MI1 = nullptr;
     603       23473 :   MachineInstr *MI2 = nullptr;
     604       46946 :   if (Op1.isReg() && TargetRegisterInfo::isVirtualRegister(Op1.getReg()))
     605       23473 :     MI1 = MRI.getUniqueVRegDef(Op1.getReg());
     606       46946 :   if (Op2.isReg() && TargetRegisterInfo::isVirtualRegister(Op2.getReg()))
     607       23473 :     MI2 = MRI.getUniqueVRegDef(Op2.getReg());
     608             : 
     609             :   // And they need to be in the trace (otherwise, they won't have a depth).
     610       23473 :   return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB;
     611             : }
     612             : 
     613       20381 : bool TargetInstrInfo::hasReassociableSibling(const MachineInstr &Inst,
     614             :                                              bool &Commuted) const {
     615       20381 :   const MachineBasicBlock *MBB = Inst.getParent();
     616       20381 :   const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
     617       20381 :   MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg());
     618       20381 :   MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg());
     619       40762 :   unsigned AssocOpcode = Inst.getOpcode();
     620             : 
     621             :   // If only one operand has the same opcode and it's the second source operand,
     622             :   // the operands must be commuted.
     623       59785 :   Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode;
     624       20381 :   if (Commuted)
     625             :     std::swap(MI1, MI2);
     626             : 
     627             :   // 1. The previous instruction must be the same type as Inst.
     628             :   // 2. The previous instruction must have virtual register definitions for its
     629             :   //    operands in the same basic block as Inst.
     630             :   // 3. The previous instruction's result must only be used by Inst.
     631       22192 :   return MI1->getOpcode() == AssocOpcode &&
     632       22163 :          hasReassociableOperands(*MI1, MBB) &&
     633       22163 :          MRI.hasOneNonDBGUse(MI1->getOperand(0).getReg());
     634             : }
     635             : 
     636             : // 1. The operation must be associative and commutative.
     637             : // 2. The instruction must have virtual register definitions for its
     638             : //    operands in the same basic block.
     639             : // 3. The instruction must have a reassociable sibling.
     640     3022230 : bool TargetInstrInfo::isReassociationCandidate(const MachineInstr &Inst,
     641             :                                                bool &Commuted) const {
     642     3044253 :   return isAssociativeAndCommutative(Inst) &&
     643     3042611 :          hasReassociableOperands(Inst, Inst.getParent()) &&
     644     3042611 :          hasReassociableSibling(Inst, Commuted);
     645             : }
     646             : 
     647             : // The concept of the reassociation pass is that these operations can benefit
     648             : // from this kind of transformation:
     649             : //
     650             : // A = ? op ?
     651             : // B = A op X (Prev)
     652             : // C = B op Y (Root)
     653             : // -->
     654             : // A = ? op ?
     655             : // B = X op Y
     656             : // C = A op B
     657             : //
     658             : // breaking the dependency between A and B, allowing them to be executed in
     659             : // parallel (or back-to-back in a pipeline) instead of depending on each other.
     660             : 
     661             : // FIXME: This has the potential to be expensive (compile time) while not
     662             : // improving the code at all. Some ways to limit the overhead:
     663             : // 1. Track successful transforms; bail out if hit rate gets too low.
     664             : // 2. Only enable at -O3 or some other non-default optimization level.
     665             : // 3. Pre-screen pattern candidates here: if an operand of the previous
     666             : //    instruction is known to not increase the critical path, then don't match
     667             : //    that pattern.
     668     3022230 : bool TargetInstrInfo::getMachineCombinerPatterns(
     669             :     MachineInstr &Root,
     670             :     SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
     671             :   bool Commute;
     672     3022230 :   if (isReassociationCandidate(Root, Commute)) {
     673             :     // We found a sequence of instructions that may be suitable for a
     674             :     // reassociation of operands to increase ILP. Specify each commutation
     675             :     // possibility for the Prev instruction in the sequence and let the
     676             :     // machine combiner decide if changing the operands is worthwhile.
     677         879 :     if (Commute) {
     678         319 :       Patterns.push_back(MachineCombinerPattern::REASSOC_AX_YB);
     679         319 :       Patterns.push_back(MachineCombinerPattern::REASSOC_XA_YB);
     680             :     } else {
     681         560 :       Patterns.push_back(MachineCombinerPattern::REASSOC_AX_BY);
     682         560 :       Patterns.push_back(MachineCombinerPattern::REASSOC_XA_BY);
     683             :     }
     684             :     return true;
     685             :   }
     686             : 
     687             :   return false;
     688             : }
     689             : /// Return true when a code sequence can improve loop throughput.
     690             : bool
     691          10 : TargetInstrInfo::isThroughputPattern(MachineCombinerPattern Pattern) const {
     692          10 :   return false;
     693             : }
     694             : /// Attempt the reassociation transformation to reduce critical path length.
     695             : /// See the above comments before getMachineCombinerPatterns().
     696        1505 : void TargetInstrInfo::reassociateOps(
     697             :     MachineInstr &Root, MachineInstr &Prev,
     698             :     MachineCombinerPattern Pattern,
     699             :     SmallVectorImpl<MachineInstr *> &InsInstrs,
     700             :     SmallVectorImpl<MachineInstr *> &DelInstrs,
     701             :     DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
     702        1505 :   MachineFunction *MF = Root.getParent()->getParent();
     703        1505 :   MachineRegisterInfo &MRI = MF->getRegInfo();
     704        1505 :   const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
     705        1505 :   const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
     706        1505 :   const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
     707             : 
     708             :   // This array encodes the operand index for each parameter because the
     709             :   // operands may be commuted. Each row corresponds to a pattern value,
     710             :   // and each column specifies the index of A, B, X, Y.
     711        1505 :   unsigned OpIdx[4][4] = {
     712             :     { 1, 1, 2, 2 },
     713             :     { 1, 2, 2, 1 },
     714             :     { 2, 1, 1, 2 },
     715             :     { 2, 2, 1, 1 }
     716             :   };
     717             : 
     718             :   int Row;
     719        1505 :   switch (Pattern) {
     720             :   case MachineCombinerPattern::REASSOC_AX_BY: Row = 0; break;
     721         319 :   case MachineCombinerPattern::REASSOC_AX_YB: Row = 1; break;
     722         357 :   case MachineCombinerPattern::REASSOC_XA_BY: Row = 2; break;
     723         269 :   case MachineCombinerPattern::REASSOC_XA_YB: Row = 3; break;
     724           0 :   default: llvm_unreachable("unexpected MachineCombinerPattern");
     725             :   }
     726             : 
     727        3010 :   MachineOperand &OpA = Prev.getOperand(OpIdx[Row][0]);
     728        3010 :   MachineOperand &OpB = Root.getOperand(OpIdx[Row][1]);
     729        3010 :   MachineOperand &OpX = Prev.getOperand(OpIdx[Row][2]);
     730        3010 :   MachineOperand &OpY = Root.getOperand(OpIdx[Row][3]);
     731        1505 :   MachineOperand &OpC = Root.getOperand(0);
     732             : 
     733        1505 :   unsigned RegA = OpA.getReg();
     734        1505 :   unsigned RegB = OpB.getReg();
     735        1505 :   unsigned RegX = OpX.getReg();
     736        1505 :   unsigned RegY = OpY.getReg();
     737        1505 :   unsigned RegC = OpC.getReg();
     738             : 
     739        1505 :   if (TargetRegisterInfo::isVirtualRegister(RegA))
     740        1505 :     MRI.constrainRegClass(RegA, RC);
     741        1505 :   if (TargetRegisterInfo::isVirtualRegister(RegB))
     742        1505 :     MRI.constrainRegClass(RegB, RC);
     743        1505 :   if (TargetRegisterInfo::isVirtualRegister(RegX))
     744        1505 :     MRI.constrainRegClass(RegX, RC);
     745        1505 :   if (TargetRegisterInfo::isVirtualRegister(RegY))
     746        1505 :     MRI.constrainRegClass(RegY, RC);
     747        1505 :   if (TargetRegisterInfo::isVirtualRegister(RegC))
     748        1505 :     MRI.constrainRegClass(RegC, RC);
     749             : 
     750             :   // Create a new virtual register for the result of (X op Y) instead of
     751             :   // recycling RegB because the MachineCombiner's computation of the critical
     752             :   // path requires a new register definition rather than an existing one.
     753        1505 :   unsigned NewVR = MRI.createVirtualRegister(RC);
     754        6020 :   InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
     755             : 
     756        3010 :   unsigned Opcode = Root.getOpcode();
     757        1505 :   bool KillA = OpA.isKill();
     758        1505 :   bool KillX = OpX.isKill();
     759        1505 :   bool KillY = OpY.isKill();
     760             : 
     761             :   // Create new instructions for insertion.
     762             :   MachineInstrBuilder MIB1 =
     763        6020 :       BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
     764        1505 :           .addReg(RegX, getKillRegState(KillX))
     765        1505 :           .addReg(RegY, getKillRegState(KillY));
     766             :   MachineInstrBuilder MIB2 =
     767        6020 :       BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
     768        1505 :           .addReg(RegA, getKillRegState(KillA))
     769        1505 :           .addReg(NewVR, getKillRegState(true));
     770             : 
     771        1505 :   setSpecialOperandAttr(Root, Prev, *MIB1, *MIB2);
     772             : 
     773             :   // Record new instructions for insertion and old instructions for deletion.
     774        1505 :   InsInstrs.push_back(MIB1);
     775        1505 :   InsInstrs.push_back(MIB2);
     776        1505 :   DelInstrs.push_back(&Prev);
     777        1505 :   DelInstrs.push_back(&Root);
     778        1505 : }
     779             : 
     780        1505 : void TargetInstrInfo::genAlternativeCodeSequence(
     781             :     MachineInstr &Root, MachineCombinerPattern Pattern,
     782             :     SmallVectorImpl<MachineInstr *> &InsInstrs,
     783             :     SmallVectorImpl<MachineInstr *> &DelInstrs,
     784             :     DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
     785        1505 :   MachineRegisterInfo &MRI = Root.getParent()->getParent()->getRegInfo();
     786             : 
     787             :   // Select the previous instruction in the sequence based on the input pattern.
     788        1505 :   MachineInstr *Prev = nullptr;
     789        1505 :   switch (Pattern) {
     790         917 :   case MachineCombinerPattern::REASSOC_AX_BY:
     791             :   case MachineCombinerPattern::REASSOC_XA_BY:
     792         917 :     Prev = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
     793         917 :     break;
     794         588 :   case MachineCombinerPattern::REASSOC_AX_YB:
     795             :   case MachineCombinerPattern::REASSOC_XA_YB:
     796         588 :     Prev = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
     797         588 :     break;
     798             :   default:
     799             :     break;
     800             :   }
     801             : 
     802             :   assert(Prev && "Unknown pattern for machine combiner");
     803             : 
     804        1505 :   reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg);
     805        1505 : }
     806             : 
     807             : /// foldMemoryOperand - Same as the previous version except it allows folding
     808             : /// of any load and store from / to any address, not just from a specific
     809             : /// stack slot.
     810       97557 : MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
     811             :                                                  ArrayRef<unsigned> Ops,
     812             :                                                  MachineInstr &LoadMI,
     813             :                                                  LiveIntervals *LIS) const {
     814             :   assert(LoadMI.canFoldAsLoad() && "LoadMI isn't foldable!");
     815             : #ifndef NDEBUG
     816             :   for (unsigned i = 0, e = Ops.size(); i != e; ++i)
     817             :     assert(MI.getOperand(Ops[i]).isUse() && "Folding load into def!");
     818             : #endif
     819       97557 :   MachineBasicBlock &MBB = *MI.getParent();
     820       97557 :   MachineFunction &MF = *MBB.getParent();
     821             : 
     822             :   // Ask the target to do the actual folding.
     823       97557 :   MachineInstr *NewMI = nullptr;
     824       97557 :   int FrameIndex = 0;
     825             : 
     826      195098 :   if ((MI.getOpcode() == TargetOpcode::STACKMAP ||
     827      195006 :        MI.getOpcode() == TargetOpcode::PATCHPOINT ||
     828      195137 :        MI.getOpcode() == TargetOpcode::STATEPOINT) &&
     829         115 :       isLoadFromStackSlot(LoadMI, FrameIndex)) {
     830             :     // Fold stackmap/patchpoint.
     831         115 :     NewMI = foldPatchpoint(MF, MI, Ops, FrameIndex, *this);
     832         115 :     if (NewMI)
     833         210 :       NewMI = &*MBB.insert(MI, NewMI);
     834             :   } else {
     835             :     // Ask the target to do the actual folding.
     836      194884 :     NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, LoadMI, LIS);
     837             :   }
     838             : 
     839       97557 :   if (!NewMI) return nullptr;
     840             : 
     841             :   // Copy the memoperands from the load to the folded instruction.
     842        4247 :   if (MI.memoperands_empty()) {
     843        8368 :     NewMI->setMemRefs(LoadMI.memoperands_begin(), LoadMI.memoperands_end());
     844             :   }
     845             :   else {
     846             :     // Handle the rare case of folding multiple loads.
     847         189 :     NewMI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
     848         126 :     for (MachineInstr::mmo_iterator I = LoadMI.memoperands_begin(),
     849         126 :                                     E = LoadMI.memoperands_end();
     850         126 :          I != E; ++I) {
     851          63 :       NewMI->addMemOperand(MF, *I);
     852             :     }
     853             :   }
     854             :   return NewMI;
     855             : }
     856             : 
     857      321413 : bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
     858             :     const MachineInstr &MI, AliasAnalysis *AA) const {
     859      321413 :   const MachineFunction &MF = *MI.getParent()->getParent();
     860      321413 :   const MachineRegisterInfo &MRI = MF.getRegInfo();
     861             : 
     862             :   // Remat clients assume operand 0 is the defined register.
     863      642826 :   if (!MI.getNumOperands() || !MI.getOperand(0).isReg())
     864             :     return false;
     865      321413 :   unsigned DefReg = MI.getOperand(0).getReg();
     866             : 
     867             :   // A sub-register definition can only be rematerialized if the instruction
     868             :   // doesn't read the other parts of the register.  Otherwise it is really a
     869             :   // read-modify-write operation on the full virtual register which cannot be
     870             :   // moved safely.
     871      642826 :   if (TargetRegisterInfo::isVirtualRegister(DefReg) &&
     872      662308 :       MI.getOperand(0).getSubReg() && MI.readsVirtualRegister(DefReg))
     873             :     return false;
     874             : 
     875             :   // A load from a fixed stack slot can be rematerialized. This may be
     876             :   // redundant with subsequent checks, but it's target-independent,
     877             :   // simple, and a common case.
     878      304621 :   int FrameIdx = 0;
     879      329967 :   if (isLoadFromStackSlot(MI, FrameIdx) &&
     880       51026 :       MF.getFrameInfo().isImmutableObjectIndex(FrameIdx))
     881             :     return true;
     882             : 
     883             :   // Avoid instructions obviously unsafe for remat.
     884      290713 :   if (MI.isNotDuplicable() || MI.mayStore() || MI.hasUnmodeledSideEffects())
     885             :     return false;
     886             : 
     887             :   // Don't remat inline asm. We have no idea how expensive it is
     888             :   // even if it's side effect free.
     889      290692 :   if (MI.isInlineAsm())
     890             :     return false;
     891             : 
     892             :   // Avoid instructions which load from potentially varying memory.
     893      290692 :   if (MI.mayLoad() && !MI.isDereferenceableInvariantLoad(AA))
     894             :     return false;
     895             : 
     896             :   // If any of the registers accessed are non-constant, conservatively assume
     897             :   // the instruction is not rematerializable.
     898     1043599 :   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     899     1821856 :     const MachineOperand &MO = MI.getOperand(i);
     900      910928 :     if (!MO.isReg()) continue;
     901      651528 :     unsigned Reg = MO.getReg();
     902      651528 :     if (Reg == 0)
     903      239633 :       continue;
     904             : 
     905             :     // Check for a well-behaved physical register.
     906      524563 :     if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
     907      114116 :       if (MO.isUse()) {
     908             :         // If the physreg has no defs anywhere, it's just an ambient register
     909             :         // and we can freely move its uses. Alternatively, if it's allocatable,
     910             :         // it could get allocated to something with a def during allocation.
     911      114116 :         if (!MRI.isConstantPhysReg(Reg))
     912             :           return false;
     913             :       } else {
     914             :         // A physreg def. We can't remat it.
     915             :         return false;
     916             :       }
     917      112668 :       continue;
     918             :     }
     919             : 
     920             :     // Only allow one virtual-register def.  There may be multiple defs of the
     921             :     // same virtual register, though.
     922      297779 :     if (MO.isDef() && Reg != DefReg)
     923             :       return false;
     924             : 
     925             :     // Don't allow any virtual-register uses. Rematting an instruction with
     926             :     // virtual register uses would length the live ranges of the uses, which
     927             :     // is not necessarily a good idea, certainly not "trivial".
     928      297779 :     if (MO.isUse())
     929             :       return false;
     930             :   }
     931             : 
     932             :   // Everything checked out.
     933             :   return true;
     934             : }
     935             : 
     936        1800 : int TargetInstrInfo::getSPAdjust(const MachineInstr &MI) const {
     937        1800 :   const MachineFunction *MF = MI.getParent()->getParent();
     938        1800 :   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
     939             :   bool StackGrowsDown =
     940        1800 :     TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
     941             : 
     942        1800 :   unsigned FrameSetupOpcode = getCallFrameSetupOpcode();
     943        1800 :   unsigned FrameDestroyOpcode = getCallFrameDestroyOpcode();
     944             : 
     945             :   if (!isFrameInstr(MI))
     946             :     return 0;
     947             : 
     948         264 :   int SPAdj = TFI->alignSPAdjust(getFrameSize(MI));
     949             : 
     950          88 :   if ((!StackGrowsDown && MI.getOpcode() == FrameSetupOpcode) ||
     951          88 :       (StackGrowsDown && MI.getOpcode() == FrameDestroyOpcode))
     952          44 :     SPAdj = -SPAdj;
     953             : 
     954             :   return SPAdj;
     955             : }
     956             : 
     957             : /// isSchedulingBoundary - Test if the given instruction should be
     958             : /// considered a scheduling boundary. This primarily includes labels
     959             : /// and terminators.
     960     4255815 : bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
     961             :                                            const MachineBasicBlock *MBB,
     962             :                                            const MachineFunction &MF) const {
     963             :   // Terminators and labels can't be scheduled around.
     964     7863024 :   if (MI.isTerminator() || MI.isPosition())
     965             :     return true;
     966             : 
     967             :   // Don't attempt to schedule around any instruction that defines
     968             :   // a stack-oriented pointer, as it's unlikely to be profitable. This
     969             :   // saves compile time, because it doesn't require every single
     970             :   // stack slot reference to depend on the instruction that does the
     971             :   // modification.
     972     3607209 :   const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
     973     3607209 :   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
     974     7214418 :   return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI);
     975             : }
     976             : 
     977             : // Provide a global flag for disabling the PreRA hazard recognizer that targets
     978             : // may choose to honor.
     979        9380 : bool TargetInstrInfo::usePreRAHazardRecognizer() const {
     980        9380 :   return !DisableHazardRecognizer;
     981             : }
     982             : 
     983             : // Default implementation of CreateTargetRAHazardRecognizer.
     984       17669 : ScheduleHazardRecognizer *TargetInstrInfo::
     985             : CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
     986             :                              const ScheduleDAG *DAG) const {
     987             :   // Dummy hazard recognizer allows all instructions to issue.
     988       35338 :   return new ScheduleHazardRecognizer();
     989             : }
     990             : 
     991             : // Default implementation of CreateTargetMIHazardRecognizer.
     992      203546 : ScheduleHazardRecognizer *TargetInstrInfo::
     993             : CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
     994             :                                const ScheduleDAG *DAG) const {
     995             :   return (ScheduleHazardRecognizer *)
     996      203546 :     new ScoreboardHazardRecognizer(II, DAG, "misched");
     997             : }
     998             : 
     999             : // Default implementation of CreateTargetPostRAHazardRecognizer.
    1000        6286 : ScheduleHazardRecognizer *TargetInstrInfo::
    1001             : CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
    1002             :                                    const ScheduleDAG *DAG) const {
    1003             :   return (ScheduleHazardRecognizer *)
    1004        6286 :     new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
    1005             : }
    1006             : 
    1007             : //===----------------------------------------------------------------------===//
    1008             : //  SelectionDAG latency interface.
    1009             : //===----------------------------------------------------------------------===//
    1010             : 
    1011             : int
    1012      109826 : TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
    1013             :                                    SDNode *DefNode, unsigned DefIdx,
    1014             :                                    SDNode *UseNode, unsigned UseIdx) const {
    1015      109826 :   if (!ItinData || ItinData->isEmpty())
    1016             :     return -1;
    1017             : 
    1018       12896 :   if (!DefNode->isMachineOpcode())
    1019             :     return -1;
    1020             : 
    1021       35348 :   unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
    1022        8837 :   if (!UseNode->isMachineOpcode())
    1023             :     return ItinData->getOperandCycle(DefClass, DefIdx);
    1024       24812 :   unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
    1025        6203 :   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
    1026             : }
    1027             : 
    1028       13190 : int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
    1029             :                                      SDNode *N) const {
    1030       13190 :   if (!ItinData || ItinData->isEmpty())
    1031             :     return 1;
    1032             : 
    1033       13190 :   if (!N->isMachineOpcode())
    1034             :     return 1;
    1035             : 
    1036       52760 :   return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
    1037             : }
    1038             : 
    1039             : //===----------------------------------------------------------------------===//
    1040             : //  MachineInstr latency interface.
    1041             : //===----------------------------------------------------------------------===//
    1042             : 
    1043           0 : unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
    1044             :                                          const MachineInstr &MI) const {
    1045           0 :   if (!ItinData || ItinData->isEmpty())
    1046             :     return 1;
    1047             : 
    1048           0 :   unsigned Class = MI.getDesc().getSchedClass();
    1049           0 :   int UOps = ItinData->Itineraries[Class].NumMicroOps;
    1050           0 :   if (UOps >= 0)
    1051           0 :     return UOps;
    1052             : 
    1053             :   // The # of u-ops is dynamically determined. The specific target should
    1054             :   // override this function to return the right number.
    1055             :   return 1;
    1056             : }
    1057             : 
    1058             : /// Return the default expected latency for a def based on it's opcode.
    1059     4159008 : unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel,
    1060             :                                             const MachineInstr &DefMI) const {
    1061             :   if (DefMI.isTransient())
    1062             :     return 0;
    1063     3199554 :   if (DefMI.mayLoad())
    1064      972771 :     return SchedModel.LoadLatency;
    1065     4453566 :   if (isHighLatencyDef(DefMI.getOpcode()))
    1066        1025 :     return SchedModel.HighLatency;
    1067             :   return 1;
    1068             : }
    1069             : 
    1070       24619 : unsigned TargetInstrInfo::getPredicationCost(const MachineInstr &) const {
    1071       24619 :   return 0;
    1072             : }
    1073             : 
    1074       26031 : unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
    1075             :                                           const MachineInstr &MI,
    1076             :                                           unsigned *PredCost) const {
    1077             :   // Default to one cycle for no itinerary. However, an "empty" itinerary may
    1078             :   // still have a MinLatency property, which getStageLatency checks.
    1079       26031 :   if (!ItinData)
    1080          45 :     return MI.mayLoad() ? 2 : 1;
    1081             : 
    1082       51972 :   return ItinData->getStageLatency(MI.getDesc().getSchedClass());
    1083             : }
    1084             : 
    1085       28388 : bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
    1086             :                                        const MachineInstr &DefMI,
    1087             :                                        unsigned DefIdx) const {
    1088          90 :   const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
    1089          90 :   if (!ItinData || ItinData->isEmpty())
    1090             :     return false;
    1091             : 
    1092          90 :   unsigned DefClass = DefMI.getDesc().getSchedClass();
    1093          90 :   int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
    1094          90 :   return (DefCycle != -1 && DefCycle <= 1);
    1095             : }
    1096             : 
    1097             : /// Both DefMI and UseMI must be valid.  By default, call directly to the
    1098             : /// itinerary. This may be overriden by the target.
    1099      244094 : int TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
    1100             :                                        const MachineInstr &DefMI,
    1101             :                                        unsigned DefIdx,
    1102             :                                        const MachineInstr &UseMI,
    1103             :                                        unsigned UseIdx) const {
    1104      488188 :   unsigned DefClass = DefMI.getDesc().getSchedClass();
    1105      488188 :   unsigned UseClass = UseMI.getDesc().getSchedClass();
    1106      244094 :   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
    1107             : }
    1108             : 
    1109             : /// If we can determine the operand latency from the def only, without itinerary
    1110             : /// lookup, do so. Otherwise return -1.
    1111           0 : int TargetInstrInfo::computeDefOperandLatency(
    1112             :     const InstrItineraryData *ItinData, const MachineInstr &DefMI) const {
    1113             : 
    1114             :   // Let the target hook getInstrLatency handle missing itineraries.
    1115           0 :   if (!ItinData)
    1116           0 :     return getInstrLatency(ItinData, DefMI);
    1117             : 
    1118           0 :   if(ItinData->isEmpty())
    1119           0 :     return defaultDefLatency(ItinData->SchedModel, DefMI);
    1120             : 
    1121             :   // ...operand lookup required
    1122             :   return -1;
    1123             : }
    1124             : 
    1125      165171 : bool TargetInstrInfo::getRegSequenceInputs(
    1126             :     const MachineInstr &MI, unsigned DefIdx,
    1127             :     SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
    1128             :   assert((MI.isRegSequence() ||
    1129             :           MI.isRegSequenceLike()) && "Instruction do not have the proper type");
    1130             : 
    1131      165171 :   if (!MI.isRegSequence())
    1132        1274 :     return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);
    1133             : 
    1134             :   // We are looking at:
    1135             :   // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
    1136             :   assert(DefIdx == 0 && "REG_SEQUENCE only has one def");
    1137      672666 :   for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx;
    1138      508769 :        OpIdx += 2) {
    1139     1017538 :     const MachineOperand &MOReg = MI.getOperand(OpIdx);
    1140     1017538 :     const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1);
    1141             :     assert(MOSubIdx.isImm() &&
    1142             :            "One of the subindex of the reg_sequence is not an immediate");
    1143             :     // Record Reg:SubReg, SubIdx.
    1144     1526307 :     InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(),
    1145             :                                             (unsigned)MOSubIdx.getImm()));
    1146             :   }
    1147             :   return true;
    1148             : }
    1149             : 
    1150        2879 : bool TargetInstrInfo::getExtractSubregInputs(
    1151             :     const MachineInstr &MI, unsigned DefIdx,
    1152             :     RegSubRegPairAndIdx &InputReg) const {
    1153             :   assert((MI.isExtractSubreg() ||
    1154             :       MI.isExtractSubregLike()) && "Instruction do not have the proper type");
    1155             : 
    1156        2879 :   if (!MI.isExtractSubreg())
    1157        2879 :     return getExtractSubregLikeInputs(MI, DefIdx, InputReg);
    1158             : 
    1159             :   // We are looking at:
    1160             :   // Def = EXTRACT_SUBREG v0.sub1, sub0.
    1161             :   assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");
    1162           0 :   const MachineOperand &MOReg = MI.getOperand(1);
    1163           0 :   const MachineOperand &MOSubIdx = MI.getOperand(2);
    1164             :   assert(MOSubIdx.isImm() &&
    1165             :          "The subindex of the extract_subreg is not an immediate");
    1166             : 
    1167           0 :   InputReg.Reg = MOReg.getReg();
    1168           0 :   InputReg.SubReg = MOReg.getSubReg();
    1169           0 :   InputReg.SubIdx = (unsigned)MOSubIdx.getImm();
    1170           0 :   return true;
    1171             : }
    1172             : 
    1173       22580 : bool TargetInstrInfo::getInsertSubregInputs(
    1174             :     const MachineInstr &MI, unsigned DefIdx,
    1175             :     RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const {
    1176             :   assert((MI.isInsertSubreg() ||
    1177             :       MI.isInsertSubregLike()) && "Instruction do not have the proper type");
    1178             : 
    1179       22580 :   if (!MI.isInsertSubreg())
    1180         195 :     return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);
    1181             : 
    1182             :   // We are looking at:
    1183             :   // Def = INSERT_SEQUENCE v0, v1, sub0.
    1184             :   assert(DefIdx == 0 && "INSERT_SUBREG only has one def");
    1185       22385 :   const MachineOperand &MOBaseReg = MI.getOperand(1);
    1186       22385 :   const MachineOperand &MOInsertedReg = MI.getOperand(2);
    1187       22385 :   const MachineOperand &MOSubIdx = MI.getOperand(3);
    1188             :   assert(MOSubIdx.isImm() &&
    1189             :          "One of the subindex of the reg_sequence is not an immediate");
    1190       22385 :   BaseReg.Reg = MOBaseReg.getReg();
    1191       22385 :   BaseReg.SubReg = MOBaseReg.getSubReg();
    1192             : 
    1193       22385 :   InsertedReg.Reg = MOInsertedReg.getReg();
    1194       22385 :   InsertedReg.SubReg = MOInsertedReg.getSubReg();
    1195       22385 :   InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm();
    1196       22385 :   return true;
    1197      216918 : }

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