LCOV - code coverage report
Current view: top level - lib/CodeGen - TargetPassConfig.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 466 498 93.6 %
Date: 2017-09-14 15:23:50 Functions: 44 48 91.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file defines interfaces to access the target independent code
      11             : // generation passes provided by the LLVM backend.
      12             : //
      13             : //===---------------------------------------------------------------------===//
      14             : 
      15             : #include "llvm/CodeGen/TargetPassConfig.h"
      16             : #include "llvm/ADT/DenseMap.h"
      17             : #include "llvm/ADT/SmallVector.h"
      18             : #include "llvm/ADT/StringRef.h"
      19             : #include "llvm/Analysis/BasicAliasAnalysis.h"
      20             : #include "llvm/Analysis/CFLAndersAliasAnalysis.h"
      21             : #include "llvm/Analysis/CFLSteensAliasAnalysis.h"
      22             : #include "llvm/Analysis/CallGraphSCCPass.h"
      23             : #include "llvm/Analysis/ScopedNoAliasAA.h"
      24             : #include "llvm/Analysis/TargetTransformInfo.h"
      25             : #include "llvm/Analysis/TypeBasedAliasAnalysis.h"
      26             : #include "llvm/CodeGen/MachineFunctionPass.h"
      27             : #include "llvm/CodeGen/MachinePassRegistry.h"
      28             : #include "llvm/CodeGen/Passes.h"
      29             : #include "llvm/CodeGen/RegAllocRegistry.h"
      30             : #include "llvm/IR/IRPrintingPasses.h"
      31             : #include "llvm/IR/LegacyPassManager.h"
      32             : #include "llvm/IR/Verifier.h"
      33             : #include "llvm/MC/MCAsmInfo.h"
      34             : #include "llvm/MC/MCTargetOptions.h"
      35             : #include "llvm/Pass.h"
      36             : #include "llvm/Support/CodeGen.h"
      37             : #include "llvm/Support/CommandLine.h"
      38             : #include "llvm/Support/Compiler.h"
      39             : #include "llvm/Support/Debug.h"
      40             : #include "llvm/Support/ErrorHandling.h"
      41             : #include "llvm/Support/Threading.h"
      42             : #include "llvm/Target/TargetMachine.h"
      43             : #include "llvm/Transforms/Scalar.h"
      44             : #include "llvm/Transforms/Utils/SymbolRewriter.h"
      45             : #include <cassert>
      46             : #include <string>
      47             : 
      48             : using namespace llvm;
      49             : 
      50      289224 : cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
      51      216918 :                          cl::desc("Enable interprocedural register allocation "
      52      216918 :                                   "to reduce load/store at procedure calls."));
      53       72306 : static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
      54      144612 :     cl::desc("Disable Post Regalloc Scheduler"));
      55       72306 : static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
      56      144612 :     cl::desc("Disable branch folding"));
      57       72306 : static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
      58      144612 :     cl::desc("Disable tail duplication"));
      59       72306 : static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
      60      144612 :     cl::desc("Disable pre-register allocation tail duplication"));
      61       72306 : static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
      62      144612 :     cl::Hidden, cl::desc("Disable probability-driven block placement"));
      63       72306 : static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
      64      144612 :     cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
      65       72306 : static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
      66      144612 :     cl::desc("Disable Stack Slot Coloring"));
      67       72306 : static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
      68      144612 :     cl::desc("Disable Machine Dead Code Elimination"));
      69       72306 : static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
      70      144612 :     cl::desc("Disable Early If-conversion"));
      71       72306 : static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
      72      144612 :     cl::desc("Disable Machine LICM"));
      73       72306 : static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
      74      144612 :     cl::desc("Disable Machine Common Subexpression Elimination"));
      75       72306 : static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
      76             :     "optimize-regalloc", cl::Hidden,
      77      144612 :     cl::desc("Enable optimized register allocation compilation path."));
      78       72306 : static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
      79             :     cl::Hidden,
      80      144612 :     cl::desc("Disable Machine LICM"));
      81       72306 : static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
      82      144612 :     cl::desc("Disable Machine Sinking"));
      83       72306 : static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
      84      144612 :     cl::desc("Disable Loop Strength Reduction Pass"));
      85       72306 : static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
      86      144612 :     cl::Hidden, cl::desc("Disable ConstantHoisting"));
      87       72306 : static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
      88      144612 :     cl::desc("Disable Codegen Prepare"));
      89       72306 : static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
      90      144612 :     cl::desc("Disable Copy Propagation pass"));
      91       72306 : static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
      92      144612 :     cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
      93       72306 : static cl::opt<bool> EnableImplicitNullChecks(
      94             :     "enable-implicit-null-checks",
      95      216918 :     cl::desc("Fold null checks into faulting memory operations"),
      96      289224 :     cl::init(false));
      97       72306 : static cl::opt<bool> EnableMergeICmps(
      98             :     "enable-mergeicmps",
      99      216918 :     cl::desc("Merge ICmp chains into a single memcmp"),
     100      289224 :     cl::init(false));
     101       72306 : static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
     102      144612 :     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
     103       72306 : static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
     104      144612 :     cl::desc("Print LLVM IR input to isel pass"));
     105       72306 : static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
     106      144612 :     cl::desc("Dump garbage collector data"));
     107       72306 : static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
     108      216918 :     cl::desc("Verify generated machine code"),
     109      216918 :     cl::init(false),
     110      216918 :     cl::ZeroOrMore);
     111       72306 : static cl::opt<bool> EnableMachineOutliner("enable-machine-outliner",
     112             :     cl::Hidden,
     113      144612 :     cl::desc("Enable machine outliner"));
     114             : // Enable or disable FastISel. Both options are needed, because
     115             : // FastISel is enabled by default with -fast, and we wish to be
     116             : // able to enable or disable fast-isel independently from -O0.
     117             : static cl::opt<cl::boolOrDefault>
     118       72306 : EnableFastISelOption("fast-isel", cl::Hidden,
     119      144612 :   cl::desc("Enable the \"fast\" instruction selector"));
     120             : 
     121             : static cl::opt<cl::boolOrDefault>
     122       72306 :     EnableGlobalISel("global-isel", cl::Hidden,
     123      144612 :                      cl::desc("Enable the \"global\" instruction selector"));
     124             : 
     125             : static cl::opt<std::string>
     126       72306 : PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
     127      216918 :                    cl::desc("Print machine instrs"),
     128      289224 :                    cl::value_desc("pass-name"), cl::init("option-unspecified"));
     129             : 
     130       72306 : static cl::opt<int> EnableGlobalISelAbort(
     131             :     "global-isel-abort", cl::Hidden,
     132      216918 :     cl::desc("Enable abort calls when \"global\" instruction selection "
     133             :              "fails to lower/select an instruction: 0 disable the abort, "
     134             :              "1 enable the abort, and "
     135             :              "2 disable the abort but emit a diagnostic on failure"),
     136      289224 :     cl::init(1));
     137             : 
     138             : // Temporary option to allow experimenting with MachineScheduler as a post-RA
     139             : // scheduler. Targets can "properly" enable this with
     140             : // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
     141             : // Targets can return true in targetSchedulesPostRAScheduling() and
     142             : // insert a PostRA scheduling pass wherever it wants.
     143       72306 : cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
     144      144612 :   cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
     145             : 
     146             : // Experimental option to run live interval analysis early.
     147       72306 : static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
     148      144612 :     cl::desc("Run live interval analysis earlier in the pipeline"));
     149             : 
     150             : // Experimental option to use CFL-AA in codegen
     151             : enum class CFLAAType { None, Steensgaard, Andersen, Both };
     152       72306 : static cl::opt<CFLAAType> UseCFLAA(
     153      216918 :     "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
     154      216918 :     cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
     155      650754 :     cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
     156             :                clEnumValN(CFLAAType::Steensgaard, "steens",
     157             :                           "Enable unification-based CFL-AA"),
     158             :                clEnumValN(CFLAAType::Andersen, "anders",
     159             :                           "Enable inclusion-based CFL-AA"),
     160             :                clEnumValN(CFLAAType::Both, "both", 
     161      216918 :                           "Enable both variants of CFL-AA")));
     162             : 
     163             : /// Option names for limiting the codegen pipeline.
     164             : /// Those are used in error reporting and we didn't want
     165             : /// to duplicate their names all over the place.
     166             : const char *StartAfterOptName = "start-after";
     167             : const char *StartBeforeOptName = "start-before";
     168             : const char *StopAfterOptName = "stop-after";
     169             : const char *StopBeforeOptName = "stop-before";
     170             : 
     171             : static cl::opt<std::string>
     172      289224 :     StartAfterOpt(StringRef(StartAfterOptName),
     173      216918 :                   cl::desc("Resume compilation after a specific pass"),
     174      289224 :                   cl::value_desc("pass-name"), cl::init(""));
     175             : 
     176             : static cl::opt<std::string>
     177      289224 :     StartBeforeOpt(StringRef(StartBeforeOptName),
     178      216918 :                    cl::desc("Resume compilation before a specific pass"),
     179      289224 :                    cl::value_desc("pass-name"), cl::init(""));
     180             : 
     181             : static cl::opt<std::string>
     182      289224 :     StopAfterOpt(StringRef(StopAfterOptName),
     183      216918 :                  cl::desc("Stop compilation after a specific pass"),
     184      289224 :                  cl::value_desc("pass-name"), cl::init(""));
     185             : 
     186             : static cl::opt<std::string>
     187      289224 :     StopBeforeOpt(StringRef(StopBeforeOptName),
     188      216918 :                   cl::desc("Stop compilation before a specific pass"),
     189      289224 :                   cl::value_desc("pass-name"), cl::init(""));
     190             : 
     191             : /// Allow standard passes to be disabled by command line options. This supports
     192             : /// simple binary flags that either suppress the pass or do nothing.
     193             : /// i.e. -disable-mypass=false has no effect.
     194             : /// These should be converted to boolOrDefault in order to use applyOverride.
     195             : static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
     196             :                                        bool Override) {
     197      217483 :   if (Override)
     198             :     return IdentifyingPassPtr();
     199      217347 :   return PassID;
     200             : }
     201             : 
     202             : /// Allow standard passes to be disabled by the command line, regardless of who
     203             : /// is adding the pass.
     204             : ///
     205             : /// StandardID is the pass identified in the standard pass pipeline and provided
     206             : /// to addPass(). It may be a target-specific ID in the case that the target
     207             : /// directly adds its own pass, but in that case we harmlessly fall through.
     208             : ///
     209             : /// TargetID is the pass that the target has configured to override StandardID.
     210             : ///
     211             : /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
     212             : /// pass to run. This allows multiple options to control a single pass depending
     213             : /// on where in the pipeline that pass is added.
     214      659247 : static IdentifyingPassPtr overridePass(AnalysisID StandardID,
     215             :                                        IdentifyingPassPtr TargetID) {
     216      659247 :   if (StandardID == &PostRASchedulerID)
     217       14824 :     return applyDisable(TargetID, DisablePostRASched);
     218             : 
     219      644423 :   if (StandardID == &BranchFolderPassID)
     220       15613 :     return applyDisable(TargetID, DisableBranchFold);
     221             : 
     222      628810 :   if (StandardID == &TailDuplicateID)
     223       15370 :     return applyDisable(TargetID, DisableTailDuplicate);
     224             : 
     225      613440 :   if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
     226       15613 :     return applyDisable(TargetID, DisableEarlyTailDup);
     227             : 
     228      597827 :   if (StandardID == &MachineBlockPlacementID)
     229       15613 :     return applyDisable(TargetID, DisableBlockPlacement);
     230             : 
     231      582214 :   if (StandardID == &StackSlotColoringID)
     232       15599 :     return applyDisable(TargetID, DisableSSC);
     233             : 
     234      566615 :   if (StandardID == &DeadMachineInstructionElimID)
     235       35073 :     return applyDisable(TargetID, DisableMachineDCE);
     236             : 
     237      531542 :   if (StandardID == &EarlyIfConverterID)
     238        9089 :     return applyDisable(TargetID, DisableEarlyIfConversion);
     239             : 
     240      522453 :   if (StandardID == &MachineLICMID)
     241       17033 :     return applyDisable(TargetID, DisableMachineLICM);
     242             : 
     243      505420 :   if (StandardID == &MachineCSEID)
     244       17033 :     return applyDisable(TargetID, DisableMachineCSE);
     245             : 
     246      488387 :   if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
     247       15397 :     return applyDisable(TargetID, DisablePostRAMachineLICM);
     248             : 
     249      472990 :   if (StandardID == &MachineSinkingID)
     250       15613 :     return applyDisable(TargetID, DisableMachineSink);
     251             : 
     252      457377 :   if (StandardID == &MachineCopyPropagationID)
     253       15613 :     return applyDisable(TargetID, DisableCopyProp);
     254             : 
     255      441764 :   return TargetID;
     256             : }
     257             : 
     258             : //===---------------------------------------------------------------------===//
     259             : /// TargetPassConfig
     260             : //===---------------------------------------------------------------------===//
     261             : 
     262     1235950 : INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
     263             :                 "Target Pass Configuration", false, false)
     264             : char TargetPassConfig::ID = 0;
     265             : 
     266             : // Pseudo Pass IDs.
     267             : char TargetPassConfig::EarlyTailDuplicateID = 0;
     268             : char TargetPassConfig::PostRAMachineLICMID = 0;
     269             : 
     270             : namespace {
     271             : 
     272             : struct InsertedPass {
     273             :   AnalysisID TargetPassID;
     274             :   IdentifyingPassPtr InsertedPassID;
     275             :   bool VerifyAfter;
     276             :   bool PrintAfter;
     277             : 
     278             :   InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
     279             :                bool VerifyAfter, bool PrintAfter)
     280        5987 :       : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
     281        5987 :         VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
     282             : 
     283             :   Pass *getInsertedPass() const {
     284             :     assert(InsertedPassID.isValid() && "Illegal Pass ID!");
     285        5955 :     if (InsertedPassID.isInstance())
     286             :       return InsertedPassID.getInstance();
     287        5955 :     Pass *NP = Pass::createPass(InsertedPassID.getID());
     288             :     assert(NP && "Pass ID not registered");
     289             :     return NP;
     290             :   }
     291             : };
     292             : 
     293             : } // end anonymous namespace
     294             : 
     295             : namespace llvm {
     296             : 
     297      121673 : class PassConfigImpl {
     298             : public:
     299             :   // List of passes explicitly substituted by this target. Normally this is
     300             :   // empty, but it is a convenient way to suppress or replace specific passes
     301             :   // that are part of a standard pass pipeline without overridding the entire
     302             :   // pipeline. This mechanism allows target options to inherit a standard pass's
     303             :   // user interface. For example, a target may disable a standard pass by
     304             :   // default by substituting a pass ID of zero, and the user may still enable
     305             :   // that standard pass with an explicit command line option.
     306             :   DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
     307             : 
     308             :   /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
     309             :   /// is inserted after each instance of the first one.
     310             :   SmallVector<InsertedPass, 4> InsertedPasses;
     311             : };
     312             : 
     313             : } // end namespace llvm
     314             : 
     315             : // Out of line virtual method.
     316       40434 : TargetPassConfig::~TargetPassConfig() {
     317       20217 :   delete Impl;
     318       20217 : }
     319             : 
     320       81358 : static const PassInfo *getPassInfo(StringRef PassName) {
     321       81358 :   if (PassName.empty())
     322             :     return nullptr;
     323             : 
     324         113 :   const PassRegistry &PR = *PassRegistry::getPassRegistry();
     325         113 :   const PassInfo *PI = PR.getPassInfo(PassName);
     326         113 :   if (!PI)
     327          16 :     report_fatal_error(Twine('\"') + Twine(PassName) +
     328           4 :                        Twine("\" pass is not registered."));
     329             :   return PI;
     330             : }
     331             : 
     332             : static AnalysisID getPassIDFromName(StringRef PassName) {
     333       81358 :   const PassInfo *PI = getPassInfo(PassName);
     334       81354 :   return PI ? PI->getTypeInfo() : nullptr;
     335             : }
     336             : 
     337       20341 : void TargetPassConfig::setStartStopPasses() {
     338       40681 :   StartBefore = getPassIDFromName(StartBeforeOpt);
     339       40679 :   StartAfter = getPassIDFromName(StartAfterOpt);
     340       40677 :   StopBefore = getPassIDFromName(StopBeforeOpt);
     341       40675 :   StopAfter = getPassIDFromName(StopAfterOpt);
     342       20337 :   if (StartBefore && StartAfter)
     343           5 :     report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
     344           3 :                        Twine(StartAfterOptName) + Twine(" specified!"));
     345       20336 :   if (StopBefore && StopAfter)
     346           5 :     report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
     347           3 :                        Twine(StopAfterOptName) + Twine(" specified!"));
     348       20335 :   Started = (StartAfter == nullptr) && (StartBefore == nullptr);
     349       20335 : }
     350             : 
     351             : // Out of line constructor provides default values for pass options and
     352             : // registers all common codegen passes.
     353       20341 : TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
     354       40682 :     : ImmutablePass(ID), PM(&pm), TM(&TM) {
     355       40682 :   Impl = new PassConfigImpl();
     356             : 
     357             :   // Register all target independent codegen passes to activate their PassIDs,
     358             :   // including this pass itself.
     359       20341 :   initializeCodeGen(*PassRegistry::getPassRegistry());
     360             : 
     361             :   // Also register alias analysis passes required by codegen passes.
     362       20341 :   initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
     363       20341 :   initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
     364             : 
     365             :   // Substitute Pseudo Pass IDs for real ones.
     366       40682 :   substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
     367       40682 :   substitutePass(&PostRAMachineLICMID, &MachineLICMID);
     368             : 
     369       61023 :   if (StringRef(PrintMachineInstrs.getValue()).equals(""))
     370           9 :     TM.Options.PrintMachineCode = true;
     371             : 
     372       20341 :   if (EnableIPRA.getNumOccurrences())
     373           6 :     TM.Options.EnableIPRA = EnableIPRA;
     374             :   else {
     375             :     // If not explicitly specified, use target default.
     376       20335 :     TM.Options.EnableIPRA = TM.useIPRA();
     377             :   }
     378             : 
     379       20341 :   if (TM.Options.EnableIPRA)
     380             :     setRequiresCodeGenSCCOrder();
     381             : 
     382       20341 :   setStartStopPasses();
     383       20335 : }
     384             : 
     385      391352 : CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
     386      391352 :   return TM->getOptLevel();
     387             : }
     388             : 
     389             : /// Insert InsertedPassID pass after TargetPassID.
     390        5987 : void TargetPassConfig::insertPass(AnalysisID TargetPassID,
     391             :                                   IdentifyingPassPtr InsertedPassID,
     392             :                                   bool VerifyAfter, bool PrintAfter) {
     393             :   assert(((!InsertedPassID.isInstance() &&
     394             :            TargetPassID != InsertedPassID.getID()) ||
     395             :           (InsertedPassID.isInstance() &&
     396             :            TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
     397             :          "Insert a pass after itself!");
     398        5987 :   Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
     399             :                                     PrintAfter);
     400        5987 : }
     401             : 
     402             : /// createPassConfig - Create a pass configuration object to be used by
     403             : /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
     404             : ///
     405             : /// Targets may override this to extend TargetPassConfig.
     406           0 : TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
     407           0 :   return new TargetPassConfig(*this, PM);
     408             : }
     409             : 
     410           1 : TargetPassConfig::TargetPassConfig()
     411           2 :   : ImmutablePass(ID) {
     412           1 :   report_fatal_error("Trying to construct TargetPassConfig without a target "
     413             :                      "machine. Scheduling a CodeGen pass without a target "
     414             :                      "triple set?");
     415             : }
     416             : 
     417       17558 : bool TargetPassConfig::hasLimitedCodeGenPipeline() const {
     418       17558 :   return StartBefore || StartAfter || StopBefore || StopAfter;
     419             : }
     420             : 
     421             : std::string
     422           0 : TargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) const {
     423           0 :   if (!hasLimitedCodeGenPipeline())
     424             :     return std::string();
     425           0 :   std::string Res;
     426             :   static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
     427             :                                               &StopAfterOpt, &StopBeforeOpt};
     428             :   static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
     429           0 :                                    StopAfterOptName, StopBeforeOptName};
     430             :   bool IsFirst = true;
     431           0 :   for (int Idx = 0; Idx < 4; ++Idx)
     432           0 :     if (!PassNames[Idx]->empty()) {
     433           0 :       if (!IsFirst)
     434             :         Res += Separator;
     435           0 :       IsFirst = false;
     436           0 :       Res += OptNames[Idx];
     437             :     }
     438           0 :   return Res;
     439             : }
     440             : 
     441             : // Helper to verify the analysis is really immutable.
     442       19272 : void TargetPassConfig::setOpt(bool &Opt, bool Val) {
     443             :   assert(!Initialized && "PassConfig is immutable");
     444       19272 :   Opt = Val;
     445       19272 : }
     446             : 
     447       52523 : void TargetPassConfig::substitutePass(AnalysisID StandardID,
     448             :                                       IdentifyingPassPtr TargetID) {
     449      105046 :   Impl->TargetPasses[StandardID] = TargetID;
     450       52523 : }
     451             : 
     452      659247 : IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
     453             :   DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
     454     1318494 :     I = Impl->TargetPasses.find(ID);
     455     1977741 :   if (I == Impl->TargetPasses.end())
     456      620441 :     return ID;
     457       38806 :   return I->second;
     458             : }
     459             : 
     460       16923 : bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
     461       16923 :   IdentifyingPassPtr TargetID = getPassSubstitution(ID);
     462       16923 :   IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
     463       33618 :   return !FinalPtr.isValid() || FinalPtr.isInstance() ||
     464       33618 :       FinalPtr.getID() != ID;
     465             : }
     466             : 
     467             : /// Add a pass to the PassManager if that pass is supposed to be run.  If the
     468             : /// Started/Stopped flags indicate either that the compilation should start at
     469             : /// a later pass or that it should stop after an earlier pass, then do not add
     470             : /// the pass.  Finally, compare the current pass against the StartAfter
     471             : /// and StopAfter options and change the Started/Stopped flags accordingly.
     472     1318886 : void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
     473             :   assert(!Initialized && "PassConfig is immutable");
     474             : 
     475             :   // Cache the Pass ID here in case the pass manager finds this pass is
     476             :   // redundant with ones already scheduled / available, and deletes it.
     477             :   // Fundamentally, once we add the pass to the manager, we no longer own it
     478             :   // and shouldn't reference it.
     479     1318886 :   AnalysisID PassID = P->getPassID();
     480             : 
     481     1318886 :   if (StartBefore == PassID)
     482          13 :     Started = true;
     483     1318886 :   if (StopBefore == PassID)
     484           8 :     Stopped = true;
     485     1318886 :   if (Started && !Stopped) {
     486     2629379 :     std::string Banner;
     487             :     // Construct banner message before PM->add() as that may delete the pass.
     488     1314689 :     if (AddingMachinePasses && (printAfter || verifyAfter))
     489     5823874 :       Banner = std::string("After ") + std::string(P->getPassName());
     490     1314689 :     PM->add(P);
     491     1314689 :     if (AddingMachinePasses) {
     492      831980 :       if (printAfter)
     493      831980 :         addPrintPass(Banner);
     494      831980 :       if (verifyAfter)
     495      537868 :         addVerifyPass(Banner);
     496             :     }
     497             : 
     498             :     // Add the passes after the pass P if there is any.
     499     4160994 :     for (auto IP : Impl->InsertedPasses) {
     500      216927 :       if (IP.TargetPassID == PassID)
     501       11910 :         addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
     502     1314690 :     }
     503             :   } else {
     504        4197 :     delete P;
     505             :   }
     506     1318886 :   if (StopAfter == PassID)
     507          56 :     Stopped = true;
     508     1318886 :   if (StartAfter == PassID)
     509          27 :     Started = true;
     510     1318886 :   if (Stopped && !Started)
     511           0 :     report_fatal_error("Cannot stop compilation after pass that is not run");
     512     1318886 : }
     513             : 
     514             : /// Add a CodeGen pass at this point in the pipeline after checking for target
     515             : /// and command line overrides.
     516             : ///
     517             : /// addPass cannot return a pointer to the pass instance because is internal the
     518             : /// PassManager and the instance we create here may already be freed.
     519      642324 : AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
     520             :                                      bool printAfter) {
     521      642324 :   IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
     522      642324 :   IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
     523      642324 :   if (!FinalPtr.isValid())
     524             :     return nullptr;
     525             : 
     526             :   Pass *P;
     527      635534 :   if (FinalPtr.isInstance())
     528             :     P = FinalPtr.getInstance();
     529             :   else {
     530      635534 :     P = Pass::createPass(FinalPtr.getID());
     531      635535 :     if (!P)
     532           0 :       llvm_unreachable("Pass ID not registered");
     533             :   }
     534      635535 :   AnalysisID FinalID = P->getPassID();
     535      635535 :   addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
     536             : 
     537      635534 :   return FinalID;
     538             : }
     539             : 
     540       19219 : void TargetPassConfig::printAndVerify(const std::string &Banner) {
     541       19219 :   addPrintPass(Banner);
     542       19219 :   addVerifyPass(Banner);
     543       19219 : }
     544             : 
     545      851199 : void TargetPassConfig::addPrintPass(const std::string &Banner) {
     546     1702398 :   if (TM->shouldPrintMachineCode())
     547         490 :     PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
     548      851199 : }
     549             : 
     550      557087 : void TargetPassConfig::addVerifyPass(const std::string &Banner) {
     551      557087 :   bool Verify = VerifyMachineCode;
     552             : #ifdef EXPENSIVE_CHECKS
     553             :   if (VerifyMachineCode == cl::BOU_UNSET)
     554             :     Verify = TM->isMachineVerifierClean();
     555             : #endif
     556      557087 :   if (Verify)
     557      117242 :     PM->add(createMachineVerifierPass(Banner));
     558      557087 : }
     559             : 
     560             : /// Add common target configurable passes that perform LLVM IR to IR transforms
     561             : /// following machine independent optimization.
     562       16923 : void TargetPassConfig::addIRPasses() {
     563       16923 :   switch (UseCFLAA) {
     564           0 :   case CFLAAType::Steensgaard:
     565           0 :     addPass(createCFLSteensAAWrapperPass());
     566           0 :     break;
     567           0 :   case CFLAAType::Andersen:
     568           0 :     addPass(createCFLAndersAAWrapperPass());
     569           0 :     break;
     570           0 :   case CFLAAType::Both:
     571           0 :     addPass(createCFLAndersAAWrapperPass());
     572           0 :     addPass(createCFLSteensAAWrapperPass());
     573           0 :     break;
     574             :   default:
     575             :     break;
     576             :   }
     577             : 
     578             :   // Basic AliasAnalysis support.
     579             :   // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
     580             :   // BasicAliasAnalysis wins if they disagree. This is intended to help
     581             :   // support "obvious" type-punning idioms.
     582       16923 :   addPass(createTypeBasedAAWrapperPass());
     583       16923 :   addPass(createScopedNoAliasAAWrapperPass());
     584       16923 :   addPass(createBasicAAWrapperPass());
     585             : 
     586             :   // Before running any passes, run the verifier to determine if the input
     587             :   // coming from the front-end and/or optimizer is valid.
     588       16923 :   if (!DisableVerify)
     589       16031 :     addPass(createVerifierPass());
     590             : 
     591             :   // Run loop strength reduction before anything else.
     592       32536 :   if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
     593       15602 :     addPass(createLoopStrengthReducePass());
     594       15602 :     if (PrintLSR)
     595           9 :       addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
     596             :   }
     597             : 
     598       32536 :   if (getOptLevel() != CodeGenOpt::None && EnableMergeICmps) {
     599           0 :     addPass(createMergeICmpsPass());
     600             :   }
     601             : 
     602             :   // Run GC lowering passes for builtin collectors
     603             :   // TODO: add a pass insertion point here
     604       16923 :   addPass(createGCLoweringPass());
     605       16923 :   addPass(createShadowStackGCLoweringPass());
     606             : 
     607             :   // Make sure that no unreachable blocks are instruction selected.
     608       16923 :   addPass(createUnreachableBlockEliminationPass());
     609             : 
     610             :   // Prepare expensive constants for SelectionDAG.
     611       32536 :   if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
     612       15612 :     addPass(createConstantHoistingPass());
     613             : 
     614       32536 :   if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
     615       15613 :     addPass(createPartiallyInlineLibCallsPass());
     616             : 
     617             :   // Insert calls to mcount-like functions.
     618       16923 :   addPass(createCountingFunctionInserterPass());
     619             : 
     620             :   // Add scalarization of target's unsupported masked memory intrinsics pass.
     621             :   // the unsupported intrinsic will be replaced with a chain of basic blocks,
     622             :   // that stores/loads element one-by-one if the appropriate mask bit is set.
     623       16923 :   addPass(createScalarizeMaskedMemIntrinPass());
     624             : 
     625             :   // Expand reduction intrinsics into shuffle sequences if the target wants to.
     626       16923 :   addPass(createExpandReductionsPass());
     627       16923 : }
     628             : 
     629             : /// Turn exception handling constructs into something the code generators can
     630             : /// handle.
     631       16923 : void TargetPassConfig::addPassesToHandleExceptions() {
     632       16923 :   const MCAsmInfo *MCAI = TM->getMCAsmInfo();
     633             :   assert(MCAI && "No MCAsmInfo");
     634       16923 :   switch (MCAI->getExceptionHandlingType()) {
     635         701 :   case ExceptionHandling::SjLj:
     636             :     // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
     637             :     // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
     638             :     // catch info can get misplaced when a selector ends up more than one block
     639             :     // removed from the parent invoke(s). This could happen when a landing
     640             :     // pad is shared by multiple invokes and is also a target of a normal
     641             :     // edge from elsewhere.
     642         701 :     addPass(createSjLjEHPreparePass());
     643             :     LLVM_FALLTHROUGH;
     644       14381 :   case ExceptionHandling::DwarfCFI:
     645             :   case ExceptionHandling::ARM:
     646       14381 :     addPass(createDwarfEHPass());
     647       14381 :     break;
     648         479 :   case ExceptionHandling::WinEH:
     649             :     // We support using both GCC-style and MSVC-style exceptions on Windows, so
     650             :     // add both preparation passes. Each pass will only actually run if it
     651             :     // recognizes the personality function.
     652         479 :     addPass(createWinEHPass());
     653         479 :     addPass(createDwarfEHPass());
     654         479 :     break;
     655        2063 :   case ExceptionHandling::None:
     656        2063 :     addPass(createLowerInvokePass());
     657             : 
     658             :     // The lower invoke pass may create unreachable code. Remove it.
     659        2063 :     addPass(createUnreachableBlockEliminationPass());
     660        2063 :     break;
     661             :   }
     662       16923 : }
     663             : 
     664             : /// Add pass to prepare the LLVM IR for code generation. This should be done
     665             : /// before exception handling preparation passes.
     666       16923 : void TargetPassConfig::addCodeGenPrepare() {
     667       32536 :   if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
     668       15609 :     addPass(createCodeGenPreparePass());
     669       16923 :   addPass(createRewriteSymbolsPass());
     670       16923 : }
     671             : 
     672             : /// Add common passes that perform LLVM IR to IR transforms in preparation for
     673             : /// instruction selection.
     674       16923 : void TargetPassConfig::addISelPrepare() {
     675       16923 :   addPreISel();
     676             : 
     677             :   // Force codegen to run according to the callgraph.
     678       16923 :   if (requiresCodeGenSCCOrder())
     679        2946 :     addPass(new DummyCGSCCPass);
     680             : 
     681             :   // Add both the safe stack and the stack protection passes: each of them will
     682             :   // only protect functions that have corresponding attributes.
     683       16923 :   addPass(createSafeStackPass());
     684       16923 :   addPass(createStackProtectorPass());
     685             : 
     686       16923 :   if (PrintISelInput)
     687           0 :     addPass(createPrintFunctionPass(
     688             :         dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
     689             : 
     690             :   // All passes which modify the LLVM IR are now complete; run the verifier
     691             :   // to ensure that the IR is valid.
     692       16923 :   if (!DisableVerify)
     693       16031 :     addPass(createVerifierPass());
     694       16923 : }
     695             : 
     696       16923 : bool TargetPassConfig::addCoreISelPasses() {
     697             :   // Enable FastISel with -fast, but allow that to be overridden.
     698       50769 :   TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
     699       33596 :   if (EnableFastISelOption == cl::BOU_TRUE ||
     700       19193 :       (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel()))
     701        1475 :     TM->setFastISel(true);
     702             : 
     703             :   // Ask the target for an isel.
     704             :   // Enable GlobalISel if the target wants to, but allow that to be overriden.
     705       33735 :   if (EnableGlobalISel == cl::BOU_TRUE ||
     706       33624 :       (EnableGlobalISel == cl::BOU_UNSET && isGlobalISelEnabled())) {
     707         114 :     if (addIRTranslator())
     708             :       return true;
     709             : 
     710         114 :     addPreLegalizeMachineIR();
     711             : 
     712         114 :     if (addLegalizeMachineIR())
     713             :       return true;
     714             : 
     715             :     // Before running the register bank selector, ask the target if it
     716             :     // wants to run some passes.
     717         114 :     addPreRegBankSelect();
     718             : 
     719         114 :     if (addRegBankSelect())
     720             :       return true;
     721             : 
     722         114 :     addPreGlobalInstructionSelect();
     723             : 
     724         114 :     if (addGlobalInstructionSelect())
     725             :       return true;
     726             : 
     727             :     // Pass to reset the MachineFunction if the ISel failed.
     728         228 :     addPass(createResetMachineFunctionPass(
     729         228 :         reportDiagnosticWhenGlobalISelFallback(), isGlobalISelAbortEnabled()));
     730             : 
     731             :     // Provide a fallback path when we do not want to abort on
     732             :     // not-yet-supported input.
     733         114 :     if (!isGlobalISelAbortEnabled() && addInstSelector())
     734             :       return true;
     735             : 
     736       16809 :   } else if (addInstSelector())
     737             :     return true;
     738             : 
     739             :   return false;
     740             : }
     741             : 
     742       16923 : bool TargetPassConfig::addISelPasses() {
     743       16923 :   if (TM->Options.EmulatedTLS)
     744          48 :     addPass(createLowerEmuTLSPass());
     745             : 
     746       16923 :   addPass(createPreISelIntrinsicLoweringPass());
     747       33846 :   addPass(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
     748       16923 :   addIRPasses();
     749       16923 :   addCodeGenPrepare();
     750       16923 :   addPassesToHandleExceptions();
     751       16923 :   addISelPrepare();
     752             : 
     753       16923 :   return addCoreISelPasses();
     754             : }
     755             : 
     756             : /// -regalloc=... command line option.
     757           0 : static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
     758             : static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
     759             :                RegisterPassParser<RegisterRegAlloc> >
     760       72306 : RegAlloc("regalloc",
     761      216918 :          cl::init(&useDefaultRegisterAllocator),
     762      289224 :          cl::desc("Register allocator to use"));
     763             : 
     764             : /// Add the complete set of target-independent postISel code generator passes.
     765             : ///
     766             : /// This can be read as the standard order of major LLVM CodeGen stages. Stages
     767             : /// with nontrivial configuration or multiple passes are broken out below in
     768             : /// add%Stage routines.
     769             : ///
     770             : /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
     771             : /// addPre/Post methods with empty header implementations allow injecting
     772             : /// target-specific fixups just before or after major stages. Additionally,
     773             : /// targets have the flexibility to change pass order within a stage by
     774             : /// overriding default implementation of add%Stage routines below. Each
     775             : /// technique has maintainability tradeoffs because alternate pass orders are
     776             : /// not well supported. addPre/Post works better if the target pass is easily
     777             : /// tied to a common pass. But if it has subtle dependencies on multiple passes,
     778             : /// the target should override the stage instead.
     779             : ///
     780             : /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
     781             : /// before/after any target-independent pass. But it's currently overkill.
     782       16923 : void TargetPassConfig::addMachinePasses() {
     783       16923 :   AddingMachinePasses = true;
     784             : 
     785             :   // Insert a machine instr printer pass after the specified pass.
     786       50760 :   if (!StringRef(PrintMachineInstrs.getValue()).equals("") &&
     787       33828 :       !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) {
     788          21 :     const PassRegistry *PR = PassRegistry::getPassRegistry();
     789          42 :     const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
     790          21 :     const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
     791             :     assert (TPI && IPI && "Pass ID not registered!");
     792          21 :     const char *TID = (const char *)(TPI->getTypeInfo());
     793          21 :     const char *IID = (const char *)(IPI->getTypeInfo());
     794          21 :     insertPass(TID, IID);
     795             :   }
     796             : 
     797             :   // Print the instruction selected machine code...
     798       50769 :   printAndVerify("After Instruction Selection");
     799             : 
     800             :   // Expand pseudo-instructions emitted by ISel.
     801       16923 :   addPass(&ExpandISelPseudosID);
     802             : 
     803             :   // Add passes that optimize machine instructions in SSA form.
     804       16923 :   if (getOptLevel() != CodeGenOpt::None) {
     805       15613 :     addMachineSSAOptimization();
     806             :   } else {
     807             :     // If the target requests it, assign local variables to stack slots relative
     808             :     // to one another and simplify frame index references where possible.
     809        1310 :     addPass(&LocalStackSlotAllocationID, false);
     810             :   }
     811             : 
     812       16923 :   if (TM->Options.EnableIPRA)
     813           6 :     addPass(createRegUsageInfoPropPass());
     814             : 
     815             :   // Run pre-ra passes.
     816       16923 :   addPreRegAlloc();
     817             : 
     818             :   // Run register allocation and passes that are tightly coupled with it,
     819             :   // including phi elimination and scheduling.
     820       16923 :   if (getOptimizeRegAlloc())
     821       15599 :     addOptimizedRegAlloc(createRegAllocPass(true));
     822             :   else {
     823        1364 :     if (RegAlloc != &useDefaultRegisterAllocator &&
     824          40 :         RegAlloc != &createFastRegisterAllocator)
     825           0 :       report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
     826        1324 :     addFastRegAlloc(createRegAllocPass(false));
     827             :   }
     828             : 
     829             :   // Run post-ra passes.
     830       16923 :   addPostRegAlloc();
     831             : 
     832             :   // Insert prolog/epilog code.  Eliminate abstract frame index references...
     833       16923 :   if (getOptLevel() != CodeGenOpt::None)
     834       15613 :     addPass(&ShrinkWrapID);
     835             : 
     836             :   // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
     837             :   // do so if it hasn't been disabled, substituted, or overridden.
     838       16923 :   if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
     839       16695 :       addPass(createPrologEpilogInserterPass());
     840             : 
     841             :   /// Add passes that optimize machine instructions after register allocation.
     842       16923 :   if (getOptLevel() != CodeGenOpt::None)
     843       15613 :     addMachineLateOptimization();
     844             : 
     845             :   // Expand pseudo instructions before second scheduling pass.
     846       16923 :   addPass(&ExpandPostRAPseudosID);
     847             : 
     848             :   // Run pre-sched2 passes.
     849       16923 :   addPreSched2();
     850             : 
     851       16923 :   if (EnableImplicitNullChecks)
     852           4 :     addPass(&ImplicitNullChecksID);
     853             : 
     854             :   // Second pass scheduler.
     855             :   // Let Target optionally insert this pass by itself at some other
     856             :   // point.
     857       32536 :   if (getOptLevel() != CodeGenOpt::None &&
     858       15613 :       !TM->targetSchedulesPostRAScheduling()) {
     859       14826 :     if (MISchedPostRA)
     860           2 :       addPass(&PostMachineSchedulerID);
     861             :     else
     862       14824 :       addPass(&PostRASchedulerID);
     863             :   }
     864             : 
     865             :   // GC
     866       16923 :   if (addGCPasses()) {
     867       15211 :     if (PrintGCInfo)
     868           0 :       addPass(createGCInfoPrinter(dbgs()), false, false);
     869             :   }
     870             : 
     871             :   // Basic block placement.
     872       16923 :   if (getOptLevel() != CodeGenOpt::None)
     873       15613 :     addBlockPlacement();
     874             : 
     875       16923 :   addPreEmitPass();
     876             : 
     877       16923 :   if (TM->Options.EnableIPRA)
     878             :     // Collect register usage information and produce a register mask of
     879             :     // clobbered registers, to be used to optimize call sites.
     880           6 :     addPass(createRegUsageInfoCollector());
     881             : 
     882       16923 :   addPass(&FuncletLayoutID, false);
     883             : 
     884       16923 :   addPass(&StackMapLivenessID, false);
     885       16923 :   addPass(&LiveDebugValuesID, false);
     886             : 
     887             :   // Insert before XRay Instrumentation.
     888       16923 :   addPass(&FEntryInserterID, false);
     889             : 
     890       16923 :   addPass(&XRayInstrumentationID, false);
     891       16923 :   addPass(&PatchableFunctionID, false);
     892             : 
     893       16923 :   if (EnableMachineOutliner)
     894           6 :     PM->add(createMachineOutlinerPass());
     895             : 
     896       16923 :   AddingMachinePasses = false;
     897       16923 : }
     898             : 
     899             : /// Add passes that optimize machine instructions in SSA form.
     900       15411 : void TargetPassConfig::addMachineSSAOptimization() {
     901             :   // Pre-ra tail duplication.
     902       15411 :   addPass(&EarlyTailDuplicateID);
     903             : 
     904             :   // Optimize PHIs before DCE: removing dead PHI cycles may make more
     905             :   // instructions dead.
     906       15411 :   addPass(&OptimizePHIsID, false);
     907             : 
     908             :   // This pass merges large allocas. StackSlotColoring is a different pass
     909             :   // which merges spill slots.
     910       15411 :   addPass(&StackColoringID, false);
     911             : 
     912             :   // If the target requests it, assign local variables to stack slots relative
     913             :   // to one another and simplify frame index references where possible.
     914       15411 :   addPass(&LocalStackSlotAllocationID, false);
     915             : 
     916             :   // With optimization, dead code should already be eliminated. However
     917             :   // there is one known exception: lowered code for arguments that are only
     918             :   // used by tail calls, where the tail calls reuse the incoming stack
     919             :   // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
     920       15411 :   addPass(&DeadMachineInstructionElimID);
     921             : 
     922             :   // Allow targets to insert passes that improve instruction level parallelism,
     923             :   // like if-conversion. Such passes will typically need dominator trees and
     924             :   // loop info, just like LICM and CSE below.
     925       15411 :   addILPOpts();
     926             : 
     927       15411 :   addPass(&MachineLICMID, false);
     928       15411 :   addPass(&MachineCSEID, false);
     929             : 
     930       15411 :   addPass(&MachineSinkingID);
     931             : 
     932       15411 :   addPass(&PeepholeOptimizerID);
     933             :   // Clean-up the dead code that may have been generated by peephole
     934             :   // rewriting.
     935       15411 :   addPass(&DeadMachineInstructionElimID);
     936       15411 : }
     937             : 
     938             : //===---------------------------------------------------------------------===//
     939             : /// Register Allocation Pass Configuration
     940             : //===---------------------------------------------------------------------===//
     941             : 
     942       16923 : bool TargetPassConfig::getOptimizeRegAlloc() const {
     943       16923 :   switch (OptimizeRegAlloc) {
     944       16885 :   case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
     945             :   case cl::BOU_TRUE:  return true;
     946          26 :   case cl::BOU_FALSE: return false;
     947             :   }
     948           0 :   llvm_unreachable("Invalid optimize-regalloc state");
     949             : }
     950             : 
     951             : /// RegisterRegAlloc's global Registry tracks allocator registration.
     952             : MachinePassRegistry RegisterRegAlloc::Registry;
     953             : 
     954             : /// A dummy default pass factory indicates whether the register allocator is
     955             : /// overridden on the command line.
     956             : static llvm::once_flag InitializeDefaultRegisterAllocatorFlag;
     957             : 
     958             : static RegisterRegAlloc
     959       72306 : defaultRegAlloc("default",
     960             :                 "pick register allocator based on -O option",
     961       72306 :                 useDefaultRegisterAllocator);
     962             : 
     963       16748 : static void initializeDefaultRegisterAllocatorOnce() {
     964       16748 :   RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
     965             : 
     966       16748 :   if (!Ctor) {
     967       16748 :     Ctor = RegAlloc;
     968       16748 :     RegisterRegAlloc::setDefault(RegAlloc);
     969             :   }
     970       16748 : }
     971             : 
     972             : /// Instantiate the default register allocator pass for this target for either
     973             : /// the optimized or unoptimized allocation path. This will be added to the pass
     974             : /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
     975             : /// in the optimized case.
     976             : ///
     977             : /// A target that uses the standard regalloc pass order for fast or optimized
     978             : /// allocation may still override this for per-target regalloc
     979             : /// selection. But -regalloc=... always takes precedence.
     980       16592 : FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
     981       16592 :   if (Optimized)
     982       15334 :     return createGreedyRegisterAllocator();
     983             :   else
     984        1258 :     return createFastRegisterAllocator();
     985             : }
     986             : 
     987             : /// Find and instantiate the register allocation pass requested by this target
     988             : /// at the current optimization level.  Different register allocators are
     989             : /// defined as separate passes because they may require different analysis.
     990             : ///
     991             : /// This helper ensures that the regalloc= option is always available,
     992             : /// even for targets that override the default allocator.
     993             : ///
     994             : /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
     995             : /// this can be folded into addPass.
     996       16923 : FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
     997             :   // Initialize the global default.
     998       16923 :   llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
     999             :                   initializeDefaultRegisterAllocatorOnce);
    1000             : 
    1001       16923 :   RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
    1002       16923 :   if (Ctor != useDefaultRegisterAllocator)
    1003         103 :     return Ctor();
    1004             : 
    1005             :   // With no -regalloc= override, ask the target for a regalloc pass.
    1006       16820 :   return createTargetRegisterAllocator(Optimized);
    1007             : }
    1008             : 
    1009             : /// Return true if the default global register allocator is in use and
    1010             : /// has not be overriden on the command line with '-regalloc=...'
    1011         914 : bool TargetPassConfig::usingDefaultRegAlloc() const {
    1012         914 :   return RegAlloc.getNumOccurrences() == 0;
    1013             : }
    1014             : 
    1015             : /// Add the minimum set of target-independent passes that are required for
    1016             : /// register allocation. No coalescing or scheduling.
    1017        1298 : void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
    1018        1298 :   addPass(&PHIEliminationID, false);
    1019        1298 :   addPass(&TwoAddressInstructionPassID, false);
    1020             : 
    1021        1298 :   if (RegAllocPass)
    1022        1298 :     addPass(RegAllocPass);
    1023        1298 : }
    1024             : 
    1025             : /// Add standard target-independent passes that are tightly coupled with
    1026             : /// optimized register allocation, including coalescing, machine instruction
    1027             : /// scheduling, and register allocation itself.
    1028       15397 : void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
    1029       15397 :   addPass(&DetectDeadLanesID, false);
    1030             : 
    1031       15397 :   addPass(&ProcessImplicitDefsID, false);
    1032             : 
    1033             :   // LiveVariables currently requires pure SSA form.
    1034             :   //
    1035             :   // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
    1036             :   // LiveVariables can be removed completely, and LiveIntervals can be directly
    1037             :   // computed. (We still either need to regenerate kill flags after regalloc, or
    1038             :   // preferably fix the scavenger to not depend on them).
    1039       15396 :   addPass(&LiveVariablesID, false);
    1040             : 
    1041             :   // Edge splitting is smarter with machine loop info.
    1042       15397 :   addPass(&MachineLoopInfoID, false);
    1043       15397 :   addPass(&PHIEliminationID, false);
    1044             : 
    1045             :   // Eventually, we want to run LiveIntervals before PHI elimination.
    1046       15397 :   if (EarlyLiveIntervals)
    1047           0 :     addPass(&LiveIntervalsID, false);
    1048             : 
    1049       15397 :   addPass(&TwoAddressInstructionPassID, false);
    1050       15397 :   addPass(&RegisterCoalescerID);
    1051             : 
    1052             :   // The machine scheduler may accidentally create disconnected components
    1053             :   // when moving subregister definitions around, avoid this by splitting them to
    1054             :   // separate vregs before. Splitting can also improve reg. allocation quality.
    1055       15397 :   addPass(&RenameIndependentSubregsID);
    1056             : 
    1057             :   // PreRA instruction scheduling.
    1058       15397 :   addPass(&MachineSchedulerID);
    1059             : 
    1060       15397 :   if (RegAllocPass) {
    1061             :     // Add the selected register allocation pass.
    1062       15397 :     addPass(RegAllocPass);
    1063             : 
    1064             :     // Allow targets to change the register assignments before rewriting.
    1065       15397 :     addPreRewrite();
    1066             : 
    1067             :     // Finally rewrite virtual registers.
    1068       15397 :     addPass(&VirtRegRewriterID);
    1069             : 
    1070             :     // Perform stack slot coloring and post-ra machine LICM.
    1071             :     //
    1072             :     // FIXME: Re-enable coloring with register when it's capable of adding
    1073             :     // kill markers.
    1074       15397 :     addPass(&StackSlotColoringID);
    1075             : 
    1076             :     // Run post-ra machine LICM to hoist reloads / remats.
    1077             :     //
    1078             :     // FIXME: can this move into MachineLateOptimization?
    1079       15397 :     addPass(&PostRAMachineLICMID);
    1080             :   }
    1081       15397 : }
    1082             : 
    1083             : //===---------------------------------------------------------------------===//
    1084             : /// Post RegAlloc Pass Configuration
    1085             : //===---------------------------------------------------------------------===//
    1086             : 
    1087             : /// Add passes that optimize machine instructions after register allocation.
    1088       15613 : void TargetPassConfig::addMachineLateOptimization() {
    1089             :   // Branch folding must be run after regalloc and prolog/epilog insertion.
    1090       15613 :   addPass(&BranchFolderPassID);
    1091             : 
    1092             :   // Tail duplication.
    1093             :   // Note that duplicating tail just increases code size and degrades
    1094             :   // performance for targets that require Structured Control Flow.
    1095             :   // In addition it can also make CFG irreducible. Thus we disable it.
    1096       31226 :   if (!TM->requiresStructuredCFG())
    1097       15370 :     addPass(&TailDuplicateID);
    1098             : 
    1099             :   // Copy propagation.
    1100       15613 :   addPass(&MachineCopyPropagationID);
    1101       15613 : }
    1102             : 
    1103             : /// Add standard GC passes.
    1104       15211 : bool TargetPassConfig::addGCPasses() {
    1105       15211 :   addPass(&GCMachineCodeAnalysisID, false);
    1106       15211 :   return true;
    1107             : }
    1108             : 
    1109             : /// Add standard basic block placement passes.
    1110       15613 : void TargetPassConfig::addBlockPlacement() {
    1111       15613 :   if (addPass(&MachineBlockPlacementID)) {
    1112             :     // Run a separate pass to collect block placement statistics.
    1113       15593 :     if (EnableBlockPlacementStats)
    1114           0 :       addPass(&MachineBlockPlacementStatsID);
    1115             :   }
    1116       15613 : }
    1117             : 
    1118             : //===---------------------------------------------------------------------===//
    1119             : /// GlobalISel Configuration
    1120             : //===---------------------------------------------------------------------===//
    1121             : 
    1122       15831 : bool TargetPassConfig::isGlobalISelEnabled() const {
    1123       15831 :   return false;
    1124             : }
    1125             : 
    1126         322 : bool TargetPassConfig::isGlobalISelAbortEnabled() const {
    1127         322 :   return EnableGlobalISelAbort == 1;
    1128             : }
    1129             : 
    1130         114 : bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
    1131         114 :   return EnableGlobalISelAbort == 2;
    1132      216918 : }

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