LCOV - code coverage report
Current view: top level - lib/CodeGen - TargetPassConfig.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 452 480 94.2 %
Date: 2018-06-17 00:07:59 Functions: 43 47 91.5 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file defines interfaces to access the target independent code
      11             : // generation passes provided by the LLVM backend.
      12             : //
      13             : //===---------------------------------------------------------------------===//
      14             : 
      15             : #include "llvm/CodeGen/TargetPassConfig.h"
      16             : #include "llvm/ADT/DenseMap.h"
      17             : #include "llvm/ADT/SmallVector.h"
      18             : #include "llvm/ADT/StringRef.h"
      19             : #include "llvm/Analysis/BasicAliasAnalysis.h"
      20             : #include "llvm/Analysis/CFLAndersAliasAnalysis.h"
      21             : #include "llvm/Analysis/CFLSteensAliasAnalysis.h"
      22             : #include "llvm/Analysis/CallGraphSCCPass.h"
      23             : #include "llvm/Analysis/ScopedNoAliasAA.h"
      24             : #include "llvm/Analysis/TargetTransformInfo.h"
      25             : #include "llvm/Analysis/TypeBasedAliasAnalysis.h"
      26             : #include "llvm/CodeGen/MachineFunctionPass.h"
      27             : #include "llvm/CodeGen/MachinePassRegistry.h"
      28             : #include "llvm/CodeGen/Passes.h"
      29             : #include "llvm/CodeGen/RegAllocRegistry.h"
      30             : #include "llvm/IR/IRPrintingPasses.h"
      31             : #include "llvm/IR/LegacyPassManager.h"
      32             : #include "llvm/IR/Verifier.h"
      33             : #include "llvm/MC/MCAsmInfo.h"
      34             : #include "llvm/MC/MCTargetOptions.h"
      35             : #include "llvm/Pass.h"
      36             : #include "llvm/Support/CodeGen.h"
      37             : #include "llvm/Support/CommandLine.h"
      38             : #include "llvm/Support/Compiler.h"
      39             : #include "llvm/Support/Debug.h"
      40             : #include "llvm/Support/ErrorHandling.h"
      41             : #include "llvm/Support/Threading.h"
      42             : #include "llvm/Target/TargetMachine.h"
      43             : #include "llvm/Transforms/Scalar.h"
      44             : #include "llvm/Transforms/Utils.h"
      45             : #include "llvm/Transforms/Utils/SymbolRewriter.h"
      46             : #include <cassert>
      47             : #include <string>
      48             : 
      49             : using namespace llvm;
      50             : 
      51      303507 : cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
      52      101169 :                          cl::desc("Enable interprocedural register allocation "
      53      303507 :                                   "to reduce load/store at procedure calls."));
      54      101169 : static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
      55      101169 :     cl::desc("Disable Post Regalloc Scheduler"));
      56      101169 : static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
      57      101169 :     cl::desc("Disable branch folding"));
      58      101169 : static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
      59      101169 :     cl::desc("Disable tail duplication"));
      60      101169 : static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
      61      101169 :     cl::desc("Disable pre-register allocation tail duplication"));
      62      101169 : static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
      63      101169 :     cl::Hidden, cl::desc("Disable probability-driven block placement"));
      64      101169 : static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
      65      101169 :     cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
      66      101169 : static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
      67      101169 :     cl::desc("Disable Stack Slot Coloring"));
      68      101169 : static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
      69      101169 :     cl::desc("Disable Machine Dead Code Elimination"));
      70      101169 : static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
      71      101169 :     cl::desc("Disable Early If-conversion"));
      72      101169 : static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
      73      101169 :     cl::desc("Disable Machine LICM"));
      74      101169 : static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
      75      101169 :     cl::desc("Disable Machine Common Subexpression Elimination"));
      76      101169 : static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
      77             :     "optimize-regalloc", cl::Hidden,
      78      101169 :     cl::desc("Enable optimized register allocation compilation path."));
      79      101169 : static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
      80             :     cl::Hidden,
      81      101169 :     cl::desc("Disable Machine LICM"));
      82      101169 : static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
      83      101169 :     cl::desc("Disable Machine Sinking"));
      84      101169 : static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
      85             :     cl::Hidden,
      86      101169 :     cl::desc("Disable PostRA Machine Sinking"));
      87      101169 : static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
      88      101169 :     cl::desc("Disable Loop Strength Reduction Pass"));
      89      101169 : static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
      90      101169 :     cl::Hidden, cl::desc("Disable ConstantHoisting"));
      91      101169 : static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
      92      101169 :     cl::desc("Disable Codegen Prepare"));
      93      101169 : static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
      94      101169 :     cl::desc("Disable Copy Propagation pass"));
      95      101169 : static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
      96      101169 :     cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
      97      101169 : static cl::opt<bool> EnableImplicitNullChecks(
      98             :     "enable-implicit-null-checks",
      99      101169 :     cl::desc("Fold null checks into faulting memory operations"),
     100      303507 :     cl::init(false), cl::Hidden);
     101      101169 : static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
     102      101169 :     cl::desc("Disable MergeICmps Pass"),
     103      303507 :     cl::init(false), cl::Hidden);
     104      101169 : static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
     105      101169 :     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
     106      101169 : static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
     107      101169 :     cl::desc("Print LLVM IR input to isel pass"));
     108      101169 : static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
     109      101169 :     cl::desc("Dump garbage collector data"));
     110      101169 : static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
     111      101169 :     cl::desc("Verify generated machine code"),
     112      202338 :     cl::init(false),
     113      303507 :     cl::ZeroOrMore);
     114      101169 : static cl::opt<bool> EnableMachineOutliner("enable-machine-outliner",
     115             :     cl::Hidden,
     116      101169 :     cl::desc("Enable machine outliner"));
     117             : // Enable or disable FastISel. Both options are needed, because
     118             : // FastISel is enabled by default with -fast, and we wish to be
     119             : // able to enable or disable fast-isel independently from -O0.
     120             : static cl::opt<cl::boolOrDefault>
     121      101169 : EnableFastISelOption("fast-isel", cl::Hidden,
     122      101169 :   cl::desc("Enable the \"fast\" instruction selector"));
     123             : 
     124      101169 : static cl::opt<cl::boolOrDefault> EnableGlobalISelOption(
     125             :     "global-isel", cl::Hidden,
     126      101169 :     cl::desc("Enable the \"global\" instruction selector"));
     127             : 
     128      101169 : static cl::opt<std::string> PrintMachineInstrs(
     129      101169 :     "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
     130      303507 :     cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
     131             : 
     132      101169 : static cl::opt<int> EnableGlobalISelAbort(
     133             :     "global-isel-abort", cl::Hidden,
     134      101169 :     cl::desc("Enable abort calls when \"global\" instruction selection "
     135             :              "fails to lower/select an instruction: 0 disable the abort, "
     136             :              "1 enable the abort, and "
     137             :              "2 disable the abort but emit a diagnostic on failure"),
     138      303507 :     cl::init(1));
     139             : 
     140             : // Temporary option to allow experimenting with MachineScheduler as a post-RA
     141             : // scheduler. Targets can "properly" enable this with
     142             : // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
     143             : // Targets can return true in targetSchedulesPostRAScheduling() and
     144             : // insert a PostRA scheduling pass wherever it wants.
     145      101169 : cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
     146      101169 :   cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
     147             : 
     148             : // Experimental option to run live interval analysis early.
     149      101169 : static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
     150      101169 :     cl::desc("Run live interval analysis earlier in the pipeline"));
     151             : 
     152             : // Experimental option to use CFL-AA in codegen
     153             : enum class CFLAAType { None, Steensgaard, Andersen, Both };
     154      101169 : static cl::opt<CFLAAType> UseCFLAA(
     155      202338 :     "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
     156      101169 :     cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
     157      607014 :     cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
     158             :                clEnumValN(CFLAAType::Steensgaard, "steens",
     159             :                           "Enable unification-based CFL-AA"),
     160             :                clEnumValN(CFLAAType::Andersen, "anders",
     161             :                           "Enable inclusion-based CFL-AA"),
     162             :                clEnumValN(CFLAAType::Both, "both", 
     163      303507 :                           "Enable both variants of CFL-AA")));
     164             : 
     165             : /// Option names for limiting the codegen pipeline.
     166             : /// Those are used in error reporting and we didn't want
     167             : /// to duplicate their names all over the place.
     168             : const char *StartAfterOptName = "start-after";
     169             : const char *StartBeforeOptName = "start-before";
     170             : const char *StopAfterOptName = "stop-after";
     171             : const char *StopBeforeOptName = "stop-before";
     172             : 
     173             : static cl::opt<std::string>
     174      303507 :     StartAfterOpt(StringRef(StartAfterOptName),
     175      101169 :                   cl::desc("Resume compilation after a specific pass"),
     176      303507 :                   cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
     177             : 
     178             : static cl::opt<std::string>
     179      303507 :     StartBeforeOpt(StringRef(StartBeforeOptName),
     180      101169 :                    cl::desc("Resume compilation before a specific pass"),
     181      303507 :                    cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
     182             : 
     183             : static cl::opt<std::string>
     184      303507 :     StopAfterOpt(StringRef(StopAfterOptName),
     185      101169 :                  cl::desc("Stop compilation after a specific pass"),
     186      303507 :                  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
     187             : 
     188             : static cl::opt<std::string>
     189      303507 :     StopBeforeOpt(StringRef(StopBeforeOptName),
     190      101169 :                   cl::desc("Stop compilation before a specific pass"),
     191      303507 :                   cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
     192             : 
     193             : /// Allow standard passes to be disabled by command line options. This supports
     194             : /// simple binary flags that either suppress the pass or do nothing.
     195             : /// i.e. -disable-mypass=false has no effect.
     196             : /// These should be converted to boolOrDefault in order to use applyOverride.
     197             : static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
     198             :                                        bool Override) {
     199      303578 :   if (Override)
     200             :     return IdentifyingPassPtr();
     201      303434 :   return PassID;
     202             : }
     203             : 
     204             : /// Allow standard passes to be disabled by the command line, regardless of who
     205             : /// is adding the pass.
     206             : ///
     207             : /// StandardID is the pass identified in the standard pass pipeline and provided
     208             : /// to addPass(). It may be a target-specific ID in the case that the target
     209             : /// directly adds its own pass, but in that case we harmlessly fall through.
     210             : ///
     211             : /// TargetID is the pass that the target has configured to override StandardID.
     212             : ///
     213             : /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
     214             : /// pass to run. This allows multiple options to control a single pass depending
     215             : /// on where in the pipeline that pass is added.
     216      872192 : static IdentifyingPassPtr overridePass(AnalysisID StandardID,
     217             :                                        IdentifyingPassPtr TargetID) {
     218      872192 :   if (StandardID == &PostRASchedulerID)
     219             :     return applyDisable(TargetID, DisablePostRASched);
     220             : 
     221      853947 :   if (StandardID == &BranchFolderPassID)
     222             :     return applyDisable(TargetID, DisableBranchFold);
     223             : 
     224      834825 :   if (StandardID == &TailDuplicateID)
     225             :     return applyDisable(TargetID, DisableTailDuplicate);
     226             : 
     227      816195 :   if (StandardID == &EarlyTailDuplicateID)
     228             :     return applyDisable(TargetID, DisableEarlyTailDup);
     229             : 
     230      797073 :   if (StandardID == &MachineBlockPlacementID)
     231             :     return applyDisable(TargetID, DisableBlockPlacement);
     232             : 
     233      777951 :   if (StandardID == &StackSlotColoringID)
     234             :     return applyDisable(TargetID, DisableSSC);
     235             : 
     236      759089 :   if (StandardID == &DeadMachineInstructionElimID)
     237             :     return applyDisable(TargetID, DisableMachineDCE);
     238             : 
     239      716162 :   if (StandardID == &EarlyIfConverterID)
     240             :     return applyDisable(TargetID, DisableEarlyIfConversion);
     241             : 
     242      705010 :   if (StandardID == &EarlyMachineLICMID)
     243             :     return applyDisable(TargetID, DisableMachineLICM);
     244             : 
     245      684142 :   if (StandardID == &MachineCSEID)
     246             :     return applyDisable(TargetID, DisableMachineCSE);
     247             : 
     248      663274 :   if (StandardID == &MachineLICMID)
     249             :     return applyDisable(TargetID, DisablePostRAMachineLICM);
     250             : 
     251      644627 :   if (StandardID == &MachineSinkingID)
     252             :     return applyDisable(TargetID, DisableMachineSink);
     253             : 
     254      625505 :   if (StandardID == &PostRAMachineSinkingID)
     255             :     return applyDisable(TargetID, DisablePostRAMachineSink);
     256             : 
     257      606383 :   if (StandardID == &MachineCopyPropagationID)
     258             :     return applyDisable(TargetID, DisableCopyProp);
     259             : 
     260      568614 :   return TargetID;
     261             : }
     262             : 
     263             : //===---------------------------------------------------------------------===//
     264             : /// TargetPassConfig
     265             : //===---------------------------------------------------------------------===//
     266             : 
     267     1201710 : INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
     268             :                 "Target Pass Configuration", false, false)
     269             : char TargetPassConfig::ID = 0;
     270             : 
     271             : namespace {
     272             : 
     273             : struct InsertedPass {
     274             :   AnalysisID TargetPassID;
     275             :   IdentifyingPassPtr InsertedPassID;
     276             :   bool VerifyAfter;
     277             :   bool PrintAfter;
     278             : 
     279             :   InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
     280             :                bool VerifyAfter, bool PrintAfter)
     281        9343 :       : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
     282        9343 :         VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
     283             : 
     284             :   Pass *getInsertedPass() const {
     285             :     assert(InsertedPassID.isValid() && "Illegal Pass ID!");
     286        9294 :     if (InsertedPassID.isInstance())
     287             :       return InsertedPassID.getInstance();
     288        9294 :     Pass *NP = Pass::createPass(InsertedPassID.getID());
     289             :     assert(NP && "Pass ID not registered");
     290             :     return NP;
     291             :   }
     292             : };
     293             : 
     294             : } // end anonymous namespace
     295             : 
     296             : namespace llvm {
     297             : 
     298       80703 : class PassConfigImpl {
     299             : public:
     300             :   // List of passes explicitly substituted by this target. Normally this is
     301             :   // empty, but it is a convenient way to suppress or replace specific passes
     302             :   // that are part of a standard pass pipeline without overridding the entire
     303             :   // pipeline. This mechanism allows target options to inherit a standard pass's
     304             :   // user interface. For example, a target may disable a standard pass by
     305             :   // default by substituting a pass ID of zero, and the user may still enable
     306             :   // that standard pass with an explicit command line option.
     307             :   DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
     308             : 
     309             :   /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
     310             :   /// is inserted after each instance of the first one.
     311             :   SmallVector<InsertedPass, 4> InsertedPasses;
     312             : };
     313             : 
     314             : } // end namespace llvm
     315             : 
     316             : // Out of line virtual method.
     317       53692 : TargetPassConfig::~TargetPassConfig() {
     318       26846 :   delete Impl;
     319       26846 : }
     320             : 
     321      108038 : static const PassInfo *getPassInfo(StringRef PassName) {
     322      108038 :   if (PassName.empty())
     323             :     return nullptr;
     324             : 
     325         300 :   const PassRegistry &PR = *PassRegistry::getPassRegistry();
     326         300 :   const PassInfo *PI = PR.getPassInfo(PassName);
     327         300 :   if (!PI)
     328           4 :     report_fatal_error(Twine('\"') + Twine(PassName) +
     329             :                        Twine("\" pass is not registered."));
     330             :   return PI;
     331             : }
     332             : 
     333             : static AnalysisID getPassIDFromName(StringRef PassName) {
     334      108038 :   const PassInfo *PI = getPassInfo(PassName);
     335      108034 :   return PI ? PI->getTypeInfo() : nullptr;
     336             : }
     337             : 
     338       27011 : void TargetPassConfig::setStartStopPasses() {
     339       27010 :   StartBefore = getPassIDFromName(StartBeforeOpt);
     340       27009 :   StartAfter = getPassIDFromName(StartAfterOpt);
     341       27008 :   StopBefore = getPassIDFromName(StopBeforeOpt);
     342       27007 :   StopAfter = getPassIDFromName(StopAfterOpt);
     343       27007 :   if (StartBefore && StartAfter)
     344           2 :     report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
     345           1 :                        Twine(StartAfterOptName) + Twine(" specified!"));
     346       27006 :   if (StopBefore && StopAfter)
     347           2 :     report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
     348           1 :                        Twine(StopAfterOptName) + Twine(" specified!"));
     349       27005 :   Started = (StartAfter == nullptr) && (StartBefore == nullptr);
     350       27005 : }
     351             : 
     352             : // Out of line constructor provides default values for pass options and
     353             : // registers all common codegen passes.
     354       27011 : TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
     355       27011 :     : ImmutablePass(ID), PM(&pm), TM(&TM) {
     356       54022 :   Impl = new PassConfigImpl();
     357             : 
     358             :   // Register all target independent codegen passes to activate their PassIDs,
     359             :   // including this pass itself.
     360       27011 :   initializeCodeGen(*PassRegistry::getPassRegistry());
     361             : 
     362             :   // Also register alias analysis passes required by codegen passes.
     363       27011 :   initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
     364       27011 :   initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
     365             : 
     366             :   if (StringRef(PrintMachineInstrs.getValue()).equals(""))
     367          10 :     TM.Options.PrintMachineCode = true;
     368             : 
     369       27011 :   if (EnableIPRA.getNumOccurrences())
     370          21 :     TM.Options.EnableIPRA = EnableIPRA;
     371             :   else {
     372             :     // If not explicitly specified, use target default.
     373       26990 :     TM.Options.EnableIPRA = TM.useIPRA();
     374             :   }
     375             : 
     376       27011 :   if (TM.Options.EnableIPRA)
     377             :     setRequiresCodeGenSCCOrder();
     378             : 
     379       27011 :   setStartStopPasses();
     380       27005 : }
     381             : 
     382      527488 : CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
     383      527488 :   return TM->getOptLevel();
     384             : }
     385             : 
     386             : /// Insert InsertedPassID pass after TargetPassID.
     387        9343 : void TargetPassConfig::insertPass(AnalysisID TargetPassID,
     388             :                                   IdentifyingPassPtr InsertedPassID,
     389             :                                   bool VerifyAfter, bool PrintAfter) {
     390             :   assert(((!InsertedPassID.isInstance() &&
     391             :            TargetPassID != InsertedPassID.getID()) ||
     392             :           (InsertedPassID.isInstance() &&
     393             :            TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
     394             :          "Insert a pass after itself!");
     395        9343 :   Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
     396             :                                     PrintAfter);
     397        9343 : }
     398             : 
     399             : /// createPassConfig - Create a pass configuration object to be used by
     400             : /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
     401             : ///
     402             : /// Targets may override this to extend TargetPassConfig.
     403           0 : TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
     404           0 :   return new TargetPassConfig(*this, PM);
     405             : }
     406             : 
     407           1 : TargetPassConfig::TargetPassConfig()
     408           1 :   : ImmutablePass(ID) {
     409           1 :   report_fatal_error("Trying to construct TargetPassConfig without a target "
     410             :                      "machine. Scheduling a CodeGen pass without a target "
     411             :                      "triple set?");
     412             : }
     413             : 
     414       23738 : bool TargetPassConfig::hasLimitedCodeGenPipeline() const {
     415       23738 :   return StartBefore || StartAfter || StopBefore || StopAfter;
     416             : }
     417             : 
     418             : std::string
     419           0 : TargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) const {
     420           0 :   if (!hasLimitedCodeGenPipeline())
     421             :     return std::string();
     422             :   std::string Res;
     423             :   static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
     424             :                                               &StopAfterOpt, &StopBeforeOpt};
     425             :   static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
     426           0 :                                    StopAfterOptName, StopBeforeOptName};
     427             :   bool IsFirst = true;
     428           0 :   for (int Idx = 0; Idx < 4; ++Idx)
     429           0 :     if (!PassNames[Idx]->empty()) {
     430           0 :       if (!IsFirst)
     431             :         Res += Separator;
     432             :       IsFirst = false;
     433           0 :       Res += OptNames[Idx];
     434             :     }
     435             :   return Res;
     436             : }
     437             : 
     438             : // Helper to verify the analysis is really immutable.
     439       28034 : void TargetPassConfig::setOpt(bool &Opt, bool Val) {
     440             :   assert(!Initialized && "PassConfig is immutable");
     441       28034 :   Opt = Val;
     442       28034 : }
     443             : 
     444       16700 : void TargetPassConfig::substitutePass(AnalysisID StandardID,
     445             :                                       IdentifyingPassPtr TargetID) {
     446       33400 :   Impl->TargetPasses[StandardID] = TargetID;
     447       16700 : }
     448             : 
     449      872192 : IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
     450             :   DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
     451     1744384 :     I = Impl->TargetPasses.find(ID);
     452     1744384 :   if (I == Impl->TargetPasses.end())
     453      860839 :     return ID;
     454       11353 :   return I->second;
     455             : }
     456             : 
     457       22791 : bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
     458       22791 :   IdentifyingPassPtr TargetID = getPassSubstitution(ID);
     459       22791 :   IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
     460       22791 :   return !FinalPtr.isValid() || FinalPtr.isInstance() ||
     461       22791 :       FinalPtr.getID() != ID;
     462             : }
     463             : 
     464             : /// Add a pass to the PassManager if that pass is supposed to be run.  If the
     465             : /// Started/Stopped flags indicate either that the compilation should start at
     466             : /// a later pass or that it should stop after an earlier pass, then do not add
     467             : /// the pass.  Finally, compare the current pass against the StartAfter
     468             : /// and StopAfter options and change the Started/Stopped flags accordingly.
     469     1868384 : void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
     470             :   assert(!Initialized && "PassConfig is immutable");
     471             : 
     472             :   // Cache the Pass ID here in case the pass manager finds this pass is
     473             :   // redundant with ones already scheduled / available, and deletes it.
     474             :   // Fundamentally, once we add the pass to the manager, we no longer own it
     475             :   // and shouldn't reference it.
     476     1868384 :   AnalysisID PassID = P->getPassID();
     477             : 
     478     1868384 :   if (StartBefore == PassID)
     479          51 :     Started = true;
     480     1868384 :   if (StopBefore == PassID)
     481          25 :     Stopped = true;
     482     1868384 :   if (Started && !Stopped) {
     483             :     std::string Banner;
     484             :     // Construct banner message before PM->add() as that may delete the pass.
     485     1856612 :     if (AddingMachinePasses && (printAfter || verifyAfter))
     486     5876800 :       Banner = std::string("After ") + std::string(P->getPassName());
     487     1856612 :     PM->add(P);
     488     1856611 :     if (AddingMachinePasses) {
     489     1175360 :       if (printAfter)
     490     1175360 :         addPrintPass(Banner);
     491     1175360 :       if (verifyAfter)
     492      795695 :         addVerifyPass(Banner);
     493             :     }
     494             : 
     495             :     // Add the passes after the pass P if there is any.
     496     4464028 :     for (auto IP : Impl->InsertedPasses) {
     497      375403 :       if (IP.TargetPassID == PassID)
     498       18588 :         addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
     499     1856612 :     }
     500             :   } else {
     501       11772 :     delete P;
     502             :   }
     503     1868385 :   if (StopAfter == PassID)
     504         141 :     Stopped = true;
     505     1868385 :   if (StartAfter == PassID)
     506          70 :     Started = true;
     507     1868385 :   if (Stopped && !Started)
     508           0 :     report_fatal_error("Cannot stop compilation after pass that is not run");
     509     1868385 : }
     510             : 
     511             : /// Add a CodeGen pass at this point in the pipeline after checking for target
     512             : /// and command line overrides.
     513             : ///
     514             : /// addPass cannot return a pointer to the pass instance because is internal the
     515             : /// PassManager and the instance we create here may already be freed.
     516      849401 : AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
     517             :                                      bool printAfter) {
     518      849401 :   IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
     519      849401 :   IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
     520      849401 :   if (!FinalPtr.isValid())
     521             :     return nullptr;
     522             : 
     523             :   Pass *P;
     524      839218 :   if (FinalPtr.isInstance())
     525             :     P = FinalPtr.getInstance();
     526             :   else {
     527      839218 :     P = Pass::createPass(FinalPtr.getID());
     528      839218 :     if (!P)
     529           0 :       llvm_unreachable("Pass ID not registered");
     530             :   }
     531      839218 :   AnalysisID FinalID = P->getPassID();
     532      839218 :   addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
     533             : 
     534      839218 :   return FinalID;
     535             : }
     536             : 
     537       25774 : void TargetPassConfig::printAndVerify(const std::string &Banner) {
     538       25774 :   addPrintPass(Banner);
     539       25774 :   addVerifyPass(Banner);
     540       25774 : }
     541             : 
     542     1201134 : void TargetPassConfig::addPrintPass(const std::string &Banner) {
     543     2402268 :   if (TM->shouldPrintMachineCode())
     544         580 :     PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
     545     1201134 : }
     546             : 
     547      821469 : void TargetPassConfig::addVerifyPass(const std::string &Banner) {
     548             :   bool Verify = VerifyMachineCode;
     549             : #ifdef EXPENSIVE_CHECKS
     550             :   if (VerifyMachineCode == cl::BOU_UNSET)
     551             :     Verify = TM->isMachineVerifierClean();
     552             : #endif
     553      821469 :   if (Verify)
     554      152824 :     PM->add(createMachineVerifierPass(Banner));
     555      821469 : }
     556             : 
     557             : /// Add common target configurable passes that perform LLVM IR to IR transforms
     558             : /// following machine independent optimization.
     559       22791 : void TargetPassConfig::addIRPasses() {
     560       22791 :   switch (UseCFLAA) {
     561           0 :   case CFLAAType::Steensgaard:
     562           0 :     addPass(createCFLSteensAAWrapperPass());
     563           0 :     break;
     564           0 :   case CFLAAType::Andersen:
     565           0 :     addPass(createCFLAndersAAWrapperPass());
     566           0 :     break;
     567           0 :   case CFLAAType::Both:
     568           0 :     addPass(createCFLAndersAAWrapperPass());
     569           0 :     addPass(createCFLSteensAAWrapperPass());
     570           0 :     break;
     571             :   default:
     572             :     break;
     573             :   }
     574             : 
     575             :   // Basic AliasAnalysis support.
     576             :   // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
     577             :   // BasicAliasAnalysis wins if they disagree. This is intended to help
     578             :   // support "obvious" type-punning idioms.
     579       22791 :   addPass(createTypeBasedAAWrapperPass());
     580       22791 :   addPass(createScopedNoAliasAAWrapperPass());
     581       22791 :   addPass(createBasicAAWrapperPass());
     582             : 
     583             :   // Before running any passes, run the verifier to determine if the input
     584             :   // coming from the front-end and/or optimizer is valid.
     585       22791 :   if (!DisableVerify)
     586       19488 :     addPass(createVerifierPass());
     587             : 
     588             :   // Run loop strength reduction before anything else.
     589       41913 :   if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
     590       19111 :     addPass(createLoopStrengthReducePass());
     591       19111 :     if (PrintLSR)
     592           6 :       addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
     593             :   }
     594             : 
     595       22791 :   if (getOptLevel() != CodeGenOpt::None) {
     596             :     // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
     597             :     // loads and compares. ExpandMemCmpPass then tries to expand those calls
     598             :     // into optimally-sized loads and compares. The transforms are enabled by a
     599             :     // target lowering hook.
     600       19122 :     if (!DisableMergeICmps)
     601       19122 :       addPass(createMergeICmpsPass());
     602       19122 :     addPass(createExpandMemCmpPass());
     603             :   }
     604             : 
     605             :   // Run GC lowering passes for builtin collectors
     606             :   // TODO: add a pass insertion point here
     607       22791 :   addPass(createGCLoweringPass());
     608       22791 :   addPass(createShadowStackGCLoweringPass());
     609             : 
     610             :   // Make sure that no unreachable blocks are instruction selected.
     611       22791 :   addPass(createUnreachableBlockEliminationPass());
     612             : 
     613             :   // Prepare expensive constants for SelectionDAG.
     614       41913 :   if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
     615       19121 :     addPass(createConstantHoistingPass());
     616             : 
     617       41913 :   if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
     618       19122 :     addPass(createPartiallyInlineLibCallsPass());
     619             : 
     620             :   // Instrument function entry and exit, e.g. with calls to mcount().
     621       22791 :   addPass(createPostInlineEntryExitInstrumenterPass());
     622             : 
     623             :   // Add scalarization of target's unsupported masked memory intrinsics pass.
     624             :   // the unsupported intrinsic will be replaced with a chain of basic blocks,
     625             :   // that stores/loads element one-by-one if the appropriate mask bit is set.
     626       22791 :   addPass(createScalarizeMaskedMemIntrinPass());
     627             : 
     628             :   // Expand reduction intrinsics into shuffle sequences if the target wants to.
     629       22791 :   addPass(createExpandReductionsPass());
     630       22791 : }
     631             : 
     632             : /// Turn exception handling constructs into something the code generators can
     633             : /// handle.
     634       22791 : void TargetPassConfig::addPassesToHandleExceptions() {
     635       22791 :   const MCAsmInfo *MCAI = TM->getMCAsmInfo();
     636             :   assert(MCAI && "No MCAsmInfo");
     637       22791 :   switch (MCAI->getExceptionHandlingType()) {
     638         713 :   case ExceptionHandling::SjLj:
     639             :     // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
     640             :     // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
     641             :     // catch info can get misplaced when a selector ends up more than one block
     642             :     // removed from the parent invoke(s). This could happen when a landing
     643             :     // pad is shared by multiple invokes and is also a target of a normal
     644             :     // edge from elsewhere.
     645         713 :     addPass(createSjLjEHPreparePass());
     646             :     LLVM_FALLTHROUGH;
     647       19458 :   case ExceptionHandling::DwarfCFI:
     648             :   case ExceptionHandling::ARM:
     649       19458 :     addPass(createDwarfEHPass());
     650       19458 :     break;
     651         623 :   case ExceptionHandling::WinEH:
     652             :     // We support using both GCC-style and MSVC-style exceptions on Windows, so
     653             :     // add both preparation passes. Each pass will only actually run if it
     654             :     // recognizes the personality function.
     655         623 :     addPass(createWinEHPass());
     656         623 :     addPass(createDwarfEHPass());
     657         623 :     break;
     658           1 :   case ExceptionHandling::Wasm:
     659             :     // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
     660             :     // on catchpads and cleanuppads because it does not outline them into
     661             :     // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
     662             :     // should remove PHIs there.
     663           1 :     addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
     664           1 :     addPass(createWasmEHPass());
     665           1 :     break;
     666        2709 :   case ExceptionHandling::None:
     667        2709 :     addPass(createLowerInvokePass());
     668             : 
     669             :     // The lower invoke pass may create unreachable code. Remove it.
     670        2709 :     addPass(createUnreachableBlockEliminationPass());
     671        2709 :     break;
     672             :   }
     673       22791 : }
     674             : 
     675             : /// Add pass to prepare the LLVM IR for code generation. This should be done
     676             : /// before exception handling preparation passes.
     677       22791 : void TargetPassConfig::addCodeGenPrepare() {
     678       41913 :   if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
     679       19118 :     addPass(createCodeGenPreparePass());
     680       22791 :   addPass(createRewriteSymbolsPass());
     681       22791 : }
     682             : 
     683             : /// Add common passes that perform LLVM IR to IR transforms in preparation for
     684             : /// instruction selection.
     685       22791 : void TargetPassConfig::addISelPrepare() {
     686       22791 :   addPreISel();
     687             : 
     688             :   // Force codegen to run according to the callgraph.
     689       22791 :   if (requiresCodeGenSCCOrder())
     690        3602 :     addPass(new DummyCGSCCPass);
     691             : 
     692             :   // Add both the safe stack and the stack protection passes: each of them will
     693             :   // only protect functions that have corresponding attributes.
     694       22791 :   addPass(createSafeStackPass());
     695       22791 :   addPass(createStackProtectorPass());
     696             : 
     697       22791 :   if (PrintISelInput)
     698           0 :     addPass(createPrintFunctionPass(
     699             :         dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
     700             : 
     701             :   // All passes which modify the LLVM IR are now complete; run the verifier
     702             :   // to ensure that the IR is valid.
     703       22791 :   if (!DisableVerify)
     704       19488 :     addPass(createVerifierPass());
     705       22791 : }
     706             : 
     707       22791 : bool TargetPassConfig::addCoreISelPasses() {
     708             :   // Enable FastISel with -fast-isel, but allow that to be overridden.
     709       45582 :   TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
     710       45205 :   if (EnableFastISelOption == cl::BOU_TRUE ||
     711       29560 :       (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel()))
     712        3916 :     TM->setFastISel(true);
     713             : 
     714             :   // Ask the target for an instruction selector.
     715             :   // Explicitly enabling fast-isel should override implicitly enabled
     716             :   // global-isel.
     717       22791 :   if (EnableGlobalISelOption == cl::BOU_TRUE ||
     718       22644 :       (EnableGlobalISelOption == cl::BOU_UNSET &&
     719       22724 :        TM->Options.EnableGlobalISel && EnableFastISelOption != cl::BOU_TRUE)) {
     720         172 :     TM->setFastISel(false);
     721             : 
     722         172 :     if (addIRTranslator())
     723             :       return true;
     724             : 
     725         172 :     addPreLegalizeMachineIR();
     726             : 
     727         172 :     if (addLegalizeMachineIR())
     728             :       return true;
     729             : 
     730             :     // Before running the register bank selector, ask the target if it
     731             :     // wants to run some passes.
     732         172 :     addPreRegBankSelect();
     733             : 
     734         172 :     if (addRegBankSelect())
     735             :       return true;
     736             : 
     737         172 :     addPreGlobalInstructionSelect();
     738             : 
     739         172 :     if (addGlobalInstructionSelect())
     740             :       return true;
     741             : 
     742             :     // Pass to reset the MachineFunction if the ISel failed.
     743         344 :     addPass(createResetMachineFunctionPass(
     744         344 :         reportDiagnosticWhenGlobalISelFallback(), isGlobalISelAbortEnabled()));
     745             : 
     746             :     // Provide a fallback path when we do not want to abort on
     747             :     // not-yet-supported input.
     748         172 :     if (!isGlobalISelAbortEnabled() && addInstSelector())
     749             :       return true;
     750             : 
     751       22619 :   } else if (addInstSelector())
     752             :     return true;
     753             : 
     754             :   return false;
     755             : }
     756             : 
     757       22791 : bool TargetPassConfig::addISelPasses() {
     758       22791 :   if (TM->useEmulatedTLS())
     759         417 :     addPass(createLowerEmuTLSPass());
     760             : 
     761       22791 :   addPass(createPreISelIntrinsicLoweringPass());
     762       45582 :   addPass(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
     763       22791 :   addIRPasses();
     764       22791 :   addCodeGenPrepare();
     765       22791 :   addPassesToHandleExceptions();
     766       22791 :   addISelPrepare();
     767             : 
     768       22791 :   return addCoreISelPasses();
     769             : }
     770             : 
     771             : /// -regalloc=... command line option.
     772           0 : static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
     773             : static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
     774             :                RegisterPassParser<RegisterRegAlloc>>
     775      303507 :     RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
     776      202338 :              cl::desc("Register allocator to use"));
     777             : 
     778             : /// Add the complete set of target-independent postISel code generator passes.
     779             : ///
     780             : /// This can be read as the standard order of major LLVM CodeGen stages. Stages
     781             : /// with nontrivial configuration or multiple passes are broken out below in
     782             : /// add%Stage routines.
     783             : ///
     784             : /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
     785             : /// addPre/Post methods with empty header implementations allow injecting
     786             : /// target-specific fixups just before or after major stages. Additionally,
     787             : /// targets have the flexibility to change pass order within a stage by
     788             : /// overriding default implementation of add%Stage routines below. Each
     789             : /// technique has maintainability tradeoffs because alternate pass orders are
     790             : /// not well supported. addPre/Post works better if the target pass is easily
     791             : /// tied to a common pass. But if it has subtle dependencies on multiple passes,
     792             : /// the target should override the stage instead.
     793             : ///
     794             : /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
     795             : /// before/after any target-independent pass. But it's currently overkill.
     796       22791 : void TargetPassConfig::addMachinePasses() {
     797       22791 :   AddingMachinePasses = true;
     798             : 
     799             :   // Insert a machine instr printer pass after the specified pass.
     800             :   if (!StringRef(PrintMachineInstrs.getValue()).equals("") &&
     801             :       !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) {
     802          21 :     const PassRegistry *PR = PassRegistry::getPassRegistry();
     803          21 :     const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
     804          21 :     const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
     805             :     assert (TPI && IPI && "Pass ID not registered!");
     806          21 :     const char *TID = (const char *)(TPI->getTypeInfo());
     807          21 :     const char *IID = (const char *)(IPI->getTypeInfo());
     808          21 :     insertPass(TID, IID);
     809             :   }
     810             : 
     811             :   // Print the instruction selected machine code...
     812       45582 :   printAndVerify("After Instruction Selection");
     813             : 
     814             :   // Expand pseudo-instructions emitted by ISel.
     815       22791 :   addPass(&ExpandISelPseudosID);
     816             : 
     817             :   // Add passes that optimize machine instructions in SSA form.
     818       22791 :   if (getOptLevel() != CodeGenOpt::None) {
     819       19122 :     addMachineSSAOptimization();
     820             :   } else {
     821             :     // If the target requests it, assign local variables to stack slots relative
     822             :     // to one another and simplify frame index references where possible.
     823        3669 :     addPass(&LocalStackSlotAllocationID, false);
     824             :   }
     825             : 
     826       22791 :   if (TM->Options.EnableIPRA)
     827        1787 :     addPass(createRegUsageInfoPropPass());
     828             : 
     829             :   // Run pre-ra passes.
     830       22791 :   addPreRegAlloc();
     831             : 
     832             :   // Run register allocation and passes that are tightly coupled with it,
     833             :   // including phi elimination and scheduling.
     834       22791 :   if (getOptimizeRegAlloc())
     835       19108 :     addOptimizedRegAlloc(createRegAllocPass(true));
     836             :   else {
     837        3683 :     if (RegAlloc != &useDefaultRegisterAllocator &&
     838             :         RegAlloc != &createFastRegisterAllocator)
     839           0 :       report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
     840        3683 :     addFastRegAlloc(createRegAllocPass(false));
     841             :   }
     842             : 
     843             :   // Run post-ra passes.
     844       22791 :   addPostRegAlloc();
     845             : 
     846             :   // Insert prolog/epilog code.  Eliminate abstract frame index references...
     847       22791 :   if (getOptLevel() != CodeGenOpt::None) {
     848       19122 :     addPass(&PostRAMachineSinkingID);
     849       19122 :     addPass(&ShrinkWrapID);
     850             :   }
     851             : 
     852             :   // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
     853             :   // do so if it hasn't been disabled, substituted, or overridden.
     854       22791 :   if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
     855       22549 :       addPass(createPrologEpilogInserterPass());
     856             : 
     857             :   /// Add passes that optimize machine instructions after register allocation.
     858       22791 :   if (getOptLevel() != CodeGenOpt::None)
     859       19122 :     addMachineLateOptimization();
     860             : 
     861             :   // Expand pseudo instructions before second scheduling pass.
     862       22791 :   addPass(&ExpandPostRAPseudosID);
     863             : 
     864             :   // Run pre-sched2 passes.
     865       22791 :   addPreSched2();
     866             : 
     867       22791 :   if (EnableImplicitNullChecks)
     868           4 :     addPass(&ImplicitNullChecksID);
     869             : 
     870             :   // Second pass scheduler.
     871             :   // Let Target optionally insert this pass by itself at some other
     872             :   // point.
     873       41913 :   if (getOptLevel() != CodeGenOpt::None &&
     874       19122 :       !TM->targetSchedulesPostRAScheduling()) {
     875       18247 :     if (MISchedPostRA)
     876           2 :       addPass(&PostMachineSchedulerID);
     877             :     else
     878       18245 :       addPass(&PostRASchedulerID);
     879             :   }
     880             : 
     881             :   // GC
     882       22791 :   if (addGCPasses()) {
     883       20466 :     if (PrintGCInfo)
     884           0 :       addPass(createGCInfoPrinter(dbgs()), false, false);
     885             :   }
     886             : 
     887             :   // Basic block placement.
     888       22791 :   if (getOptLevel() != CodeGenOpt::None)
     889       19122 :     addBlockPlacement();
     890             : 
     891       22791 :   addPreEmitPass();
     892             : 
     893       22791 :   if (TM->Options.EnableIPRA)
     894             :     // Collect register usage information and produce a register mask of
     895             :     // clobbered registers, to be used to optimize call sites.
     896        1787 :     addPass(createRegUsageInfoCollector());
     897             : 
     898       22791 :   addPass(&FuncletLayoutID, false);
     899             : 
     900       22791 :   addPass(&StackMapLivenessID, false);
     901       22791 :   addPass(&LiveDebugValuesID, false);
     902             : 
     903             :   // Insert before XRay Instrumentation.
     904       22791 :   addPass(&FEntryInserterID, false);
     905             : 
     906       22791 :   addPass(&XRayInstrumentationID, false);
     907       22791 :   addPass(&PatchableFunctionID, false);
     908             : 
     909       22791 :   if (EnableMachineOutliner)
     910          14 :     addPass(createMachineOutlinerPass());
     911             : 
     912             :   // Add passes that directly emit MI after all other MI passes.
     913       22791 :   addPreEmitPass2();
     914             : 
     915       22791 :   AddingMachinePasses = false;
     916       22791 : }
     917             : 
     918             : /// Add passes that optimize machine instructions in SSA form.
     919       18907 : void TargetPassConfig::addMachineSSAOptimization() {
     920             :   // Pre-ra tail duplication.
     921       18907 :   addPass(&EarlyTailDuplicateID);
     922             : 
     923             :   // Optimize PHIs before DCE: removing dead PHI cycles may make more
     924             :   // instructions dead.
     925       18907 :   addPass(&OptimizePHIsID, false);
     926             : 
     927             :   // This pass merges large allocas. StackSlotColoring is a different pass
     928             :   // which merges spill slots.
     929       18907 :   addPass(&StackColoringID, false);
     930             : 
     931             :   // If the target requests it, assign local variables to stack slots relative
     932             :   // to one another and simplify frame index references where possible.
     933       18907 :   addPass(&LocalStackSlotAllocationID, false);
     934             : 
     935             :   // With optimization, dead code should already be eliminated. However
     936             :   // there is one known exception: lowered code for arguments that are only
     937             :   // used by tail calls, where the tail calls reuse the incoming stack
     938             :   // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
     939       18907 :   addPass(&DeadMachineInstructionElimID);
     940             : 
     941             :   // Allow targets to insert passes that improve instruction level parallelism,
     942             :   // like if-conversion. Such passes will typically need dominator trees and
     943             :   // loop info, just like LICM and CSE below.
     944       18907 :   addILPOpts();
     945             : 
     946       18907 :   addPass(&EarlyMachineLICMID, false);
     947       18907 :   addPass(&MachineCSEID, false);
     948             : 
     949       18907 :   addPass(&MachineSinkingID);
     950             : 
     951       18907 :   addPass(&PeepholeOptimizerID);
     952             :   // Clean-up the dead code that may have been generated by peephole
     953             :   // rewriting.
     954       18907 :   addPass(&DeadMachineInstructionElimID);
     955       18907 : }
     956             : 
     957             : //===---------------------------------------------------------------------===//
     958             : /// Register Allocation Pass Configuration
     959             : //===---------------------------------------------------------------------===//
     960             : 
     961       22791 : bool TargetPassConfig::getOptimizeRegAlloc() const {
     962       22791 :   switch (OptimizeRegAlloc) {
     963       22753 :   case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
     964             :   case cl::BOU_TRUE:  return true;
     965          26 :   case cl::BOU_FALSE: return false;
     966             :   }
     967           0 :   llvm_unreachable("Invalid optimize-regalloc state");
     968             : }
     969             : 
     970             : /// RegisterRegAlloc's global Registry tracks allocator registration.
     971             : MachinePassRegistry RegisterRegAlloc::Registry;
     972             : 
     973             : /// A dummy default pass factory indicates whether the register allocator is
     974             : /// overridden on the command line.
     975             : static llvm::once_flag InitializeDefaultRegisterAllocatorFlag;
     976             : 
     977             : static RegisterRegAlloc
     978      101169 : defaultRegAlloc("default",
     979             :                 "pick register allocator based on -O option",
     980             :                 useDefaultRegisterAllocator);
     981             : 
     982       22482 : static void initializeDefaultRegisterAllocatorOnce() {
     983             :   RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
     984             : 
     985       22482 :   if (!Ctor) {
     986             :     Ctor = RegAlloc;
     987             :     RegisterRegAlloc::setDefault(RegAlloc);
     988             :   }
     989       22482 : }
     990             : 
     991             : /// Instantiate the default register allocator pass for this target for either
     992             : /// the optimized or unoptimized allocation path. This will be added to the pass
     993             : /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
     994             : /// in the optimized case.
     995             : ///
     996             : /// A target that uses the standard regalloc pass order for fast or optimized
     997             : /// allocation may still override this for per-target regalloc
     998             : /// selection. But -regalloc=... always takes precedence.
     999       22192 : FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
    1000       22192 :   if (Optimized)
    1001       18582 :     return createGreedyRegisterAllocator();
    1002             :   else
    1003        3610 :     return createFastRegisterAllocator();
    1004             : }
    1005             : 
    1006             : /// Find and instantiate the register allocation pass requested by this target
    1007             : /// at the current optimization level.  Different register allocators are
    1008             : /// defined as separate passes because they may require different analysis.
    1009             : ///
    1010             : /// This helper ensures that the regalloc= option is always available,
    1011             : /// even for targets that override the default allocator.
    1012             : ///
    1013             : /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
    1014             : /// this can be folded into addPass.
    1015       22791 : FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
    1016             :   // Initialize the global default.
    1017             :   llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
    1018             :                   initializeDefaultRegisterAllocatorOnce);
    1019             : 
    1020             :   RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
    1021       22791 :   if (Ctor != useDefaultRegisterAllocator)
    1022         105 :     return Ctor();
    1023             : 
    1024             :   // With no -regalloc= override, ask the target for a regalloc pass.
    1025       22686 :   return createTargetRegisterAllocator(Optimized);
    1026             : }
    1027             : 
    1028             : /// Return true if the default global register allocator is in use and
    1029             : /// has not be overriden on the command line with '-regalloc=...'
    1030        1030 : bool TargetPassConfig::usingDefaultRegAlloc() const {
    1031        1030 :   return RegAlloc.getNumOccurrences() == 0;
    1032             : }
    1033             : 
    1034             : /// Add the minimum set of target-independent passes that are required for
    1035             : /// register allocation. No coalescing or scheduling.
    1036        3656 : void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
    1037        3656 :   addPass(&PHIEliminationID, false);
    1038        3656 :   addPass(&TwoAddressInstructionPassID, false);
    1039             : 
    1040        3656 :   if (RegAllocPass)
    1041        3650 :     addPass(RegAllocPass);
    1042        3656 : }
    1043             : 
    1044             : /// Add standard target-independent passes that are tightly coupled with
    1045             : /// optimized register allocation, including coalescing, machine instruction
    1046             : /// scheduling, and register allocation itself.
    1047       18893 : void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
    1048       18893 :   addPass(&DetectDeadLanesID, false);
    1049             : 
    1050       18893 :   addPass(&ProcessImplicitDefsID, false);
    1051             : 
    1052             :   // LiveVariables currently requires pure SSA form.
    1053             :   //
    1054             :   // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
    1055             :   // LiveVariables can be removed completely, and LiveIntervals can be directly
    1056             :   // computed. (We still either need to regenerate kill flags after regalloc, or
    1057             :   // preferably fix the scavenger to not depend on them).
    1058       18893 :   addPass(&LiveVariablesID, false);
    1059             : 
    1060             :   // Edge splitting is smarter with machine loop info.
    1061       18893 :   addPass(&MachineLoopInfoID, false);
    1062       18893 :   addPass(&PHIEliminationID, false);
    1063             : 
    1064             :   // Eventually, we want to run LiveIntervals before PHI elimination.
    1065       18893 :   if (EarlyLiveIntervals)
    1066           0 :     addPass(&LiveIntervalsID, false);
    1067             : 
    1068       18893 :   addPass(&TwoAddressInstructionPassID, false);
    1069       18893 :   addPass(&RegisterCoalescerID);
    1070             : 
    1071             :   // The machine scheduler may accidentally create disconnected components
    1072             :   // when moving subregister definitions around, avoid this by splitting them to
    1073             :   // separate vregs before. Splitting can also improve reg. allocation quality.
    1074       18893 :   addPass(&RenameIndependentSubregsID);
    1075             : 
    1076             :   // PreRA instruction scheduling.
    1077       18893 :   addPass(&MachineSchedulerID);
    1078             : 
    1079       18893 :   if (RegAllocPass) {
    1080             :     // Add the selected register allocation pass.
    1081       18647 :     addPass(RegAllocPass);
    1082             : 
    1083             :     // Allow targets to change the register assignments before rewriting.
    1084       18647 :     addPreRewrite();
    1085             : 
    1086             :     // Finally rewrite virtual registers.
    1087       18647 :     addPass(&VirtRegRewriterID);
    1088             : 
    1089             :     // Perform stack slot coloring and post-ra machine LICM.
    1090             :     //
    1091             :     // FIXME: Re-enable coloring with register when it's capable of adding
    1092             :     // kill markers.
    1093       18647 :     addPass(&StackSlotColoringID);
    1094             : 
    1095             :     // Copy propagate to forward register uses and try to eliminate COPYs that
    1096             :     // were not coalesced.
    1097       18647 :     addPass(&MachineCopyPropagationID);
    1098             : 
    1099             :     // Run post-ra machine LICM to hoist reloads / remats.
    1100             :     //
    1101             :     // FIXME: can this move into MachineLateOptimization?
    1102       18647 :     addPass(&MachineLICMID);
    1103             :   }
    1104       18893 : }
    1105             : 
    1106             : //===---------------------------------------------------------------------===//
    1107             : /// Post RegAlloc Pass Configuration
    1108             : //===---------------------------------------------------------------------===//
    1109             : 
    1110             : /// Add passes that optimize machine instructions after register allocation.
    1111       19122 : void TargetPassConfig::addMachineLateOptimization() {
    1112             :   // Branch folding must be run after regalloc and prolog/epilog insertion.
    1113       19122 :   addPass(&BranchFolderPassID);
    1114             : 
    1115             :   // Tail duplication.
    1116             :   // Note that duplicating tail just increases code size and degrades
    1117             :   // performance for targets that require Structured Control Flow.
    1118             :   // In addition it can also make CFG irreducible. Thus we disable it.
    1119       38244 :   if (!TM->requiresStructuredCFG())
    1120       18630 :     addPass(&TailDuplicateID);
    1121             : 
    1122             :   // Copy propagation.
    1123       19122 :   addPass(&MachineCopyPropagationID);
    1124       19122 : }
    1125             : 
    1126             : /// Add standard GC passes.
    1127       20466 : bool TargetPassConfig::addGCPasses() {
    1128       20466 :   addPass(&GCMachineCodeAnalysisID, false);
    1129       20466 :   return true;
    1130             : }
    1131             : 
    1132             : /// Add standard basic block placement passes.
    1133       19122 : void TargetPassConfig::addBlockPlacement() {
    1134       19122 :   if (addPass(&MachineBlockPlacementID)) {
    1135             :     // Run a separate pass to collect block placement statistics.
    1136       19098 :     if (EnableBlockPlacementStats)
    1137           0 :       addPass(&MachineBlockPlacementStatsID);
    1138             :   }
    1139       19122 : }
    1140             : 
    1141             : //===---------------------------------------------------------------------===//
    1142             : /// GlobalISel Configuration
    1143             : //===---------------------------------------------------------------------===//
    1144         558 : bool TargetPassConfig::isGlobalISelAbortEnabled() const {
    1145         558 :   if (EnableGlobalISelAbort.getNumOccurrences() > 0)
    1146         242 :     return EnableGlobalISelAbort == 1;
    1147             : 
    1148             :   // When no abort behaviour is specified, we don't abort if the target says
    1149             :   // that GISel is enabled.
    1150         316 :   return !TM->Options.EnableGlobalISel;
    1151             : }
    1152             : 
    1153         172 : bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
    1154         172 :   return EnableGlobalISelAbort == 2;
    1155      303507 : }

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