LCOV - code coverage report
Current view: top level - lib/CodeGen - TargetPassConfig.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 446 474 94.1 %
Date: 2018-02-23 15:42:53 Functions: 43 47 91.5 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file defines interfaces to access the target independent code
      11             : // generation passes provided by the LLVM backend.
      12             : //
      13             : //===---------------------------------------------------------------------===//
      14             : 
      15             : #include "llvm/CodeGen/TargetPassConfig.h"
      16             : #include "llvm/ADT/DenseMap.h"
      17             : #include "llvm/ADT/SmallVector.h"
      18             : #include "llvm/ADT/StringRef.h"
      19             : #include "llvm/Analysis/BasicAliasAnalysis.h"
      20             : #include "llvm/Analysis/CFLAndersAliasAnalysis.h"
      21             : #include "llvm/Analysis/CFLSteensAliasAnalysis.h"
      22             : #include "llvm/Analysis/CallGraphSCCPass.h"
      23             : #include "llvm/Analysis/ScopedNoAliasAA.h"
      24             : #include "llvm/Analysis/TargetTransformInfo.h"
      25             : #include "llvm/Analysis/TypeBasedAliasAnalysis.h"
      26             : #include "llvm/CodeGen/MachineFunctionPass.h"
      27             : #include "llvm/CodeGen/MachinePassRegistry.h"
      28             : #include "llvm/CodeGen/Passes.h"
      29             : #include "llvm/CodeGen/RegAllocRegistry.h"
      30             : #include "llvm/IR/IRPrintingPasses.h"
      31             : #include "llvm/IR/LegacyPassManager.h"
      32             : #include "llvm/IR/Verifier.h"
      33             : #include "llvm/MC/MCAsmInfo.h"
      34             : #include "llvm/MC/MCTargetOptions.h"
      35             : #include "llvm/Pass.h"
      36             : #include "llvm/Support/CodeGen.h"
      37             : #include "llvm/Support/CommandLine.h"
      38             : #include "llvm/Support/Compiler.h"
      39             : #include "llvm/Support/Debug.h"
      40             : #include "llvm/Support/ErrorHandling.h"
      41             : #include "llvm/Support/Threading.h"
      42             : #include "llvm/Target/TargetMachine.h"
      43             : #include "llvm/Transforms/Scalar.h"
      44             : #include "llvm/Transforms/Utils/SymbolRewriter.h"
      45             : #include <cassert>
      46             : #include <string>
      47             : 
      48             : using namespace llvm;
      49             : 
      50      245058 : cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
      51       81686 :                          cl::desc("Enable interprocedural register allocation "
      52      245058 :                                   "to reduce load/store at procedure calls."));
      53       81686 : static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
      54       81686 :     cl::desc("Disable Post Regalloc Scheduler"));
      55       81686 : static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
      56       81686 :     cl::desc("Disable branch folding"));
      57       81686 : static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
      58       81686 :     cl::desc("Disable tail duplication"));
      59       81686 : static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
      60       81686 :     cl::desc("Disable pre-register allocation tail duplication"));
      61       81686 : static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
      62       81686 :     cl::Hidden, cl::desc("Disable probability-driven block placement"));
      63       81686 : static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
      64       81686 :     cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
      65       81686 : static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
      66       81686 :     cl::desc("Disable Stack Slot Coloring"));
      67       81686 : static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
      68       81686 :     cl::desc("Disable Machine Dead Code Elimination"));
      69       81686 : static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
      70       81686 :     cl::desc("Disable Early If-conversion"));
      71       81686 : static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
      72       81686 :     cl::desc("Disable Machine LICM"));
      73       81686 : static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
      74       81686 :     cl::desc("Disable Machine Common Subexpression Elimination"));
      75       81686 : static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
      76             :     "optimize-regalloc", cl::Hidden,
      77       81686 :     cl::desc("Enable optimized register allocation compilation path."));
      78       81686 : static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
      79             :     cl::Hidden,
      80       81686 :     cl::desc("Disable Machine LICM"));
      81       81686 : static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
      82       81686 :     cl::desc("Disable Machine Sinking"));
      83       81686 : static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
      84       81686 :     cl::desc("Disable Loop Strength Reduction Pass"));
      85       81686 : static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
      86       81686 :     cl::Hidden, cl::desc("Disable ConstantHoisting"));
      87       81686 : static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
      88       81686 :     cl::desc("Disable Codegen Prepare"));
      89       81686 : static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
      90       81686 :     cl::desc("Disable Copy Propagation pass"));
      91       81686 : static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
      92       81686 :     cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
      93       81686 : static cl::opt<bool> EnableImplicitNullChecks(
      94             :     "enable-implicit-null-checks",
      95       81686 :     cl::desc("Fold null checks into faulting memory operations"),
      96      245058 :     cl::init(false), cl::Hidden);
      97       81686 : static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
      98       81686 :     cl::desc("Disable MergeICmps Pass"),
      99      245058 :     cl::init(false), cl::Hidden);
     100       81686 : static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
     101       81686 :     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
     102       81686 : static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
     103       81686 :     cl::desc("Print LLVM IR input to isel pass"));
     104       81686 : static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
     105       81686 :     cl::desc("Dump garbage collector data"));
     106       81686 : static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
     107       81686 :     cl::desc("Verify generated machine code"),
     108      163372 :     cl::init(false),
     109      245058 :     cl::ZeroOrMore);
     110       81686 : static cl::opt<bool> EnableMachineOutliner("enable-machine-outliner",
     111             :     cl::Hidden,
     112       81686 :     cl::desc("Enable machine outliner"));
     113       81686 : static cl::opt<bool> EnableLinkOnceODROutlining(
     114             :     "enable-linkonceodr-outlining",
     115             :     cl::Hidden,
     116       81686 :     cl::desc("Enable the machine outliner on linkonceodr functions"),
     117      245058 :     cl::init(false));
     118             : // Enable or disable FastISel. Both options are needed, because
     119             : // FastISel is enabled by default with -fast, and we wish to be
     120             : // able to enable or disable fast-isel independently from -O0.
     121             : static cl::opt<cl::boolOrDefault>
     122       81686 : EnableFastISelOption("fast-isel", cl::Hidden,
     123       81686 :   cl::desc("Enable the \"fast\" instruction selector"));
     124             : 
     125       81686 : static cl::opt<cl::boolOrDefault> EnableGlobalISelOption(
     126             :     "global-isel", cl::Hidden,
     127       81686 :     cl::desc("Enable the \"global\" instruction selector"));
     128             : 
     129       81686 : static cl::opt<std::string> PrintMachineInstrs(
     130       81686 :     "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
     131      245058 :     cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
     132             : 
     133       81686 : static cl::opt<int> EnableGlobalISelAbort(
     134             :     "global-isel-abort", cl::Hidden,
     135       81686 :     cl::desc("Enable abort calls when \"global\" instruction selection "
     136             :              "fails to lower/select an instruction: 0 disable the abort, "
     137             :              "1 enable the abort, and "
     138             :              "2 disable the abort but emit a diagnostic on failure"),
     139      245058 :     cl::init(1));
     140             : 
     141             : // Temporary option to allow experimenting with MachineScheduler as a post-RA
     142             : // scheduler. Targets can "properly" enable this with
     143             : // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
     144             : // Targets can return true in targetSchedulesPostRAScheduling() and
     145             : // insert a PostRA scheduling pass wherever it wants.
     146       81686 : cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
     147       81686 :   cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
     148             : 
     149             : // Experimental option to run live interval analysis early.
     150       81686 : static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
     151       81686 :     cl::desc("Run live interval analysis earlier in the pipeline"));
     152             : 
     153             : // Experimental option to use CFL-AA in codegen
     154             : enum class CFLAAType { None, Steensgaard, Andersen, Both };
     155       81686 : static cl::opt<CFLAAType> UseCFLAA(
     156      163372 :     "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
     157       81686 :     cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
     158      490116 :     cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
     159             :                clEnumValN(CFLAAType::Steensgaard, "steens",
     160             :                           "Enable unification-based CFL-AA"),
     161             :                clEnumValN(CFLAAType::Andersen, "anders",
     162             :                           "Enable inclusion-based CFL-AA"),
     163             :                clEnumValN(CFLAAType::Both, "both", 
     164      245058 :                           "Enable both variants of CFL-AA")));
     165             : 
     166             : /// Option names for limiting the codegen pipeline.
     167             : /// Those are used in error reporting and we didn't want
     168             : /// to duplicate their names all over the place.
     169             : const char *StartAfterOptName = "start-after";
     170             : const char *StartBeforeOptName = "start-before";
     171             : const char *StopAfterOptName = "stop-after";
     172             : const char *StopBeforeOptName = "stop-before";
     173             : 
     174             : static cl::opt<std::string>
     175      245058 :     StartAfterOpt(StringRef(StartAfterOptName),
     176       81686 :                   cl::desc("Resume compilation after a specific pass"),
     177      245058 :                   cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
     178             : 
     179             : static cl::opt<std::string>
     180      245058 :     StartBeforeOpt(StringRef(StartBeforeOptName),
     181       81686 :                    cl::desc("Resume compilation before a specific pass"),
     182      245058 :                    cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
     183             : 
     184             : static cl::opt<std::string>
     185      245058 :     StopAfterOpt(StringRef(StopAfterOptName),
     186       81686 :                  cl::desc("Stop compilation after a specific pass"),
     187      245058 :                  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
     188             : 
     189             : static cl::opt<std::string>
     190      245058 :     StopBeforeOpt(StringRef(StopBeforeOptName),
     191       81686 :                   cl::desc("Stop compilation before a specific pass"),
     192      245058 :                   cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
     193             : 
     194             : /// Allow standard passes to be disabled by command line options. This supports
     195             : /// simple binary flags that either suppress the pass or do nothing.
     196             : /// i.e. -disable-mypass=false has no effect.
     197             : /// These should be converted to boolOrDefault in order to use applyOverride.
     198             : static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
     199             :                                        bool Override) {
     200      242963 :   if (Override)
     201             :     return IdentifyingPassPtr();
     202      242824 :   return PassID;
     203             : }
     204             : 
     205             : /// Allow standard passes to be disabled by the command line, regardless of who
     206             : /// is adding the pass.
     207             : ///
     208             : /// StandardID is the pass identified in the standard pass pipeline and provided
     209             : /// to addPass(). It may be a target-specific ID in the case that the target
     210             : /// directly adds its own pass, but in that case we harmlessly fall through.
     211             : ///
     212             : /// TargetID is the pass that the target has configured to override StandardID.
     213             : ///
     214             : /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
     215             : /// pass to run. This allows multiple options to control a single pass depending
     216             : /// on where in the pipeline that pass is added.
     217      735721 : static IdentifyingPassPtr overridePass(AnalysisID StandardID,
     218             :                                        IdentifyingPassPtr TargetID) {
     219      735721 :   if (StandardID == &PostRASchedulerID)
     220             :     return applyDisable(TargetID, DisablePostRASched);
     221             : 
     222      719127 :   if (StandardID == &BranchFolderPassID)
     223             :     return applyDisable(TargetID, DisableBranchFold);
     224             : 
     225      701725 :   if (StandardID == &TailDuplicateID)
     226             :     return applyDisable(TargetID, DisableTailDuplicate);
     227             : 
     228      684596 :   if (StandardID == &EarlyTailDuplicateID)
     229             :     return applyDisable(TargetID, DisableEarlyTailDup);
     230             : 
     231      667194 :   if (StandardID == &MachineBlockPlacementID)
     232             :     return applyDisable(TargetID, DisableBlockPlacement);
     233             : 
     234      649792 :   if (StandardID == &StackSlotColoringID)
     235             :     return applyDisable(TargetID, DisableSSC);
     236             : 
     237      632404 :   if (StandardID == &DeadMachineInstructionElimID)
     238             :     return applyDisable(TargetID, DisableMachineDCE);
     239             : 
     240      593153 :   if (StandardID == &EarlyIfConverterID)
     241             :     return applyDisable(TargetID, DisableEarlyIfConversion);
     242             : 
     243      582820 :   if (StandardID == &EarlyMachineLICMID)
     244             :     return applyDisable(TargetID, DisableMachineLICM);
     245             : 
     246      563780 :   if (StandardID == &MachineCSEID)
     247             :     return applyDisable(TargetID, DisableMachineCSE);
     248             : 
     249      544740 :   if (StandardID == &MachineLICMID)
     250             :     return applyDisable(TargetID, DisablePostRAMachineLICM);
     251             : 
     252      527562 :   if (StandardID == &MachineSinkingID)
     253             :     return applyDisable(TargetID, DisableMachineSink);
     254             : 
     255      510160 :   if (StandardID == &MachineCopyPropagationID)
     256             :     return applyDisable(TargetID, DisableCopyProp);
     257             : 
     258      492758 :   return TargetID;
     259             : }
     260             : 
     261             : //===---------------------------------------------------------------------===//
     262             : /// TargetPassConfig
     263             : //===---------------------------------------------------------------------===//
     264             : 
     265      958290 : INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
     266             :                 "Target Pass Configuration", false, false)
     267             : char TargetPassConfig::ID = 0;
     268             : 
     269             : namespace {
     270             : 
     271             : struct InsertedPass {
     272             :   AnalysisID TargetPassID;
     273             :   IdentifyingPassPtr InsertedPassID;
     274             :   bool VerifyAfter;
     275             :   bool PrintAfter;
     276             : 
     277             :   InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
     278             :                bool VerifyAfter, bool PrintAfter)
     279        6888 :       : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
     280        6888 :         VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
     281             : 
     282             :   Pass *getInsertedPass() const {
     283             :     assert(InsertedPassID.isValid() && "Illegal Pass ID!");
     284        6852 :     if (InsertedPassID.isInstance())
     285             :       return InsertedPassID.getInstance();
     286        6852 :     Pass *NP = Pass::createPass(InsertedPassID.getID());
     287             :     assert(NP && "Pass ID not registered");
     288             :     return NP;
     289             :   }
     290             : };
     291             : 
     292             : } // end anonymous namespace
     293             : 
     294             : namespace llvm {
     295             : 
     296       67261 : class PassConfigImpl {
     297             : public:
     298             :   // List of passes explicitly substituted by this target. Normally this is
     299             :   // empty, but it is a convenient way to suppress or replace specific passes
     300             :   // that are part of a standard pass pipeline without overridding the entire
     301             :   // pipeline. This mechanism allows target options to inherit a standard pass's
     302             :   // user interface. For example, a target may disable a standard pass by
     303             :   // default by substituting a pass ID of zero, and the user may still enable
     304             :   // that standard pass with an explicit command line option.
     305             :   DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
     306             : 
     307             :   /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
     308             :   /// is inserted after each instance of the first one.
     309             :   SmallVector<InsertedPass, 4> InsertedPasses;
     310             : };
     311             : 
     312             : } // end namespace llvm
     313             : 
     314             : // Out of line virtual method.
     315       44738 : TargetPassConfig::~TargetPassConfig() {
     316       22369 :   delete Impl;
     317       22369 : }
     318             : 
     319       90097 : static const PassInfo *getPassInfo(StringRef PassName) {
     320       90097 :   if (PassName.empty())
     321             :     return nullptr;
     322             : 
     323         218 :   const PassRegistry &PR = *PassRegistry::getPassRegistry();
     324         218 :   const PassInfo *PI = PR.getPassInfo(PassName);
     325         218 :   if (!PI)
     326           4 :     report_fatal_error(Twine('\"') + Twine(PassName) +
     327             :                        Twine("\" pass is not registered."));
     328             :   return PI;
     329             : }
     330             : 
     331             : static AnalysisID getPassIDFromName(StringRef PassName) {
     332       90097 :   const PassInfo *PI = getPassInfo(PassName);
     333       90094 :   return PI ? PI->getTypeInfo() : nullptr;
     334             : }
     335             : 
     336       22525 : void TargetPassConfig::setStartStopPasses() {
     337       22525 :   StartBefore = getPassIDFromName(StartBeforeOpt);
     338       22524 :   StartAfter = getPassIDFromName(StartAfterOpt);
     339       22523 :   StopBefore = getPassIDFromName(StopBeforeOpt);
     340       22522 :   StopAfter = getPassIDFromName(StopAfterOpt);
     341       22522 :   if (StartBefore && StartAfter)
     342           2 :     report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
     343           1 :                        Twine(StartAfterOptName) + Twine(" specified!"));
     344       22521 :   if (StopBefore && StopAfter)
     345           2 :     report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
     346           1 :                        Twine(StopAfterOptName) + Twine(" specified!"));
     347       22520 :   Started = (StartAfter == nullptr) && (StartBefore == nullptr);
     348       22520 : }
     349             : 
     350             : // Out of line constructor provides default values for pass options and
     351             : // registers all common codegen passes.
     352       22526 : TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
     353       22526 :     : ImmutablePass(ID), PM(&pm), TM(&TM) {
     354       45052 :   Impl = new PassConfigImpl();
     355             : 
     356             :   // Register all target independent codegen passes to activate their PassIDs,
     357             :   // including this pass itself.
     358       22526 :   initializeCodeGen(*PassRegistry::getPassRegistry());
     359             : 
     360             :   // Also register alias analysis passes required by codegen passes.
     361       22526 :   initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
     362       22526 :   initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
     363             : 
     364             :   if (StringRef(PrintMachineInstrs.getValue()).equals(""))
     365          10 :     TM.Options.PrintMachineCode = true;
     366             : 
     367       22526 :   if (EnableIPRA.getNumOccurrences())
     368          20 :     TM.Options.EnableIPRA = EnableIPRA;
     369             :   else {
     370             :     // If not explicitly specified, use target default.
     371       22506 :     TM.Options.EnableIPRA = TM.useIPRA();
     372             :   }
     373             : 
     374       22526 :   if (TM.Options.EnableIPRA)
     375             :     setRequiresCodeGenSCCOrder();
     376             : 
     377       22526 :   setStartStopPasses();
     378       22520 : }
     379             : 
     380      443521 : CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
     381      443521 :   return TM->getOptLevel();
     382             : }
     383             : 
     384             : /// Insert InsertedPassID pass after TargetPassID.
     385        6888 : void TargetPassConfig::insertPass(AnalysisID TargetPassID,
     386             :                                   IdentifyingPassPtr InsertedPassID,
     387             :                                   bool VerifyAfter, bool PrintAfter) {
     388             :   assert(((!InsertedPassID.isInstance() &&
     389             :            TargetPassID != InsertedPassID.getID()) ||
     390             :           (InsertedPassID.isInstance() &&
     391             :            TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
     392             :          "Insert a pass after itself!");
     393        6888 :   Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
     394             :                                     PrintAfter);
     395        6888 : }
     396             : 
     397             : /// createPassConfig - Create a pass configuration object to be used by
     398             : /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
     399             : ///
     400             : /// Targets may override this to extend TargetPassConfig.
     401           0 : TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
     402           0 :   return new TargetPassConfig(*this, PM);
     403             : }
     404             : 
     405           1 : TargetPassConfig::TargetPassConfig()
     406           1 :   : ImmutablePass(ID) {
     407           1 :   report_fatal_error("Trying to construct TargetPassConfig without a target "
     408             :                      "machine. Scheduling a CodeGen pass without a target "
     409             :                      "triple set?");
     410             : }
     411             : 
     412       19548 : bool TargetPassConfig::hasLimitedCodeGenPipeline() const {
     413       19548 :   return StartBefore || StartAfter || StopBefore || StopAfter;
     414             : }
     415             : 
     416             : std::string
     417           0 : TargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) const {
     418           0 :   if (!hasLimitedCodeGenPipeline())
     419             :     return std::string();
     420             :   std::string Res;
     421             :   static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
     422             :                                               &StopAfterOpt, &StopBeforeOpt};
     423             :   static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
     424           0 :                                    StopAfterOptName, StopBeforeOptName};
     425             :   bool IsFirst = true;
     426           0 :   for (int Idx = 0; Idx < 4; ++Idx)
     427           0 :     if (!PassNames[Idx]->empty()) {
     428           0 :       if (!IsFirst)
     429             :         Res += Separator;
     430             :       IsFirst = false;
     431           0 :       Res += OptNames[Idx];
     432             :     }
     433             :   return Res;
     434             : }
     435             : 
     436             : // Helper to verify the analysis is really immutable.
     437       23453 : void TargetPassConfig::setOpt(bool &Opt, bool Val) {
     438             :   assert(!Initialized && "PassConfig is immutable");
     439       23453 :   Opt = Val;
     440       23453 : }
     441             : 
     442       13326 : void TargetPassConfig::substitutePass(AnalysisID StandardID,
     443             :                                       IdentifyingPassPtr TargetID) {
     444       26652 :   Impl->TargetPasses[StandardID] = TargetID;
     445       13326 : }
     446             : 
     447      735721 : IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
     448             :   DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
     449     1471442 :     I = Impl->TargetPasses.find(ID);
     450     1471442 :   if (I == Impl->TargetPasses.end())
     451      727021 :     return ID;
     452        8700 :   return I->second;
     453             : }
     454             : 
     455       18804 : bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
     456       18804 :   IdentifyingPassPtr TargetID = getPassSubstitution(ID);
     457       18804 :   IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
     458       18804 :   return !FinalPtr.isValid() || FinalPtr.isInstance() ||
     459       18804 :       FinalPtr.getID() != ID;
     460             : }
     461             : 
     462             : /// Add a pass to the PassManager if that pass is supposed to be run.  If the
     463             : /// Started/Stopped flags indicate either that the compilation should start at
     464             : /// a later pass or that it should stop after an earlier pass, then do not add
     465             : /// the pass.  Finally, compare the current pass against the StartAfter
     466             : /// and StopAfter options and change the Started/Stopped flags accordingly.
     467     1556747 : void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
     468             :   assert(!Initialized && "PassConfig is immutable");
     469             : 
     470             :   // Cache the Pass ID here in case the pass manager finds this pass is
     471             :   // redundant with ones already scheduled / available, and deletes it.
     472             :   // Fundamentally, once we add the pass to the manager, we no longer own it
     473             :   // and shouldn't reference it.
     474     1556747 :   AnalysisID PassID = P->getPassID();
     475             : 
     476     1556747 :   if (StartBefore == PassID)
     477          26 :     Started = true;
     478     1556747 :   if (StopBefore == PassID)
     479          13 :     Stopped = true;
     480     1556747 :   if (Started && !Stopped) {
     481             :     std::string Banner;
     482             :     // Construct banner message before PM->add() as that may delete the pass.
     483     1548211 :     if (AddingMachinePasses && (printAfter || verifyAfter))
     484     4825015 :       Banner = std::string("After ") + std::string(P->getPassName());
     485     1548211 :     PM->add(P);
     486     1548211 :     if (AddingMachinePasses) {
     487      965002 :       if (printAfter)
     488      965002 :         addPrintPass(Banner);
     489      965002 :       if (verifyAfter)
     490      637996 :         addVerifyPass(Banner);
     491             :     }
     492             : 
     493             :     // Add the passes after the pass P if there is any.
     494     3610126 :     for (auto IP : Impl->InsertedPasses) {
     495      256852 :       if (IP.TargetPassID == PassID)
     496       13704 :         addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
     497     1548211 :     }
     498             :   } else {
     499        8536 :     delete P;
     500             :   }
     501     1556748 :   if (StopAfter == PassID)
     502         105 :     Stopped = true;
     503     1556748 :   if (StartAfter == PassID)
     504          62 :     Started = true;
     505     1556748 :   if (Stopped && !Started)
     506           0 :     report_fatal_error("Cannot stop compilation after pass that is not run");
     507     1556748 : }
     508             : 
     509             : /// Add a CodeGen pass at this point in the pipeline after checking for target
     510             : /// and command line overrides.
     511             : ///
     512             : /// addPass cannot return a pointer to the pass instance because is internal the
     513             : /// PassManager and the instance we create here may already be freed.
     514      716917 : AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
     515             :                                      bool printAfter) {
     516      716917 :   IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
     517      716917 :   IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
     518      716917 :   if (!FinalPtr.isValid())
     519             :     return nullptr;
     520             : 
     521             :   Pass *P;
     522      709320 :   if (FinalPtr.isInstance())
     523             :     P = FinalPtr.getInstance();
     524             :   else {
     525      709320 :     P = Pass::createPass(FinalPtr.getID());
     526      709320 :     if (!P)
     527           0 :       llvm_unreachable("Pass ID not registered");
     528             :   }
     529      709320 :   AnalysisID FinalID = P->getPassID();
     530      709320 :   addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
     531             : 
     532      709320 :   return FinalID;
     533             : }
     534             : 
     535       21359 : void TargetPassConfig::printAndVerify(const std::string &Banner) {
     536       21359 :   addPrintPass(Banner);
     537       21359 :   addVerifyPass(Banner);
     538       21359 : }
     539             : 
     540      986361 : void TargetPassConfig::addPrintPass(const std::string &Banner) {
     541     1972722 :   if (TM->shouldPrintMachineCode())
     542         552 :     PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
     543      986361 : }
     544             : 
     545      659355 : void TargetPassConfig::addVerifyPass(const std::string &Banner) {
     546             :   bool Verify = VerifyMachineCode;
     547             : #ifdef EXPENSIVE_CHECKS
     548             :   if (VerifyMachineCode == cl::BOU_UNSET)
     549             :     Verify = TM->isMachineVerifierClean();
     550             : #endif
     551      659355 :   if (Verify)
     552      136688 :     PM->add(createMachineVerifierPass(Banner));
     553      659355 : }
     554             : 
     555             : /// Add common target configurable passes that perform LLVM IR to IR transforms
     556             : /// following machine independent optimization.
     557       18804 : void TargetPassConfig::addIRPasses() {
     558       18804 :   switch (UseCFLAA) {
     559           0 :   case CFLAAType::Steensgaard:
     560           0 :     addPass(createCFLSteensAAWrapperPass());
     561           0 :     break;
     562           0 :   case CFLAAType::Andersen:
     563           0 :     addPass(createCFLAndersAAWrapperPass());
     564           0 :     break;
     565           0 :   case CFLAAType::Both:
     566           0 :     addPass(createCFLAndersAAWrapperPass());
     567           0 :     addPass(createCFLSteensAAWrapperPass());
     568           0 :     break;
     569             :   default:
     570             :     break;
     571             :   }
     572             : 
     573             :   // Basic AliasAnalysis support.
     574             :   // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
     575             :   // BasicAliasAnalysis wins if they disagree. This is intended to help
     576             :   // support "obvious" type-punning idioms.
     577       18804 :   addPass(createTypeBasedAAWrapperPass());
     578       18804 :   addPass(createScopedNoAliasAAWrapperPass());
     579       18804 :   addPass(createBasicAAWrapperPass());
     580             : 
     581             :   // Before running any passes, run the verifier to determine if the input
     582             :   // coming from the front-end and/or optimizer is valid.
     583       18804 :   if (!DisableVerify)
     584       17718 :     addPass(createVerifierPass());
     585             : 
     586             :   // Run loop strength reduction before anything else.
     587       36206 :   if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
     588       17391 :     addPass(createLoopStrengthReducePass());
     589       17391 :     if (PrintLSR)
     590           6 :       addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
     591             :   }
     592             : 
     593       18804 :   if (getOptLevel() != CodeGenOpt::None) {
     594             :     // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
     595             :     // loads and compares. ExpandMemCmpPass then tries to expand those calls
     596             :     // into optimally-sized loads and compares. The transforms are enabled by a
     597             :     // target lowering hook.
     598       17402 :     if (!DisableMergeICmps)
     599       17402 :       addPass(createMergeICmpsPass());
     600       17402 :     addPass(createExpandMemCmpPass());
     601             :   }
     602             : 
     603             :   // Run GC lowering passes for builtin collectors
     604             :   // TODO: add a pass insertion point here
     605       18804 :   addPass(createGCLoweringPass());
     606       18804 :   addPass(createShadowStackGCLoweringPass());
     607             : 
     608             :   // Make sure that no unreachable blocks are instruction selected.
     609       18804 :   addPass(createUnreachableBlockEliminationPass());
     610             : 
     611             :   // Prepare expensive constants for SelectionDAG.
     612       36206 :   if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
     613       17401 :     addPass(createConstantHoistingPass());
     614             : 
     615       36206 :   if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
     616       17402 :     addPass(createPartiallyInlineLibCallsPass());
     617             : 
     618             :   // Instrument function entry and exit, e.g. with calls to mcount().
     619       18804 :   addPass(createPostInlineEntryExitInstrumenterPass());
     620             : 
     621             :   // Add scalarization of target's unsupported masked memory intrinsics pass.
     622             :   // the unsupported intrinsic will be replaced with a chain of basic blocks,
     623             :   // that stores/loads element one-by-one if the appropriate mask bit is set.
     624       18804 :   addPass(createScalarizeMaskedMemIntrinPass());
     625             : 
     626             :   // Expand reduction intrinsics into shuffle sequences if the target wants to.
     627       18804 :   addPass(createExpandReductionsPass());
     628       18804 : }
     629             : 
     630             : /// Turn exception handling constructs into something the code generators can
     631             : /// handle.
     632       18804 : void TargetPassConfig::addPassesToHandleExceptions() {
     633       18804 :   const MCAsmInfo *MCAI = TM->getMCAsmInfo();
     634             :   assert(MCAI && "No MCAsmInfo");
     635       18804 :   switch (MCAI->getExceptionHandlingType()) {
     636         709 :   case ExceptionHandling::SjLj:
     637             :     // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
     638             :     // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
     639             :     // catch info can get misplaced when a selector ends up more than one block
     640             :     // removed from the parent invoke(s). This could happen when a landing
     641             :     // pad is shared by multiple invokes and is also a target of a normal
     642             :     // edge from elsewhere.
     643         709 :     addPass(createSjLjEHPreparePass());
     644             :     LLVM_FALLTHROUGH;
     645       15959 :   case ExceptionHandling::DwarfCFI:
     646             :   case ExceptionHandling::ARM:
     647       15959 :     addPass(createDwarfEHPass());
     648       15959 :     break;
     649         585 :   case ExceptionHandling::WinEH:
     650             :     // We support using both GCC-style and MSVC-style exceptions on Windows, so
     651             :     // add both preparation passes. Each pass will only actually run if it
     652             :     // recognizes the personality function.
     653         585 :     addPass(createWinEHPass());
     654         585 :     addPass(createDwarfEHPass());
     655         585 :     break;
     656        2260 :   case ExceptionHandling::None:
     657        2260 :     addPass(createLowerInvokePass());
     658             : 
     659             :     // The lower invoke pass may create unreachable code. Remove it.
     660        2260 :     addPass(createUnreachableBlockEliminationPass());
     661        2260 :     break;
     662             :   }
     663       18804 : }
     664             : 
     665             : /// Add pass to prepare the LLVM IR for code generation. This should be done
     666             : /// before exception handling preparation passes.
     667       18804 : void TargetPassConfig::addCodeGenPrepare() {
     668       36206 :   if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
     669       17398 :     addPass(createCodeGenPreparePass());
     670       18804 :   addPass(createRewriteSymbolsPass());
     671       18804 : }
     672             : 
     673             : /// Add common passes that perform LLVM IR to IR transforms in preparation for
     674             : /// instruction selection.
     675       18804 : void TargetPassConfig::addISelPrepare() {
     676       18804 :   addPreISel();
     677             : 
     678             :   // Force codegen to run according to the callgraph.
     679       18804 :   if (requiresCodeGenSCCOrder())
     680        3382 :     addPass(new DummyCGSCCPass);
     681             : 
     682             :   // Add both the safe stack and the stack protection passes: each of them will
     683             :   // only protect functions that have corresponding attributes.
     684       18804 :   addPass(createSafeStackPass());
     685       18804 :   addPass(createStackProtectorPass());
     686             : 
     687       18804 :   if (PrintISelInput)
     688           0 :     addPass(createPrintFunctionPass(
     689             :         dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
     690             : 
     691             :   // All passes which modify the LLVM IR are now complete; run the verifier
     692             :   // to ensure that the IR is valid.
     693       18804 :   if (!DisableVerify)
     694       17718 :     addPass(createVerifierPass());
     695       18804 : }
     696             : 
     697       18804 : bool TargetPassConfig::addCoreISelPasses() {
     698             :   // Enable FastISel with -fast-isel, but allow that to be overridden.
     699       37608 :   TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
     700       37295 :   if (EnableFastISelOption == cl::BOU_TRUE ||
     701       21103 :       (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel()))
     702        1585 :     TM->setFastISel(true);
     703             : 
     704             :   // Ask the target for an instruction selector.
     705             :   // Explicitly enabling fast-isel should override implicitly enabled
     706             :   // global-isel.
     707       18804 :   if (EnableGlobalISelOption == cl::BOU_TRUE ||
     708       18674 :       (EnableGlobalISelOption == cl::BOU_UNSET &&
     709       18753 :        TM->Options.EnableGlobalISel && EnableFastISelOption != cl::BOU_TRUE)) {
     710         154 :     TM->setFastISel(false);
     711             : 
     712         154 :     if (addIRTranslator())
     713             :       return true;
     714             : 
     715         154 :     addPreLegalizeMachineIR();
     716             : 
     717         154 :     if (addLegalizeMachineIR())
     718             :       return true;
     719             : 
     720             :     // Before running the register bank selector, ask the target if it
     721             :     // wants to run some passes.
     722         154 :     addPreRegBankSelect();
     723             : 
     724         154 :     if (addRegBankSelect())
     725             :       return true;
     726             : 
     727         154 :     addPreGlobalInstructionSelect();
     728             : 
     729         154 :     if (addGlobalInstructionSelect())
     730             :       return true;
     731             : 
     732             :     // Pass to reset the MachineFunction if the ISel failed.
     733         308 :     addPass(createResetMachineFunctionPass(
     734         308 :         reportDiagnosticWhenGlobalISelFallback(), isGlobalISelAbortEnabled()));
     735             : 
     736             :     // Provide a fallback path when we do not want to abort on
     737             :     // not-yet-supported input.
     738         154 :     if (!isGlobalISelAbortEnabled() && addInstSelector())
     739             :       return true;
     740             : 
     741       18650 :   } else if (addInstSelector())
     742             :     return true;
     743             : 
     744             :   return false;
     745             : }
     746             : 
     747       18804 : bool TargetPassConfig::addISelPasses() {
     748       18804 :   if (TM->Options.EmulatedTLS)
     749         320 :     addPass(createLowerEmuTLSPass());
     750             : 
     751       18804 :   addPass(createPreISelIntrinsicLoweringPass());
     752       37608 :   addPass(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
     753       18804 :   addIRPasses();
     754       18804 :   addCodeGenPrepare();
     755       18804 :   addPassesToHandleExceptions();
     756       18804 :   addISelPrepare();
     757             : 
     758       18804 :   return addCoreISelPasses();
     759             : }
     760             : 
     761             : /// -regalloc=... command line option.
     762           0 : static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
     763             : static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
     764             :                RegisterPassParser<RegisterRegAlloc>>
     765      245058 :     RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
     766      163372 :              cl::desc("Register allocator to use"));
     767             : 
     768             : /// Add the complete set of target-independent postISel code generator passes.
     769             : ///
     770             : /// This can be read as the standard order of major LLVM CodeGen stages. Stages
     771             : /// with nontrivial configuration or multiple passes are broken out below in
     772             : /// add%Stage routines.
     773             : ///
     774             : /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
     775             : /// addPre/Post methods with empty header implementations allow injecting
     776             : /// target-specific fixups just before or after major stages. Additionally,
     777             : /// targets have the flexibility to change pass order within a stage by
     778             : /// overriding default implementation of add%Stage routines below. Each
     779             : /// technique has maintainability tradeoffs because alternate pass orders are
     780             : /// not well supported. addPre/Post works better if the target pass is easily
     781             : /// tied to a common pass. But if it has subtle dependencies on multiple passes,
     782             : /// the target should override the stage instead.
     783             : ///
     784             : /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
     785             : /// before/after any target-independent pass. But it's currently overkill.
     786       18804 : void TargetPassConfig::addMachinePasses() {
     787       18804 :   AddingMachinePasses = true;
     788             : 
     789             :   // Insert a machine instr printer pass after the specified pass.
     790             :   if (!StringRef(PrintMachineInstrs.getValue()).equals("") &&
     791             :       !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) {
     792          21 :     const PassRegistry *PR = PassRegistry::getPassRegistry();
     793          21 :     const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
     794          21 :     const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
     795             :     assert (TPI && IPI && "Pass ID not registered!");
     796          21 :     const char *TID = (const char *)(TPI->getTypeInfo());
     797          21 :     const char *IID = (const char *)(IPI->getTypeInfo());
     798          21 :     insertPass(TID, IID);
     799             :   }
     800             : 
     801             :   // Print the instruction selected machine code...
     802       37608 :   printAndVerify("After Instruction Selection");
     803             : 
     804             :   // Expand pseudo-instructions emitted by ISel.
     805       18804 :   addPass(&ExpandISelPseudosID);
     806             : 
     807             :   // Add passes that optimize machine instructions in SSA form.
     808       18804 :   if (getOptLevel() != CodeGenOpt::None) {
     809       17402 :     addMachineSSAOptimization();
     810             :   } else {
     811             :     // If the target requests it, assign local variables to stack slots relative
     812             :     // to one another and simplify frame index references where possible.
     813        1402 :     addPass(&LocalStackSlotAllocationID, false);
     814             :   }
     815             : 
     816       18804 :   if (TM->Options.EnableIPRA)
     817        1677 :     addPass(createRegUsageInfoPropPass());
     818             : 
     819             :   // Run pre-ra passes.
     820       18804 :   addPreRegAlloc();
     821             : 
     822             :   // Run register allocation and passes that are tightly coupled with it,
     823             :   // including phi elimination and scheduling.
     824       18804 :   if (getOptimizeRegAlloc())
     825       17388 :     addOptimizedRegAlloc(createRegAllocPass(true));
     826             :   else {
     827        1416 :     if (RegAlloc != &useDefaultRegisterAllocator &&
     828             :         RegAlloc != &createFastRegisterAllocator)
     829           0 :       report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
     830        1416 :     addFastRegAlloc(createRegAllocPass(false));
     831             :   }
     832             : 
     833             :   // Run post-ra passes.
     834       18804 :   addPostRegAlloc();
     835             : 
     836             :   // Insert prolog/epilog code.  Eliminate abstract frame index references...
     837       18804 :   if (getOptLevel() != CodeGenOpt::None)
     838       17402 :     addPass(&ShrinkWrapID);
     839             : 
     840             :   // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
     841             :   // do so if it hasn't been disabled, substituted, or overridden.
     842       18804 :   if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
     843       18567 :       addPass(createPrologEpilogInserterPass());
     844             : 
     845             :   /// Add passes that optimize machine instructions after register allocation.
     846       18804 :   if (getOptLevel() != CodeGenOpt::None)
     847       17402 :     addMachineLateOptimization();
     848             : 
     849             :   // Expand pseudo instructions before second scheduling pass.
     850       18804 :   addPass(&ExpandPostRAPseudosID);
     851             : 
     852             :   // Run pre-sched2 passes.
     853       18804 :   addPreSched2();
     854             : 
     855       18804 :   if (EnableImplicitNullChecks)
     856           4 :     addPass(&ImplicitNullChecksID);
     857             : 
     858             :   // Second pass scheduler.
     859             :   // Let Target optionally insert this pass by itself at some other
     860             :   // point.
     861       36206 :   if (getOptLevel() != CodeGenOpt::None &&
     862       17402 :       !TM->targetSchedulesPostRAScheduling()) {
     863       16596 :     if (MISchedPostRA)
     864           2 :       addPass(&PostMachineSchedulerID);
     865             :     else
     866       16594 :       addPass(&PostRASchedulerID);
     867             :   }
     868             : 
     869             :   // GC
     870       18804 :   if (addGCPasses()) {
     871       16844 :     if (PrintGCInfo)
     872           0 :       addPass(createGCInfoPrinter(dbgs()), false, false);
     873             :   }
     874             : 
     875             :   // Basic block placement.
     876       18804 :   if (getOptLevel() != CodeGenOpt::None)
     877       17402 :     addBlockPlacement();
     878             : 
     879       18804 :   addPreEmitPass();
     880             : 
     881       18804 :   if (TM->Options.EnableIPRA)
     882             :     // Collect register usage information and produce a register mask of
     883             :     // clobbered registers, to be used to optimize call sites.
     884        1677 :     addPass(createRegUsageInfoCollector());
     885             : 
     886       18804 :   addPass(&FuncletLayoutID, false);
     887             : 
     888       18804 :   addPass(&StackMapLivenessID, false);
     889       18804 :   addPass(&LiveDebugValuesID, false);
     890             : 
     891             :   // Insert before XRay Instrumentation.
     892       18804 :   addPass(&FEntryInserterID, false);
     893             : 
     894       18804 :   addPass(&XRayInstrumentationID, false);
     895       18804 :   addPass(&PatchableFunctionID, false);
     896             : 
     897       18804 :   if (EnableMachineOutliner)
     898          16 :     PM->add(createMachineOutlinerPass(EnableLinkOnceODROutlining));
     899             : 
     900             :   // Add passes that directly emit MI after all other MI passes.
     901       18804 :   addPreEmitPass2();
     902             : 
     903       18804 :   AddingMachinePasses = false;
     904       18804 : }
     905             : 
     906             : /// Add passes that optimize machine instructions in SSA form.
     907       17192 : void TargetPassConfig::addMachineSSAOptimization() {
     908             :   // Pre-ra tail duplication.
     909       17192 :   addPass(&EarlyTailDuplicateID);
     910             : 
     911             :   // Optimize PHIs before DCE: removing dead PHI cycles may make more
     912             :   // instructions dead.
     913       17192 :   addPass(&OptimizePHIsID, false);
     914             : 
     915             :   // This pass merges large allocas. StackSlotColoring is a different pass
     916             :   // which merges spill slots.
     917       17192 :   addPass(&StackColoringID, false);
     918             : 
     919             :   // If the target requests it, assign local variables to stack slots relative
     920             :   // to one another and simplify frame index references where possible.
     921       17192 :   addPass(&LocalStackSlotAllocationID, false);
     922             : 
     923             :   // With optimization, dead code should already be eliminated. However
     924             :   // there is one known exception: lowered code for arguments that are only
     925             :   // used by tail calls, where the tail calls reuse the incoming stack
     926             :   // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
     927       17192 :   addPass(&DeadMachineInstructionElimID);
     928             : 
     929             :   // Allow targets to insert passes that improve instruction level parallelism,
     930             :   // like if-conversion. Such passes will typically need dominator trees and
     931             :   // loop info, just like LICM and CSE below.
     932       17192 :   addILPOpts();
     933             : 
     934       17192 :   addPass(&EarlyMachineLICMID, false);
     935       17192 :   addPass(&MachineCSEID, false);
     936             : 
     937       17192 :   addPass(&MachineSinkingID);
     938             : 
     939       17192 :   addPass(&PeepholeOptimizerID);
     940             :   // Clean-up the dead code that may have been generated by peephole
     941             :   // rewriting.
     942       17192 :   addPass(&DeadMachineInstructionElimID);
     943       17192 : }
     944             : 
     945             : //===---------------------------------------------------------------------===//
     946             : /// Register Allocation Pass Configuration
     947             : //===---------------------------------------------------------------------===//
     948             : 
     949       18804 : bool TargetPassConfig::getOptimizeRegAlloc() const {
     950       18804 :   switch (OptimizeRegAlloc) {
     951       18766 :   case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
     952             :   case cl::BOU_TRUE:  return true;
     953          26 :   case cl::BOU_FALSE: return false;
     954             :   }
     955           0 :   llvm_unreachable("Invalid optimize-regalloc state");
     956             : }
     957             : 
     958             : /// RegisterRegAlloc's global Registry tracks allocator registration.
     959             : MachinePassRegistry RegisterRegAlloc::Registry;
     960             : 
     961             : /// A dummy default pass factory indicates whether the register allocator is
     962             : /// overridden on the command line.
     963             : static llvm::once_flag InitializeDefaultRegisterAllocatorFlag;
     964             : 
     965             : static RegisterRegAlloc
     966       81686 : defaultRegAlloc("default",
     967             :                 "pick register allocator based on -O option",
     968             :                 useDefaultRegisterAllocator);
     969             : 
     970       18529 : static void initializeDefaultRegisterAllocatorOnce() {
     971             :   RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
     972             : 
     973       18529 :   if (!Ctor) {
     974             :     Ctor = RegAlloc;
     975             :     RegisterRegAlloc::setDefault(RegAlloc);
     976             :   }
     977       18529 : }
     978             : 
     979             : /// Instantiate the default register allocator pass for this target for either
     980             : /// the optimized or unoptimized allocation path. This will be added to the pass
     981             : /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
     982             : /// in the optimized case.
     983             : ///
     984             : /// A target that uses the standard regalloc pass order for fast or optimized
     985             : /// allocation may still override this for per-target regalloc
     986             : /// selection. But -regalloc=... always takes precedence.
     987       18462 : FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
     988       18462 :   if (Optimized)
     989       17113 :     return createGreedyRegisterAllocator();
     990             :   else
     991        1349 :     return createFastRegisterAllocator();
     992             : }
     993             : 
     994             : /// Find and instantiate the register allocation pass requested by this target
     995             : /// at the current optimization level.  Different register allocators are
     996             : /// defined as separate passes because they may require different analysis.
     997             : ///
     998             : /// This helper ensures that the regalloc= option is always available,
     999             : /// even for targets that override the default allocator.
    1000             : ///
    1001             : /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
    1002             : /// this can be folded into addPass.
    1003       18804 : FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
    1004             :   // Initialize the global default.
    1005             :   llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
    1006             :                   initializeDefaultRegisterAllocatorOnce);
    1007             : 
    1008             :   RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
    1009       18804 :   if (Ctor != useDefaultRegisterAllocator)
    1010         105 :     return Ctor();
    1011             : 
    1012             :   // With no -regalloc= override, ask the target for a regalloc pass.
    1013       18699 :   return createTargetRegisterAllocator(Optimized);
    1014             : }
    1015             : 
    1016             : /// Return true if the default global register allocator is in use and
    1017             : /// has not be overriden on the command line with '-regalloc=...'
    1018         967 : bool TargetPassConfig::usingDefaultRegAlloc() const {
    1019         967 :   return RegAlloc.getNumOccurrences() == 0;
    1020             : }
    1021             : 
    1022             : /// Add the minimum set of target-independent passes that are required for
    1023             : /// register allocation. No coalescing or scheduling.
    1024        1389 : void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
    1025        1389 :   addPass(&PHIEliminationID, false);
    1026        1389 :   addPass(&TwoAddressInstructionPassID, false);
    1027             : 
    1028        1389 :   if (RegAllocPass)
    1029        1389 :     addPass(RegAllocPass);
    1030        1389 : }
    1031             : 
    1032             : /// Add standard target-independent passes that are tightly coupled with
    1033             : /// optimized register allocation, including coalescing, machine instruction
    1034             : /// scheduling, and register allocation itself.
    1035       17178 : void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
    1036       17178 :   addPass(&DetectDeadLanesID, false);
    1037             : 
    1038       17178 :   addPass(&ProcessImplicitDefsID, false);
    1039             : 
    1040             :   // LiveVariables currently requires pure SSA form.
    1041             :   //
    1042             :   // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
    1043             :   // LiveVariables can be removed completely, and LiveIntervals can be directly
    1044             :   // computed. (We still either need to regenerate kill flags after regalloc, or
    1045             :   // preferably fix the scavenger to not depend on them).
    1046       17178 :   addPass(&LiveVariablesID, false);
    1047             : 
    1048             :   // Edge splitting is smarter with machine loop info.
    1049       17178 :   addPass(&MachineLoopInfoID, false);
    1050       17178 :   addPass(&PHIEliminationID, false);
    1051             : 
    1052             :   // Eventually, we want to run LiveIntervals before PHI elimination.
    1053       17178 :   if (EarlyLiveIntervals)
    1054           0 :     addPass(&LiveIntervalsID, false);
    1055             : 
    1056       17178 :   addPass(&TwoAddressInstructionPassID, false);
    1057       17178 :   addPass(&RegisterCoalescerID);
    1058             : 
    1059             :   // The machine scheduler may accidentally create disconnected components
    1060             :   // when moving subregister definitions around, avoid this by splitting them to
    1061             :   // separate vregs before. Splitting can also improve reg. allocation quality.
    1062       17178 :   addPass(&RenameIndependentSubregsID);
    1063             : 
    1064             :   // PreRA instruction scheduling.
    1065       17178 :   addPass(&MachineSchedulerID);
    1066             : 
    1067       17178 :   if (RegAllocPass) {
    1068             :     // Add the selected register allocation pass.
    1069       17178 :     addPass(RegAllocPass);
    1070             : 
    1071             :     // Allow targets to change the register assignments before rewriting.
    1072       17178 :     addPreRewrite();
    1073             : 
    1074             :     // Finally rewrite virtual registers.
    1075       17178 :     addPass(&VirtRegRewriterID);
    1076             : 
    1077             :     // Perform stack slot coloring and post-ra machine LICM.
    1078             :     //
    1079             :     // FIXME: Re-enable coloring with register when it's capable of adding
    1080             :     // kill markers.
    1081       17178 :     addPass(&StackSlotColoringID);
    1082             : 
    1083             :     // Run post-ra machine LICM to hoist reloads / remats.
    1084             :     //
    1085             :     // FIXME: can this move into MachineLateOptimization?
    1086       17178 :     addPass(&MachineLICMID);
    1087             :   }
    1088       17178 : }
    1089             : 
    1090             : //===---------------------------------------------------------------------===//
    1091             : /// Post RegAlloc Pass Configuration
    1092             : //===---------------------------------------------------------------------===//
    1093             : 
    1094             : /// Add passes that optimize machine instructions after register allocation.
    1095       17402 : void TargetPassConfig::addMachineLateOptimization() {
    1096             :   // Branch folding must be run after regalloc and prolog/epilog insertion.
    1097       17402 :   addPass(&BranchFolderPassID);
    1098             : 
    1099             :   // Tail duplication.
    1100             :   // Note that duplicating tail just increases code size and degrades
    1101             :   // performance for targets that require Structured Control Flow.
    1102             :   // In addition it can also make CFG irreducible. Thus we disable it.
    1103       34804 :   if (!TM->requiresStructuredCFG())
    1104       17129 :     addPass(&TailDuplicateID);
    1105             : 
    1106             :   // Copy propagation.
    1107       17402 :   addPass(&MachineCopyPropagationID);
    1108       17402 : }
    1109             : 
    1110             : /// Add standard GC passes.
    1111       16844 : bool TargetPassConfig::addGCPasses() {
    1112       16844 :   addPass(&GCMachineCodeAnalysisID, false);
    1113       16844 :   return true;
    1114             : }
    1115             : 
    1116             : /// Add standard basic block placement passes.
    1117       17402 : void TargetPassConfig::addBlockPlacement() {
    1118       17402 :   if (addPass(&MachineBlockPlacementID)) {
    1119             :     // Run a separate pass to collect block placement statistics.
    1120       17382 :     if (EnableBlockPlacementStats)
    1121           0 :       addPass(&MachineBlockPlacementStatsID);
    1122             :   }
    1123       17402 : }
    1124             : 
    1125             : //===---------------------------------------------------------------------===//
    1126             : /// GlobalISel Configuration
    1127             : //===---------------------------------------------------------------------===//
    1128         481 : bool TargetPassConfig::isGlobalISelAbortEnabled() const {
    1129         481 :   if (EnableGlobalISelAbort.getNumOccurrences() > 0)
    1130         203 :     return EnableGlobalISelAbort == 1;
    1131             : 
    1132             :   // When no abort behaviour is specified, we don't abort if the target says
    1133             :   // that GISel is enabled.
    1134         278 :   return !TM->Options.EnableGlobalISel;
    1135             : }
    1136             : 
    1137         154 : bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
    1138         154 :   return EnableGlobalISelAbort == 2;
    1139      245058 : }

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