LCOV - code coverage report
Current view: top level - lib/CodeGen - TargetRegisterInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 132 165 80.0 %
Date: 2018-02-23 15:42:53 Functions: 21 26 80.8 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements the TargetRegisterInfo interface.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      15             : #include "llvm/ADT/ArrayRef.h"
      16             : #include "llvm/ADT/BitVector.h"
      17             : #include "llvm/ADT/STLExtras.h"
      18             : #include "llvm/ADT/StringExtras.h"
      19             : #include "llvm/CodeGen/MachineFrameInfo.h"
      20             : #include "llvm/CodeGen/MachineFunction.h"
      21             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      22             : #include "llvm/CodeGen/MachineValueType.h"
      23             : #include "llvm/CodeGen/TargetFrameLowering.h"
      24             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      25             : #include "llvm/CodeGen/VirtRegMap.h"
      26             : #include "llvm/IR/Attributes.h"
      27             : #include "llvm/IR/Function.h"
      28             : #include "llvm/MC/MCRegisterInfo.h"
      29             : #include "llvm/Support/Compiler.h"
      30             : #include "llvm/Support/Debug.h"
      31             : #include "llvm/Support/MathExtras.h"
      32             : #include "llvm/Support/Printable.h"
      33             : #include "llvm/Support/raw_ostream.h"
      34             : #include <cassert>
      35             : #include <utility>
      36             : 
      37             : #define DEBUG_TYPE "target-reg-info"
      38             : 
      39             : using namespace llvm;
      40             : 
      41       31124 : TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
      42             :                              regclass_iterator RCB, regclass_iterator RCE,
      43             :                              const char *const *SRINames,
      44             :                              const LaneBitmask *SRILaneMasks,
      45             :                              LaneBitmask SRICoveringLanes,
      46             :                              const RegClassInfo *const RCIs,
      47       31124 :                              unsigned Mode)
      48             :   : InfoDesc(ID), SubRegIndexNames(SRINames),
      49             :     SubRegIndexLaneMasks(SRILaneMasks),
      50             :     RegClassBegin(RCB), RegClassEnd(RCE),
      51             :     CoveringLanes(SRICoveringLanes),
      52       31124 :     RCInfos(RCIs), HwMode(Mode) {
      53       31124 : }
      54             : 
      55             : TargetRegisterInfo::~TargetRegisterInfo() = default;
      56             : 
      57     1331934 : void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet, unsigned Reg)
      58             :     const {
      59     6852097 :   for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
      60             :     RegisterSet.set(*AI);
      61     1331934 : }
      62             : 
      63           0 : bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,
      64             :     ArrayRef<MCPhysReg> Exceptions) const {
      65             :   // Check that all super registers of reserved regs are reserved as well.
      66           0 :   BitVector Checked(getNumRegs());
      67           0 :   for (unsigned Reg : RegisterSet.set_bits()) {
      68           0 :     if (Checked[Reg])
      69           0 :       continue;
      70           0 :     for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
      71           0 :       if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
      72           0 :         dbgs() << "Error: Super register " << printReg(*SR, this)
      73           0 :                << " of reserved register " << printReg(Reg, this)
      74           0 :                << " is not reserved.\n";
      75             :         return false;
      76             :       }
      77             : 
      78             :       // We transitively check superregs. So we can remember this for later
      79             :       // to avoid compiletime explosion in deep register hierarchies.
      80             :       Checked.set(*SR);
      81             :     }
      82             :   }
      83           0 :   return true;
      84             : }
      85             : 
      86             : namespace llvm {
      87             : 
      88      431440 : Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI,
      89             :                    unsigned SubIdx) {
      90     1663050 :   return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
      91      431440 :     if (!Reg)
      92        6882 :       OS << "$noreg";
      93      424558 :     else if (TargetRegisterInfo::isStackSlot(Reg))
      94           0 :       OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
      95      424558 :     else if (TargetRegisterInfo::isVirtualRegister(Reg))
      96             :       OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
      97      375612 :     else if (!TRI)
      98           1 :       OS << '$' << "physreg" << Reg;
      99      375611 :     else if (Reg < TRI->getNumRegs()) {
     100             :       OS << '$';
     101      375611 :       printLowerCase(TRI->getName(Reg), OS);
     102             :     } else
     103           0 :       llvm_unreachable("Register kind is unsupported.");
     104             : 
     105      431440 :     if (SubIdx) {
     106           0 :       if (TRI)
     107           0 :         OS << ':' << TRI->getSubRegIndexName(SubIdx);
     108             :       else
     109           0 :         OS << ":sub(" << SubIdx << ')';
     110             :     }
     111      862880 :   });
     112             : }
     113             : 
     114           0 : Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
     115           0 :   return Printable([Unit, TRI](raw_ostream &OS) {
     116             :     // Generic printout when TRI is missing.
     117           0 :     if (!TRI) {
     118           0 :       OS << "Unit~" << Unit;
     119             :       return;
     120             :     }
     121             : 
     122             :     // Check for invalid register units.
     123           0 :     if (Unit >= TRI->getNumRegUnits()) {
     124           0 :       OS << "BadUnit~" << Unit;
     125             :       return;
     126             :     }
     127             : 
     128             :     // Normal units have at least one root.
     129           0 :     MCRegUnitRootIterator Roots(Unit, TRI);
     130             :     assert(Roots.isValid() && "Unit has no roots.");
     131           0 :     OS << TRI->getName(*Roots);
     132           0 :     for (++Roots; Roots.isValid(); ++Roots)
     133           0 :       OS << '~' << TRI->getName(*Roots);
     134           0 :   });
     135             : }
     136             : 
     137           0 : Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
     138           0 :   return Printable([Unit, TRI](raw_ostream &OS) {
     139           0 :     if (TRI && TRI->isVirtualRegister(Unit)) {
     140             :       OS << '%' << TargetRegisterInfo::virtReg2Index(Unit);
     141             :     } else {
     142           0 :       OS << printRegUnit(Unit, TRI);
     143             :     }
     144           0 :   });
     145             : }
     146             : 
     147       38616 : Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo,
     148             :                               const TargetRegisterInfo *TRI) {
     149       62246 :   return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
     150       28398 :     if (RegInfo.getRegClassOrNull(Reg))
     151       70890 :       OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
     152       10218 :     else if (RegInfo.getRegBankOrNull(Reg))
     153        6198 :       OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
     154             :     else {
     155       12920 :       OS << "_";
     156             :       assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
     157             :              "Generic registers must have a valid type");
     158             :     }
     159       77232 :   });
     160             : }
     161             : 
     162             : } // end namespace llvm
     163             : 
     164             : /// getAllocatableClass - Return the maximal subclass of the given register
     165             : /// class that is alloctable, or NULL.
     166             : const TargetRegisterClass *
     167     4760223 : TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
     168     8925572 :   if (!RC || RC->isAllocatable())
     169             :     return RC;
     170             : 
     171       41767 :   for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
     172             :        ++It) {
     173       14211 :     const TargetRegisterClass *SubRC = getRegClass(It.getID());
     174       28422 :     if (SubRC->isAllocatable())
     175         268 :       return SubRC;
     176             :   }
     177       13644 :   return nullptr;
     178             : }
     179             : 
     180             : /// getMinimalPhysRegClass - Returns the Register Class of a physical
     181             : /// register of the given type, picking the most sub register class of
     182             : /// the right type that contains this physreg.
     183             : const TargetRegisterClass *
     184      676587 : TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, MVT VT) const {
     185             :   assert(isPhysicalRegister(reg) && "reg must be a physical register");
     186             : 
     187             :   // Pick the most sub register class of the right type that contains
     188             :   // this physreg.
     189             :   const TargetRegisterClass* BestRC = nullptr;
     190   103519803 :   for (const TargetRegisterClass* RC : regclasses()) {
     191    48595769 :     if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
     192    79059382 :         RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
     193             :       BestRC = RC;
     194             :   }
     195             : 
     196             :   assert(BestRC && "Couldn't find the register class");
     197      676587 :   return BestRC;
     198             : }
     199             : 
     200             : /// getAllocatableSetForRC - Toggle the bits that represent allocatable
     201             : /// registers for the specific register class.
     202       13933 : static void getAllocatableSetForRC(const MachineFunction &MF,
     203             :                                    const TargetRegisterClass *RC, BitVector &R){
     204             :   assert(RC->isAllocatable() && "invalid for nonallocatable sets");
     205             :   ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF);
     206      917283 :   for (unsigned i = 0; i != Order.size(); ++i)
     207      451675 :     R.set(Order[i]);
     208       13933 : }
     209             : 
     210       13361 : BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
     211             :                                           const TargetRegisterClass *RC) const {
     212       13361 :   BitVector Allocatable(getNumRegs());
     213       13361 :   if (RC) {
     214             :     // A register class with no allocatable subclass returns an empty set.
     215       13350 :     const TargetRegisterClass *SubClass = getAllocatableClass(RC);
     216       13350 :     if (SubClass)
     217       13350 :       getAllocatableSetForRC(MF, SubClass, Allocatable);
     218             :   } else {
     219        1617 :     for (const TargetRegisterClass *C : regclasses())
     220        1606 :       if (C->isAllocatable())
     221         583 :         getAllocatableSetForRC(MF, C, Allocatable);
     222             :   }
     223             : 
     224             :   // Mask out the reserved registers
     225       13361 :   BitVector Reserved = getReservedRegs(MF);
     226       13361 :   Allocatable &= Reserved.flip();
     227             : 
     228       13361 :   return Allocatable;
     229             : }
     230             : 
     231             : static inline
     232     8562845 : const TargetRegisterClass *firstCommonClass(const uint32_t *A,
     233             :                                             const uint32_t *B,
     234             :                                             const TargetRegisterInfo *TRI,
     235             :                                             const MVT::SimpleValueType SVT =
     236             :                                             MVT::SimpleValueType::Any) {
     237             :   const MVT VT(SVT);
     238    48265495 :   for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
     239    22522629 :     if (unsigned Common = *A++ & *B++) {
     240             :       const TargetRegisterClass *RC =
     241     2671308 :           TRI->getRegClass(I + countTrailingZeros(Common));
     242     2673254 :       if (SVT == MVT::SimpleValueType::Any || TRI->isTypeLegalForClass(*RC, VT))
     243             :         return RC;
     244             :     }
     245             :   return nullptr;
     246             : }
     247             : 
     248             : const TargetRegisterClass *
     249    13273567 : TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
     250             :                                       const TargetRegisterClass *B,
     251             :                                       const MVT::SimpleValueType SVT) const {
     252             :   // First take care of the trivial cases.
     253    13273567 :   if (A == B)
     254             :     return A;
     255     6654252 :   if (!A || !B)
     256             :     return nullptr;
     257             : 
     258             :   // Register classes are ordered topologically, so the largest common
     259             :   // sub-class it the common sub-class with the smallest ID.
     260     6654252 :   return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this, SVT);
     261             : }
     262             : 
     263             : const TargetRegisterClass *
     264     1614362 : TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
     265             :                                              const TargetRegisterClass *B,
     266             :                                              unsigned Idx) const {
     267             :   assert(A && B && "Missing register class");
     268             :   assert(Idx && "Bad sub-register index");
     269             : 
     270             :   // Find Idx in the list of super-register indices.
     271     3199165 :   for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
     272     3194774 :     if (RCI.getSubReg() == Idx)
     273             :       // The bit mask contains all register classes that are projected into B
     274             :       // by Idx. Find a class that is also a sub-class of A.
     275     1609971 :       return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
     276             :   return nullptr;
     277             : }
     278             : 
     279       46830 : const TargetRegisterClass *TargetRegisterInfo::
     280             : getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
     281             :                        const TargetRegisterClass *RCB, unsigned SubB,
     282             :                        unsigned &PreA, unsigned &PreB) const {
     283             :   assert(RCA && SubA && RCB && SubB && "Invalid arguments");
     284             : 
     285             :   // Search all pairs of sub-register indices that project into RCA and RCB
     286             :   // respectively. This is quadratic, but usually the sets are very small. On
     287             :   // most targets like X86, there will only be a single sub-register index
     288             :   // (e.g., sub_16bit projecting into GR16).
     289             :   //
     290             :   // The worst case is a register class like DPR on ARM.
     291             :   // We have indices dsub_0..dsub_7 projecting into that class.
     292             :   //
     293             :   // It is very common that one register class is a sub-register of the other.
     294             :   // Arrange for RCA to be the larger register so the answer will be found in
     295             :   // the first iteration. This makes the search linear for the most common
     296             :   // case.
     297             :   const TargetRegisterClass *BestRC = nullptr;
     298             :   unsigned *BestPreA = &PreA;
     299             :   unsigned *BestPreB = &PreB;
     300       46830 :   if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
     301             :     std::swap(RCA, RCB);
     302             :     std::swap(SubA, SubB);
     303             :     std::swap(BestPreA, BestPreB);
     304             :   }
     305             : 
     306             :   // Also terminate the search one we have found a register class as small as
     307             :   // RCA.
     308             :   unsigned MinSize = getRegSizeInBits(*RCA);
     309             : 
     310       63672 :   for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
     311             :     unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
     312      315464 :     for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
     313             :       // Check if a common super-register class exists for this index pair.
     314             :       const TargetRegisterClass *RC =
     315      298622 :         firstCommonClass(IA.getMask(), IB.getMask(), this);
     316      545414 :       if (!RC || getRegSizeInBits(*RC) < MinSize)
     317       51830 :         continue;
     318             : 
     319             :       // The indexes must compose identically: PreA+SubA == PreB+SubB.
     320             :       unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
     321      246792 :       if (FinalA != FinalB)
     322      189496 :         continue;
     323             : 
     324             :       // Is RC a better candidate than BestRC?
     325       79289 :       if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))
     326       10988 :         continue;
     327             : 
     328             :       // Yes, RC is the smallest super-register seen so far.
     329             :       BestRC = RC;
     330       46308 :       *BestPreA = IA.getSubReg();
     331       46308 :       *BestPreB = IB.getSubReg();
     332             : 
     333             :       // Bail early if we reached MinSize. We won't find a better candidate.
     334       46308 :       if (getRegSizeInBits(*BestRC) == MinSize)
     335             :         return BestRC;
     336             :     }
     337             :   }
     338        1591 :   return BestRC;
     339             : }
     340             : 
     341             : /// \brief Check if the registers defined by the pair (RegisterClass, SubReg)
     342             : /// share the same register file.
     343      126455 : static bool shareSameRegisterFile(const TargetRegisterInfo &TRI,
     344             :                                   const TargetRegisterClass *DefRC,
     345             :                                   unsigned DefSubReg,
     346             :                                   const TargetRegisterClass *SrcRC,
     347             :                                   unsigned SrcSubReg) {
     348             :   // Same register class.
     349      126455 :   if (DefRC == SrcRC)
     350             :     return true;
     351             : 
     352             :   // Both operands are sub registers. Check if they share a register class.
     353             :   unsigned SrcIdx, DefIdx;
     354       96729 :   if (SrcSubReg && DefSubReg) {
     355           2 :     return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
     356           2 :                                       SrcIdx, DefIdx) != nullptr;
     357             :   }
     358             : 
     359             :   // At most one of the register is a sub register, make it Src to avoid
     360             :   // duplicating the test.
     361       96727 :   if (!SrcSubReg) {
     362             :     std::swap(DefSubReg, SrcSubReg);
     363             :     std::swap(DefRC, SrcRC);
     364             :   }
     365             : 
     366             :   // One of the register is a sub register, check if we can get a superclass.
     367       96727 :   if (SrcSubReg)
     368       76404 :     return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
     369             : 
     370             :   // Plain copy.
     371       20323 :   return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
     372             : }
     373             : 
     374      126455 : bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
     375             :                                               unsigned DefSubReg,
     376             :                                               const TargetRegisterClass *SrcRC,
     377             :                                               unsigned SrcSubReg) const {
     378             :   // If this source does not incur a cross register bank copy, use it.
     379      126455 :   return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
     380             : }
     381             : 
     382             : // Compute target-independent register allocator hints to help eliminate copies.
     383             : bool
     384     1539661 : TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
     385             :                                           ArrayRef<MCPhysReg> Order,
     386             :                                           SmallVectorImpl<MCPhysReg> &Hints,
     387             :                                           const MachineFunction &MF,
     388             :                                           const VirtRegMap *VRM,
     389             :                                           const LiveRegMatrix *Matrix) const {
     390     1539661 :   const MachineRegisterInfo &MRI = MF.getRegInfo();
     391             :   const std::pair<unsigned, SmallVector<unsigned, 4>> &Hints_MRI =
     392             :     MRI.getRegAllocationHints(VirtReg);
     393             : 
     394             :   // First hint may be a target hint.
     395     1539661 :   bool Skip = (Hints_MRI.first != 0);
     396     3137155 :   for (auto Reg : Hints_MRI.second) {
     397      798747 :     if (Skip) {
     398             :       Skip = false;
     399      102870 :       continue;
     400             :     }
     401             : 
     402             :     // Target-independent hints are either a physical or a virtual register.
     403      798747 :     unsigned Phys = Reg;
     404     1597494 :     if (VRM && isVirtualRegister(Phys))
     405      168519 :       Phys = VRM->getPhys(Phys);
     406             : 
     407             :     // Check that Phys is a valid hint in VirtReg's register class.
     408     1597494 :     if (!isPhysicalRegister(Phys))
     409       79920 :       continue;
     410      718827 :     if (MRI.isReserved(Phys))
     411           0 :       continue;
     412             :     // Check that Phys is in the allocation order. We shouldn't heed hints
     413             :     // from VirtReg's register class if they aren't in the allocation order. The
     414             :     // target probably has a reason for removing the register.
     415      718827 :     if (!is_contained(Order, Phys))
     416       22950 :       continue;
     417             : 
     418             :     // All clear, tell the register allocator to prefer this register.
     419      695877 :     Hints.push_back(Phys);
     420             :   }
     421     1539661 :   return false;
     422             : }
     423             : 
     424      153071 : bool TargetRegisterInfo::canRealignStack(const MachineFunction &MF) const {
     425      306142 :   return !MF.getFunction().hasFnAttribute("no-realign-stack");
     426             : }
     427             : 
     428     3712918 : bool TargetRegisterInfo::needsStackRealignment(
     429             :     const MachineFunction &MF) const {
     430     3712918 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
     431     3712918 :   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
     432     3712919 :   const Function &F = MF.getFunction();
     433     3712919 :   unsigned StackAlign = TFI->getStackAlignment();
     434     7287090 :   bool requiresRealignment = ((MFI.getMaxAlignment() > StackAlign) ||
     435             :                               F.hasFnAttribute(Attribute::StackAlignment));
     436     3712920 :   if (F.hasFnAttribute("stackrealign") || requiresRealignment) {
     437      142043 :     if (canRealignStack(MF))
     438             :       return true;
     439             :     DEBUG(dbgs() << "Can't realign function's stack: " << F.getName() << "\n");
     440             :   }
     441             :   return false;
     442             : }
     443             : 
     444         299 : bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0,
     445             :                                             const uint32_t *mask1) const {
     446         299 :   unsigned N = (getNumRegs()+31) / 32;
     447        5583 :   for (unsigned I = 0; I < N; ++I)
     448        2667 :     if ((mask0[I] & mask1[I]) != mask0[I])
     449             :       return false;
     450             :   return true;
     451             : }
     452             : 
     453       19017 : unsigned TargetRegisterInfo::getRegSizeInBits(unsigned Reg,
     454             :                                          const MachineRegisterInfo &MRI) const {
     455             :   const TargetRegisterClass *RC{};
     456       19017 :   if (isPhysicalRegister(Reg)) {
     457             :     // The size is not directly available for physical registers.
     458             :     // Instead, we need to access a register class that contains Reg and
     459             :     // get the size of that register class.
     460        8360 :     RC = getMinimalPhysRegClass(Reg);
     461             :   } else {
     462       10657 :     LLT Ty = MRI.getType(Reg);
     463       10657 :     unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
     464             :     // If Reg is not a generic register, query the register class to
     465             :     // get its size.
     466       10630 :     if (RegSize)
     467       10630 :       return RegSize;
     468             :     // Since Reg is not a generic register, it must have a register class.
     469             :     RC = MRI.getRegClass(Reg);
     470             :   }
     471             :   assert(RC && "Unable to deduce the register class");
     472        8387 :   return getRegSizeInBits(*RC);
     473             : }
     474             : 
     475             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
     476             : LLVM_DUMP_METHOD
     477             : void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,
     478             :                                  const TargetRegisterInfo *TRI) {
     479             :   dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
     480             : }
     481             : #endif

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