LCOV - code coverage report
Current view: top level - lib/CodeGen - TargetSubtargetInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 38 46 82.6 %
Date: 2017-09-14 15:23:50 Functions: 9 10 90.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file This file describes the general parts of a Subtarget.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "llvm/Target/TargetSubtargetInfo.h"
      15             : #include "llvm/ADT/Optional.h"
      16             : #include "llvm/CodeGen/MachineInstr.h"
      17             : #include "llvm/CodeGen/TargetSchedule.h"
      18             : #include "llvm/MC/MCInst.h"
      19             : #include "llvm/Support/Format.h"
      20             : #include "llvm/Support/raw_ostream.h"
      21             : #include "llvm/Target/TargetInstrInfo.h"
      22             : #include <string>
      23             : 
      24             : using namespace llvm;
      25             : 
      26       28520 : TargetSubtargetInfo::TargetSubtargetInfo(
      27             :     const Triple &TT, StringRef CPU, StringRef FS,
      28             :     ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
      29             :     const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
      30             :     const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
      31       28520 :     const InstrStage *IS, const unsigned *OC, const unsigned *FP)
      32       28520 :     : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
      33       28520 : }
      34             : 
      35             : TargetSubtargetInfo::~TargetSubtargetInfo() = default;
      36             : 
      37      105819 : bool TargetSubtargetInfo::enableAtomicExpand() const {
      38      105819 :   return true;
      39             : }
      40             : 
      41       62970 : bool TargetSubtargetInfo::enableMachineScheduler() const {
      42       62970 :   return false;
      43             : }
      44             : 
      45      135788 : bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
      46      135788 :   return enableMachineScheduler();
      47             : }
      48             : 
      49      134612 : bool TargetSubtargetInfo::enableRALocalReassignment(
      50             :     CodeGenOpt::Level OptLevel) const {
      51      134612 :   return true;
      52             : }
      53             : 
      54       93301 : bool TargetSubtargetInfo::enablePostRAScheduler() const {
      55       93301 :   return getSchedModel().PostRAScheduler;
      56             : }
      57             : 
      58     3161532 : bool TargetSubtargetInfo::useAA() const {
      59     3161532 :   return false;
      60             : }
      61             : 
      62       17027 : static std::string createSchedInfoStr(unsigned Latency,
      63             :                                      Optional<double> RThroughput) {
      64             :   static const char *SchedPrefix = " sched: [";
      65       17027 :   std::string Comment;
      66       34054 :   raw_string_ostream CS(Comment);
      67       17027 :   if (Latency > 0 && RThroughput.hasValue())
      68       82645 :     CS << SchedPrefix << Latency << format(":%2.2f", RThroughput.getValue())
      69       16529 :        << "]";
      70         498 :   else if (Latency > 0)
      71         306 :     CS << SchedPrefix << Latency << ":?]";
      72         345 :   else if (RThroughput.hasValue())
      73           0 :     CS << SchedPrefix << "?:" << RThroughput.getValue() << "]";
      74       17027 :   CS.flush();
      75       17027 :   return Comment;
      76             : }
      77             : 
      78             : /// Returns string representation of scheduler comment
      79           0 : std::string TargetSubtargetInfo::getSchedInfoStr(const MachineInstr &MI) const {
      80           0 :   if (MI.isPseudo() || MI.isTerminator())
      81             :     return std::string();
      82             :   // We don't cache TSchedModel because it depends on TargetInstrInfo
      83             :   // that could be changed during the compilation
      84           0 :   TargetSchedModel TSchedModel;
      85           0 :   TSchedModel.init(getSchedModel(), this, getInstrInfo());
      86           0 :   unsigned Latency = TSchedModel.computeInstrLatency(&MI);
      87           0 :   Optional<double> RThroughput = TSchedModel.computeInstrRThroughput(&MI);
      88           0 :   return createSchedInfoStr(Latency, RThroughput);
      89             : }
      90             : 
      91             : /// Returns string representation of scheduler comment
      92       17334 : std::string TargetSubtargetInfo::getSchedInfoStr(MCInst const &MCI) const {
      93             :   // We don't cache TSchedModel because it depends on TargetInstrInfo
      94             :   // that could be changed during the compilation
      95       34668 :   TargetSchedModel TSchedModel;
      96       17334 :   TSchedModel.init(getSchedModel(), this, getInstrInfo());
      97             :   unsigned Latency;
      98       17334 :   if (TSchedModel.hasInstrSchedModel())
      99       15820 :     Latency = TSchedModel.computeInstrLatency(MCI.getOpcode());
     100        1514 :   else if (TSchedModel.hasInstrItineraries()) {
     101        1207 :     auto *ItinData = TSchedModel.getInstrItineraries();
     102        1207 :     Latency = ItinData->getStageLatency(
     103        2414 :         getInstrInfo()->get(MCI.getOpcode()).getSchedClass());
     104             :   } else
     105             :     return std::string();
     106             :   Optional<double> RThroughput =
     107       17027 :       TSchedModel.computeInstrRThroughput(MCI.getOpcode());
     108       34054 :   return createSchedInfoStr(Latency, RThroughput);
     109             : }

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