LCOV - code coverage report
Current view: top level - lib/CodeGen - TargetSubtargetInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 41 46 89.1 %
Date: 2018-07-13 00:08:38 Functions: 12 13 92.3 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file This file describes the general parts of a Subtarget.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      15             : #include "llvm/ADT/Optional.h"
      16             : #include "llvm/CodeGen/MachineInstr.h"
      17             : #include "llvm/CodeGen/TargetInstrInfo.h"
      18             : #include "llvm/CodeGen/TargetSchedule.h"
      19             : #include "llvm/MC/MCInst.h"
      20             : #include "llvm/Support/Format.h"
      21             : #include "llvm/Support/raw_ostream.h"
      22             : #include <string>
      23             : 
      24             : using namespace llvm;
      25             : 
      26       37850 : TargetSubtargetInfo::TargetSubtargetInfo(
      27             :     const Triple &TT, StringRef CPU, StringRef FS,
      28             :     ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
      29             :     const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
      30             :     const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
      31       37850 :     const InstrStage *IS, const unsigned *OC, const unsigned *FP)
      32       37850 :     : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
      33       37850 : }
      34             : 
      35             : TargetSubtargetInfo::~TargetSubtargetInfo() = default;
      36             : 
      37      178500 : bool TargetSubtargetInfo::enableAtomicExpand() const {
      38      178500 :   return true;
      39             : }
      40             : 
      41           0 : bool TargetSubtargetInfo::enableIndirectBrExpand() const {
      42           0 :   return false;
      43             : }
      44             : 
      45       44600 : bool TargetSubtargetInfo::enableMachineScheduler() const {
      46       44600 :   return false;
      47             : }
      48             : 
      49      184243 : bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
      50      184243 :   return enableMachineScheduler();
      51             : }
      52             : 
      53      181593 : bool TargetSubtargetInfo::enableRALocalReassignment(
      54             :     CodeGenOpt::Level OptLevel) const {
      55      181593 :   return true;
      56             : }
      57             : 
      58       78241 : bool TargetSubtargetInfo::enableAdvancedRASplitCost() const {
      59       78241 :   return false;
      60             : }
      61             : 
      62      131866 : bool TargetSubtargetInfo::enablePostRAScheduler() const {
      63      131866 :   return getSchedModel().PostRAScheduler;
      64             : }
      65             : 
      66     3085986 : bool TargetSubtargetInfo::useAA() const {
      67     3085986 :   return false;
      68             : }
      69             : 
      70       60468 : static std::string createSchedInfoStr(unsigned Latency, double RThroughput) {
      71             :   static const char *SchedPrefix = " sched: [";
      72             :   std::string Comment;
      73       60468 :   raw_string_ostream CS(Comment);
      74       60468 :   if (RThroughput != 0.0)
      75      181404 :     CS << SchedPrefix << Latency << format(":%2.2f", RThroughput)
      76       60468 :        << "]";
      77             :   else
      78           0 :     CS << SchedPrefix << Latency << ":?]";
      79             :   CS.flush();
      80       60468 :   return Comment;
      81             : }
      82             : 
      83             : /// Returns string representation of scheduler comment
      84           8 : std::string TargetSubtargetInfo::getSchedInfoStr(const MachineInstr &MI) const {
      85          16 :   if (MI.isPseudo() || MI.isTerminator())
      86             :     return std::string();
      87             :   // We don't cache TSchedModel because it depends on TargetInstrInfo
      88             :   // that could be changed during the compilation
      89           8 :   TargetSchedModel TSchedModel;
      90           8 :   TSchedModel.init(this);
      91           8 :   unsigned Latency = TSchedModel.computeInstrLatency(&MI);
      92           8 :   double RThroughput = TSchedModel.computeReciprocalThroughput(&MI);
      93           8 :   return createSchedInfoStr(Latency, RThroughput);
      94             : }
      95             : 
      96             : /// Returns string representation of scheduler comment
      97       63182 : std::string TargetSubtargetInfo::getSchedInfoStr(MCInst const &MCI) const {
      98             :   // We don't cache TSchedModel because it depends on TargetInstrInfo
      99             :   // that could be changed during the compilation
     100       63182 :   TargetSchedModel TSchedModel;
     101       63182 :   TSchedModel.init(this);
     102             :   unsigned Latency;
     103       63182 :   if (TSchedModel.hasInstrSchedModel())
     104       60460 :     Latency = TSchedModel.computeInstrLatency(MCI);
     105        2722 :   else if (TSchedModel.hasInstrItineraries()) {
     106             :     auto *ItinData = TSchedModel.getInstrItineraries();
     107           0 :     Latency = ItinData->getStageLatency(
     108           0 :         getInstrInfo()->get(MCI.getOpcode()).getSchedClass());
     109             :   } else
     110             :     return std::string();
     111       60460 :   double RThroughput = TSchedModel.computeReciprocalThroughput(MCI);
     112       60460 :   return createSchedInfoStr(Latency, RThroughput);
     113             : }
     114             : 
     115        3077 : void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const {
     116        3077 : }

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