LCOV - code coverage report
Current view: top level - lib/CodeGen - TwoAddressInstructionPass.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 582 643 90.5 %
Date: 2018-02-23 15:42:53 Functions: 32 32 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- TwoAddressInstructionPass.cpp - Two-Address instruction pass -------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements the TwoAddress instruction pass which is used
      11             : // by most register allocators. Two-Address instructions are rewritten
      12             : // from:
      13             : //
      14             : //     A = B op C
      15             : //
      16             : // to:
      17             : //
      18             : //     A = B
      19             : //     A op= C
      20             : //
      21             : // Note that if a register allocator chooses to use this pass, that it
      22             : // has to be capable of handling the non-SSA nature of these rewritten
      23             : // virtual registers.
      24             : //
      25             : // It is also worth noting that the duplicate operand of the two
      26             : // address instruction is removed.
      27             : //
      28             : //===----------------------------------------------------------------------===//
      29             : 
      30             : #include "llvm/ADT/DenseMap.h"
      31             : #include "llvm/ADT/SmallPtrSet.h"
      32             : #include "llvm/ADT/SmallSet.h"
      33             : #include "llvm/ADT/SmallVector.h"
      34             : #include "llvm/ADT/Statistic.h"
      35             : #include "llvm/ADT/iterator_range.h"
      36             : #include "llvm/Analysis/AliasAnalysis.h"
      37             : #include "llvm/CodeGen/LiveInterval.h"
      38             : #include "llvm/CodeGen/LiveIntervals.h"
      39             : #include "llvm/CodeGen/LiveVariables.h"
      40             : #include "llvm/CodeGen/MachineBasicBlock.h"
      41             : #include "llvm/CodeGen/MachineFunction.h"
      42             : #include "llvm/CodeGen/MachineFunctionPass.h"
      43             : #include "llvm/CodeGen/MachineInstr.h"
      44             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      45             : #include "llvm/CodeGen/MachineOperand.h"
      46             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      47             : #include "llvm/CodeGen/Passes.h"
      48             : #include "llvm/CodeGen/SlotIndexes.h"
      49             : #include "llvm/CodeGen/TargetInstrInfo.h"
      50             : #include "llvm/CodeGen/TargetOpcodes.h"
      51             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      52             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      53             : #include "llvm/MC/MCInstrDesc.h"
      54             : #include "llvm/MC/MCInstrItineraries.h"
      55             : #include "llvm/Pass.h"
      56             : #include "llvm/Support/CodeGen.h"
      57             : #include "llvm/Support/CommandLine.h"
      58             : #include "llvm/Support/Debug.h"
      59             : #include "llvm/Support/ErrorHandling.h"
      60             : #include "llvm/Support/raw_ostream.h"
      61             : #include "llvm/Target/TargetMachine.h"
      62             : #include <cassert>
      63             : #include <iterator>
      64             : #include <utility>
      65             : 
      66             : using namespace llvm;
      67             : 
      68             : #define DEBUG_TYPE "twoaddressinstruction"
      69             : 
      70             : STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
      71             : STATISTIC(NumCommuted        , "Number of instructions commuted to coalesce");
      72             : STATISTIC(NumAggrCommuted    , "Number of instructions aggressively commuted");
      73             : STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
      74             : STATISTIC(Num3AddrSunk,        "Number of 3-address instructions sunk");
      75             : STATISTIC(NumReSchedUps,       "Number of instructions re-scheduled up");
      76             : STATISTIC(NumReSchedDowns,     "Number of instructions re-scheduled down");
      77             : 
      78             : // Temporary flag to disable rescheduling.
      79             : static cl::opt<bool>
      80       81686 : EnableRescheduling("twoaddr-reschedule",
      81       81686 :                    cl::desc("Coalesce copies by rescheduling (default=true)"),
      82      245058 :                    cl::init(true), cl::Hidden);
      83             : 
      84             : // Limit the number of dataflow edges to traverse when evaluating the benefit
      85             : // of commuting operands.
      86       81686 : static cl::opt<unsigned> MaxDataFlowEdge(
      87      163372 :     "dataflow-edge-limit", cl::Hidden, cl::init(3),
      88       81686 :     cl::desc("Maximum number of dataflow edges to traverse when evaluating "
      89       81686 :              "the benefit of commuting operands"));
      90             : 
      91             : namespace {
      92             : 
      93       56095 : class TwoAddressInstructionPass : public MachineFunctionPass {
      94             :   MachineFunction *MF;
      95             :   const TargetInstrInfo *TII;
      96             :   const TargetRegisterInfo *TRI;
      97             :   const InstrItineraryData *InstrItins;
      98             :   MachineRegisterInfo *MRI;
      99             :   LiveVariables *LV;
     100             :   LiveIntervals *LIS;
     101             :   AliasAnalysis *AA;
     102             :   CodeGenOpt::Level OptLevel;
     103             : 
     104             :   // The current basic block being processed.
     105             :   MachineBasicBlock *MBB;
     106             : 
     107             :   // Keep track the distance of a MI from the start of the current basic block.
     108             :   DenseMap<MachineInstr*, unsigned> DistanceMap;
     109             : 
     110             :   // Set of already processed instructions in the current block.
     111             :   SmallPtrSet<MachineInstr*, 8> Processed;
     112             : 
     113             :   // Set of instructions converted to three-address by target and then sunk
     114             :   // down current basic block.
     115             :   SmallPtrSet<MachineInstr*, 8> SunkInstrs;
     116             : 
     117             :   // A map from virtual registers to physical registers which are likely targets
     118             :   // to be coalesced to due to copies from physical registers to virtual
     119             :   // registers. e.g. v1024 = move r0.
     120             :   DenseMap<unsigned, unsigned> SrcRegMap;
     121             : 
     122             :   // A map from virtual registers to physical registers which are likely targets
     123             :   // to be coalesced to due to copies to physical registers from virtual
     124             :   // registers. e.g. r1 = move v1024.
     125             :   DenseMap<unsigned, unsigned> DstRegMap;
     126             : 
     127             :   bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
     128             :                             MachineBasicBlock::iterator OldPos);
     129             : 
     130             :   bool isRevCopyChain(unsigned FromReg, unsigned ToReg, int Maxlen);
     131             : 
     132             :   bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
     133             : 
     134             :   bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
     135             :                              MachineInstr *MI, unsigned Dist);
     136             : 
     137             :   bool commuteInstruction(MachineInstr *MI, unsigned DstIdx,
     138             :                           unsigned RegBIdx, unsigned RegCIdx, unsigned Dist);
     139             : 
     140             :   bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
     141             : 
     142             :   bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
     143             :                           MachineBasicBlock::iterator &nmi,
     144             :                           unsigned RegA, unsigned RegB, unsigned Dist);
     145             : 
     146             :   bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
     147             : 
     148             :   bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
     149             :                              MachineBasicBlock::iterator &nmi,
     150             :                              unsigned Reg);
     151             :   bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
     152             :                              MachineBasicBlock::iterator &nmi,
     153             :                              unsigned Reg);
     154             : 
     155             :   bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
     156             :                                MachineBasicBlock::iterator &nmi,
     157             :                                unsigned SrcIdx, unsigned DstIdx,
     158             :                                unsigned Dist, bool shouldOnlyCommute);
     159             : 
     160             :   bool tryInstructionCommute(MachineInstr *MI,
     161             :                              unsigned DstOpIdx,
     162             :                              unsigned BaseOpIdx,
     163             :                              bool BaseOpKilled,
     164             :                              unsigned Dist);
     165             :   void scanUses(unsigned DstReg);
     166             : 
     167             :   void processCopy(MachineInstr *MI);
     168             : 
     169             :   using TiedPairList = SmallVector<std::pair<unsigned, unsigned>, 4>;
     170             :   using TiedOperandMap = SmallDenseMap<unsigned, TiedPairList>;
     171             : 
     172             :   bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
     173             :   void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
     174             :   void eliminateRegSequence(MachineBasicBlock::iterator&);
     175             : 
     176             : public:
     177             :   static char ID; // Pass identification, replacement for typeid
     178             : 
     179       56415 :   TwoAddressInstructionPass() : MachineFunctionPass(ID) {
     180       18805 :     initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
     181       18805 :   }
     182             : 
     183       18682 :   void getAnalysisUsage(AnalysisUsage &AU) const override {
     184       18682 :     AU.setPreservesCFG();
     185             :     AU.addUsedIfAvailable<AAResultsWrapperPass>();
     186             :     AU.addUsedIfAvailable<LiveVariables>();
     187             :     AU.addPreserved<LiveVariables>();
     188             :     AU.addPreserved<SlotIndexes>();
     189             :     AU.addPreserved<LiveIntervals>();
     190       18682 :     AU.addPreservedID(MachineLoopInfoID);
     191       18682 :     AU.addPreservedID(MachineDominatorsID);
     192       18682 :     MachineFunctionPass::getAnalysisUsage(AU);
     193       18682 :   }
     194             : 
     195             :   /// Pass entry point.
     196             :   bool runOnMachineFunction(MachineFunction&) override;
     197             : };
     198             : 
     199             : } // end anonymous namespace
     200             : 
     201             : char TwoAddressInstructionPass::ID = 0;
     202             : 
     203             : char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
     204             : 
     205       22315 : INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, DEBUG_TYPE,
     206             :                 "Two-Address instruction pass", false, false)
     207       22315 : INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
     208      164066 : INITIALIZE_PASS_END(TwoAddressInstructionPass, DEBUG_TYPE,
     209             :                 "Two-Address instruction pass", false, false)
     210             : 
     211             : static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
     212             : 
     213             : /// A two-address instruction has been converted to a three-address instruction
     214             : /// to avoid clobbering a register. Try to sink it past the instruction that
     215             : /// would kill the above mentioned register to reduce register pressure.
     216        4813 : bool TwoAddressInstructionPass::
     217             : sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
     218             :                      MachineBasicBlock::iterator OldPos) {
     219             :   // FIXME: Shouldn't we be trying to do this before we three-addressify the
     220             :   // instruction?  After this transformation is done, we no longer need
     221             :   // the instruction to be in three-address form.
     222             : 
     223             :   // Check if it's safe to move this instruction.
     224        4813 :   bool SeenStore = true; // Be conservative.
     225        4813 :   if (!MI->isSafeToMove(AA, SeenStore))
     226             :     return false;
     227             : 
     228             :   unsigned DefReg = 0;
     229        4770 :   SmallSet<unsigned, 4> UseRegs;
     230             : 
     231       61784 :   for (const MachineOperand &MO : MI->operands()) {
     232       28836 :     if (!MO.isReg())
     233        9593 :       continue;
     234       19243 :     unsigned MOReg = MO.getReg();
     235       19243 :     if (!MOReg)
     236        7488 :       continue;
     237       11755 :     if (MO.isUse() && MOReg != SavedReg)
     238        1828 :       UseRegs.insert(MO.getReg());
     239       11755 :     if (!MO.isDef())
     240        6656 :       continue;
     241        5099 :     if (MO.isImplicit())
     242             :       // Don't try to move it if it implicitly defines a register.
     243             :       return false;
     244        4770 :     if (DefReg)
     245             :       // For now, don't move any instructions that define multiple registers.
     246             :       return false;
     247        4770 :     DefReg = MO.getReg();
     248             :   }
     249             : 
     250             :   // Find the instruction that kills SavedReg.
     251             :   MachineInstr *KillMI = nullptr;
     252        4441 :   if (LIS) {
     253           0 :     LiveInterval &LI = LIS->getInterval(SavedReg);
     254             :     assert(LI.end() != LI.begin() &&
     255             :            "Reg should not have empty live interval.");
     256             : 
     257           0 :     SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
     258           0 :     LiveInterval::const_iterator I = LI.find(MBBEndIdx);
     259           0 :     if (I != LI.end() && I->start < MBBEndIdx)
     260             :       return false;
     261             : 
     262             :     --I;
     263             :     KillMI = LIS->getInstructionFromIndex(I->end);
     264             :   }
     265           0 :   if (!KillMI) {
     266       30284 :     for (MachineOperand &UseMO : MRI->use_nodbg_operands(SavedReg)) {
     267       25468 :       if (!UseMO.isKill())
     268             :         continue;
     269        4066 :       KillMI = UseMO.getParent();
     270        4066 :       break;
     271             :     }
     272             :   }
     273             : 
     274             :   // If we find the instruction that kills SavedReg, and it is in an
     275             :   // appropriate location, we can try to sink the current instruction
     276             :   // past it.
     277        5946 :   if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
     278        5595 :       MachineBasicBlock::iterator(KillMI) == OldPos || KillMI->isTerminator())
     279             :     return false;
     280             : 
     281             :   // If any of the definitions are used by another instruction between the
     282             :   // position and the kill use, then it's not safe to sink it.
     283             :   //
     284             :   // FIXME: This can be sped up if there is an easy way to query whether an
     285             :   // instruction is before or after another instruction. Then we can use
     286             :   // MachineRegisterInfo def / use instead.
     287             :   MachineOperand *KillMO = nullptr;
     288             :   MachineBasicBlock::iterator KillPos = KillMI;
     289             :   ++KillPos;
     290             : 
     291             :   unsigned NumVisited = 0;
     292        5203 :   for (MachineInstr &OtherMI : make_range(std::next(OldPos), KillPos)) {
     293             :     // DBG_VALUE cannot be counted against the limit.
     294        3640 :     if (OtherMI.isDebugValue())
     295         156 :       continue;
     296        3484 :     if (NumVisited > 30)  // FIXME: Arbitrary limit to reduce compile time cost.
     297         745 :       return false;
     298        3480 :     ++NumVisited;
     299       17960 :     for (unsigned i = 0, e = OtherMI.getNumOperands(); i != e; ++i) {
     300       15221 :       MachineOperand &MO = OtherMI.getOperand(i);
     301       15221 :       if (!MO.isReg())
     302       10621 :         continue;
     303       11094 :       unsigned MOReg = MO.getReg();
     304       11094 :       if (!MOReg)
     305        2367 :         continue;
     306        8727 :       if (DefReg == MOReg)
     307         741 :         return false;
     308             : 
     309        8027 :       if (MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))) {
     310        1827 :         if (&OtherMI == KillMI && MOReg == SavedReg)
     311             :           // Save the operand that kills the register. We want to unset the kill
     312             :           // marker if we can sink MI past it.
     313             :           KillMO = &MO;
     314        1369 :         else if (UseRegs.count(MOReg))
     315             :           // One of the uses is killed before the destination.
     316             :           return false;
     317             :       }
     318             :     }
     319             :   }
     320             :   assert(KillMO && "Didn't find kill");
     321             : 
     322         409 :   if (!LIS) {
     323             :     // Update kill and LV information.
     324             :     KillMO->setIsKill(false);
     325         409 :     KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
     326             :     KillMO->setIsKill(true);
     327             : 
     328         409 :     if (LV)
     329         409 :       LV->replaceKillInstruction(SavedReg, *KillMI, *MI);
     330             :   }
     331             : 
     332             :   // Move instruction to its destination.
     333         409 :   MBB->remove(MI);
     334         409 :   MBB->insert(KillPos, MI);
     335             : 
     336         409 :   if (LIS)
     337           0 :     LIS->handleMove(*MI);
     338             : 
     339             :   ++Num3AddrSunk;
     340             :   return true;
     341             : }
     342             : 
     343             : /// Return the MachineInstr* if it is the single def of the Reg in current BB.
     344       42680 : static MachineInstr *getSingleDef(unsigned Reg, MachineBasicBlock *BB,
     345             :                                   const MachineRegisterInfo *MRI) {
     346             :   MachineInstr *Ret = nullptr;
     347       84516 :   for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
     348      120309 :     if (DefMI.getParent() != BB || DefMI.isDebugValue())
     349        3557 :       continue;
     350       58376 :     if (!Ret)
     351             :       Ret = &DefMI;
     352       20097 :     else if (Ret != &DefMI)
     353             :       return nullptr;
     354             :   }
     355             :   return Ret;
     356             : }
     357             : 
     358             : /// Check if there is a reversed copy chain from FromReg to ToReg:
     359             : /// %Tmp1 = copy %Tmp2;
     360             : /// %FromReg = copy %Tmp1;
     361             : /// %ToReg = add %FromReg ...
     362             : /// %Tmp2 = copy %ToReg;
     363             : /// MaxLen specifies the maximum length of the copy chain the func
     364             : /// can walk through.
     365       35618 : bool TwoAddressInstructionPass::isRevCopyChain(unsigned FromReg, unsigned ToReg,
     366             :                                                int Maxlen) {
     367             :   unsigned TmpReg = FromReg;
     368       49856 :   for (int i = 0; i < Maxlen; i++) {
     369       42680 :     MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI);
     370       60862 :     if (!Def || !Def->isCopy())
     371             :       return false;
     372             : 
     373        7295 :     TmpReg = Def->getOperand(1).getReg();
     374             : 
     375        7295 :     if (TmpReg == ToReg)
     376             :       return true;
     377             :   }
     378             :   return false;
     379             : }
     380             : 
     381             : /// Return true if there are no intervening uses between the last instruction
     382             : /// in the MBB that defines the specified register and the two-address
     383             : /// instruction which is being processed. It also returns the last def location
     384             : /// by reference.
     385       40278 : bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist,
     386             :                                                   unsigned &LastDef) {
     387       40278 :   LastDef = 0;
     388             :   unsigned LastUse = Dist;
     389      217713 :   for (MachineOperand &MO : MRI->reg_operands(Reg)) {
     390      137157 :     MachineInstr *MI = MO.getParent();
     391      268599 :     if (MI->getParent() != MBB || MI->isDebugValue())
     392       11705 :       continue;
     393      131318 :     DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
     394      131318 :     if (DI == DistanceMap.end())
     395          27 :       continue;
     396      131291 :     if (MO.isUse() && DI->second < LastUse)
     397             :       LastUse = DI->second;
     398      131291 :     if (MO.isDef() && DI->second > LastDef)
     399       58002 :       LastDef = DI->second;
     400             :   }
     401             : 
     402       40278 :   return !(LastUse > LastDef && LastUse < Dist);
     403             : }
     404             : 
     405             : /// Return true if the specified MI is a copy instruction or an extract_subreg
     406             : /// instruction. It also returns the source and destination registers and
     407             : /// whether they are physical registers by reference.
     408             : static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
     409             :                         unsigned &SrcReg, unsigned &DstReg,
     410             :                         bool &IsSrcPhys, bool &IsDstPhys) {
     411             :   SrcReg = 0;
     412      641934 :   DstReg = 0;
     413     4899288 :   if (MI.isCopy()) {
     414     1255056 :     DstReg = MI.getOperand(0).getReg();
     415     1110040 :     SrcReg = MI.getOperand(1).getReg();
     416     3644232 :   } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
     417       73739 :     DstReg = MI.getOperand(0).getReg();
     418       50853 :     SrcReg = MI.getOperand(2).getReg();
     419             :   } else
     420             :     return false;
     421             : 
     422             :   IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
     423      335804 :   IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
     424             :   return true;
     425             : }
     426             : 
     427             : /// Test if the given register value, which is used by the
     428             : /// given instruction, is killed by the given instruction.
     429      298306 : static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg,
     430             :                             LiveIntervals *LIS) {
     431      298306 :   if (LIS && TargetRegisterInfo::isVirtualRegister(Reg) &&
     432           0 :       !LIS->isNotInMIMap(*MI)) {
     433             :     // FIXME: Sometimes tryInstructionTransform() will add instructions and
     434             :     // test whether they can be folded before keeping them. In this case it
     435             :     // sets a kill before recursively calling tryInstructionTransform() again.
     436             :     // If there is no interval available, we assume that this instruction is
     437             :     // one of those. A kill flag is manually inserted on the operand so the
     438             :     // check below will handle it.
     439           0 :     LiveInterval &LI = LIS->getInterval(Reg);
     440             :     // This is to match the kill flag version where undefs don't have kill
     441             :     // flags.
     442           0 :     if (!LI.hasAtLeastOneValue())
     443             :       return false;
     444             : 
     445           0 :     SlotIndex useIdx = LIS->getInstructionIndex(*MI);
     446           0 :     LiveInterval::const_iterator I = LI.find(useIdx);
     447             :     assert(I != LI.end() && "Reg must be live-in to use.");
     448           0 :     return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
     449             :   }
     450             : 
     451      298306 :   return MI->killsRegister(Reg);
     452             : }
     453             : 
     454             : /// Test if the given register value, which is used by the given
     455             : /// instruction, is killed by the given instruction. This looks through
     456             : /// coalescable copies to see if the original value is potentially not killed.
     457             : ///
     458             : /// For example, in this code:
     459             : ///
     460             : ///   %reg1034 = copy %reg1024
     461             : ///   %reg1035 = copy killed %reg1025
     462             : ///   %reg1036 = add killed %reg1034, killed %reg1035
     463             : ///
     464             : /// %reg1034 is not considered to be killed, since it is copied from a
     465             : /// register which is not killed. Treating it as not killed lets the
     466             : /// normal heuristics commute the (two-address) add, which lets
     467             : /// coalescing eliminate the extra copy.
     468             : ///
     469             : /// If allowFalsePositives is true then likely kills are treated as kills even
     470             : /// if it can't be proven that they are kills.
     471      241826 : static bool isKilled(MachineInstr &MI, unsigned Reg,
     472             :                      const MachineRegisterInfo *MRI,
     473             :                      const TargetInstrInfo *TII,
     474             :                      LiveIntervals *LIS,
     475             :                      bool allowFalsePositives) {
     476             :   MachineInstr *DefMI = &MI;
     477             :   while (true) {
     478             :     // All uses of physical registers are likely to be kills.
     479      291608 :     if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
     480         296 :         (allowFalsePositives || MRI->hasOneUse(Reg)))
     481      241826 :       return true;
     482      261987 :     if (!isPlainlyKilled(DefMI, Reg, LIS))
     483             :       return false;
     484      225679 :     if (TargetRegisterInfo::isPhysicalRegister(Reg))
     485             :       return true;
     486      225541 :     MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
     487             :     // If there are multiple defs, we can't do a simple analysis, so just
     488             :     // go with what the kill flag says.
     489      225541 :     if (std::next(Begin) != MRI->def_end())
     490             :       return true;
     491      177541 :     DefMI = Begin->getParent();
     492             :     bool IsSrcPhys, IsDstPhys;
     493             :     unsigned SrcReg,  DstReg;
     494             :     // If the def is something other than a copy, then it isn't going to
     495             :     // be coalesced, so follow the kill flag.
     496      177541 :     if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
     497             :       return true;
     498             :     Reg = SrcReg;
     499       49782 :   }
     500             : }
     501             : 
     502             : /// Return true if the specified MI uses the specified register as a two-address
     503             : /// use. If so, return the destination register by reference.
     504      507013 : static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
     505     2491702 :   for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
     506     2126271 :     const MachineOperand &MO = MI.getOperand(i);
     507     3746447 :     if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
     508     1612222 :       continue;
     509             :     unsigned ti;
     510      514049 :     if (MI.isRegTiedToDefOperand(i, &ti)) {
     511      283164 :       DstReg = MI.getOperand(ti).getReg();
     512      141582 :       return true;
     513             :     }
     514             :   }
     515             :   return false;
     516             : }
     517             : 
     518             : /// Given a register, if has a single in-basic block use, return the use
     519             : /// instruction if it's a copy or a two-address use.
     520             : static
     521      795590 : MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
     522             :                                      MachineRegisterInfo *MRI,
     523             :                                      const TargetInstrInfo *TII,
     524             :                                      bool &IsCopy,
     525             :                                      unsigned &DstReg, bool &IsDstPhys) {
     526      795590 :   if (!MRI->hasOneNonDBGUse(Reg))
     527             :     // None or more than one use.
     528             :     return nullptr;
     529     1347678 :   MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(Reg);
     530      673839 :   if (UseMI.getParent() != MBB)
     531             :     return nullptr;
     532             :   unsigned SrcReg;
     533             :   bool IsSrcPhys;
     534             :   if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
     535      167902 :     IsCopy = true;
     536             :     return &UseMI;
     537             :   }
     538      474032 :   IsDstPhys = false;
     539      474032 :   if (isTwoAddrUse(UseMI, Reg, DstReg)) {
     540      249712 :     IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
     541             :     return &UseMI;
     542             :   }
     543             :   return nullptr;
     544             : }
     545             : 
     546             : /// Return the physical register the specified virtual register might be mapped
     547             : /// to.
     548             : static unsigned
     549       89433 : getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
     550      454989 :   while (TargetRegisterInfo::isVirtualRegister(Reg))  {
     551      151965 :     DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
     552      151965 :     if (SI == RegMap.end())
     553       59924 :       return 0;
     554       92041 :     Reg = SI->second;
     555             :   }
     556       29509 :   if (TargetRegisterInfo::isPhysicalRegister(Reg))
     557       29509 :     return Reg;
     558             :   return 0;
     559             : }
     560             : 
     561             : /// Return true if the two registers are equal or aliased.
     562             : static bool
     563             : regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
     564       12094 :   if (RegA == RegB)
     565             :     return true;
     566             :   if (!RegA || !RegB)
     567             :     return false;
     568        5820 :   return TRI->regsOverlap(RegA, RegB);
     569             : }
     570             : 
     571             : // Returns true if Reg is equal or aliased to at least one register in Set.
     572             : static bool regOverlapsSet(const SmallVectorImpl<unsigned> &Set, unsigned Reg,
     573             :                            const TargetRegisterInfo *TRI) {
     574      192616 :   for (unsigned R : Set)
     575       74409 :     if (TRI->regsOverlap(R, Reg))
     576             :       return true;
     577             : 
     578             :   return false;
     579             : }
     580             : 
     581             : /// Return true if it's potentially profitable to commute the two-address
     582             : /// instruction that's being processed.
     583             : bool
     584       36319 : TwoAddressInstructionPass::
     585             : isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
     586             :                       MachineInstr *MI, unsigned Dist) {
     587       36319 :   if (OptLevel == CodeGenOpt::None)
     588             :     return false;
     589             : 
     590             :   // Determine if it's profitable to commute this two address instruction. In
     591             :   // general, we want no uses between this instruction and the definition of
     592             :   // the two-address register.
     593             :   // e.g.
     594             :   // %reg1028 = EXTRACT_SUBREG killed %reg1027, 1
     595             :   // %reg1029 = MOV8rr %reg1028
     596             :   // %reg1029 = SHR8ri %reg1029, 7, implicit dead %eflags
     597             :   // insert => %reg1030 = MOV8rr %reg1028
     598             :   // %reg1030 = ADD8rr killed %reg1028, killed %reg1029, implicit dead %eflags
     599             :   // In this case, it might not be possible to coalesce the second MOV8rr
     600             :   // instruction if the first one is coalesced. So it would be profitable to
     601             :   // commute it:
     602             :   // %reg1028 = EXTRACT_SUBREG killed %reg1027, 1
     603             :   // %reg1029 = MOV8rr %reg1028
     604             :   // %reg1029 = SHR8ri %reg1029, 7, implicit dead %eflags
     605             :   // insert => %reg1030 = MOV8rr %reg1029
     606             :   // %reg1030 = ADD8rr killed %reg1029, killed %reg1028, implicit dead %eflags
     607             : 
     608       36319 :   if (!isPlainlyKilled(MI, regC, LIS))
     609             :     return false;
     610             : 
     611             :   // Ok, we have something like:
     612             :   // %reg1030 = ADD8rr killed %reg1028, killed %reg1029, implicit dead %eflags
     613             :   // let's see if it's worth commuting it.
     614             : 
     615             :   // Look for situations like this:
     616             :   // %reg1024 = MOV r1
     617             :   // %reg1025 = MOV r0
     618             :   // %reg1026 = ADD %reg1024, %reg1025
     619             :   // r0            = MOV %reg1026
     620             :   // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
     621       26182 :   unsigned ToRegA = getMappedReg(regA, DstRegMap);
     622       26182 :   if (ToRegA) {
     623        9295 :     unsigned FromRegB = getMappedReg(regB, SrcRegMap);
     624        9295 :     unsigned FromRegC = getMappedReg(regC, SrcRegMap);
     625       11120 :     bool CompB = FromRegB && regsAreCompatible(FromRegB, ToRegA, TRI);
     626       12431 :     bool CompC = FromRegC && regsAreCompatible(FromRegC, ToRegA, TRI);
     627             : 
     628             :     // Compute if any of the following are true:
     629             :     // -RegB is not tied to a register and RegC is compatible with RegA.
     630             :     // -RegB is tied to the wrong physical register, but RegC is.
     631             :     // -RegB is tied to the wrong physical register, and RegC isn't tied.
     632        9295 :     if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
     633             :       return true;
     634             :     // Don't compute if any of the following are true:
     635             :     // -RegC is not tied to a register and RegB is compatible with RegA.
     636             :     // -RegC is tied to the wrong physical register, but RegB is.
     637             :     // -RegC is tied to the wrong physical register, and RegB isn't tied.
     638        7989 :     if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
     639             :       return false;
     640             :   }
     641             : 
     642             :   // If there is a use of regC between its last def (could be livein) and this
     643             :   // instruction, then bail.
     644       21175 :   unsigned LastDefC = 0;
     645       21175 :   if (!noUseAfterLastDef(regC, Dist, LastDefC))
     646             :     return false;
     647             : 
     648             :   // If there is a use of regB between its last def (could be livein) and this
     649             :   // instruction, then go ahead and make this transformation.
     650       19103 :   unsigned LastDefB = 0;
     651       19103 :   if (!noUseAfterLastDef(regB, Dist, LastDefB))
     652             :     return true;
     653             : 
     654             :   // Look for situation like this:
     655             :   // %reg101 = MOV %reg100
     656             :   // %reg102 = ...
     657             :   // %reg103 = ADD %reg102, %reg101
     658             :   // ... = %reg103 ...
     659             :   // %reg100 = MOV %reg103
     660             :   // If there is a reversed copy chain from reg101 to reg103, commute the ADD
     661             :   // to eliminate an otherwise unavoidable copy.
     662             :   // FIXME:
     663             :   // We can extend the logic further: If an pair of operands in an insn has
     664             :   // been merged, the insn could be regarded as a virtual copy, and the virtual
     665             :   // copy could also be used to construct a copy chain.
     666             :   // To more generally minimize register copies, ideally the logic of two addr
     667             :   // instruction pass should be integrated with register allocation pass where
     668             :   // interference graph is available.
     669       17823 :   if (isRevCopyChain(regC, regA, MaxDataFlowEdge))
     670             :     return true;
     671             : 
     672       17795 :   if (isRevCopyChain(regB, regA, MaxDataFlowEdge))
     673             :     return false;
     674             : 
     675             :   // Since there are no intervening uses for both registers, then commute
     676             :   // if the def of regC is closer. Its live interval is shorter.
     677       17647 :   return LastDefB && LastDefC && LastDefC > LastDefB;
     678             : }
     679             : 
     680             : /// Commute a two-address instruction and update the basic block, distance map,
     681             : /// and live variables if needed. Return true if it is successful.
     682       14834 : bool TwoAddressInstructionPass::commuteInstruction(MachineInstr *MI,
     683             :                                                    unsigned DstIdx,
     684             :                                                    unsigned RegBIdx,
     685             :                                                    unsigned RegCIdx,
     686             :                                                    unsigned Dist) {
     687       29668 :   unsigned RegC = MI->getOperand(RegCIdx).getReg();
     688             :   DEBUG(dbgs() << "2addr: COMMUTING  : " << *MI);
     689       14834 :   MachineInstr *NewMI = TII->commuteInstruction(*MI, false, RegBIdx, RegCIdx);
     690             : 
     691       14834 :   if (NewMI == nullptr) {
     692             :     DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
     693             :     return false;
     694             :   }
     695             : 
     696             :   DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
     697             :   assert(NewMI == MI &&
     698             :          "TargetInstrInfo::commuteInstruction() should not return a new "
     699             :          "instruction unless it was requested.");
     700             : 
     701             :   // Update source register map.
     702       14828 :   unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
     703       14828 :   if (FromRegC) {
     704        7904 :     unsigned RegA = MI->getOperand(DstIdx).getReg();
     705        3952 :     SrcRegMap[RegA] = FromRegC;
     706             :   }
     707             : 
     708             :   return true;
     709             : }
     710             : 
     711             : /// Return true if it is profitable to convert the given 2-address instruction
     712             : /// to a 3-address one.
     713             : bool
     714       25665 : TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
     715             :   // Look for situations like this:
     716             :   // %reg1024 = MOV r1
     717             :   // %reg1025 = MOV r0
     718             :   // %reg1026 = ADD %reg1024, %reg1025
     719             :   // r2            = MOV %reg1026
     720             :   // Turn ADD into a 3-address instruction to avoid a copy.
     721       25665 :   unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
     722       25665 :   if (!FromRegB)
     723             :     return false;
     724        4168 :   unsigned ToRegA = getMappedReg(RegA, DstRegMap);
     725        5027 :   return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
     726             : }
     727             : 
     728             : /// Convert the specified two-address instruction into a three address one.
     729             : /// Return true if this transformation was successful.
     730             : bool
     731        6941 : TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
     732             :                                               MachineBasicBlock::iterator &nmi,
     733             :                                               unsigned RegA, unsigned RegB,
     734             :                                               unsigned Dist) {
     735             :   // FIXME: Why does convertToThreeAddress() need an iterator reference?
     736        6941 :   MachineFunction::iterator MFI = MBB->getIterator();
     737       13882 :   MachineInstr *NewMI = TII->convertToThreeAddress(MFI, *mi, LV);
     738             :   assert(MBB->getIterator() == MFI &&
     739             :          "convertToThreeAddress changed iterator reference");
     740        6941 :   if (!NewMI)
     741             :     return false;
     742             : 
     743             :   DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
     744             :   DEBUG(dbgs() << "2addr:         TO 3-ADDR: " << *NewMI);
     745             :   bool Sunk = false;
     746             : 
     747        5590 :   if (LIS)
     748           0 :     LIS->ReplaceMachineInstrInMaps(*mi, *NewMI);
     749             : 
     750       10403 :   if (NewMI->findRegisterUseOperand(RegB, false, TRI))
     751             :     // FIXME: Temporary workaround. If the new instruction doesn't
     752             :     // uses RegB, convertToThreeAddress must have created more
     753             :     // then one instruction.
     754        4813 :     Sunk = sink3AddrInstruction(NewMI, RegB, mi);
     755             : 
     756        5590 :   MBB->erase(mi); // Nuke the old inst.
     757             : 
     758        5590 :   if (!Sunk) {
     759       10362 :     DistanceMap.insert(std::make_pair(NewMI, Dist));
     760        5181 :     mi = NewMI;
     761        5181 :     nmi = std::next(mi);
     762             :   }
     763             :   else
     764         409 :     SunkInstrs.insert(NewMI);
     765             : 
     766             :   // Update source and destination register maps.
     767        5590 :   SrcRegMap.erase(RegA);
     768        5590 :   DstRegMap.erase(RegB);
     769        5590 :   return true;
     770             : }
     771             : 
     772             : /// Scan forward recursively for only uses, update maps if the use is a copy or
     773             : /// a two-address instruction.
     774             : void
     775      577803 : TwoAddressInstructionPass::scanUses(unsigned DstReg) {
     776             :   SmallVector<unsigned, 4> VirtRegPairs;
     777             :   bool IsDstPhys;
     778      577803 :   bool IsCopy = false;
     779      577803 :   unsigned NewReg = 0;
     780             :   unsigned Reg = DstReg;
     781      795590 :   while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
     782      795590 :                                                       NewReg, IsDstPhys)) {
     783      292758 :     if (IsCopy && !Processed.insert(UseMI).second)
     784             :       break;
     785             : 
     786      266281 :     DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
     787      266281 :     if (DI != DistanceMap.end())
     788             :       // Earlier in the same MBB.Reached via a back edge.
     789             :       break;
     790             : 
     791      266281 :     if (IsDstPhys) {
     792       48494 :       VirtRegPairs.push_back(NewReg);
     793       48494 :       break;
     794             :     }
     795      435574 :     bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
     796             :     if (!isNew)
     797             :       assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
     798      217787 :     VirtRegPairs.push_back(NewReg);
     799      217787 :     Reg = NewReg;
     800             :   }
     801             : 
     802      577803 :   if (!VirtRegPairs.empty()) {
     803      145115 :     unsigned ToReg = VirtRegPairs.back();
     804             :     VirtRegPairs.pop_back();
     805      387447 :     while (!VirtRegPairs.empty()) {
     806      121166 :       unsigned FromReg = VirtRegPairs.back();
     807             :       VirtRegPairs.pop_back();
     808      242332 :       bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
     809             :       if (!isNew)
     810             :         assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
     811             :       ToReg = FromReg;
     812             :     }
     813      290230 :     bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
     814             :     if (!isNew)
     815             :       assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
     816             :   }
     817      577803 : }
     818             : 
     819             : /// If the specified instruction is not yet processed, process it if it's a
     820             : /// copy. For a copy instruction, we find the physical registers the
     821             : /// source and destination registers might be mapped to. These are kept in
     822             : /// point-to maps used to determine future optimizations. e.g.
     823             : /// v1024 = mov r0
     824             : /// v1025 = mov r1
     825             : /// v1026 = add v1024, v1025
     826             : /// r1    = mov r1026
     827             : /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
     828             : /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
     829             : /// potentially joined with r1 on the output side. It's worthwhile to commute
     830             : /// 'add' to eliminate a copy.
     831     4224964 : void TwoAddressInstructionPass::processCopy(MachineInstr *MI) {
     832     4224964 :   if (Processed.count(MI))
     833             :     return;
     834             : 
     835             :   bool IsSrcPhys, IsDstPhys;
     836             :   unsigned SrcReg, DstReg;
     837     4079813 :   if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
     838             :     return;
     839             : 
     840     1111111 :   if (IsDstPhys && !IsSrcPhys)
     841      936836 :     DstRegMap.insert(std::make_pair(SrcReg, DstReg));
     842      642693 :   else if (!IsDstPhys && IsSrcPhys) {
     843      692460 :     bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
     844             :     if (!isNew)
     845             :       assert(SrcRegMap[DstReg] == SrcReg &&
     846             :              "Can't map to two src physical registers!");
     847             : 
     848      346230 :     scanUses(DstReg);
     849             :   }
     850             : 
     851     1111111 :   Processed.insert(MI);
     852             : }
     853             : 
     854             : /// If there is one more local instruction that reads 'Reg' and it kills 'Reg,
     855             : /// consider moving the instruction below the kill instruction in order to
     856             : /// eliminate the need for the copy.
     857      216654 : bool TwoAddressInstructionPass::
     858             : rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
     859             :                       MachineBasicBlock::iterator &nmi,
     860             :                       unsigned Reg) {
     861             :   // Bail immediately if we don't have LV or LIS available. We use them to find
     862             :   // kills efficiently.
     863      216654 :   if (!LV && !LIS)
     864             :     return false;
     865             : 
     866             :   MachineInstr *MI = &*mi;
     867      216626 :   DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
     868      216626 :   if (DI == DistanceMap.end())
     869             :     // Must be created from unfolded load. Don't waste time trying this.
     870             :     return false;
     871             : 
     872             :   MachineInstr *KillMI = nullptr;
     873      216626 :   if (LIS) {
     874           0 :     LiveInterval &LI = LIS->getInterval(Reg);
     875             :     assert(LI.end() != LI.begin() &&
     876             :            "Reg should not have empty live interval.");
     877             : 
     878           0 :     SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
     879           0 :     LiveInterval::const_iterator I = LI.find(MBBEndIdx);
     880           0 :     if (I != LI.end() && I->start < MBBEndIdx)
     881             :       return false;
     882             : 
     883             :     --I;
     884             :     KillMI = LIS->getInstructionFromIndex(I->end);
     885             :   } else {
     886      216626 :     KillMI = LV->getVarInfo(Reg).findKill(MBB);
     887             :   }
     888      236195 :   if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
     889             :     // Don't mess with copies, they may be coalesced later.
     890             :     return false;
     891             : 
     892       53009 :   if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
     893       35344 :       KillMI->isBranch() || KillMI->isTerminator())
     894             :     // Don't move pass calls, etc.
     895             :     return false;
     896             : 
     897             :   unsigned DstReg;
     898       17665 :   if (isTwoAddrUse(*KillMI, Reg, DstReg))
     899             :     return false;
     900             : 
     901        9142 :   bool SeenStore = true;
     902        9142 :   if (!MI->isSafeToMove(AA, SeenStore))
     903             :     return false;
     904             : 
     905        8742 :   if (TII->getInstrLatency(InstrItins, *MI) > 1)
     906             :     // FIXME: Needs more sophisticated heuristics.
     907             :     return false;
     908             : 
     909             :   SmallVector<unsigned, 2> Uses;
     910             :   SmallVector<unsigned, 2> Kills;
     911             :   SmallVector<unsigned, 2> Defs;
     912       73739 :   for (const MachineOperand &MO : MI->operands()) {
     913       32513 :     if (!MO.isReg())
     914       11701 :       continue;
     915       26742 :     unsigned MOReg = MO.getReg();
     916       26742 :     if (!MOReg)
     917         159 :       continue;
     918       26583 :     if (MO.isDef())
     919       14474 :       Defs.push_back(MOReg);
     920             :     else {
     921       12109 :       Uses.push_back(MOReg);
     922       17704 :       if (MOReg != Reg && (MO.isKill() ||
     923        2302 :                            (LIS && isPlainlyKilled(MI, MOReg, LIS))))
     924         991 :         Kills.push_back(MOReg);
     925             :     }
     926             :   }
     927             : 
     928             :   // Move the copies connected to MI down as well.
     929             :   MachineBasicBlock::iterator Begin = MI;
     930             :   MachineBasicBlock::iterator AfterMI = std::next(Begin);
     931        8713 :   MachineBasicBlock::iterator End = AfterMI;
     932        9300 :   while (End->isCopy() &&
     933         366 :          regOverlapsSet(Defs, End->getOperand(1).getReg(), TRI)) {
     934         221 :     Defs.push_back(End->getOperand(0).getReg());
     935             :     ++End;
     936             :   }
     937             : 
     938             :   // Check if the reschedule will not break dependencies.
     939             :   unsigned NumVisited = 0;
     940             :   MachineBasicBlock::iterator KillPos = KillMI;
     941             :   ++KillPos;
     942       24033 :   for (MachineInstr &OtherMI : make_range(End, KillPos)) {
     943             :     // DBG_VALUE cannot be counted against the limit.
     944       14136 :     if (OtherMI.isDebugValue())
     945         126 :       continue;
     946       14010 :     if (NumVisited > 10)  // FIXME: Arbitrary limit to reduce compile time cost.
     947        7529 :       return false;
     948       13777 :     ++NumVisited;
     949       41298 :     if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
     950       27523 :         OtherMI.isBranch() || OtherMI.isTerminator())
     951             :       // Don't move pass calls, etc.
     952             :       return false;
     953       82756 :     for (const MachineOperand &MO : OtherMI.operands()) {
     954       41770 :       if (!MO.isReg())
     955        6645 :         continue;
     956       35125 :       unsigned MOReg = MO.getReg();
     957       35125 :       if (!MOReg)
     958        3309 :         continue;
     959       31816 :       if (MO.isDef()) {
     960       28924 :         if (regOverlapsSet(Uses, MOReg, TRI))
     961             :           // Physical register use would be clobbered.
     962             :           return false;
     963       26625 :         if (!MO.isDead() && regOverlapsSet(Defs, MOReg, TRI))
     964             :           // May clobber a physical register def.
     965             :           // FIXME: This may be too conservative. It's ok if the instruction
     966             :           // is sunken completely below the use.
     967             :           return false;
     968             :       } else {
     969       34708 :         if (regOverlapsSet(Defs, MOReg, TRI))
     970             :           return false;
     971             :         bool isKill =
     972       11536 :             MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS));
     973       24996 :         if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg, TRI)) ||
     974        8999 :                              regOverlapsSet(Kills, MOReg, TRI)))
     975             :           // Don't want to extend other live ranges and update kills.
     976             :           return false;
     977       10922 :         if (MOReg == Reg && !isKill)
     978             :           // We can't schedule across a use of the register in question.
     979             :           return false;
     980             :         // Ensure that if this is register in question, its the kill we expect.
     981             :         assert((MOReg != Reg || &OtherMI == KillMI) &&
     982             :                "Found multiple kills of a register in a basic block");
     983             :       }
     984             :     }
     985             :   }
     986             : 
     987             :   // Move debug info as well.
     988        3930 :   while (Begin != MBB->begin() && std::prev(Begin)->isDebugValue())
     989             :     --Begin;
     990             : 
     991        1184 :   nmi = End;
     992        1184 :   MachineBasicBlock::iterator InsertPos = KillPos;
     993        1184 :   if (LIS) {
     994             :     // We have to move the copies first so that the MBB is still well-formed
     995             :     // when calling handleMove().
     996           0 :     for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
     997             :       auto CopyMI = MBBI++;
     998           0 :       MBB->splice(InsertPos, MBB, CopyMI);
     999           0 :       LIS->handleMove(*CopyMI);
    1000             :       InsertPos = CopyMI;
    1001             :     }
    1002           0 :     End = std::next(MachineBasicBlock::iterator(MI));
    1003             :   }
    1004             : 
    1005             :   // Copies following MI may have been moved as well.
    1006        1184 :   MBB->splice(InsertPos, MBB, Begin, End);
    1007             :   DistanceMap.erase(DI);
    1008             : 
    1009             :   // Update live variables
    1010        1184 :   if (LIS) {
    1011           0 :     LIS->handleMove(*MI);
    1012             :   } else {
    1013        1184 :     LV->removeVirtualRegisterKilled(Reg, *KillMI);
    1014        1184 :     LV->addVirtualRegisterKilled(Reg, *MI);
    1015             :   }
    1016             : 
    1017             :   DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
    1018             :   return true;
    1019             : }
    1020             : 
    1021             : /// Return true if the re-scheduling will put the given instruction too close
    1022             : /// to the defs of its register dependencies.
    1023       11565 : bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
    1024             :                                               MachineInstr *MI) {
    1025       35641 :   for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
    1026       32940 :     if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())
    1027       11093 :       continue;
    1028        2945 :     if (&DefMI == MI)
    1029        1527 :       return true; // MI is defining something KillMI uses
    1030        2522 :     DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(&DefMI);
    1031        2522 :     if (DDI == DistanceMap.end())
    1032             :       return true;  // Below MI
    1033        1426 :     unsigned DefDist = DDI->second;
    1034             :     assert(Dist > DefDist && "Visited def already?");
    1035        1426 :     if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
    1036             :       return true;
    1037             :   }
    1038             :   return false;
    1039             : }
    1040             : 
    1041             : /// If there is one more local instruction that reads 'Reg' and it kills 'Reg,
    1042             : /// consider moving the kill instruction above the current two-address
    1043             : /// instruction in order to eliminate the need for the copy.
    1044      209968 : bool TwoAddressInstructionPass::
    1045             : rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
    1046             :                       MachineBasicBlock::iterator &nmi,
    1047             :                       unsigned Reg) {
    1048             :   // Bail immediately if we don't have LV or LIS available. We use them to find
    1049             :   // kills efficiently.
    1050      209968 :   if (!LV && !LIS)
    1051             :     return false;
    1052             : 
    1053             :   MachineInstr *MI = &*mi;
    1054      209949 :   DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
    1055      209949 :   if (DI == DistanceMap.end())
    1056             :     // Must be created from unfolded load. Don't waste time trying this.
    1057             :     return false;
    1058             : 
    1059             :   MachineInstr *KillMI = nullptr;
    1060      209949 :   if (LIS) {
    1061           0 :     LiveInterval &LI = LIS->getInterval(Reg);
    1062             :     assert(LI.end() != LI.begin() &&
    1063             :            "Reg should not have empty live interval.");
    1064             : 
    1065           0 :     SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
    1066           0 :     LiveInterval::const_iterator I = LI.find(MBBEndIdx);
    1067           0 :     if (I != LI.end() && I->start < MBBEndIdx)
    1068             :       return false;
    1069             : 
    1070             :     --I;
    1071             :     KillMI = LIS->getInstructionFromIndex(I->end);
    1072             :   } else {
    1073      209949 :     KillMI = LV->getVarInfo(Reg).findKill(MBB);
    1074             :   }
    1075      226677 :   if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
    1076             :     // Don't mess with copies, they may be coalesced later.
    1077             :     return false;
    1078             : 
    1079             :   unsigned DstReg;
    1080       15316 :   if (isTwoAddrUse(*KillMI, Reg, DstReg))
    1081             :     return false;
    1082             : 
    1083        7113 :   bool SeenStore = true;
    1084        7113 :   if (!KillMI->isSafeToMove(AA, SeenStore))
    1085             :     return false;
    1086             : 
    1087        6605 :   SmallSet<unsigned, 2> Uses;
    1088        6605 :   SmallSet<unsigned, 2> Kills;
    1089        6605 :   SmallSet<unsigned, 2> Defs;
    1090        6605 :   SmallSet<unsigned, 2> LiveDefs;
    1091       27481 :   for (const MachineOperand &MO : KillMI->operands()) {
    1092       15460 :     if (!MO.isReg())
    1093        1028 :       continue;
    1094       14986 :     unsigned MOReg = MO.getReg();
    1095       14986 :     if (MO.isUse()) {
    1096       11645 :       if (!MOReg)
    1097          80 :         continue;
    1098       11565 :       if (isDefTooClose(MOReg, DI->second, MI))
    1099        5022 :         return false;
    1100       10038 :       bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS));
    1101       10038 :       if (MOReg == Reg && !isKill)
    1102             :         return false;
    1103        6543 :       Uses.insert(MOReg);
    1104        6543 :       if (isKill && MOReg != Reg)
    1105         982 :         Kills.insert(MOReg);
    1106        3341 :     } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
    1107         603 :       Defs.insert(MOReg);
    1108         603 :       if (!MO.isDead())
    1109         395 :         LiveDefs.insert(MOReg);
    1110             :     }
    1111             :   }
    1112             : 
    1113             :   // Check if the reschedule will not break depedencies.
    1114             :   unsigned NumVisited = 0;
    1115             :   for (MachineInstr &OtherMI :
    1116        9872 :        make_range(mi, MachineBasicBlock::iterator(KillMI))) {
    1117             :     // DBG_VALUE cannot be counted against the limit.
    1118        8093 :     if (OtherMI.isDebugValue())
    1119           4 :       continue;
    1120        8089 :     if (NumVisited > 10)  // FIXME: Arbitrary limit to reduce compile time cost.
    1121        1387 :       return false;
    1122        7728 :     ++NumVisited;
    1123       23147 :     if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
    1124       15422 :         OtherMI.isBranch() || OtherMI.isTerminator())
    1125             :       // Don't move pass calls, etc.
    1126             :       return false;
    1127             :     SmallVector<unsigned, 2> OtherDefs;
    1128       64304 :     for (const MachineOperand &MO : OtherMI.operands()) {
    1129       28946 :       if (!MO.isReg())
    1130       16630 :         continue;
    1131       22452 :       unsigned MOReg = MO.getReg();
    1132       22452 :       if (!MOReg)
    1133        3642 :         continue;
    1134       18810 :       if (MO.isUse()) {
    1135       10785 :         if (Defs.count(MOReg))
    1136             :           // Moving KillMI can clobber the physical register if the def has
    1137             :           // not been seen.
    1138         641 :           return false;
    1139       10765 :         if (Kills.count(MOReg))
    1140             :           // Don't want to extend other live ranges and update kills.
    1141             :           return false;
    1142       10668 :         if (&OtherMI != MI && MOReg == Reg &&
    1143         262 :             !(MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))))
    1144             :           // We can't schedule across a use of the register in question.
    1145             :           return false;
    1146             :       } else {
    1147        8025 :         OtherDefs.push_back(MOReg);
    1148             :       }
    1149             :     }
    1150             : 
    1151       14066 :     for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
    1152       14728 :       unsigned MOReg = OtherDefs[i];
    1153        7364 :       if (Uses.count(MOReg))
    1154         351 :         return false;
    1155        8559 :       if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
    1156        1360 :           LiveDefs.count(MOReg))
    1157             :         return false;
    1158             :       // Physical register def is seen.
    1159        7013 :       Defs.erase(MOReg);
    1160             :     }
    1161             :   }
    1162             : 
    1163             :   // Move the old kill above MI, don't forget to move debug info as well.
    1164         196 :   MachineBasicBlock::iterator InsertPos = mi;
    1165         591 :   while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugValue())
    1166             :     --InsertPos;
    1167             :   MachineBasicBlock::iterator From = KillMI;
    1168             :   MachineBasicBlock::iterator To = std::next(From);
    1169         196 :   while (std::prev(From)->isDebugValue())
    1170             :     --From;
    1171         196 :   MBB->splice(InsertPos, MBB, From, To);
    1172             : 
    1173         196 :   nmi = std::prev(InsertPos); // Backtrack so we process the moved instr.
    1174             :   DistanceMap.erase(DI);
    1175             : 
    1176             :   // Update live variables
    1177         196 :   if (LIS) {
    1178           0 :     LIS->handleMove(*KillMI);
    1179             :   } else {
    1180         196 :     LV->removeVirtualRegisterKilled(Reg, *KillMI);
    1181         196 :     LV->addVirtualRegisterKilled(Reg, *MI);
    1182             :   }
    1183             : 
    1184             :   DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
    1185             :   return true;
    1186             : }
    1187             : 
    1188             : /// Tries to commute the operand 'BaseOpIdx' and some other operand in the
    1189             : /// given machine instruction to improve opportunities for coalescing and
    1190             : /// elimination of a register to register copy.
    1191             : ///
    1192             : /// 'DstOpIdx' specifies the index of MI def operand.
    1193             : /// 'BaseOpKilled' specifies if the register associated with 'BaseOpIdx'
    1194             : /// operand is killed by the given instruction.
    1195             : /// The 'Dist' arguments provides the distance of MI from the start of the
    1196             : /// current basic block and it is used to determine if it is profitable
    1197             : /// to commute operands in the instruction.
    1198             : ///
    1199             : /// Returns true if the transformation happened. Otherwise, returns false.
    1200      231592 : bool TwoAddressInstructionPass::tryInstructionCommute(MachineInstr *MI,
    1201             :                                                       unsigned DstOpIdx,
    1202             :                                                       unsigned BaseOpIdx,
    1203             :                                                       bool BaseOpKilled,
    1204             :                                                       unsigned Dist) {
    1205      231592 :   if (!MI->isCommutable())
    1206             :     return false;
    1207             : 
    1208       84500 :   unsigned DstOpReg = MI->getOperand(DstOpIdx).getReg();
    1209       84500 :   unsigned BaseOpReg = MI->getOperand(BaseOpIdx).getReg();
    1210       42250 :   unsigned OpsNum = MI->getDesc().getNumOperands();
    1211       84500 :   unsigned OtherOpIdx = MI->getDesc().getNumDefs();
    1212      196546 :   for (; OtherOpIdx < OpsNum; OtherOpIdx++) {
    1213             :     // The call of findCommutedOpIndices below only checks if BaseOpIdx
    1214             :     // and OtherOpIdx are commutable, it does not really search for
    1215             :     // other commutable operands and does not change the values of passed
    1216             :     // variables.
    1217      188251 :     if (OtherOpIdx == BaseOpIdx || !MI->getOperand(OtherOpIdx).isReg() ||
    1218       46457 :         !TII->findCommutedOpIndices(*MI, BaseOpIdx, OtherOpIdx))
    1219       52012 :       continue;
    1220             : 
    1221       79928 :     unsigned OtherOpReg = MI->getOperand(OtherOpIdx).getReg();
    1222             :     bool AggressiveCommute = false;
    1223             : 
    1224             :     // If OtherOp dies but BaseOp does not, swap the OtherOp and BaseOp
    1225             :     // operands. This makes the live ranges of DstOp and OtherOp joinable.
    1226             :     bool DoCommute =
    1227       39964 :         !BaseOpKilled && isKilled(*MI, OtherOpReg, MRI, TII, LIS, false);
    1228             : 
    1229       36319 :     if (!DoCommute &&
    1230       36319 :         isProfitableToCommute(DstOpReg, BaseOpReg, OtherOpReg, MI, Dist)) {
    1231             :       DoCommute = true;
    1232             :       AggressiveCommute = true;
    1233             :     }
    1234             : 
    1235             :     // If it's profitable to commute, try to do so.
    1236       28775 :     if (DoCommute && commuteInstruction(MI, DstOpIdx, BaseOpIdx, OtherOpIdx,
    1237             :                                         Dist)) {
    1238             :       ++NumCommuted;
    1239             :       if (AggressiveCommute)
    1240             :         ++NumAggrCommuted;
    1241             :       return true;
    1242             :     }
    1243             :   }
    1244             :   return false;
    1245             : }
    1246             : 
    1247             : /// For the case where an instruction has a single pair of tied register
    1248             : /// operands, attempt some transformations that may either eliminate the tied
    1249             : /// operands or improve the opportunities for coalescing away the register copy.
    1250             : /// Returns true if no copy needs to be inserted to untie mi's operands
    1251             : /// (either because they were untied, or because mi was rescheduled, and will
    1252             : /// be visited again later). If the shouldOnlyCommute flag is true, only
    1253             : /// instruction commutation is attempted.
    1254      234629 : bool TwoAddressInstructionPass::
    1255             : tryInstructionTransform(MachineBasicBlock::iterator &mi,
    1256             :                         MachineBasicBlock::iterator &nmi,
    1257             :                         unsigned SrcIdx, unsigned DstIdx,
    1258             :                         unsigned Dist, bool shouldOnlyCommute) {
    1259      234629 :   if (OptLevel == CodeGenOpt::None)
    1260             :     return false;
    1261             : 
    1262             :   MachineInstr &MI = *mi;
    1263      463184 :   unsigned regA = MI.getOperand(DstIdx).getReg();
    1264      231592 :   unsigned regB = MI.getOperand(SrcIdx).getReg();
    1265             : 
    1266             :   assert(TargetRegisterInfo::isVirtualRegister(regB) &&
    1267             :          "cannot make instruction into two-address form");
    1268      231592 :   bool regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
    1269             : 
    1270      231592 :   if (TargetRegisterInfo::isVirtualRegister(regA))
    1271      231573 :     scanUses(regA);
    1272             : 
    1273      231592 :   bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist);
    1274             : 
    1275             :   // If the instruction is convertible to 3 Addr, instead
    1276             :   // of returning try 3 Addr transformation aggresively and
    1277             :   // use this variable to check later. Because it might be better.
    1278             :   // For example, we can just use `leal (%rsi,%rdi), %eax` and `ret`
    1279             :   // instead of the following code.
    1280             :   //   addl     %esi, %edi
    1281             :   //   movl     %edi, %eax
    1282             :   //   ret
    1283      246420 :   if (Commuted && !MI.isConvertibleTo3Addr())
    1284             :     return false;
    1285             : 
    1286      219562 :   if (shouldOnlyCommute)
    1287             :     return false;
    1288             : 
    1289             :   // If there is one more use of regB later in the same MBB, consider
    1290             :   // re-schedule this MI below it.
    1291      435967 :   if (!Commuted && EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) {
    1292             :     ++NumReSchedDowns;
    1293             :     return true;
    1294             :   }
    1295             : 
    1296             :   // If we commuted, regB may have changed so we should re-sample it to avoid
    1297             :   // confusing the three address conversion below.
    1298      218129 :   if (Commuted) {
    1299        5318 :     regB = MI.getOperand(SrcIdx).getReg();
    1300        2659 :     regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
    1301             :   }
    1302             : 
    1303      218129 :   if (MI.isConvertibleTo3Addr()) {
    1304             :     // This instruction is potentially convertible to a true
    1305             :     // three-address instruction.  Check if it is profitable.
    1306       31752 :     if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
    1307             :       // Try to convert it.
    1308        6941 :       if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
    1309             :         ++NumConvertedTo3Addr;
    1310             :         return true; // Done with this instruction.
    1311             :       }
    1312             :     }
    1313             :   }
    1314             : 
    1315             :   // Return if it is commuted but 3 addr conversion is failed.
    1316      212539 :   if (Commuted)
    1317             :     return false;
    1318             : 
    1319             :   // If there is one more use of regB later in the same MBB, consider
    1320             :   // re-schedule it before this MI if it's legal.
    1321      209968 :   if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, regB)) {
    1322             :     ++NumReSchedUps;
    1323             :     return true;
    1324             :   }
    1325             : 
    1326             :   // If this is an instruction with a load folded into it, try unfolding
    1327             :   // the load, e.g. avoid this:
    1328             :   //   movq %rdx, %rcx
    1329             :   //   addq (%rax), %rcx
    1330             :   // in favor of this:
    1331             :   //   movq (%rax), %rcx
    1332             :   //   addq %rdx, %rcx
    1333             :   // because it's preferable to schedule a load than a register copy.
    1334      209772 :   if (MI.mayLoad() && !regBKilled) {
    1335             :     // Determine if a load can be unfolded.
    1336             :     unsigned LoadRegIndex;
    1337             :     unsigned NewOpc =
    1338        5228 :       TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
    1339             :                                       /*UnfoldLoad=*/true,
    1340             :                                       /*UnfoldStore=*/false,
    1341        5228 :                                       &LoadRegIndex);
    1342        2614 :     if (NewOpc != 0) {
    1343        2063 :       const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
    1344        2063 :       if (UnfoldMCID.getNumDefs() == 1) {
    1345             :         // Unfold the load.
    1346             :         DEBUG(dbgs() << "2addr:   UNFOLDING: " << MI);
    1347             :         const TargetRegisterClass *RC =
    1348        4126 :           TRI->getAllocatableClass(
    1349        4126 :             TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
    1350        2063 :         unsigned Reg = MRI->createVirtualRegister(RC);
    1351             :         SmallVector<MachineInstr *, 2> NewMIs;
    1352        4126 :         if (!TII->unfoldMemoryOperand(*MF, MI, Reg,
    1353             :                                       /*UnfoldLoad=*/true,
    1354        2063 :                                       /*UnfoldStore=*/false, NewMIs)) {
    1355             :           DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
    1356             :           return false;
    1357             :         }
    1358             :         assert(NewMIs.size() == 2 &&
    1359             :                "Unfolded a load into multiple instructions!");
    1360             :         // The load was previously folded, so this is the only use.
    1361        2063 :         NewMIs[1]->addRegisterKilled(Reg, TRI);
    1362             : 
    1363             :         // Tentatively insert the instructions into the block so that they
    1364             :         // look "normal" to the transformation logic.
    1365        4126 :         MBB->insert(mi, NewMIs[0]);
    1366        4126 :         MBB->insert(mi, NewMIs[1]);
    1367             : 
    1368             :         DEBUG(dbgs() << "2addr:    NEW LOAD: " << *NewMIs[0]
    1369             :                      << "2addr:    NEW INST: " << *NewMIs[1]);
    1370             : 
    1371             :         // Transform the instruction, now that it no longer has a load.
    1372        2063 :         unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
    1373        2063 :         unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
    1374        2063 :         MachineBasicBlock::iterator NewMI = NewMIs[1];
    1375             :         bool TransformResult =
    1376        2063 :           tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true);
    1377             :         (void)TransformResult;
    1378             :         assert(!TransformResult &&
    1379             :                "tryInstructionTransform() should return false.");
    1380        4126 :         if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
    1381             :           // Success, or at least we made an improvement. Keep the unfolded
    1382             :           // instructions and discard the original.
    1383        1954 :           if (LV) {
    1384       15908 :             for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
    1385       13959 :               MachineOperand &MO = MI.getOperand(i);
    1386       23877 :               if (MO.isReg() &&
    1387        9918 :                   TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
    1388        4987 :                 if (MO.isUse()) {
    1389        3038 :                   if (MO.isKill()) {
    1390         168 :                     if (NewMIs[0]->killsRegister(MO.getReg()))
    1391         136 :                       LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[0]);
    1392             :                     else {
    1393             :                       assert(NewMIs[1]->killsRegister(MO.getReg()) &&
    1394             :                              "Kill missing after load unfold!");
    1395          32 :                       LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[1]);
    1396             :                     }
    1397             :                   }
    1398        1949 :                 } else if (LV->removeVirtualRegisterDead(MO.getReg(), MI)) {
    1399           0 :                   if (NewMIs[1]->registerDefIsDead(MO.getReg()))
    1400           0 :                     LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[1]);
    1401             :                   else {
    1402             :                     assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
    1403             :                            "Dead flag missing after load unfold!");
    1404           0 :                     LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[0]);
    1405             :                   }
    1406             :                 }
    1407             :               }
    1408             :             }
    1409        3898 :             LV->addVirtualRegisterKilled(Reg, *NewMIs[1]);
    1410             :           }
    1411             : 
    1412             :           SmallVector<unsigned, 4> OrigRegs;
    1413        1954 :           if (LIS) {
    1414           0 :             for (const MachineOperand &MO : MI.operands()) {
    1415           0 :               if (MO.isReg())
    1416           0 :                 OrigRegs.push_back(MO.getReg());
    1417             :             }
    1418             :           }
    1419             : 
    1420        1954 :           MI.eraseFromParent();
    1421             : 
    1422             :           // Update LiveIntervals.
    1423        1954 :           if (LIS) {
    1424           0 :             MachineBasicBlock::iterator Begin(NewMIs[0]);
    1425           0 :             MachineBasicBlock::iterator End(NewMIs[1]);
    1426           0 :             LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);
    1427             :           }
    1428             : 
    1429        1954 :           mi = NewMIs[1];
    1430             :         } else {
    1431             :           // Transforming didn't eliminate the tie and didn't lead to an
    1432             :           // improvement. Clean up the unfolded instructions and keep the
    1433             :           // original.
    1434             :           DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
    1435         109 :           NewMIs[0]->eraseFromParent();
    1436         109 :           NewMIs[1]->eraseFromParent();
    1437             :         }
    1438             :       }
    1439             :     }
    1440             :   }
    1441             : 
    1442             :   return false;
    1443             : }
    1444             : 
    1445             : // Collect tied operands of MI that need to be handled.
    1446             : // Rewrite trivial cases immediately.
    1447             : // Return true if any tied operands where found, including the trivial ones.
    1448     4224964 : bool TwoAddressInstructionPass::
    1449             : collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
    1450     4224964 :   const MCInstrDesc &MCID = MI->getDesc();
    1451             :   bool AnyOps = false;
    1452     4224964 :   unsigned NumOps = MI->getNumOperands();
    1453             : 
    1454    39087452 :   for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
    1455    17431244 :     unsigned DstIdx = 0;
    1456    17431244 :     if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
    1457    34372745 :       continue;
    1458             :     AnyOps = true;
    1459      255189 :     MachineOperand &SrcMO = MI->getOperand(SrcIdx);
    1460      255189 :     MachineOperand &DstMO = MI->getOperand(DstIdx);
    1461      255189 :     unsigned SrcReg = SrcMO.getReg();
    1462      255189 :     unsigned DstReg = DstMO.getReg();
    1463             :     // Tied constraint already satisfied?
    1464      255189 :     if (SrcReg == DstReg)
    1465          51 :       continue;
    1466             : 
    1467             :     assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
    1468             : 
    1469             :     // Deal with undef uses immediately - simply rewrite the src operand.
    1470      275722 :     if (SrcMO.isUndef() && !DstMO.getSubReg()) {
    1471             :       // Constrain the DstReg register class if required.
    1472       20584 :       if (TargetRegisterInfo::isVirtualRegister(DstReg))
    1473       61752 :         if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
    1474       41168 :                                                              TRI, *MF))
    1475        1116 :           MRI->constrainRegClass(DstReg, RC);
    1476       20584 :       SrcMO.setReg(DstReg);
    1477             :       SrcMO.setSubReg(0);
    1478             :       DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
    1479       20584 :       continue;
    1480             :     }
    1481      234554 :     TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
    1482             :   }
    1483     4224964 :   return AnyOps;
    1484             : }
    1485             : 
    1486             : // Process a list of tied MI operands that all use the same source register.
    1487             : // The tied pairs are of the form (SrcIdx, DstIdx).
    1488             : void
    1489      227483 : TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
    1490             :                                             TiedPairList &TiedPairs,
    1491             :                                             unsigned &Dist) {
    1492             :   bool IsEarlyClobber = false;
    1493      455067 :   for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
    1494      455168 :     const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second);
    1495      227584 :     IsEarlyClobber |= DstMO.isEarlyClobber();
    1496             :   }
    1497             : 
    1498             :   bool RemovedKillFlag = false;
    1499             :   bool AllUsesCopied = true;
    1500             :   unsigned LastCopiedReg = 0;
    1501             :   SlotIndex LastCopyIdx;
    1502             :   unsigned RegB = 0;
    1503             :   unsigned SubRegB = 0;
    1504      682651 :   for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
    1505      455168 :     unsigned SrcIdx = TiedPairs[tpi].first;
    1506      227584 :     unsigned DstIdx = TiedPairs[tpi].second;
    1507             : 
    1508      227584 :     const MachineOperand &DstMO = MI->getOperand(DstIdx);
    1509      227584 :     unsigned RegA = DstMO.getReg();
    1510             : 
    1511             :     // Grab RegB from the instruction because it may have changed if the
    1512             :     // instruction was commuted.
    1513      227584 :     RegB = MI->getOperand(SrcIdx).getReg();
    1514             :     SubRegB = MI->getOperand(SrcIdx).getSubReg();
    1515             : 
    1516      227584 :     if (RegA == RegB) {
    1517             :       // The register is tied to multiple destinations (or else we would
    1518             :       // not have continued this far), but this use of the register
    1519             :       // already matches the tied destination.  Leave it.
    1520             :       AllUsesCopied = false;
    1521           0 :       continue;
    1522             :     }
    1523             :     LastCopiedReg = RegA;
    1524             : 
    1525             :     assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
    1526             :            "cannot make instruction into two-address form");
    1527             : 
    1528             : #ifndef NDEBUG
    1529             :     // First, verify that we don't have a use of "a" in the instruction
    1530             :     // (a = b + a for example) because our transformation will not
    1531             :     // work. This should never occur because we are in SSA form.
    1532             :     for (unsigned i = 0; i != MI->getNumOperands(); ++i)
    1533             :       assert(i == DstIdx ||
    1534             :              !MI->getOperand(i).isReg() ||
    1535             :              MI->getOperand(i).getReg() != RegA);
    1536             : #endif
    1537             : 
    1538             :     // Emit a copy.
    1539      227584 :     MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
    1540      455168 :                                       TII->get(TargetOpcode::COPY), RegA);
    1541             :     // If this operand is folding a truncation, the truncation now moves to the
    1542             :     // copy so that the register classes remain valid for the operands.
    1543      227584 :     MIB.addReg(RegB, 0, SubRegB);
    1544      227584 :     const TargetRegisterClass *RC = MRI->getRegClass(RegB);
    1545      227584 :     if (SubRegB) {
    1546           0 :       if (TargetRegisterInfo::isVirtualRegister(RegA)) {
    1547             :         assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
    1548             :                                              SubRegB) &&
    1549             :                "tied subregister must be a truncation");
    1550             :         // The superreg class will not be used to constrain the subreg class.
    1551             :         RC = nullptr;
    1552             :       }
    1553             :       else {
    1554             :         assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
    1555             :                && "tied subregister must be a truncation");
    1556             :       }
    1557             :     }
    1558             : 
    1559             :     // Update DistanceMap.
    1560      227584 :     MachineBasicBlock::iterator PrevMI = MI;
    1561             :     --PrevMI;
    1562      682752 :     DistanceMap.insert(std::make_pair(&*PrevMI, Dist));
    1563      455168 :     DistanceMap[MI] = ++Dist;
    1564             : 
    1565      227584 :     if (LIS) {
    1566           0 :       LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).getRegSlot();
    1567             : 
    1568           0 :       if (TargetRegisterInfo::isVirtualRegister(RegA)) {
    1569           0 :         LiveInterval &LI = LIS->getInterval(RegA);
    1570           0 :         VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
    1571             :         SlotIndex endIdx =
    1572           0 :             LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber);
    1573           0 :         LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
    1574             :       }
    1575             :     }
    1576             : 
    1577             :     DEBUG(dbgs() << "\t\tprepend:\t" << *MIB);
    1578             : 
    1579      227584 :     MachineOperand &MO = MI->getOperand(SrcIdx);
    1580             :     assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
    1581             :            "inconsistent operand info for 2-reg pass");
    1582      227584 :     if (MO.isKill()) {
    1583             :       MO.setIsKill(false);
    1584             :       RemovedKillFlag = true;
    1585             :     }
    1586             : 
    1587             :     // Make sure regA is a legal regclass for the SrcIdx operand.
    1588      682698 :     if (TargetRegisterInfo::isVirtualRegister(RegA) &&
    1589             :         TargetRegisterInfo::isVirtualRegister(RegB))
    1590      227530 :       MRI->constrainRegClass(RegA, RC);
    1591      227584 :     MO.setReg(RegA);
    1592             :     // The getMatchingSuper asserts guarantee that the register class projected
    1593             :     // by SubRegB is compatible with RegA with no subregister. So regardless of
    1594             :     // whether the dest oper writes a subreg, the source oper should not.
    1595             :     MO.setSubReg(0);
    1596             : 
    1597             :     // Propagate SrcRegMap.
    1598      455168 :     SrcRegMap[RegA] = RegB;
    1599             :   }
    1600             : 
    1601      227483 :   if (AllUsesCopied) {
    1602      227483 :     if (!IsEarlyClobber) {
    1603             :       // Replace other (un-tied) uses of regB with LastCopiedReg.
    1604     2182466 :       for (MachineOperand &MO : MI->operands()) {
    1605      869461 :         if (MO.isReg() && MO.getReg() == RegB &&
    1606             :             MO.isUse()) {
    1607        3187 :           if (MO.isKill()) {
    1608             :             MO.setIsKill(false);
    1609             :             RemovedKillFlag = true;
    1610             :           }
    1611        3187 :           MO.setReg(LastCopiedReg);
    1612             :           MO.setSubReg(MO.getSubReg());
    1613             :         }
    1614             :       }
    1615             :     }
    1616             : 
    1617             :     // Update live variables for regB.
    1618      227483 :     if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(*MI)) {
    1619      204584 :       MachineBasicBlock::iterator PrevMI = MI;
    1620             :       --PrevMI;
    1621      409168 :       LV->addVirtualRegisterKilled(RegB, *PrevMI);
    1622             :     }
    1623             : 
    1624             :     // Update LiveIntervals.
    1625      227483 :     if (LIS) {
    1626           0 :       LiveInterval &LI = LIS->getInterval(RegB);
    1627           0 :       SlotIndex MIIdx = LIS->getInstructionIndex(*MI);
    1628           0 :       LiveInterval::const_iterator I = LI.find(MIIdx);
    1629             :       assert(I != LI.end() && "RegB must be live-in to use.");
    1630             : 
    1631             :       SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber);
    1632           0 :       if (I->end == UseIdx)
    1633           0 :         LI.removeSegment(LastCopyIdx, UseIdx);
    1634             :     }
    1635           0 :   } else if (RemovedKillFlag) {
    1636             :     // Some tied uses of regB matched their destination registers, so
    1637             :     // regB is still used in this instruction, but a kill flag was
    1638             :     // removed from a different tied use of regB, so now we need to add
    1639             :     // a kill flag to one of the remaining uses of regB.
    1640           0 :     for (MachineOperand &MO : MI->operands()) {
    1641           0 :       if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
    1642             :         MO.setIsKill(true);
    1643             :         break;
    1644             :       }
    1645             :     }
    1646             :   }
    1647      227483 : }
    1648             : 
    1649             : /// Reduce two-address instructions to two operands.
    1650      167206 : bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
    1651      167206 :   MF = &Func;
    1652      167206 :   const TargetMachine &TM = MF->getTarget();
    1653      167206 :   MRI = &MF->getRegInfo();
    1654      167206 :   TII = MF->getSubtarget().getInstrInfo();
    1655      167206 :   TRI = MF->getSubtarget().getRegisterInfo();
    1656      167206 :   InstrItins = MF->getSubtarget().getInstrItineraryData();
    1657      167206 :   LV = getAnalysisIfAvailable<LiveVariables>();
    1658      167206 :   LIS = getAnalysisIfAvailable<LiveIntervals>();
    1659      167206 :   if (auto *AAPass = getAnalysisIfAvailable<AAResultsWrapperPass>())
    1660      160553 :     AA = &AAPass->getAAResults();
    1661             :   else
    1662        6653 :     AA = nullptr;
    1663      167206 :   OptLevel = TM.getOptLevel();
    1664             :   // Disable optimizations if requested. We cannot skip the whole pass as some
    1665             :   // fixups are necessary for correctness.
    1666      167206 :   if (skipFunction(Func.getFunction()))
    1667         464 :     OptLevel = CodeGenOpt::None;
    1668             : 
    1669             :   bool MadeChange = false;
    1670             : 
    1671             :   DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
    1672             :   DEBUG(dbgs() << "********** Function: "
    1673             :         << MF->getName() << '\n');
    1674             : 
    1675             :   // This pass takes the function out of SSA form.
    1676      167206 :   MRI->leaveSSA();
    1677             : 
    1678      167206 :   TiedOperandMap TiedOperands;
    1679      167206 :   for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
    1680      491119 :        MBBI != MBBE; ++MBBI) {
    1681      323913 :     MBB = &*MBBI;
    1682      323913 :     unsigned Dist = 0;
    1683      323913 :     DistanceMap.clear();
    1684      323913 :     SrcRegMap.clear();
    1685      323913 :     DstRegMap.clear();
    1686      323913 :     Processed.clear();
    1687      323913 :     SunkInstrs.clear();
    1688      647826 :     for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
    1689     4576261 :          mi != me; ) {
    1690     4252348 :       MachineBasicBlock::iterator nmi = std::next(mi);
    1691             :       // Don't revisit an instruction previously converted by target. It may
    1692             :       // contain undef register operands (%noreg), which are not handled.
    1693     4279732 :       if (mi->isDebugValue() || SunkInstrs.count(&*mi)) {
    1694       27384 :         mi = nmi;
    1695     4032725 :         continue;
    1696             :       }
    1697             : 
    1698             :       // Expand REG_SEQUENCE instructions. This will position mi at the first
    1699             :       // expanded instruction.
    1700     4224964 :       if (mi->isRegSequence())
    1701       43523 :         eliminateRegSequence(mi);
    1702             : 
    1703    12674892 :       DistanceMap.insert(std::make_pair(&*mi, ++Dist));
    1704             : 
    1705     4224964 :       processCopy(&*mi);
    1706             : 
    1707             :       // First scan through all the tied register uses in this instruction
    1708             :       // and record a list of pairs of tied operands for each register.
    1709     8195951 :       if (!collectTiedOperands(&*mi, TiedOperands)) {
    1710     3970987 :         mi = nmi;
    1711     3970987 :         continue;
    1712             :       }
    1713             : 
    1714             :       ++NumTwoAddressInstrs;
    1715             :       MadeChange = true;
    1716             :       DEBUG(dbgs() << '\t' << *mi);
    1717             : 
    1718             :       // If the instruction has a single pair of tied operands, try some
    1719             :       // transformations that may either eliminate the tied operands or
    1720             :       // improve the opportunities for coalescing away the register copy.
    1721      253977 :       if (TiedOperands.size() == 1) {
    1722             :         SmallVectorImpl<std::pair<unsigned, unsigned>> &TiedPairs
    1723      232585 :           = TiedOperands.begin()->second;
    1724      232585 :         if (TiedPairs.size() == 1) {
    1725      232566 :           unsigned SrcIdx = TiedPairs[0].first;
    1726      232566 :           unsigned DstIdx = TiedPairs[0].second;
    1727      465132 :           unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
    1728      232566 :           unsigned DstReg = mi->getOperand(DstIdx).getReg();
    1729      472102 :           if (SrcReg != DstReg &&
    1730      232566 :               tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {
    1731             :             // The tied operands have been eliminated or shifted further down
    1732             :             // the block to ease elimination. Continue processing with 'nmi'.
    1733        6970 :             TiedOperands.clear();
    1734        6970 :             mi = nmi;
    1735        6970 :             continue;
    1736             :           }
    1737             :         }
    1738             :       }
    1739             : 
    1740             :       // Now iterate over the information collected above.
    1741      721497 :       for (auto &TO : TiedOperands) {
    1742      454966 :         processTiedPairs(&*mi, TO.second, Dist);
    1743             :         DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
    1744             :       }
    1745             : 
    1746             :       // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
    1747      247007 :       if (mi->isInsertSubreg()) {
    1748             :         // From %reg = INSERT_SUBREG %reg, %subreg, subidx
    1749             :         // To   %reg:subidx = COPY %subreg
    1750       42314 :         unsigned SubIdx = mi->getOperand(3).getImm();
    1751       42314 :         mi->RemoveOperand(3);
    1752             :         assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
    1753       42314 :         mi->getOperand(0).setSubReg(SubIdx);
    1754       42314 :         mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
    1755       42314 :         mi->RemoveOperand(1);
    1756       42314 :         mi->setDesc(TII->get(TargetOpcode::COPY));
    1757             :         DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
    1758             :       }
    1759             : 
    1760             :       // Clear TiedOperands here instead of at the top of the loop
    1761             :       // since most instructions do not have tied operands.
    1762      247007 :       TiedOperands.clear();
    1763      247007 :       mi = nmi;
    1764             :     }
    1765             :   }
    1766             : 
    1767      167206 :   if (LIS)
    1768           0 :     MF->verify(this, "After two-address instruction pass");
    1769             : 
    1770      167206 :   return MadeChange;
    1771             : }
    1772             : 
    1773             : /// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process.
    1774             : ///
    1775             : /// The instruction is turned into a sequence of sub-register copies:
    1776             : ///
    1777             : ///   %dst = REG_SEQUENCE %v1, ssub0, %v2, ssub1
    1778             : ///
    1779             : /// Becomes:
    1780             : ///
    1781             : ///   undef %dst:ssub0 = COPY %v1
    1782             : ///   %dst:ssub1 = COPY %v2
    1783       43523 : void TwoAddressInstructionPass::
    1784             : eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
    1785             :   MachineInstr &MI = *MBBI;
    1786       43523 :   unsigned DstReg = MI.getOperand(0).getReg();
    1787       43523 :   if (MI.getOperand(0).getSubReg() ||
    1788       87046 :       TargetRegisterInfo::isPhysicalRegister(DstReg) ||
    1789       43523 :       !(MI.getNumOperands() & 1)) {
    1790             :     DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << MI);
    1791           0 :     llvm_unreachable(nullptr);
    1792             :   }
    1793             : 
    1794             :   SmallVector<unsigned, 4> OrigRegs;
    1795       43523 :   if (LIS) {
    1796           0 :     OrigRegs.push_back(MI.getOperand(0).getReg());
    1797           0 :     for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2)
    1798           0 :       OrigRegs.push_back(MI.getOperand(i).getReg());
    1799             :   }
    1800             : 
    1801             :   bool DefEmitted = false;
    1802      173512 :   for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) {
    1803      129989 :     MachineOperand &UseMO = MI.getOperand(i);
    1804      129989 :     unsigned SrcReg = UseMO.getReg();
    1805      259978 :     unsigned SubIdx = MI.getOperand(i+1).getImm();
    1806             :     // Nothing needs to be inserted for undef operands.
    1807      129989 :     if (UseMO.isUndef())
    1808        3924 :       continue;
    1809             : 
    1810             :     // Defer any kill flag to the last operand using SrcReg. Otherwise, we
    1811             :     // might insert a COPY that uses SrcReg after is was killed.
    1812             :     bool isKill = UseMO.isKill();
    1813      126065 :     if (isKill)
    1814      239104 :       for (unsigned j = i + 2; j < e; j += 2)
    1815      135139 :         if (MI.getOperand(j).getReg() == SrcReg) {
    1816             :           MI.getOperand(j).setIsKill();
    1817             :           UseMO.setIsKill(false);
    1818             :           isKill = false;
    1819        6779 :           break;
    1820             :         }
    1821             : 
    1822             :     // Insert the sub-register copy.
    1823      252130 :     MachineInstr *CopyMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
    1824      126065 :                                    TII->get(TargetOpcode::COPY))
    1825      126065 :                                .addReg(DstReg, RegState::Define, SubIdx)
    1826      126065 :                                .add(UseMO);
    1827             : 
    1828             :     // The first def needs an undef flag because there is no live register
    1829             :     // before it.
    1830      126065 :     if (!DefEmitted) {
    1831       43523 :       CopyMI->getOperand(0).setIsUndef(true);
    1832             :       // Return an iterator pointing to the first inserted instr.
    1833       43523 :       MBBI = CopyMI;
    1834             :     }
    1835             :     DefEmitted = true;
    1836             : 
    1837             :     // Update LiveVariables' kill info.
    1838      229953 :     if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
    1839      103888 :       LV->replaceKillInstruction(SrcReg, MI, *CopyMI);
    1840             : 
    1841             :     DEBUG(dbgs() << "Inserted: " << *CopyMI);
    1842             :   }
    1843             : 
    1844             :   MachineBasicBlock::iterator EndMBBI =
    1845       43523 :       std::next(MachineBasicBlock::iterator(MI));
    1846             : 
    1847       43523 :   if (!DefEmitted) {
    1848             :     DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF");
    1849           0 :     MI.setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
    1850           0 :     for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j)
    1851           0 :       MI.RemoveOperand(j);
    1852             :   } else {
    1853             :     DEBUG(dbgs() << "Eliminated: " << MI);
    1854       43523 :     MI.eraseFromParent();
    1855             :   }
    1856             : 
    1857             :   // Udpate LiveIntervals.
    1858       43523 :   if (LIS)
    1859           0 :     LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);
    1860      288581 : }

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