LCOV - code coverage report
Current view: top level - lib/CodeGen - VirtRegMap.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 210 225 93.3 %
Date: 2017-09-14 15:23:50 Functions: 23 25 92.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements the VirtRegMap class.
      11             : //
      12             : // It also contains implementations of the Spiller interface, which, given a
      13             : // virtual register map and a machine function, eliminates all virtual
      14             : // references by replacing them with physical register references - adding spill
      15             : // code as necessary.
      16             : //
      17             : //===----------------------------------------------------------------------===//
      18             : 
      19             : #include "llvm/CodeGen/VirtRegMap.h"
      20             : #include "LiveDebugVariables.h"
      21             : #include "llvm/ADT/STLExtras.h"
      22             : #include "llvm/ADT/Statistic.h"
      23             : #include "llvm/CodeGen/LiveIntervalAnalysis.h"
      24             : #include "llvm/CodeGen/LiveStackAnalysis.h"
      25             : #include "llvm/CodeGen/MachineFrameInfo.h"
      26             : #include "llvm/CodeGen/MachineFunction.h"
      27             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      28             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      29             : #include "llvm/CodeGen/Passes.h"
      30             : #include "llvm/IR/Function.h"
      31             : #include "llvm/Support/Compiler.h"
      32             : #include "llvm/Support/Debug.h"
      33             : #include "llvm/Support/raw_ostream.h"
      34             : #include "llvm/Target/TargetInstrInfo.h"
      35             : #include "llvm/Target/TargetMachine.h"
      36             : #include "llvm/Target/TargetRegisterInfo.h"
      37             : #include "llvm/Target/TargetSubtargetInfo.h"
      38             : #include <algorithm>
      39             : using namespace llvm;
      40             : 
      41             : #define DEBUG_TYPE "regalloc"
      42             : 
      43             : STATISTIC(NumSpillSlots, "Number of spill slots allocated");
      44             : STATISTIC(NumIdCopies,   "Number of identity moves eliminated after rewriting");
      45             : 
      46             : //===----------------------------------------------------------------------===//
      47             : //  VirtRegMap implementation
      48             : //===----------------------------------------------------------------------===//
      49             : 
      50             : char VirtRegMap::ID = 0;
      51             : 
      52      393764 : INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
      53             : 
      54      134835 : bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
      55      134835 :   MRI = &mf.getRegInfo();
      56      134835 :   TII = mf.getSubtarget().getInstrInfo();
      57      134835 :   TRI = mf.getSubtarget().getRegisterInfo();
      58      134835 :   MF = &mf;
      59             : 
      60      269670 :   Virt2PhysMap.clear();
      61      269670 :   Virt2StackSlotMap.clear();
      62      269670 :   Virt2SplitMap.clear();
      63             : 
      64      134835 :   grow();
      65      134835 :   return false;
      66             : }
      67             : 
      68      387728 : void VirtRegMap::grow() {
      69      775456 :   unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
      70      775456 :   Virt2PhysMap.resize(NumRegs);
      71      775456 :   Virt2StackSlotMap.resize(NumRegs);
      72      775456 :   Virt2SplitMap.resize(NumRegs);
      73      387728 : }
      74             : 
      75     1222276 : void VirtRegMap::assignVirt2Phys(unsigned virtReg, MCPhysReg physReg) {
      76             :   assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
      77             :          TargetRegisterInfo::isPhysicalRegister(physReg));
      78             :   assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
      79             :          "attempt to assign physical register to already mapped "
      80             :          "virtual register");
      81             :   assert(!getRegInfo().isReserved(physReg) &&
      82             :          "Attempt to map virtReg to a reserved physReg");
      83     2444552 :   Virt2PhysMap[virtReg] = physReg;
      84     1222276 : }
      85             : 
      86       12819 : unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
      87       12819 :   unsigned Size = TRI->getSpillSize(*RC);
      88       25638 :   unsigned Align = TRI->getSpillAlignment(*RC);
      89       12819 :   int SS = MF->getFrameInfo().CreateSpillStackObject(Size, Align);
      90       12819 :   ++NumSpillSlots;
      91       12819 :   return SS;
      92             : }
      93             : 
      94      723696 : bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
      95     1447363 :   unsigned Hint = MRI->getSimpleHint(VirtReg);
      96      723667 :   if (!Hint)
      97             :     return false;
      98      344167 :   if (TargetRegisterInfo::isVirtualRegister(Hint))
      99      153074 :     Hint = getPhys(Hint);
     100             :   return getPhys(VirtReg) == Hint;
     101             : }
     102             : 
     103     1275095 : bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
     104     2550190 :   std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
     105     2550190 :   if (TargetRegisterInfo::isPhysicalRegister(Hint.second))
     106             :     return true;
     107      771203 :   if (TargetRegisterInfo::isVirtualRegister(Hint.second))
     108      267722 :     return hasPhys(Hint.second);
     109             :   return false;
     110             : }
     111             : 
     112       12819 : int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
     113             :   assert(TargetRegisterInfo::isVirtualRegister(virtReg));
     114             :   assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
     115             :          "attempt to assign stack slot to already spilled register");
     116       25638 :   const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
     117       25638 :   return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
     118             : }
     119             : 
     120        9022 : void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
     121             :   assert(TargetRegisterInfo::isVirtualRegister(virtReg));
     122             :   assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
     123             :          "attempt to assign stack slot to already spilled register");
     124             :   assert((SS >= 0 ||
     125             :           (SS >= MF->getFrameInfo().getObjectIndexBegin())) &&
     126             :          "illegal fixed frame index");
     127       18044 :   Virt2StackSlotMap[virtReg] = SS;
     128        9022 : }
     129             : 
     130           0 : void VirtRegMap::print(raw_ostream &OS, const Module*) const {
     131           0 :   OS << "********** REGISTER MAP **********\n";
     132           0 :   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
     133           0 :     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
     134           0 :     if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
     135           0 :       OS << '[' << PrintReg(Reg, TRI) << " -> "
     136           0 :          << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
     137           0 :          << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
     138             :     }
     139             :   }
     140             : 
     141           0 :   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
     142           0 :     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
     143           0 :     if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
     144           0 :       OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
     145           0 :          << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
     146             :     }
     147             :   }
     148           0 :   OS << '\n';
     149           0 : }
     150             : 
     151             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
     152             : LLVM_DUMP_METHOD void VirtRegMap::dump() const {
     153             :   print(dbgs());
     154             : }
     155             : #endif
     156             : 
     157             : //===----------------------------------------------------------------------===//
     158             : //                              VirtRegRewriter
     159             : //===----------------------------------------------------------------------===//
     160             : //
     161             : // The VirtRegRewriter is the last of the register allocator passes.
     162             : // It rewrites virtual registers to physical registers as specified in the
     163             : // VirtRegMap analysis. It also updates live-in information on basic blocks
     164             : // according to LiveIntervals.
     165             : //
     166             : namespace {
     167       15309 : class VirtRegRewriter : public MachineFunctionPass {
     168             :   MachineFunction *MF;
     169             :   const TargetMachine *TM;
     170             :   const TargetRegisterInfo *TRI;
     171             :   const TargetInstrInfo *TII;
     172             :   MachineRegisterInfo *MRI;
     173             :   SlotIndexes *Indexes;
     174             :   LiveIntervals *LIS;
     175             :   VirtRegMap *VRM;
     176             : 
     177             :   void rewrite();
     178             :   void addMBBLiveIns();
     179             :   bool readsUndefSubreg(const MachineOperand &MO) const;
     180             :   void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const;
     181             :   void handleIdentityCopy(MachineInstr &MI) const;
     182             :   void expandCopyBundle(MachineInstr &MI) const;
     183             :   bool subRegLiveThrough(const MachineInstr &MI, unsigned SuperPhysReg) const;
     184             : 
     185             : public:
     186             :   static char ID;
     187       15400 :   VirtRegRewriter() : MachineFunctionPass(ID) {}
     188             : 
     189             :   void getAnalysisUsage(AnalysisUsage &AU) const override;
     190             : 
     191             :   bool runOnMachineFunction(MachineFunction&) override;
     192       15354 :   MachineFunctionProperties getSetProperties() const override {
     193       46062 :     return MachineFunctionProperties().set(
     194       46062 :         MachineFunctionProperties::Property::NoVRegs);
     195             :   }
     196             : };
     197             : } // end anonymous namespace
     198             : 
     199             : char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
     200             : 
     201       20212 : INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
     202             :                       "Virtual Register Rewriter", false, false)
     203       20212 : INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
     204       20212 : INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
     205       20212 : INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
     206       20212 : INITIALIZE_PASS_DEPENDENCY(LiveStacks)
     207       20212 : INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
     208      151199 : INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
     209             :                     "Virtual Register Rewriter", false, false)
     210             : 
     211             : char VirtRegRewriter::ID = 0;
     212             : 
     213       15350 : void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
     214       15350 :   AU.setPreservesCFG();
     215       15350 :   AU.addRequired<LiveIntervals>();
     216       15350 :   AU.addRequired<SlotIndexes>();
     217       15350 :   AU.addPreserved<SlotIndexes>();
     218       15350 :   AU.addRequired<LiveDebugVariables>();
     219       15350 :   AU.addRequired<LiveStacks>();
     220       15350 :   AU.addPreserved<LiveStacks>();
     221       15350 :   AU.addRequired<VirtRegMap>();
     222       15350 :   MachineFunctionPass::getAnalysisUsage(AU);
     223       15350 : }
     224             : 
     225      134820 : bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
     226      134820 :   MF = &fn;
     227      134820 :   TM = &MF->getTarget();
     228      134820 :   TRI = MF->getSubtarget().getRegisterInfo();
     229      134820 :   TII = MF->getSubtarget().getInstrInfo();
     230      134820 :   MRI = &MF->getRegInfo();
     231      134820 :   Indexes = &getAnalysis<SlotIndexes>();
     232      134820 :   LIS = &getAnalysis<LiveIntervals>();
     233      134820 :   VRM = &getAnalysis<VirtRegMap>();
     234             :   DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
     235             :                << "********** Function: "
     236             :                << MF->getName() << '\n');
     237             :   DEBUG(VRM->dump());
     238             : 
     239             :   // Add kill flags while we still have virtual registers.
     240      134820 :   LIS->addKillFlags(VRM);
     241             : 
     242             :   // Live-in lists on basic blocks are required for physregs.
     243      134820 :   addMBBLiveIns();
     244             : 
     245             :   // Rewrite virtual registers.
     246      134820 :   rewrite();
     247             : 
     248             :   // Write out new DBG_VALUE instructions.
     249      134820 :   getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
     250             : 
     251             :   // All machine operands and other references to virtual registers have been
     252             :   // replaced. Remove the virtual registers and release all the transient data.
     253      269640 :   VRM->clearAllVirt();
     254      134820 :   MRI->clearVirtRegs();
     255      134820 :   return true;
     256             : }
     257             : 
     258         677 : void VirtRegRewriter::addLiveInsForSubRanges(const LiveInterval &LI,
     259             :                                              unsigned PhysReg) const {
     260             :   assert(!LI.empty());
     261             :   assert(LI.hasSubRanges());
     262             : 
     263             :   typedef std::pair<const LiveInterval::SubRange *,
     264             :                     LiveInterval::const_iterator> SubRangeIteratorPair;
     265        1354 :   SmallVector<SubRangeIteratorPair, 4> SubRanges;
     266         677 :   SlotIndex First;
     267         677 :   SlotIndex Last;
     268        3583 :   for (const LiveInterval::SubRange &SR : LI.subranges()) {
     269        6687 :     SubRanges.push_back(std::make_pair(&SR, SR.begin()));
     270        5333 :     if (!First.isValid() || SR.segments.front().start < First)
     271        1716 :       First = SR.segments.front().start;
     272        5333 :     if (!Last.isValid() || SR.segments.back().end > Last)
     273        1588 :       Last = SR.segments.back().end;
     274             :   }
     275             : 
     276             :   // Check all mbb start positions between First and Last while
     277             :   // simulatenously advancing an iterator for each subrange.
     278        3400 :   for (SlotIndexes::MBBIndexIterator MBBI = Indexes->findMBBIndex(First);
     279        7672 :        MBBI != Indexes->MBBIndexEnd() && MBBI->first <= Last; ++MBBI) {
     280        2046 :     SlotIndex MBBBegin = MBBI->first;
     281             :     // Advance all subrange iterators so that their end position is just
     282             :     // behind MBBBegin (or the iterator is at the end).
     283        2046 :     LaneBitmask LaneMask;
     284       12648 :     for (auto &RangeIterPair : SubRanges) {
     285        6510 :       const LiveInterval::SubRange *SR = RangeIterPair.first;
     286        6510 :       LiveInterval::const_iterator &SRI = RangeIterPair.second;
     287       23487 :       while (SRI != SR->end() && SRI->end <= MBBBegin)
     288        1574 :         ++SRI;
     289       13785 :       if (SRI == SR->end())
     290             :         continue;
     291       11490 :       if (SRI->start <= MBBBegin)
     292             :         LaneMask |= SR->LaneMask;
     293             :     }
     294        2046 :     if (LaneMask.none())
     295         291 :       continue;
     296        1755 :     MachineBasicBlock *MBB = MBBI->second;
     297        3510 :     MBB->addLiveIn(PhysReg, LaneMask);
     298             :   }
     299         677 : }
     300             : 
     301             : // Compute MBB live-in lists from virtual register live ranges and their
     302             : // assignments.
     303      134820 : void VirtRegRewriter::addMBBLiveIns() {
     304     2704104 :   for (unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
     305     2434464 :     unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx);
     306     4868928 :     if (MRI->reg_nodbg_empty(VirtReg))
     307     1255358 :       continue;
     308     1179106 :     LiveInterval &LI = LIS->getInterval(VirtReg);
     309     2358212 :     if (LI.empty() || LIS->intervalIsInOneMBB(LI))
     310     1096036 :       continue;
     311             :     // This is a virtual register that is live across basic blocks. Its
     312             :     // assigned PhysReg must be marked as live-in to those blocks.
     313      166140 :     unsigned PhysReg = VRM->getPhys(VirtReg);
     314             :     assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
     315             : 
     316       83070 :     if (LI.hasSubRanges()) {
     317         677 :       addLiveInsForSubRanges(LI, PhysReg);
     318             :     } else {
     319             :       // Go over MBB begin positions and see if we have segments covering them.
     320             :       // The following works because segments and the MBBIndex list are both
     321             :       // sorted by slot indexes.
     322      164786 :       SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin();
     323      480447 :       for (const auto &Seg : LI) {
     324      466536 :         I = Indexes->advanceMBBIndex(I, Seg.start);
     325     2082212 :         for (; I != Indexes->MBBIndexEnd() && I->first < Seg.end; ++I) {
     326      350349 :           MachineBasicBlock *MBB = I->second;
     327      700698 :           MBB->addLiveIn(PhysReg);
     328             :         }
     329             :       }
     330             :     }
     331             :   }
     332             : 
     333             :   // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
     334             :   // each MBB's LiveIns set before calling addLiveIn on them.
     335      687469 :   for (MachineBasicBlock &MBB : *MF)
     336      283009 :     MBB.sortUniqueLiveIns();
     337      134820 : }
     338             : 
     339             : /// Returns true if the given machine operand \p MO only reads undefined lanes.
     340             : /// The function only works for use operands with a subregister set.
     341       72217 : bool VirtRegRewriter::readsUndefSubreg(const MachineOperand &MO) const {
     342             :   // Shortcut if the operand is already marked undef.
     343       72217 :   if (MO.isUndef())
     344             :     return true;
     345             : 
     346       72087 :   unsigned Reg = MO.getReg();
     347       72087 :   const LiveInterval &LI = LIS->getInterval(Reg);
     348       72087 :   const MachineInstr &MI = *MO.getParent();
     349      144174 :   SlotIndex BaseIndex = LIS->getInstructionIndex(MI);
     350             :   // This code is only meant to handle reading undefined subregisters which
     351             :   // we couldn't properly detect before.
     352             :   assert(LI.liveAt(BaseIndex) &&
     353             :          "Reads of completely dead register should be marked undef already");
     354       72087 :   unsigned SubRegIdx = MO.getSubReg();
     355             :   assert(SubRegIdx != 0 && LI.hasSubRanges());
     356      144174 :   LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
     357             :   // See if any of the relevant subregister liveranges is defined at this point.
     358      234193 :   for (const LiveInterval::SubRange &SR : LI.subranges()) {
     359      324212 :     if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex))
     360             :       return false;
     361             :   }
     362             :   return true;
     363             : }
     364             : 
     365     3598538 : void VirtRegRewriter::handleIdentityCopy(MachineInstr &MI) const {
     366      552582 :   if (!MI.isIdentityCopy())
     367             :     return;
     368             :   DEBUG(dbgs() << "Identity copy: " << MI);
     369      552582 :   ++NumIdCopies;
     370             : 
     371             :   // Copies like:
     372             :   //    %R0 = COPY %R0<undef>
     373             :   //    %AL = COPY %AL, %EAX<imp-def>
     374             :   // give us additional liveness information: The target (super-)register
     375             :   // must not be valid before this point. Replace the COPY with a KILL
     376             :   // instruction to maintain this information.
     377     1105164 :   if (MI.getOperand(0).isUndef() || MI.getNumOperands() > 2) {
     378       16540 :     MI.setDesc(TII->get(TargetOpcode::KILL));
     379             :     DEBUG(dbgs() << "  replace by: " << MI);
     380             :     return;
     381             :   }
     382             : 
     383      544312 :   if (Indexes)
     384      544312 :     Indexes->removeSingleMachineInstrFromMaps(MI);
     385      544312 :   MI.eraseFromBundle();
     386             :   DEBUG(dbgs() << "  deleted.\n");
     387             : }
     388             : 
     389             : /// The liverange splitting logic sometimes produces bundles of copies when
     390             : /// subregisters are involved. Expand these into a sequence of copy instructions
     391             : /// after processing the last in the bundle. Does not update LiveIntervals
     392             : /// which we shouldn't need for this instruction anymore.
     393     3598538 : void VirtRegRewriter::expandCopyBundle(MachineInstr &MI) const {
     394     3598538 :   if (!MI.isCopy())
     395             :     return;
     396             : 
     397      723472 :   if (MI.isBundledWithPred() && !MI.isBundledWithSucc()) {
     398             :     // Only do this when the complete bundle is made out of COPYs.
     399           1 :     MachineBasicBlock &MBB = *MI.getParent();
     400             :     for (MachineBasicBlock::reverse_instr_iterator I =
     401           4 :          std::next(MI.getReverseIterator()), E = MBB.instr_rend();
     402           6 :          I != E && I->isBundledWithSucc(); ++I) {
     403           2 :       if (!I->isCopy())
     404             :         return;
     405             :     }
     406             : 
     407             :     for (MachineBasicBlock::reverse_instr_iterator I = MI.getReverseIterator();
     408           4 :          I->isBundledWithPred(); ) {
     409           1 :       MachineInstr &MI = *I;
     410           1 :       ++I;
     411             : 
     412           1 :       MI.unbundleFromPred();
     413           1 :       if (Indexes)
     414           1 :         Indexes->insertMachineInstrInMaps(MI);
     415             :     }
     416             :   }
     417             : }
     418             : 
     419             : /// Check whether (part of) \p SuperPhysReg is live through \p MI.
     420             : /// \pre \p MI defines a subregister of a virtual register that
     421             : /// has been assigned to \p SuperPhysReg.
     422       30567 : bool VirtRegRewriter::subRegLiveThrough(const MachineInstr &MI,
     423             :                                         unsigned SuperPhysReg) const {
     424       61134 :   SlotIndex MIIndex = LIS->getInstructionIndex(MI);
     425       30567 :   SlotIndex BeforeMIUses = MIIndex.getBaseIndex();
     426       30567 :   SlotIndex AfterMIDefs = MIIndex.getBoundaryIndex();
     427      109974 :   for (MCRegUnitIterator Unit(SuperPhysReg, TRI); Unit.isValid(); ++Unit) {
     428       98622 :     const LiveRange &UnitRange = LIS->getRegUnit(*Unit);
     429             :     // If the regunit is live both before and after MI,
     430             :     // we assume it is live through.
     431             :     // Generally speaking, this is not true, because something like
     432             :     // "RU = op RU" would match that description.
     433             :     // However, we know that we are trying to assess whether
     434             :     // a def of a virtual reg, vreg, is live at the same time of RU.
     435             :     // If we are in the "RU = op RU" situation, that means that vreg
     436             :     // is defined at the same time as RU (i.e., "vreg, RU = op RU").
     437             :     // Thus, vreg and RU interferes and vreg cannot be assigned to
     438             :     // SuperPhysReg. Therefore, this situation cannot happen.
     439       49311 :     if (UnitRange.liveAt(AfterMIDefs) && UnitRange.liveAt(BeforeMIUses))
     440             :       return true;
     441             :   }
     442             :   return false;
     443             : }
     444             : 
     445      134820 : void VirtRegRewriter::rewrite() {
     446      134820 :   bool NoSubRegLiveness = !MRI->subRegLivenessEnabled();
     447      269640 :   SmallVector<unsigned, 8> SuperDeads;
     448      269640 :   SmallVector<unsigned, 8> SuperDefs;
     449      269640 :   SmallVector<unsigned, 8> SuperKills;
     450             : 
     451      404460 :   for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
     452      417829 :        MBBI != MBBE; ++MBBI) {
     453             :     DEBUG(MBBI->print(dbgs(), Indexes));
     454     3598538 :     for (MachineBasicBlock::instr_iterator
     455     1132036 :            MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
     456     3598538 :       MachineInstr *MI = &*MII;
     457     3598538 :       ++MII;
     458             : 
     459    18374758 :       for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
     460     3598538 :            MOE = MI->operands_end(); MOI != MOE; ++MOI) {
     461    14776220 :         MachineOperand &MO = *MOI;
     462             : 
     463             :         // Make sure MRI knows about registers clobbered by regmasks.
     464    14776220 :         if (MO.isRegMask())
     465      186799 :           MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
     466             : 
     467    24257583 :         if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
     468    11059487 :           continue;
     469     3716733 :         unsigned VirtReg = MO.getReg();
     470     7433466 :         unsigned PhysReg = VRM->getPhys(VirtReg);
     471             :         assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
     472             :                "Instruction uses unmapped VirtReg");
     473             :         assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
     474             : 
     475             :         // Preserve semantics of sub-register operands.
     476     3716733 :         unsigned SubReg = MO.getSubReg();
     477     3716733 :         if (SubReg != 0) {
     478      277347 :           if (NoSubRegLiveness) {
     479             :             // A virtual register kill refers to the whole register, so we may
     480             :             // have to add <imp-use,kill> operands for the super-register.  A
     481             :             // partial redef always kills and redefines the super-register.
     482      172324 :             if ((MO.readsReg() && (MO.isDef() || MO.isKill())) ||
     483       76096 :                 (MO.isDef() && subRegLiveThrough(*MI, PhysReg)))
     484       63930 :               SuperKills.push_back(PhysReg);
     485             : 
     486      108988 :             if (MO.isDef()) {
     487             :               // Also add implicit defs for the super-register.
     488       60402 :               if (MO.isDead())
     489          55 :                 SuperDeads.push_back(PhysReg);
     490             :               else
     491       60347 :                 SuperDefs.push_back(PhysReg);
     492             :             }
     493             :           } else {
     494      168359 :             if (MO.isUse()) {
     495       72217 :               if (readsUndefSubreg(MO))
     496             :                 // We need to add an <undef> flag if the subregister is
     497             :                 // completely undefined (and we are not adding super-register
     498             :                 // defs).
     499             :                 MO.setIsUndef(true);
     500             :             } else if (!MO.isDead()) {
     501             :               assert(MO.isDef());
     502             :             }
     503             :           }
     504             : 
     505             :           // The <def,undef> and <def,internal> flags only make sense for
     506             :           // sub-register defs, and we are substituting a full physreg.  An
     507             :           // <imp-use,kill> operand from the SuperKills list will represent the
     508             :           // partial read of the super-register.
     509      277347 :           if (MO.isDef()) {
     510      156544 :             MO.setIsUndef(false);
     511             :             MO.setIsInternalRead(false);
     512             :           }
     513             : 
     514             :           // PhysReg operands cannot have subregister indexes.
     515      277347 :           PhysReg = TRI->getSubReg(PhysReg, SubReg);
     516             :           assert(PhysReg && "Invalid SubReg for physical register");
     517             :           MO.setSubReg(0);
     518             :         }
     519             :         // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
     520             :         // we need the inlining here.
     521     3716733 :         MO.setReg(PhysReg);
     522             :       }
     523             : 
     524             :       // Add any missing super-register kills after rewriting the whole
     525             :       // instruction.
     526       63930 :       while (!SuperKills.empty())
     527      127860 :         MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
     528             : 
     529          55 :       while (!SuperDeads.empty())
     530         110 :         MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
     531             : 
     532       60347 :       while (!SuperDefs.empty())
     533      120694 :         MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
     534             : 
     535             :       DEBUG(dbgs() << "> " << *MI);
     536             : 
     537     3598538 :       expandCopyBundle(*MI);
     538             : 
     539             :       // We can remove identity copies right now.
     540     3598538 :       handleIdentityCopy(*MI);
     541             :     }
     542             :   }
     543      134820 : }

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