LCOV - code coverage report
Current view: top level - lib/CodeGen - VirtRegMap.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 171 183 93.4 %
Date: 2018-02-17 17:14:17 Functions: 23 25 92.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map -----------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements the VirtRegMap class.
      11             : //
      12             : // It also contains implementations of the Spiller interface, which, given a
      13             : // virtual register map and a machine function, eliminates all virtual
      14             : // references by replacing them with physical register references - adding spill
      15             : // code as necessary.
      16             : //
      17             : //===----------------------------------------------------------------------===//
      18             : 
      19             : #include "llvm/CodeGen/VirtRegMap.h"
      20             : #include "LiveDebugVariables.h"
      21             : #include "llvm/ADT/SmallVector.h"
      22             : #include "llvm/ADT/Statistic.h"
      23             : #include "llvm/CodeGen/LiveInterval.h"
      24             : #include "llvm/CodeGen/LiveIntervals.h"
      25             : #include "llvm/CodeGen/LiveStacks.h"
      26             : #include "llvm/CodeGen/MachineBasicBlock.h"
      27             : #include "llvm/CodeGen/MachineFrameInfo.h"
      28             : #include "llvm/CodeGen/MachineFunction.h"
      29             : #include "llvm/CodeGen/MachineFunctionPass.h"
      30             : #include "llvm/CodeGen/MachineInstr.h"
      31             : #include "llvm/CodeGen/MachineOperand.h"
      32             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      33             : #include "llvm/CodeGen/SlotIndexes.h"
      34             : #include "llvm/CodeGen/TargetInstrInfo.h"
      35             : #include "llvm/CodeGen/TargetOpcodes.h"
      36             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      37             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      38             : #include "llvm/MC/LaneBitmask.h"
      39             : #include "llvm/Pass.h"
      40             : #include "llvm/Support/Compiler.h"
      41             : #include "llvm/Support/Debug.h"
      42             : #include "llvm/Support/raw_ostream.h"
      43             : #include <cassert>
      44             : #include <iterator>
      45             : #include <utility>
      46             : 
      47             : using namespace llvm;
      48             : 
      49             : #define DEBUG_TYPE "regalloc"
      50             : 
      51             : STATISTIC(NumSpillSlots, "Number of spill slots allocated");
      52             : STATISTIC(NumIdCopies,   "Number of identity moves eliminated after rewriting");
      53             : 
      54             : //===----------------------------------------------------------------------===//
      55             : //  VirtRegMap implementation
      56             : //===----------------------------------------------------------------------===//
      57             : 
      58             : char VirtRegMap::ID = 0;
      59             : 
      60      328596 : INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
      61             : 
      62      158641 : bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
      63      158641 :   MRI = &mf.getRegInfo();
      64      158641 :   TII = mf.getSubtarget().getInstrInfo();
      65      158641 :   TRI = mf.getSubtarget().getRegisterInfo();
      66      158641 :   MF = &mf;
      67             : 
      68             :   Virt2PhysMap.clear();
      69             :   Virt2StackSlotMap.clear();
      70             :   Virt2SplitMap.clear();
      71             : 
      72      158641 :   grow();
      73      158641 :   return false;
      74             : }
      75             : 
      76      440126 : void VirtRegMap::grow() {
      77      440126 :   unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
      78      440126 :   Virt2PhysMap.resize(NumRegs);
      79             :   Virt2StackSlotMap.resize(NumRegs);
      80             :   Virt2SplitMap.resize(NumRegs);
      81      440126 : }
      82             : 
      83     1328845 : void VirtRegMap::assignVirt2Phys(unsigned virtReg, MCPhysReg physReg) {
      84             :   assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
      85             :          TargetRegisterInfo::isPhysicalRegister(physReg));
      86             :   assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
      87             :          "attempt to assign physical register to already mapped "
      88             :          "virtual register");
      89             :   assert(!getRegInfo().isReserved(physReg) &&
      90             :          "Attempt to map virtReg to a reserved physReg");
      91     1328845 :   Virt2PhysMap[virtReg] = physReg;
      92     1328845 : }
      93             : 
      94       13718 : unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
      95       13718 :   unsigned Size = TRI->getSpillSize(*RC);
      96             :   unsigned Align = TRI->getSpillAlignment(*RC);
      97       13718 :   int SS = MF->getFrameInfo().CreateSpillStackObject(Size, Align);
      98             :   ++NumSpillSlots;
      99       13718 :   return SS;
     100             : }
     101             : 
     102      638243 : bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
     103      638243 :   unsigned Hint = MRI->getSimpleHint(VirtReg);
     104      638214 :   if (!Hint)
     105             :     return false;
     106      346058 :   if (TargetRegisterInfo::isVirtualRegister(Hint))
     107             :     Hint = getPhys(Hint);
     108      346058 :   return getPhys(VirtReg) == Hint;
     109             : }
     110             : 
     111     1366182 : bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
     112     1366182 :   std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
     113     1366182 :   if (TargetRegisterInfo::isPhysicalRegister(Hint.second))
     114             :     return true;
     115      787831 :   if (TargetRegisterInfo::isVirtualRegister(Hint.second))
     116      130941 :     return hasPhys(Hint.second);
     117             :   return false;
     118             : }
     119             : 
     120       13718 : int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
     121             :   assert(TargetRegisterInfo::isVirtualRegister(virtReg));
     122             :   assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
     123             :          "attempt to assign stack slot to already spilled register");
     124       13718 :   const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
     125       27436 :   return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
     126             : }
     127             : 
     128        9914 : void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
     129             :   assert(TargetRegisterInfo::isVirtualRegister(virtReg));
     130             :   assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
     131             :          "attempt to assign stack slot to already spilled register");
     132             :   assert((SS >= 0 ||
     133             :           (SS >= MF->getFrameInfo().getObjectIndexBegin())) &&
     134             :          "illegal fixed frame index");
     135        9914 :   Virt2StackSlotMap[virtReg] = SS;
     136        9914 : }
     137             : 
     138           0 : void VirtRegMap::print(raw_ostream &OS, const Module*) const {
     139           0 :   OS << "********** REGISTER MAP **********\n";
     140           0 :   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
     141             :     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
     142           0 :     if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
     143           0 :       OS << '[' << printReg(Reg, TRI) << " -> "
     144           0 :          << printReg(Virt2PhysMap[Reg], TRI) << "] "
     145           0 :          << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
     146             :     }
     147             :   }
     148             : 
     149           0 :   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
     150             :     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
     151           0 :     if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
     152           0 :       OS << '[' << printReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
     153           0 :          << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
     154             :     }
     155             :   }
     156             :   OS << '\n';
     157           0 : }
     158             : 
     159             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
     160             : LLVM_DUMP_METHOD void VirtRegMap::dump() const {
     161             :   print(dbgs());
     162             : }
     163             : #endif
     164             : 
     165             : //===----------------------------------------------------------------------===//
     166             : //                              VirtRegRewriter
     167             : //===----------------------------------------------------------------------===//
     168             : //
     169             : // The VirtRegRewriter is the last of the register allocator passes.
     170             : // It rewrites virtual registers to physical registers as specified in the
     171             : // VirtRegMap analysis. It also updates live-in information on basic blocks
     172             : // according to LiveIntervals.
     173             : //
     174             : namespace {
     175             : 
     176       17070 : class VirtRegRewriter : public MachineFunctionPass {
     177             :   MachineFunction *MF;
     178             :   const TargetRegisterInfo *TRI;
     179             :   const TargetInstrInfo *TII;
     180             :   MachineRegisterInfo *MRI;
     181             :   SlotIndexes *Indexes;
     182             :   LiveIntervals *LIS;
     183             :   VirtRegMap *VRM;
     184             : 
     185             :   void rewrite();
     186             :   void addMBBLiveIns();
     187             :   bool readsUndefSubreg(const MachineOperand &MO) const;
     188             :   void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const;
     189             :   void handleIdentityCopy(MachineInstr &MI) const;
     190             :   void expandCopyBundle(MachineInstr &MI) const;
     191             :   bool subRegLiveThrough(const MachineInstr &MI, unsigned SuperPhysReg) const;
     192             : 
     193             : public:
     194             :   static char ID;
     195             : 
     196       17163 :   VirtRegRewriter() : MachineFunctionPass(ID) {}
     197             : 
     198             :   void getAnalysisUsage(AnalysisUsage &AU) const override;
     199             : 
     200             :   bool runOnMachineFunction(MachineFunction&) override;
     201             : 
     202       17066 :   MachineFunctionProperties getSetProperties() const override {
     203       34132 :     return MachineFunctionProperties().set(
     204       17066 :         MachineFunctionProperties::Property::NoVRegs);
     205             :   }
     206             : };
     207             : 
     208             : } // end anonymous namespace
     209             : 
     210             : char VirtRegRewriter::ID = 0;
     211             : 
     212             : char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
     213             : 
     214       24288 : INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
     215             :                       "Virtual Register Rewriter", false, false)
     216       24288 : INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
     217       24288 : INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
     218       24288 : INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
     219       24288 : INITIALIZE_PASS_DEPENDENCY(LiveStacks)
     220       24288 : INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
     221      134278 : INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
     222             :                     "Virtual Register Rewriter", false, false)
     223             : 
     224       17062 : void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
     225       17062 :   AU.setPreservesCFG();
     226             :   AU.addRequired<LiveIntervals>();
     227             :   AU.addRequired<SlotIndexes>();
     228             :   AU.addPreserved<SlotIndexes>();
     229             :   AU.addRequired<LiveDebugVariables>();
     230             :   AU.addRequired<LiveStacks>();
     231             :   AU.addPreserved<LiveStacks>();
     232             :   AU.addRequired<VirtRegMap>();
     233       17062 :   MachineFunctionPass::getAnalysisUsage(AU);
     234       17062 : }
     235             : 
     236      158620 : bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
     237      158620 :   MF = &fn;
     238      158620 :   TRI = MF->getSubtarget().getRegisterInfo();
     239      158620 :   TII = MF->getSubtarget().getInstrInfo();
     240      158620 :   MRI = &MF->getRegInfo();
     241      158620 :   Indexes = &getAnalysis<SlotIndexes>();
     242      158620 :   LIS = &getAnalysis<LiveIntervals>();
     243      158620 :   VRM = &getAnalysis<VirtRegMap>();
     244             :   DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
     245             :                << "********** Function: "
     246             :                << MF->getName() << '\n');
     247             :   DEBUG(VRM->dump());
     248             : 
     249             :   // Add kill flags while we still have virtual registers.
     250      158620 :   LIS->addKillFlags(VRM);
     251             : 
     252             :   // Live-in lists on basic blocks are required for physregs.
     253      158620 :   addMBBLiveIns();
     254             : 
     255             :   // Rewrite virtual registers.
     256      158620 :   rewrite();
     257             : 
     258             :   // Write out new DBG_VALUE instructions.
     259      158620 :   getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
     260             : 
     261             :   // All machine operands and other references to virtual registers have been
     262             :   // replaced. Remove the virtual registers and release all the transient data.
     263      158620 :   VRM->clearAllVirt();
     264      158620 :   MRI->clearVirtRegs();
     265      158620 :   return true;
     266             : }
     267             : 
     268         758 : void VirtRegRewriter::addLiveInsForSubRanges(const LiveInterval &LI,
     269             :                                              unsigned PhysReg) const {
     270             :   assert(!LI.empty());
     271             :   assert(LI.hasSubRanges());
     272             : 
     273             :   using SubRangeIteratorPair =
     274             :       std::pair<const LiveInterval::SubRange *, LiveInterval::const_iterator>;
     275             : 
     276             :   SmallVector<SubRangeIteratorPair, 4> SubRanges;
     277             :   SlotIndex First;
     278             :   SlotIndex Last;
     279        3206 :   for (const LiveInterval::SubRange &SR : LI.subranges()) {
     280        2448 :     SubRanges.push_back(std::make_pair(&SR, SR.begin()));
     281        4138 :     if (!First.isValid() || SR.segments.front().start < First)
     282         945 :       First = SR.segments.front().start;
     283        4138 :     if (!Last.isValid() || SR.segments.back().end > Last)
     284         892 :       Last = SR.segments.back().end;
     285             :   }
     286             : 
     287             :   // Check all mbb start positions between First and Last while
     288             :   // simulatenously advancing an iterator for each subrange.
     289        3240 :   for (SlotIndexes::MBBIndexIterator MBBI = Indexes->findMBBIndex(First);
     290        9167 :        MBBI != Indexes->MBBIndexEnd() && MBBI->first <= Last; ++MBBI) {
     291             :     SlotIndex MBBBegin = MBBI->first;
     292             :     // Advance all subrange iterators so that their end position is just
     293             :     // behind MBBBegin (or the iterator is at the end).
     294             :     LaneBitmask LaneMask;
     295       18122 :     for (auto &RangeIterPair : SubRanges) {
     296        7820 :       const LiveInterval::SubRange *SR = RangeIterPair.first;
     297             :       LiveInterval::const_iterator &SRI = RangeIterPair.second;
     298       27877 :       while (SRI != SR->end() && SRI->end <= MBBBegin)
     299        1778 :         ++SRI;
     300        8737 :       if (SRI == SR->end())
     301             :         continue;
     302        6903 :       if (SRI->start <= MBBBegin)
     303             :         LaneMask |= SR->LaneMask;
     304             :     }
     305        2482 :     if (LaneMask.none())
     306             :       continue;
     307        2167 :     MachineBasicBlock *MBB = MBBI->second;
     308        2167 :     MBB->addLiveIn(PhysReg, LaneMask);
     309             :   }
     310         758 : }
     311             : 
     312             : // Compute MBB live-in lists from virtual register live ranges and their
     313             : // assignments.
     314      158620 : void VirtRegRewriter::addMBBLiveIns() {
     315     5482062 :   for (unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
     316             :     unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx);
     317     5164822 :     if (MRI->reg_nodbg_empty(VirtReg))
     318     1314430 :       continue;
     319     1267981 :     LiveInterval &LI = LIS->getInterval(VirtReg);
     320     1267981 :     if (LI.empty() || LIS->intervalIsInOneMBB(LI))
     321     1181167 :       continue;
     322             :     // This is a virtual register that is live across basic blocks. Its
     323             :     // assigned PhysReg must be marked as live-in to those blocks.
     324       86814 :     unsigned PhysReg = VRM->getPhys(VirtReg);
     325             :     assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
     326             : 
     327       86814 :     if (LI.hasSubRanges()) {
     328         758 :       addLiveInsForSubRanges(LI, PhysReg);
     329             :     } else {
     330             :       // Go over MBB begin positions and see if we have segments covering them.
     331             :       // The following works because segments and the MBBIndex list are both
     332             :       // sorted by slot indexes.
     333       86056 :       SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin();
     334      571882 :       for (const auto &Seg : LI) {
     335      242913 :         I = Indexes->advanceMBBIndex(I, Seg.start);
     336     2205381 :         for (; I != Indexes->MBBIndexEnd() && I->first < Seg.end; ++I) {
     337      374157 :           MachineBasicBlock *MBB = I->second;
     338      374157 :           MBB->addLiveIn(PhysReg);
     339             :         }
     340             :       }
     341             :     }
     342             :   }
     343             : 
     344             :   // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
     345             :   // each MBB's LiveIns set before calling addLiveIn on them.
     346      630046 :   for (MachineBasicBlock &MBB : *MF)
     347      312806 :     MBB.sortUniqueLiveIns();
     348      158620 : }
     349             : 
     350             : /// Returns true if the given machine operand \p MO only reads undefined lanes.
     351             : /// The function only works for use operands with a subregister set.
     352       70586 : bool VirtRegRewriter::readsUndefSubreg(const MachineOperand &MO) const {
     353             :   // Shortcut if the operand is already marked undef.
     354       70586 :   if (MO.isUndef())
     355             :     return true;
     356             : 
     357             :   unsigned Reg = MO.getReg();
     358       70469 :   const LiveInterval &LI = LIS->getInterval(Reg);
     359             :   const MachineInstr &MI = *MO.getParent();
     360      140938 :   SlotIndex BaseIndex = LIS->getInstructionIndex(MI);
     361             :   // This code is only meant to handle reading undefined subregisters which
     362             :   // we couldn't properly detect before.
     363             :   assert(LI.liveAt(BaseIndex) &&
     364             :          "Reads of completely dead register should be marked undef already");
     365             :   unsigned SubRegIdx = MO.getSubReg();
     366             :   assert(SubRegIdx != 0 && LI.hasSubRanges());
     367       70469 :   LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
     368             :   // See if any of the relevant subregister liveranges is defined at this point.
     369      162988 :   for (const LiveInterval::SubRange &SR : LI.subranges()) {
     370      162988 :     if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex))
     371             :       return false;
     372             :   }
     373             :   return true;
     374             : }
     375             : 
     376     3813778 : void VirtRegRewriter::handleIdentityCopy(MachineInstr &MI) const {
     377             :   if (!MI.isIdentityCopy())
     378             :     return;
     379             :   DEBUG(dbgs() << "Identity copy: " << MI);
     380             :   ++NumIdCopies;
     381             : 
     382             :   // Copies like:
     383             :   //    %r0 = COPY undef %r0
     384             :   //    %al = COPY %al, implicit-def %eax
     385             :   // give us additional liveness information: The target (super-)register
     386             :   // must not be valid before this point. Replace the COPY with a KILL
     387             :   // instruction to maintain this information.
     388      618974 :   if (MI.getOperand(0).isUndef() || MI.getNumOperands() > 2) {
     389       10525 :     MI.setDesc(TII->get(TargetOpcode::KILL));
     390             :     DEBUG(dbgs() << "  replace by: " << MI);
     391             :     return;
     392             :   }
     393             : 
     394      608449 :   if (Indexes)
     395      608449 :     Indexes->removeSingleMachineInstrFromMaps(MI);
     396      608449 :   MI.eraseFromBundle();
     397             :   DEBUG(dbgs() << "  deleted.\n");
     398             : }
     399             : 
     400             : /// The liverange splitting logic sometimes produces bundles of copies when
     401             : /// subregisters are involved. Expand these into a sequence of copy instructions
     402             : /// after processing the last in the bundle. Does not update LiveIntervals
     403             : /// which we shouldn't need for this instruction anymore.
     404     3813778 : void VirtRegRewriter::expandCopyBundle(MachineInstr &MI) const {
     405     3813778 :   if (!MI.isCopy())
     406             :     return;
     407             : 
     408      792141 :   if (MI.isBundledWithPred() && !MI.isBundledWithSucc()) {
     409             :     // Only do this when the complete bundle is made out of COPYs.
     410             :     MachineBasicBlock &MBB = *MI.getParent();
     411             :     for (MachineBasicBlock::reverse_instr_iterator I =
     412           1 :          std::next(MI.getReverseIterator()), E = MBB.instr_rend();
     413           2 :          I != E && I->isBundledWithSucc(); ++I) {
     414           1 :       if (!I->isCopy())
     415             :         return;
     416             :     }
     417             : 
     418             :     for (MachineBasicBlock::reverse_instr_iterator I = MI.getReverseIterator();
     419           2 :          I->isBundledWithPred(); ) {
     420             :       MachineInstr &MI = *I;
     421             :       ++I;
     422             : 
     423           1 :       MI.unbundleFromPred();
     424           1 :       if (Indexes)
     425           1 :         Indexes->insertMachineInstrInMaps(MI);
     426             :     }
     427             :   }
     428             : }
     429             : 
     430             : /// Check whether (part of) \p SuperPhysReg is live through \p MI.
     431             : /// \pre \p MI defines a subregister of a virtual register that
     432             : /// has been assigned to \p SuperPhysReg.
     433       33800 : bool VirtRegRewriter::subRegLiveThrough(const MachineInstr &MI,
     434             :                                         unsigned SuperPhysReg) const {
     435       33800 :   SlotIndex MIIndex = LIS->getInstructionIndex(MI);
     436       33800 :   SlotIndex BeforeMIUses = MIIndex.getBaseIndex();
     437       33800 :   SlotIndex AfterMIDefs = MIIndex.getBoundaryIndex();
     438      120185 :   for (MCRegUnitIterator Unit(SuperPhysReg, TRI); Unit.isValid(); ++Unit) {
     439      106292 :     const LiveRange &UnitRange = LIS->getRegUnit(*Unit);
     440             :     // If the regunit is live both before and after MI,
     441             :     // we assume it is live through.
     442             :     // Generally speaking, this is not true, because something like
     443             :     // "RU = op RU" would match that description.
     444             :     // However, we know that we are trying to assess whether
     445             :     // a def of a virtual reg, vreg, is live at the same time of RU.
     446             :     // If we are in the "RU = op RU" situation, that means that vreg
     447             :     // is defined at the same time as RU (i.e., "vreg, RU = op RU").
     448             :     // Thus, vreg and RU interferes and vreg cannot be assigned to
     449             :     // SuperPhysReg. Therefore, this situation cannot happen.
     450       53146 :     if (UnitRange.liveAt(AfterMIDefs) && UnitRange.liveAt(BeforeMIUses))
     451             :       return true;
     452             :   }
     453             :   return false;
     454             : }
     455             : 
     456      158620 : void VirtRegRewriter::rewrite() {
     457      158620 :   bool NoSubRegLiveness = !MRI->subRegLivenessEnabled();
     458             :   SmallVector<unsigned, 8> SuperDeads;
     459             :   SmallVector<unsigned, 8> SuperDefs;
     460             :   SmallVector<unsigned, 8> SuperKills;
     461             : 
     462      158620 :   for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
     463      471426 :        MBBI != MBBE; ++MBBI) {
     464             :     DEBUG(MBBI->print(dbgs(), Indexes));
     465     3813778 :     for (MachineBasicBlock::instr_iterator
     466     4126584 :            MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
     467             :       MachineInstr *MI = &*MII;
     468             :       ++MII;
     469             : 
     470    16615464 :       for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
     471    20429242 :            MOE = MI->operands_end(); MOI != MOE; ++MOI) {
     472             :         MachineOperand &MO = *MOI;
     473             : 
     474             :         // Make sure MRI knows about registers clobbered by regmasks.
     475    16615464 :         if (MO.isRegMask())
     476      193421 :           MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
     477             : 
     478    27714501 :         if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
     479    12649514 :           continue;
     480             :         unsigned VirtReg = MO.getReg();
     481     7931900 :         unsigned PhysReg = VRM->getPhys(VirtReg);
     482             :         assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
     483             :                "Instruction uses unmapped VirtReg");
     484             :         assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
     485             : 
     486             :         // Preserve semantics of sub-register operands.
     487             :         unsigned SubReg = MO.getSubReg();
     488     3965950 :         if (SubReg != 0) {
     489      282403 :           if (NoSubRegLiveness) {
     490             :             // A virtual register kill refers to the whole register, so we may
     491             :             // have to add implicit killed operands for the super-register.  A
     492             :             // partial redef always kills and redefines the super-register.
     493      177097 :             if ((MO.readsReg() && (MO.isDef() || MO.isKill())) ||
     494       33800 :                 (MO.isDef() && subRegLiveThrough(*MI, PhysReg)))
     495       64209 :               SuperKills.push_back(PhysReg);
     496             : 
     497      112946 :             if (MO.isDef()) {
     498             :               // Also add implicit defs for the super-register.
     499       64075 :               if (MO.isDead())
     500          70 :                 SuperDeads.push_back(PhysReg);
     501             :               else
     502       64005 :                 SuperDefs.push_back(PhysReg);
     503             :             }
     504             :           } else {
     505      169457 :             if (MO.isUse()) {
     506       70586 :               if (readsUndefSubreg(MO))
     507             :                 // We need to add an <undef> flag if the subregister is
     508             :                 // completely undefined (and we are not adding super-register
     509             :                 // defs).
     510             :                 MO.setIsUndef(true);
     511             :             } else if (!MO.isDead()) {
     512             :               assert(MO.isDef());
     513             :             }
     514             :           }
     515             : 
     516             :           // The def undef and def internal flags only make sense for
     517             :           // sub-register defs, and we are substituting a full physreg.  An
     518             :           // implicit killed operand from the SuperKills list will represent the
     519             :           // partial read of the super-register.
     520      282403 :           if (MO.isDef()) {
     521             :             MO.setIsUndef(false);
     522             :             MO.setIsInternalRead(false);
     523             :           }
     524             : 
     525             :           // PhysReg operands cannot have subregister indexes.
     526      282403 :           PhysReg = TRI->getSubReg(PhysReg, SubReg);
     527             :           assert(PhysReg && "Invalid SubReg for physical register");
     528             :           MO.setSubReg(0);
     529             :         }
     530             :         // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
     531             :         // we need the inlining here.
     532     3965950 :         MO.setReg(PhysReg);
     533     3965950 :         MO.setIsRenamableIfNoExtraRegAllocReq();
     534             :       }
     535             : 
     536             :       // Add any missing super-register kills after rewriting the whole
     537             :       // instruction.
     538       64209 :       while (!SuperKills.empty())
     539      128418 :         MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
     540             : 
     541          70 :       while (!SuperDeads.empty())
     542         140 :         MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
     543             : 
     544       64005 :       while (!SuperDefs.empty())
     545      128010 :         MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
     546             : 
     547             :       DEBUG(dbgs() << "> " << *MI);
     548             : 
     549     3813778 :       expandCopyBundle(*MI);
     550             : 
     551             :       // We can remove identity copies right now.
     552     3813778 :       handleIdentityCopy(*MI);
     553             :     }
     554             :   }
     555      158620 : }

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