LCOV - code coverage report
Current view: top level - lib/ExecutionEngine/RuntimeDyld/Targets - RuntimeDyldMachOAArch64.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 146 189 77.2 %
Date: 2017-09-14 15:23:50 Functions: 9 10 90.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- RuntimeDyldMachOAArch64.h -- MachO/AArch64 specific code. -*- C++ -*-=//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : 
      10             : #ifndef LLVM_LIB_EXECUTIONENGINE_RUNTIMEDYLD_TARGETS_RUNTIMEDYLDMACHOAARCH64_H
      11             : #define LLVM_LIB_EXECUTIONENGINE_RUNTIMEDYLD_TARGETS_RUNTIMEDYLDMACHOAARCH64_H
      12             : 
      13             : #include "../RuntimeDyldMachO.h"
      14             : #include "llvm/Support/Endian.h"
      15             : 
      16             : #define DEBUG_TYPE "dyld"
      17             : 
      18             : namespace llvm {
      19             : 
      20           2 : class RuntimeDyldMachOAArch64
      21             :     : public RuntimeDyldMachOCRTPBase<RuntimeDyldMachOAArch64> {
      22             : public:
      23             : 
      24             :   typedef uint64_t TargetPtrT;
      25             : 
      26             :   RuntimeDyldMachOAArch64(RuntimeDyld::MemoryManager &MM,
      27             :                           JITSymbolResolver &Resolver)
      28           2 :       : RuntimeDyldMachOCRTPBase(MM, Resolver) {}
      29             : 
      30           3 :   unsigned getMaxStubSize() override { return 8; }
      31             : 
      32           6 :   unsigned getStubAlignment() override { return 8; }
      33             : 
      34             :   /// Extract the addend encoded in the instruction / memory location.
      35           6 :   int64_t decodeAddend(const RelocationEntry &RE) const {
      36          12 :     const SectionEntry &Section = Sections[RE.SectionID];
      37          12 :     uint8_t *LocalAddress = Section.getAddressWithOffset(RE.Offset);
      38           6 :     unsigned NumBytes = 1 << RE.Size;
      39           6 :     int64_t Addend = 0;
      40             :     // Verify that the relocation has the correct size and alignment.
      41           6 :     switch (RE.RelType) {
      42           0 :     default:
      43           0 :       llvm_unreachable("Unsupported relocation type!");
      44             :     case MachO::ARM64_RELOC_UNSIGNED:
      45             :       assert((NumBytes == 4 || NumBytes == 8) && "Invalid relocation size.");
      46             :       break;
      47             :     case MachO::ARM64_RELOC_BRANCH26:
      48             :     case MachO::ARM64_RELOC_PAGE21:
      49             :     case MachO::ARM64_RELOC_PAGEOFF12:
      50             :     case MachO::ARM64_RELOC_GOT_LOAD_PAGE21:
      51             :     case MachO::ARM64_RELOC_GOT_LOAD_PAGEOFF12:
      52             :       assert(NumBytes == 4 && "Invalid relocation size.");
      53             :       assert((((uintptr_t)LocalAddress & 0x3) == 0) &&
      54             :              "Instruction address is not aligned to 4 bytes.");
      55             :       break;
      56             :     }
      57             : 
      58           6 :     switch (RE.RelType) {
      59           0 :     default:
      60           0 :       llvm_unreachable("Unsupported relocation type!");
      61           1 :     case MachO::ARM64_RELOC_UNSIGNED:
      62             :       // This could be an unaligned memory location.
      63           1 :       if (NumBytes == 4)
      64           0 :         Addend = *reinterpret_cast<support::ulittle32_t *>(LocalAddress);
      65             :       else
      66           1 :         Addend = *reinterpret_cast<support::ulittle64_t *>(LocalAddress);
      67             :       break;
      68           0 :     case MachO::ARM64_RELOC_BRANCH26: {
      69             :       // Verify that the relocation points to the expected branch instruction.
      70           0 :       auto *p = reinterpret_cast<support::aligned_ulittle32_t *>(LocalAddress);
      71             :       assert((*p & 0xFC000000) == 0x14000000 && "Expected branch instruction.");
      72             : 
      73             :       // Get the 26 bit addend encoded in the branch instruction and sign-extend
      74             :       // to 64 bit. The lower 2 bits are always zeros and are therefore implicit
      75             :       // (<< 2).
      76           0 :       Addend = (*p & 0x03FFFFFF) << 2;
      77           0 :       Addend = SignExtend64(Addend, 28);
      78           0 :       break;
      79             :     }
      80           2 :     case MachO::ARM64_RELOC_GOT_LOAD_PAGE21:
      81             :     case MachO::ARM64_RELOC_PAGE21: {
      82             :       // Verify that the relocation points to the expected adrp instruction.
      83           2 :       auto *p = reinterpret_cast<support::aligned_ulittle32_t *>(LocalAddress);
      84             :       assert((*p & 0x9F000000) == 0x90000000 && "Expected adrp instruction.");
      85             : 
      86             :       // Get the 21 bit addend encoded in the adrp instruction and sign-extend
      87             :       // to 64 bit. The lower 12 bits (4096 byte page) are always zeros and are
      88             :       // therefore implicit (<< 12).
      89           4 :       Addend = ((*p & 0x60000000) >> 29) | ((*p & 0x01FFFFE0) >> 3) << 12;
      90           4 :       Addend = SignExtend64(Addend, 33);
      91           2 :       break;
      92             :     }
      93             :     case MachO::ARM64_RELOC_GOT_LOAD_PAGEOFF12: {
      94             :       // Verify that the relocation points to one of the expected load / store
      95             :       // instructions.
      96             :       auto *p = reinterpret_cast<support::aligned_ulittle32_t *>(LocalAddress);
      97             :       (void)p;
      98             :       assert((*p & 0x3B000000) == 0x39000000 &&
      99             :              "Only expected load / store instructions.");
     100             :       LLVM_FALLTHROUGH;
     101             :     }
     102           3 :     case MachO::ARM64_RELOC_PAGEOFF12: {
     103             :       // Verify that the relocation points to one of the expected load / store
     104             :       // or add / sub instructions.
     105           3 :       auto *p = reinterpret_cast<support::aligned_ulittle32_t *>(LocalAddress);
     106             :       assert((((*p & 0x3B000000) == 0x39000000) ||
     107             :               ((*p & 0x11C00000) == 0x11000000)   ) &&
     108             :              "Expected load / store  or add/sub instruction.");
     109             : 
     110             :       // Get the 12 bit addend encoded in the instruction.
     111           3 :       Addend = (*p & 0x003FFC00) >> 10;
     112             : 
     113             :       // Check which instruction we are decoding to obtain the implicit shift
     114             :       // factor of the instruction.
     115           3 :       int ImplicitShift = 0;
     116           3 :       if ((*p & 0x3B000000) == 0x39000000) { // << load / store
     117             :         // For load / store instructions the size is encoded in bits 31:30.
     118           2 :         ImplicitShift = ((*p >> 30) & 0x3);
     119           2 :         if (ImplicitShift == 0) {
     120             :           // Check if this a vector op to get the correct shift value.
     121           0 :           if ((*p & 0x04800000) == 0x04800000)
     122           0 :             ImplicitShift = 4;
     123             :         }
     124             :       }
     125             :       // Compensate for implicit shift.
     126           3 :       Addend <<= ImplicitShift;
     127           3 :       break;
     128             :     }
     129             :     }
     130           6 :     return Addend;
     131             :   }
     132             : 
     133             :   /// Extract the addend encoded in the instruction.
     134           7 :   void encodeAddend(uint8_t *LocalAddress, unsigned NumBytes,
     135             :                     MachO::RelocationInfoType RelType, int64_t Addend) const {
     136             :     // Verify that the relocation has the correct alignment.
     137             :     switch (RelType) {
     138           0 :     default:
     139           0 :       llvm_unreachable("Unsupported relocation type!");
     140             :     case MachO::ARM64_RELOC_UNSIGNED:
     141             :       assert((NumBytes == 4 || NumBytes == 8) && "Invalid relocation size.");
     142             :       break;
     143             :     case MachO::ARM64_RELOC_BRANCH26:
     144             :     case MachO::ARM64_RELOC_PAGE21:
     145             :     case MachO::ARM64_RELOC_PAGEOFF12:
     146             :     case MachO::ARM64_RELOC_GOT_LOAD_PAGE21:
     147             :     case MachO::ARM64_RELOC_GOT_LOAD_PAGEOFF12:
     148             :       assert(NumBytes == 4 && "Invalid relocation size.");
     149             :       assert((((uintptr_t)LocalAddress & 0x3) == 0) &&
     150             :              "Instruction address is not aligned to 4 bytes.");
     151             :       break;
     152             :     }
     153             : 
     154           7 :     switch (RelType) {
     155           0 :     default:
     156           0 :       llvm_unreachable("Unsupported relocation type!");
     157           2 :     case MachO::ARM64_RELOC_UNSIGNED:
     158             :       // This could be an unaligned memory location.
     159           2 :       if (NumBytes == 4)
     160           0 :         *reinterpret_cast<support::ulittle32_t *>(LocalAddress) = Addend;
     161             :       else
     162           2 :         *reinterpret_cast<support::ulittle64_t *>(LocalAddress) = Addend;
     163             :       break;
     164           0 :     case MachO::ARM64_RELOC_BRANCH26: {
     165           0 :       auto *p = reinterpret_cast<support::aligned_ulittle32_t *>(LocalAddress);
     166             :       // Verify that the relocation points to the expected branch instruction.
     167             :       assert((*p & 0xFC000000) == 0x14000000 && "Expected branch instruction.");
     168             : 
     169             :       // Verify addend value.
     170             :       assert((Addend & 0x3) == 0 && "Branch target is not aligned");
     171             :       assert(isInt<28>(Addend) && "Branch target is out of range.");
     172             : 
     173             :       // Encode the addend as 26 bit immediate in the branch instruction.
     174           0 :       *p = (*p & 0xFC000000) | ((uint32_t)(Addend >> 2) & 0x03FFFFFF);
     175             :       break;
     176             :     }
     177           2 :     case MachO::ARM64_RELOC_GOT_LOAD_PAGE21:
     178             :     case MachO::ARM64_RELOC_PAGE21: {
     179             :       // Verify that the relocation points to the expected adrp instruction.
     180           2 :       auto *p = reinterpret_cast<support::aligned_ulittle32_t *>(LocalAddress);
     181             :       assert((*p & 0x9F000000) == 0x90000000 && "Expected adrp instruction.");
     182             : 
     183             :       // Check that the addend fits into 21 bits (+ 12 lower bits).
     184             :       assert((Addend & 0xFFF) == 0 && "ADRP target is not page aligned.");
     185             :       assert(isInt<33>(Addend) && "Invalid page reloc value.");
     186             : 
     187             :       // Encode the addend into the instruction.
     188           2 :       uint32_t ImmLoValue = ((uint64_t)Addend << 17) & 0x60000000;
     189           2 :       uint32_t ImmHiValue = ((uint64_t)Addend >> 9) & 0x00FFFFE0;
     190           2 :       *p = (*p & 0x9F00001F) | ImmHiValue | ImmLoValue;
     191             :       break;
     192             :     }
     193             :     case MachO::ARM64_RELOC_GOT_LOAD_PAGEOFF12: {
     194             :       // Verify that the relocation points to one of the expected load / store
     195             :       // instructions.
     196             :       auto *p = reinterpret_cast<support::aligned_ulittle32_t *>(LocalAddress);
     197             :       assert((*p & 0x3B000000) == 0x39000000 &&
     198             :              "Only expected load / store instructions.");
     199             :       (void)p;
     200             :       LLVM_FALLTHROUGH;
     201             :     }
     202           3 :     case MachO::ARM64_RELOC_PAGEOFF12: {
     203             :       // Verify that the relocation points to one of the expected load / store
     204             :       // or add / sub instructions.
     205           3 :       auto *p = reinterpret_cast<support::aligned_ulittle32_t *>(LocalAddress);
     206             :       assert((((*p & 0x3B000000) == 0x39000000) ||
     207             :               ((*p & 0x11C00000) == 0x11000000)   ) &&
     208             :              "Expected load / store  or add/sub instruction.");
     209             : 
     210             :       // Check which instruction we are decoding to obtain the implicit shift
     211             :       // factor of the instruction and verify alignment.
     212           3 :       int ImplicitShift = 0;
     213           3 :       if ((*p & 0x3B000000) == 0x39000000) { // << load / store
     214             :         // For load / store instructions the size is encoded in bits 31:30.
     215           2 :         ImplicitShift = ((*p >> 30) & 0x3);
     216           2 :         switch (ImplicitShift) {
     217           0 :         case 0:
     218             :           // Check if this a vector op to get the correct shift value.
     219           0 :           if ((*p & 0x04800000) == 0x04800000) {
     220           0 :             ImplicitShift = 4;
     221             :             assert(((Addend & 0xF) == 0) &&
     222             :                    "128-bit LDR/STR not 16-byte aligned.");
     223             :           }
     224             :           break;
     225             :         case 1:
     226             :           assert(((Addend & 0x1) == 0) && "16-bit LDR/STR not 2-byte aligned.");
     227             :           break;
     228             :         case 2:
     229             :           assert(((Addend & 0x3) == 0) && "32-bit LDR/STR not 4-byte aligned.");
     230             :           break;
     231             :         case 3:
     232             :           assert(((Addend & 0x7) == 0) && "64-bit LDR/STR not 8-byte aligned.");
     233             :           break;
     234             :         }
     235             :       }
     236             :       // Compensate for implicit shift.
     237           3 :       Addend >>= ImplicitShift;
     238             :       assert(isUInt<12>(Addend) && "Addend cannot be encoded.");
     239             : 
     240             :       // Encode the addend into the instruction.
     241           3 :       *p = (*p & 0xFFC003FF) | ((uint32_t)(Addend << 10) & 0x003FFC00);
     242             :       break;
     243             :     }
     244             :     }
     245           7 :   }
     246             : 
     247             :   Expected<relocation_iterator>
     248           7 :   processRelocationRef(unsigned SectionID, relocation_iterator RelI,
     249             :                        const ObjectFile &BaseObjT,
     250             :                        ObjSectionToIDMap &ObjSectionToID,
     251             :                        StubMap &Stubs) override {
     252           7 :     const MachOObjectFile &Obj =
     253             :       static_cast<const MachOObjectFile &>(BaseObjT);
     254             :     MachO::any_relocation_info RelInfo =
     255          14 :         Obj.getRelocation(RelI->getRawDataRefImpl());
     256             : 
     257           7 :     if (Obj.isRelocationScattered(RelInfo))
     258           0 :       return make_error<RuntimeDyldError>("Scattered relocations not supported "
     259           0 :                                           "for MachO AArch64");
     260             : 
     261             :     // ARM64 has an ARM64_RELOC_ADDEND relocation type that carries an explicit
     262             :     // addend for the following relocation. If found: (1) store the associated
     263             :     // addend, (2) consume the next relocation, and (3) use the stored addend to
     264             :     // override the addend.
     265           7 :     int64_t ExplicitAddend = 0;
     266           7 :     if (Obj.getAnyRelocationType(RelInfo) == MachO::ARM64_RELOC_ADDEND) {
     267             :       assert(!Obj.getPlainRelocationExternal(RelInfo));
     268             :       assert(!Obj.getAnyRelocationPCRel(RelInfo));
     269             :       assert(Obj.getAnyRelocationLength(RelInfo) == 2);
     270           1 :       int64_t RawAddend = Obj.getPlainRelocationSymbolNum(RelInfo);
     271             :       // Sign-extend the 24-bit to 64-bit.
     272           2 :       ExplicitAddend = SignExtend64(RawAddend, 24);
     273           1 :       ++RelI;
     274           2 :       RelInfo = Obj.getRelocation(RelI->getRawDataRefImpl());
     275             :     }
     276             : 
     277           7 :     if (Obj.getAnyRelocationType(RelInfo) == MachO::ARM64_RELOC_SUBTRACTOR)
     278           1 :       return processSubtractRelocation(SectionID, RelI, Obj, ObjSectionToID);
     279             : 
     280           6 :     RelocationEntry RE(getRelocationEntry(SectionID, Obj, RelI));
     281           6 :     RE.Addend = decodeAddend(RE);
     282             : 
     283             :     assert((ExplicitAddend == 0 || RE.Addend == 0) && "Relocation has "\
     284             :       "ARM64_RELOC_ADDEND and embedded addend in the instruction.");
     285           6 :     if (ExplicitAddend)
     286           1 :       RE.Addend = ExplicitAddend;
     287             : 
     288           6 :     RelocationValueRef Value;
     289          18 :     if (auto ValueOrErr = getRelocationValueRef(Obj, RelI, RE, ObjSectionToID))
     290           6 :       Value = *ValueOrErr;
     291             :     else
     292           0 :       return ValueOrErr.takeError();
     293             : 
     294           6 :     bool IsExtern = Obj.getPlainRelocationExternal(RelInfo);
     295           6 :     if (!IsExtern && RE.IsPCRel)
     296           0 :       makeValueAddendPCRel(Value, RelI, 1 << RE.Size);
     297             : 
     298           6 :     RE.Addend = Value.Offset;
     299             : 
     300           6 :     if (RE.RelType == MachO::ARM64_RELOC_GOT_LOAD_PAGE21 ||
     301             :         RE.RelType == MachO::ARM64_RELOC_GOT_LOAD_PAGEOFF12)
     302           2 :       processGOTRelocation(RE, Value, Stubs);
     303             :     else {
     304           4 :       if (Value.SymbolName)
     305           0 :         addRelocationForSymbol(RE, Value.SymbolName);
     306             :       else
     307           4 :         addRelocationForSection(RE, Value.SectionID);
     308             :     }
     309             : 
     310           6 :     return ++RelI;
     311             :   }
     312             : 
     313           8 :   void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override {
     314             :     DEBUG(dumpRelocationToResolve(RE, Value));
     315             : 
     316          16 :     const SectionEntry &Section = Sections[RE.SectionID];
     317          16 :     uint8_t *LocalAddress = Section.getAddressWithOffset(RE.Offset);
     318           8 :     MachO::RelocationInfoType RelType =
     319             :       static_cast<MachO::RelocationInfoType>(RE.RelType);
     320             : 
     321           8 :     switch (RelType) {
     322           0 :     default:
     323           0 :       llvm_unreachable("Invalid relocation type!");
     324           2 :     case MachO::ARM64_RELOC_UNSIGNED: {
     325             :       assert(!RE.IsPCRel && "PCRel and ARM64_RELOC_UNSIGNED not supported");
     326             :       // Mask in the target value a byte at a time (we don't have an alignment
     327             :       // guarantee for the target address, so this is safest).
     328           2 :       if (RE.Size < 2)
     329           0 :         llvm_unreachable("Invalid size for ARM64_RELOC_UNSIGNED");
     330             : 
     331           2 :       encodeAddend(LocalAddress, 1 << RE.Size, RelType, Value + RE.Addend);
     332           2 :       break;
     333             :     }
     334           0 :     case MachO::ARM64_RELOC_BRANCH26: {
     335             :       assert(RE.IsPCRel && "not PCRel and ARM64_RELOC_BRANCH26 not supported");
     336             :       // Check if branch is in range.
     337           0 :       uint64_t FinalAddress = Section.getLoadAddressWithOffset(RE.Offset);
     338           0 :       int64_t PCRelVal = Value - FinalAddress + RE.Addend;
     339           0 :       encodeAddend(LocalAddress, /*Size=*/4, RelType, PCRelVal);
     340           0 :       break;
     341             :     }
     342           2 :     case MachO::ARM64_RELOC_GOT_LOAD_PAGE21:
     343             :     case MachO::ARM64_RELOC_PAGE21: {
     344             :       assert(RE.IsPCRel && "not PCRel and ARM64_RELOC_PAGE21 not supported");
     345             :       // Adjust for PC-relative relocation and offset.
     346           4 :       uint64_t FinalAddress = Section.getLoadAddressWithOffset(RE.Offset);
     347           2 :       int64_t PCRelVal =
     348           2 :         ((Value + RE.Addend) & (-4096)) - (FinalAddress & (-4096));
     349           2 :       encodeAddend(LocalAddress, /*Size=*/4, RelType, PCRelVal);
     350           2 :       break;
     351             :     }
     352           3 :     case MachO::ARM64_RELOC_GOT_LOAD_PAGEOFF12:
     353             :     case MachO::ARM64_RELOC_PAGEOFF12: {
     354             :       assert(!RE.IsPCRel && "PCRel and ARM64_RELOC_PAGEOFF21 not supported");
     355             :       // Add the offset from the symbol.
     356           3 :       Value += RE.Addend;
     357             :       // Mask out the page address and only use the lower 12 bits.
     358           3 :       Value &= 0xFFF;
     359           3 :       encodeAddend(LocalAddress, /*Size=*/4, RelType, Value);
     360           3 :       break;
     361             :     }
     362           1 :     case MachO::ARM64_RELOC_SUBTRACTOR: {
     363           2 :       uint64_t SectionABase = Sections[RE.Sections.SectionA].getLoadAddress();
     364           2 :       uint64_t SectionBBase = Sections[RE.Sections.SectionB].getLoadAddress();
     365             :       assert((Value == SectionABase || Value == SectionBBase) &&
     366             :              "Unexpected SUBTRACTOR relocation value.");
     367           1 :       Value = SectionABase - SectionBBase + RE.Addend;
     368           1 :       writeBytesUnaligned(Value, LocalAddress, 1 << RE.Size);
     369           1 :       break;
     370             :     }
     371           0 :     case MachO::ARM64_RELOC_POINTER_TO_GOT:
     372             :     case MachO::ARM64_RELOC_TLVP_LOAD_PAGE21:
     373             :     case MachO::ARM64_RELOC_TLVP_LOAD_PAGEOFF12:
     374           0 :       llvm_unreachable("Relocation type not yet implemented!");
     375           0 :     case MachO::ARM64_RELOC_ADDEND:
     376           0 :       llvm_unreachable("ARM64_RELOC_ADDEND should have been handeled by "
     377             :                        "processRelocationRef!");
     378             :     }
     379           8 :   }
     380             : 
     381             :   Error finalizeSection(const ObjectFile &Obj, unsigned SectionID,
     382             :                        const SectionRef &Section) {
     383             :     return Error::success();
     384             :   }
     385             : 
     386             : private:
     387           2 :   void processGOTRelocation(const RelocationEntry &RE,
     388             :                             RelocationValueRef &Value, StubMap &Stubs) {
     389             :     assert(RE.Size == 2);
     390           4 :     SectionEntry &Section = Sections[RE.SectionID];
     391           4 :     StubMap::const_iterator i = Stubs.find(Value);
     392             :     int64_t Offset;
     393           2 :     if (i != Stubs.end())
     394           1 :       Offset = static_cast<int64_t>(i->second);
     395             :     else {
     396             :       // FIXME: There must be a better way to do this then to check and fix the
     397             :       // alignment every time!!!
     398           1 :       uintptr_t BaseAddress = uintptr_t(Section.getAddress());
     399           1 :       uintptr_t StubAlignment = getStubAlignment();
     400             :       uintptr_t StubAddress =
     401           1 :           (BaseAddress + Section.getStubOffset() + StubAlignment - 1) &
     402           1 :           -StubAlignment;
     403           1 :       unsigned StubOffset = StubAddress - BaseAddress;
     404           1 :       Stubs[Value] = StubOffset;
     405             :       assert(((StubAddress % getStubAlignment()) == 0) &&
     406             :              "GOT entry not aligned");
     407           1 :       RelocationEntry GOTRE(RE.SectionID, StubOffset,
     408           1 :                             MachO::ARM64_RELOC_UNSIGNED, Value.Offset,
     409           2 :                             /*IsPCRel=*/false, /*Size=*/3);
     410           1 :       if (Value.SymbolName)
     411           0 :         addRelocationForSymbol(GOTRE, Value.SymbolName);
     412             :       else
     413           1 :         addRelocationForSection(GOTRE, Value.SectionID);
     414           2 :       Section.advanceStubOffset(getMaxStubSize());
     415           1 :       Offset = static_cast<int64_t>(StubOffset);
     416             :     }
     417           2 :     RelocationEntry TargetRE(RE.SectionID, RE.Offset, RE.RelType, Offset,
     418           4 :                              RE.IsPCRel, RE.Size);
     419           2 :     addRelocationForSection(TargetRE, RE.SectionID);
     420           2 :   }
     421             : 
     422             :   Expected<relocation_iterator>
     423           1 :   processSubtractRelocation(unsigned SectionID, relocation_iterator RelI,
     424             :                             const ObjectFile &BaseObjT,
     425             :                             ObjSectionToIDMap &ObjSectionToID) {
     426           1 :     const MachOObjectFile &Obj =
     427             :         static_cast<const MachOObjectFile&>(BaseObjT);
     428             :     MachO::any_relocation_info RE =
     429           2 :         Obj.getRelocation(RelI->getRawDataRefImpl());
     430             : 
     431           1 :     unsigned Size = Obj.getAnyRelocationLength(RE);
     432           2 :     uint64_t Offset = RelI->getOffset();
     433           3 :     uint8_t *LocalAddress = Sections[SectionID].getAddressWithOffset(Offset);
     434           1 :     unsigned NumBytes = 1 << Size;
     435             : 
     436           5 :     Expected<StringRef> SubtrahendNameOrErr = RelI->getSymbol()->getName();
     437           1 :     if (!SubtrahendNameOrErr)
     438           0 :       return SubtrahendNameOrErr.takeError();
     439           2 :     auto SubtrahendI = GlobalSymbolTable.find(*SubtrahendNameOrErr);
     440           1 :     unsigned SectionBID = SubtrahendI->second.getSectionID();
     441           1 :     uint64_t SectionBOffset = SubtrahendI->second.getOffset();
     442             :     int64_t Addend =
     443           2 :       SignExtend64(readBytesUnaligned(LocalAddress, NumBytes), NumBytes * 8);
     444             : 
     445           1 :     ++RelI;
     446           4 :     Expected<StringRef> MinuendNameOrErr = RelI->getSymbol()->getName();
     447           1 :     if (!MinuendNameOrErr)
     448           0 :       return MinuendNameOrErr.takeError();
     449           2 :     auto MinuendI = GlobalSymbolTable.find(*MinuendNameOrErr);
     450           1 :     unsigned SectionAID = MinuendI->second.getSectionID();
     451           1 :     uint64_t SectionAOffset = MinuendI->second.getOffset();
     452             : 
     453             :     RelocationEntry R(SectionID, Offset, MachO::ARM64_RELOC_SUBTRACTOR, (uint64_t)Addend,
     454             :                       SectionAID, SectionAOffset, SectionBID, SectionBOffset,
     455           1 :                       false, Size);
     456             : 
     457           1 :     addRelocationForSection(R, SectionAID);
     458             : 
     459           1 :     return ++RelI;
     460             :   }
     461             : 
     462             : };
     463             : }
     464             : 
     465             : #undef DEBUG_TYPE
     466             : 
     467             : #endif

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