LCOV - code coverage report
Current view: top level - lib/Target/AArch64 - AArch64AsmPrinter.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 231 259 89.2 %
Date: 2018-02-23 15:42:53 Functions: 21 22 95.5 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer ---------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains a printer that converts from our internal representation
      11             : // of machine-dependent LLVM code to the AArch64 assembly language.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "AArch64.h"
      16             : #include "AArch64MCInstLower.h"
      17             : #include "AArch64MachineFunctionInfo.h"
      18             : #include "AArch64RegisterInfo.h"
      19             : #include "AArch64Subtarget.h"
      20             : #include "AArch64TargetObjectFile.h"
      21             : #include "InstPrinter/AArch64InstPrinter.h"
      22             : #include "MCTargetDesc/AArch64AddressingModes.h"
      23             : #include "MCTargetDesc/AArch64MCTargetDesc.h"
      24             : #include "Utils/AArch64BaseInfo.h"
      25             : #include "llvm/ADT/SmallString.h"
      26             : #include "llvm/ADT/SmallVector.h"
      27             : #include "llvm/ADT/StringRef.h"
      28             : #include "llvm/ADT/Triple.h"
      29             : #include "llvm/ADT/Twine.h"
      30             : #include "llvm/CodeGen/AsmPrinter.h"
      31             : #include "llvm/CodeGen/MachineBasicBlock.h"
      32             : #include "llvm/CodeGen/MachineFunction.h"
      33             : #include "llvm/CodeGen/MachineInstr.h"
      34             : #include "llvm/CodeGen/MachineOperand.h"
      35             : #include "llvm/CodeGen/StackMaps.h"
      36             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      37             : #include "llvm/IR/DataLayout.h"
      38             : #include "llvm/IR/DebugInfoMetadata.h"
      39             : #include "llvm/MC/MCAsmInfo.h"
      40             : #include "llvm/MC/MCContext.h"
      41             : #include "llvm/MC/MCInst.h"
      42             : #include "llvm/MC/MCInstBuilder.h"
      43             : #include "llvm/MC/MCStreamer.h"
      44             : #include "llvm/MC/MCSymbol.h"
      45             : #include "llvm/Support/Casting.h"
      46             : #include "llvm/Support/ErrorHandling.h"
      47             : #include "llvm/Support/TargetRegistry.h"
      48             : #include "llvm/Support/raw_ostream.h"
      49             : #include "llvm/Target/TargetMachine.h"
      50             : #include <algorithm>
      51             : #include <cassert>
      52             : #include <cstdint>
      53             : #include <map>
      54             : #include <memory>
      55             : 
      56             : using namespace llvm;
      57             : 
      58             : #define DEBUG_TYPE "asm-printer"
      59             : 
      60             : namespace {
      61             : 
      62        4124 : class AArch64AsmPrinter : public AsmPrinter {
      63             :   AArch64MCInstLower MCInstLowering;
      64             :   StackMaps SM;
      65             :   const AArch64Subtarget *STI;
      66             : 
      67             : public:
      68        1042 :   AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
      69        1042 :       : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this),
      70        4168 :         SM(*this) {}
      71             : 
      72          10 :   StringRef getPassName() const override { return "AArch64 Assembly Printer"; }
      73             : 
      74             :   /// \brief Wrapper for MCInstLowering.lowerOperand() for the
      75             :   /// tblgen'erated pseudo lowering.
      76             :   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
      77             :     return MCInstLowering.lowerOperand(MO, MCOp);
      78             :   }
      79             : 
      80             :   void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
      81             :                      const MachineInstr &MI);
      82             :   void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
      83             :                        const MachineInstr &MI);
      84             : 
      85             :   void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI);
      86             :   void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI);
      87             :   void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI);
      88             : 
      89             :   void EmitSled(const MachineInstr &MI, SledKind Kind);
      90             : 
      91             :   /// \brief tblgen'erated driver function for lowering simple MI->MC
      92             :   /// pseudo instructions.
      93             :   bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
      94             :                                    const MachineInstr *MI);
      95             : 
      96             :   void EmitInstruction(const MachineInstr *MI) override;
      97             : 
      98        1041 :   void getAnalysisUsage(AnalysisUsage &AU) const override {
      99        1041 :     AsmPrinter::getAnalysisUsage(AU);
     100             :     AU.setPreservesAll();
     101        1041 :   }
     102             : 
     103       13339 :   bool runOnMachineFunction(MachineFunction &F) override {
     104       13339 :     AArch64FI = F.getInfo<AArch64FunctionInfo>();
     105       13339 :     STI = static_cast<const AArch64Subtarget*>(&F.getSubtarget());
     106       13339 :     bool Result = AsmPrinter::runOnMachineFunction(F);
     107       13339 :     emitXRayTable();
     108       13339 :     return Result;
     109             :   }
     110             : 
     111             : private:
     112             :   void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O);
     113             :   bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
     114             :   bool printAsmRegInClass(const MachineOperand &MO,
     115             :                           const TargetRegisterClass *RC, bool isVector,
     116             :                           raw_ostream &O);
     117             : 
     118             :   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
     119             :                        unsigned AsmVariant, const char *ExtraCode,
     120             :                        raw_ostream &O) override;
     121             :   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
     122             :                              unsigned AsmVariant, const char *ExtraCode,
     123             :                              raw_ostream &O) override;
     124             : 
     125             :   void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
     126             : 
     127             :   void EmitFunctionBodyEnd() override;
     128             : 
     129             :   MCSymbol *GetCPISymbol(unsigned CPID) const override;
     130             :   void EmitEndOfAsmFile(Module &M) override;
     131             : 
     132             :   AArch64FunctionInfo *AArch64FI = nullptr;
     133             : 
     134             :   /// \brief Emit the LOHs contained in AArch64FI.
     135             :   void EmitLOHs();
     136             : 
     137             :   /// Emit instruction to set float register to zero.
     138             :   void EmitFMov0(const MachineInstr &MI);
     139             : 
     140             :   using MInstToMCSymbol = std::map<const MachineInstr *, MCSymbol *>;
     141             : 
     142             :   MInstToMCSymbol LOHInstToLabel;
     143             : };
     144             : 
     145             : } // end anonymous namespace
     146             : 
     147             : void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
     148             : {
     149           3 :   EmitSled(MI, SledKind::FUNCTION_ENTER);
     150             : }
     151             : 
     152             : void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
     153             : {
     154           3 :   EmitSled(MI, SledKind::FUNCTION_EXIT);
     155             : }
     156             : 
     157             : void AArch64AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
     158             : {
     159           0 :   EmitSled(MI, SledKind::TAIL_CALL);
     160             : }
     161             : 
     162           6 : void AArch64AsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
     163             : {
     164             :   static const int8_t NoopsInSledCount = 7;
     165             :   // We want to emit the following pattern:
     166             :   //
     167             :   // .Lxray_sled_N:
     168             :   //   ALIGN
     169             :   //   B #32
     170             :   //   ; 7 NOP instructions (28 bytes)
     171             :   // .tmpN
     172             :   //
     173             :   // We need the 28 bytes (7 instructions) because at runtime, we'd be patching
     174             :   // over the full 32 bytes (8 instructions) with the following pattern:
     175             :   //
     176             :   //   STP X0, X30, [SP, #-16]! ; push X0 and the link register to the stack
     177             :   //   LDR W0, #12 ; W0 := function ID
     178             :   //   LDR X16,#12 ; X16 := addr of __xray_FunctionEntry or __xray_FunctionExit
     179             :   //   BLR X16 ; call the tracing trampoline
     180             :   //   ;DATA: 32 bits of function ID
     181             :   //   ;DATA: lower 32 bits of the address of the trampoline
     182             :   //   ;DATA: higher 32 bits of the address of the trampoline
     183             :   //   LDP X0, X30, [SP], #16 ; pop X0 and the link register from the stack
     184             :   //
     185           6 :   OutStreamer->EmitCodeAlignment(4);
     186          12 :   auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
     187           6 :   OutStreamer->EmitLabel(CurSled);
     188           6 :   auto Target = OutContext.createTempSymbol();
     189             : 
     190             :   // Emit "B #32" instruction, which jumps over the next 28 bytes.
     191             :   // The operand has to be the number of 4-byte instructions to jump over,
     192             :   // including the current instruction.
     193          18 :   EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8));
     194             : 
     195          90 :   for (int8_t I = 0; I < NoopsInSledCount; I++)
     196          84 :     EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
     197             : 
     198           6 :   OutStreamer->EmitLabel(Target);
     199           6 :   recordSled(CurSled, MI, Kind);
     200           6 : }
     201             : 
     202        1030 : void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) {
     203        1030 :   const Triple &TT = TM.getTargetTriple();
     204        1030 :   if (TT.isOSBinFormatMachO()) {
     205             :     // Funny Darwin hack: This flag tells the linker that no global symbols
     206             :     // contain code that falls through to other global symbols (e.g. the obvious
     207             :     // implementation of multiple entry points).  If this doesn't occur, the
     208             :     // linker can safely perform dead code stripping.  Since LLVM never
     209             :     // generates code that does this, it is always safe to set.
     210         297 :     OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
     211         297 :     SM.serializeToStackMapSection();
     212             :   }
     213        1030 : }
     214             : 
     215         154 : void AArch64AsmPrinter::EmitLOHs() {
     216             :   SmallVector<MCSymbol *, 3> MCArgs;
     217             : 
     218         742 :   for (const auto &D : AArch64FI->getLOHContainer()) {
     219        1195 :     for (const MachineInstr *MI : D.getArgs()) {
     220             :       MInstToMCSymbol::iterator LabelIt = LOHInstToLabel.find(MI);
     221             :       assert(LabelIt != LOHInstToLabel.end() &&
     222             :              "Label hasn't been inserted for LOH related instruction");
     223         489 :       MCArgs.push_back(LabelIt->second);
     224             :     }
     225         217 :     OutStreamer->EmitLOHDirective(D.getKind(), MCArgs);
     226             :     MCArgs.clear();
     227             :   }
     228         154 : }
     229             : 
     230       13339 : void AArch64AsmPrinter::EmitFunctionBodyEnd() {
     231       26678 :   if (!AArch64FI->getLOHRelated().empty())
     232         154 :     EmitLOHs();
     233       13339 : }
     234             : 
     235             : /// GetCPISymbol - Return the symbol for the specified constant pool entry.
     236         338 : MCSymbol *AArch64AsmPrinter::GetCPISymbol(unsigned CPID) const {
     237             :   // Darwin uses a linker-private symbol name for constant-pools (to
     238             :   // avoid addends on the relocation?), ELF has no such concept and
     239             :   // uses a normal private symbol.
     240         676 :   if (!getDataLayout().getLinkerPrivateGlobalPrefix().empty())
     241         102 :     return OutContext.getOrCreateSymbol(
     242         306 :         Twine(getDataLayout().getLinkerPrivateGlobalPrefix()) + "CPI" +
     243         306 :         Twine(getFunctionNumber()) + "_" + Twine(CPID));
     244             : 
     245         236 :   return OutContext.getOrCreateSymbol(
     246         472 :       Twine(getDataLayout().getPrivateGlobalPrefix()) + "CPI" +
     247         708 :       Twine(getFunctionNumber()) + "_" + Twine(CPID));
     248             : }
     249             : 
     250          29 : void AArch64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum,
     251             :                                      raw_ostream &O) {
     252          29 :   const MachineOperand &MO = MI->getOperand(OpNum);
     253          29 :   switch (MO.getType()) {
     254           0 :   default:
     255           0 :     llvm_unreachable("<unknown operand type>");
     256           0 :   case MachineOperand::MO_Register: {
     257           0 :     unsigned Reg = MO.getReg();
     258             :     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
     259             :     assert(!MO.getSubReg() && "Subregs should be eliminated!");
     260           0 :     O << AArch64InstPrinter::getRegisterName(Reg);
     261           0 :     break;
     262             :   }
     263          23 :   case MachineOperand::MO_Immediate: {
     264          23 :     int64_t Imm = MO.getImm();
     265          23 :     O << '#' << Imm;
     266          23 :     break;
     267             :   }
     268           6 :   case MachineOperand::MO_GlobalAddress: {
     269           6 :     const GlobalValue *GV = MO.getGlobal();
     270           6 :     MCSymbol *Sym = getSymbol(GV);
     271             : 
     272             :     // FIXME: Can we get anything other than a plain symbol here?
     273             :     assert(!MO.getTargetFlags() && "Unknown operand target flag!");
     274             : 
     275           6 :     Sym->print(O, MAI);
     276          12 :     printOffset(MO.getOffset(), O);
     277           6 :     break;
     278             :   }
     279             :   }
     280          29 : }
     281             : 
     282          53 : bool AArch64AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode,
     283             :                                           raw_ostream &O) {
     284          53 :   unsigned Reg = MO.getReg();
     285          53 :   switch (Mode) {
     286             :   default:
     287             :     return true; // Unknown mode.
     288          22 :   case 'w':
     289          22 :     Reg = getWRegFromXReg(Reg);
     290          22 :     break;
     291          31 :   case 'x':
     292          31 :     Reg = getXRegFromWReg(Reg);
     293          31 :     break;
     294             :   }
     295             : 
     296          53 :   O << AArch64InstPrinter::getRegisterName(Reg);
     297          53 :   return false;
     298             : }
     299             : 
     300             : // Prints the register in MO using class RC using the offset in the
     301             : // new register class. This should not be used for cross class
     302             : // printing.
     303          20 : bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO,
     304             :                                            const TargetRegisterClass *RC,
     305             :                                            bool isVector, raw_ostream &O) {
     306             :   assert(MO.isReg() && "Should only get here with a register!");
     307          20 :   const TargetRegisterInfo *RI = STI->getRegisterInfo();
     308          20 :   unsigned Reg = MO.getReg();
     309          40 :   unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
     310             :   assert(RI->regsOverlap(RegToPrint, Reg));
     311          20 :   O << AArch64InstPrinter::getRegisterName(
     312          20 :            RegToPrint, isVector ? AArch64::vreg : AArch64::NoRegAltName);
     313          20 :   return false;
     314             : }
     315             : 
     316         107 : bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
     317             :                                         unsigned AsmVariant,
     318             :                                         const char *ExtraCode, raw_ostream &O) {
     319         107 :   const MachineOperand &MO = MI->getOperand(OpNum);
     320             : 
     321             :   // First try the generic code, which knows about modifiers like 'c' and 'n'.
     322         107 :   if (!AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O))
     323             :     return false;
     324             : 
     325             :   // Does this asm operand have a single letter operand modifier?
     326         105 :   if (ExtraCode && ExtraCode[0]) {
     327          42 :     if (ExtraCode[1] != 0)
     328             :       return true; // Unknown modifier.
     329             : 
     330          42 :     switch (ExtraCode[0]) {
     331             :     default:
     332             :       return true; // Unknown modifier.
     333           1 :     case 'a':      // Print 'a' modifier
     334           1 :       PrintAsmMemoryOperand(MI, OpNum, AsmVariant, ExtraCode, O);
     335           1 :       return false;
     336             :     case 'w':      // Print W register
     337             :     case 'x':      // Print X register
     338          29 :       if (MO.isReg())
     339          27 :         return printAsmMRegister(MO, ExtraCode[0], O);
     340           2 :       if (MO.isImm() && MO.getImm() == 0) {
     341           2 :         unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR;
     342           2 :         O << AArch64InstPrinter::getRegisterName(Reg);
     343           2 :         return false;
     344             :       }
     345           0 :       printOperand(MI, OpNum, O);
     346           0 :       return false;
     347             :     case 'b': // Print B register.
     348             :     case 'h': // Print H register.
     349             :     case 's': // Print S register.
     350             :     case 'd': // Print D register.
     351             :     case 'q': // Print Q register.
     352          12 :       if (MO.isReg()) {
     353             :         const TargetRegisterClass *RC;
     354          12 :         switch (ExtraCode[0]) {
     355             :         case 'b':
     356             :           RC = &AArch64::FPR8RegClass;
     357             :           break;
     358           4 :         case 'h':
     359             :           RC = &AArch64::FPR16RegClass;
     360           4 :           break;
     361           5 :         case 's':
     362             :           RC = &AArch64::FPR32RegClass;
     363           5 :           break;
     364           1 :         case 'd':
     365             :           RC = &AArch64::FPR64RegClass;
     366           1 :           break;
     367           1 :         case 'q':
     368             :           RC = &AArch64::FPR128RegClass;
     369           1 :           break;
     370             :         default:
     371             :           return true;
     372             :         }
     373          12 :         return printAsmRegInClass(MO, RC, false /* vector */, O);
     374           0 :       }
     375           0 :       printOperand(MI, OpNum, O);
     376           0 :       return false;
     377             :     }
     378             :   }
     379             : 
     380             :   // According to ARM, we should emit x and v registers unless we have a
     381             :   // modifier.
     382          63 :   if (MO.isReg()) {
     383          34 :     unsigned Reg = MO.getReg();
     384             : 
     385             :     // If this is a w or x register, print an x register.
     386          78 :     if (AArch64::GPR32allRegClass.contains(Reg) ||
     387          21 :         AArch64::GPR64allRegClass.contains(Reg))
     388          26 :       return printAsmMRegister(MO, 'x', O);
     389             : 
     390             :     // If this is a b, h, s, d, or q register, print it as a v register.
     391             :     return printAsmRegInClass(MO, &AArch64::FPR128RegClass, true /* vector */,
     392           8 :                               O);
     393             :   }
     394             : 
     395          29 :   printOperand(MI, OpNum, O);
     396          29 :   return false;
     397             : }
     398             : 
     399           3 : bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
     400             :                                               unsigned OpNum,
     401             :                                               unsigned AsmVariant,
     402             :                                               const char *ExtraCode,
     403             :                                               raw_ostream &O) {
     404           3 :   if (ExtraCode && ExtraCode[0] && ExtraCode[0] != 'a')
     405             :     return true; // Unknown modifier.
     406             : 
     407           3 :   const MachineOperand &MO = MI->getOperand(OpNum);
     408             :   assert(MO.isReg() && "unexpected inline asm memory operand");
     409           3 :   O << "[" << AArch64InstPrinter::getRegisterName(MO.getReg()) << "]";
     410           3 :   return false;
     411             : }
     412             : 
     413           0 : void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
     414             :                                                raw_ostream &OS) {
     415           0 :   unsigned NOps = MI->getNumOperands();
     416             :   assert(NOps == 4);
     417           0 :   OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
     418             :   // cast away const; DIetc do not take const operands for some reason.
     419           0 :   OS << cast<DILocalVariable>(MI->getOperand(NOps - 2).getMetadata())
     420             :             ->getName();
     421           0 :   OS << " <- ";
     422             :   // Frame address.  Currently handles register +- offset only.
     423             :   assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
     424             :   OS << '[';
     425           0 :   printOperand(MI, 0, OS);
     426             :   OS << '+';
     427           0 :   printOperand(MI, 1, OS);
     428             :   OS << ']';
     429           0 :   OS << "+";
     430           0 :   printOperand(MI, NOps - 2, OS);
     431           0 : }
     432             : 
     433          15 : void AArch64AsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
     434             :                                       const MachineInstr &MI) {
     435          30 :   unsigned NumNOPBytes = StackMapOpers(&MI).getNumPatchBytes();
     436             : 
     437          15 :   SM.recordStackMap(MI);
     438             :   assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
     439             : 
     440             :   // Scan ahead to trim the shadow.
     441          15 :   const MachineBasicBlock &MBB = *MI.getParent();
     442             :   MachineBasicBlock::const_iterator MII(MI);
     443             :   ++MII;
     444          75 :   while (NumNOPBytes > 0) {
     445          62 :     if (MII == MBB.end() || MII->isCall() ||
     446          60 :         MII->getOpcode() == AArch64::DBG_VALUE ||
     447          63 :         MII->getOpcode() == TargetOpcode::PATCHPOINT ||
     448             :         MII->getOpcode() == TargetOpcode::STACKMAP)
     449             :       break;
     450             :     ++MII;
     451          30 :     NumNOPBytes -= 4;
     452             :   }
     453             : 
     454             :   // Emit nops.
     455          23 :   for (unsigned i = 0; i < NumNOPBytes; i += 4)
     456          12 :     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
     457          15 : }
     458             : 
     459             : // Lower a patchpoint of the form:
     460             : // [<def>], <id>, <numBytes>, <target>, <numArgs>
     461          46 : void AArch64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
     462             :                                         const MachineInstr &MI) {
     463          46 :   SM.recordPatchPoint(MI);
     464             : 
     465          46 :   PatchPointOpers Opers(&MI);
     466             : 
     467          46 :   int64_t CallTarget = Opers.getCallTarget().getImm();
     468             :   unsigned EncodedBytes = 0;
     469          46 :   if (CallTarget) {
     470             :     assert((CallTarget & 0xFFFFFFFFFFFF) == CallTarget &&
     471             :            "High 16 bits of call target should be zero.");
     472          66 :     unsigned ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
     473             :     EncodedBytes = 16;
     474             :     // Materialize the jump address:
     475          99 :     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVZXi)
     476          33 :                                     .addReg(ScratchReg)
     477          33 :                                     .addImm((CallTarget >> 32) & 0xFFFF)
     478             :                                     .addImm(32));
     479          66 :     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
     480          33 :                                     .addReg(ScratchReg)
     481          33 :                                     .addReg(ScratchReg)
     482          33 :                                     .addImm((CallTarget >> 16) & 0xFFFF)
     483             :                                     .addImm(16));
     484          66 :     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
     485          33 :                                     .addReg(ScratchReg)
     486          33 :                                     .addReg(ScratchReg)
     487          33 :                                     .addImm(CallTarget & 0xFFFF)
     488             :                                     .addImm(0));
     489          99 :     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
     490             :   }
     491             :   // Emit padding.
     492             :   unsigned NumBytes = Opers.getNumPatchBytes();
     493             :   assert(NumBytes >= EncodedBytes &&
     494             :          "Patchpoint can't request size less than the length of a call.");
     495             :   assert((NumBytes - EncodedBytes) % 4 == 0 &&
     496             :          "Invalid number of NOP bytes requested!");
     497         266 :   for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
     498         330 :     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
     499          46 : }
     500             : 
     501          75 : void AArch64AsmPrinter::EmitFMov0(const MachineInstr &MI) {
     502          75 :   unsigned DestReg = MI.getOperand(0).getReg();
     503          75 :   if (STI->hasZeroCycleZeroing() && !STI->hasZeroCycleZeroingFPWorkaround()) {
     504             :     // Convert H/S/D register to corresponding Q register
     505          21 :     if (AArch64::H0 <= DestReg && DestReg <= AArch64::H31)
     506           1 :       DestReg = AArch64::Q0 + (DestReg - AArch64::H0);
     507          20 :     else if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31)
     508          12 :       DestReg = AArch64::Q0 + (DestReg - AArch64::S0);
     509             :     else {
     510             :       assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31);
     511           8 :       DestReg = AArch64::Q0 + (DestReg - AArch64::D0);
     512             :     }
     513             :     MCInst MOVI;
     514             :     MOVI.setOpcode(AArch64::MOVIv2d_ns);
     515          42 :     MOVI.addOperand(MCOperand::createReg(DestReg));
     516          42 :     MOVI.addOperand(MCOperand::createImm(0));
     517          42 :     EmitToStreamer(*OutStreamer, MOVI);
     518             :   } else {
     519             :     MCInst FMov;
     520         108 :     switch (MI.getOpcode()) {
     521           0 :     default: llvm_unreachable("Unexpected opcode");
     522             :     case AArch64::FMOVH0:
     523             :       FMov.setOpcode(AArch64::FMOVWHr);
     524           4 :       FMov.addOperand(MCOperand::createReg(DestReg));
     525           4 :       FMov.addOperand(MCOperand::createReg(AArch64::WZR));
     526           2 :       break;
     527             :     case AArch64::FMOVS0:
     528             :       FMov.setOpcode(AArch64::FMOVWSr);
     529          72 :       FMov.addOperand(MCOperand::createReg(DestReg));
     530          72 :       FMov.addOperand(MCOperand::createReg(AArch64::WZR));
     531          36 :       break;
     532             :     case AArch64::FMOVD0:
     533             :       FMov.setOpcode(AArch64::FMOVXDr);
     534          32 :       FMov.addOperand(MCOperand::createReg(DestReg));
     535          32 :       FMov.addOperand(MCOperand::createReg(AArch64::XZR));
     536          16 :       break;
     537             :     }
     538         108 :     EmitToStreamer(*OutStreamer, FMov);
     539             :   }
     540          75 : }
     541             : 
     542             : // Simple pseudo-instructions have their lowering (with expansion to real
     543             : // instructions) auto-generated.
     544             : #include "AArch64GenMCPseudoLowering.inc"
     545             : 
     546       68723 : void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
     547             :   // Do any auto-generated pseudo lowerings.
     548       68723 :   if (emitPseudoExpansionLowering(*OutStreamer, MI))
     549         367 :     return;
     550             : 
     551       68723 :   if (AArch64FI->getLOHRelated().count(MI)) {
     552             :     // Generate a label for LOH related instruction
     553         946 :     MCSymbol *LOHLabel = createTempSymbol("loh");
     554             :     // Associate the instruction with the label
     555         473 :     LOHInstToLabel[MI] = LOHLabel;
     556         473 :     OutStreamer->EmitLabel(LOHLabel);
     557             :   }
     558             : 
     559             :   // Do any manual lowerings.
     560      137446 :   switch (MI->getOpcode()) {
     561             :   default:
     562             :     break;
     563          79 :   case AArch64::MOVIv2d_ns:
     564             :     // If the target has <rdar://problem/16473581>, lower this
     565             :     // instruction to movi.16b instead.
     566          85 :     if (STI->hasZeroCycleZeroingFPWorkaround() &&
     567           6 :         MI->getOperand(1).getImm() == 0) {
     568             :       MCInst TmpInst;
     569             :       TmpInst.setOpcode(AArch64::MOVIv16b_ns);
     570          18 :       TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
     571          18 :       TmpInst.addOperand(MCOperand::createImm(MI->getOperand(1).getImm()));
     572          12 :       EmitToStreamer(*OutStreamer, TmpInst);
     573             :       return;
     574             :     }
     575             :     break;
     576             : 
     577           0 :   case AArch64::DBG_VALUE: {
     578           0 :     if (isVerbose() && OutStreamer->hasRawTextSupport()) {
     579             :       SmallString<128> TmpStr;
     580             :       raw_svector_ostream OS(TmpStr);
     581           0 :       PrintDebugValueComment(MI, OS);
     582           0 :       OutStreamer->EmitRawText(StringRef(OS.str()));
     583             :     }
     584             :     return;
     585             :   }
     586             : 
     587             :   // Tail calls use pseudo instructions so they have the proper code-gen
     588             :   // attributes (isCall, isReturn, etc.). We lower them to the real
     589             :   // instruction here.
     590             :   case AArch64::TCRETURNri: {
     591             :     MCInst TmpInst;
     592             :     TmpInst.setOpcode(AArch64::BR);
     593          24 :     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
     594          16 :     EmitToStreamer(*OutStreamer, TmpInst);
     595             :     return;
     596             :   }
     597             :   case AArch64::TCRETURNdi: {
     598             :     MCOperand Dest;
     599         187 :     MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
     600             :     MCInst TmpInst;
     601             :     TmpInst.setOpcode(AArch64::B);
     602             :     TmpInst.addOperand(Dest);
     603         374 :     EmitToStreamer(*OutStreamer, TmpInst);
     604             :     return;
     605             :   }
     606          24 :   case AArch64::TLSDESC_CALLSEQ: {
     607             :     /// lower this to:
     608             :     ///    adrp  x0, :tlsdesc:var
     609             :     ///    ldr   x1, [x0, #:tlsdesc_lo12:var]
     610             :     ///    add   x0, x0, #:tlsdesc_lo12:var
     611             :     ///    .tlsdesccall var
     612             :     ///    blr   x1
     613             :     ///    (TPIDR_EL0 offset now in x0)
     614          24 :     const MachineOperand &MO_Sym = MI->getOperand(0);
     615          24 :     MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
     616             :     MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
     617             :     MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF);
     618             :     MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
     619          24 :     MCInstLowering.lowerOperand(MO_Sym, Sym);
     620          24 :     MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
     621          24 :     MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
     622             : 
     623             :     MCInst Adrp;
     624             :     Adrp.setOpcode(AArch64::ADRP);
     625          48 :     Adrp.addOperand(MCOperand::createReg(AArch64::X0));
     626             :     Adrp.addOperand(SymTLSDesc);
     627          48 :     EmitToStreamer(*OutStreamer, Adrp);
     628             : 
     629             :     MCInst Ldr;
     630             :     Ldr.setOpcode(AArch64::LDRXui);
     631          48 :     Ldr.addOperand(MCOperand::createReg(AArch64::X1));
     632          48 :     Ldr.addOperand(MCOperand::createReg(AArch64::X0));
     633             :     Ldr.addOperand(SymTLSDescLo12);
     634          48 :     Ldr.addOperand(MCOperand::createImm(0));
     635          24 :     EmitToStreamer(*OutStreamer, Ldr);
     636             : 
     637             :     MCInst Add;
     638             :     Add.setOpcode(AArch64::ADDXri);
     639          48 :     Add.addOperand(MCOperand::createReg(AArch64::X0));
     640          48 :     Add.addOperand(MCOperand::createReg(AArch64::X0));
     641             :     Add.addOperand(SymTLSDescLo12);
     642          48 :     Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0)));
     643          24 :     EmitToStreamer(*OutStreamer, Add);
     644             : 
     645             :     // Emit a relocation-annotation. This expands to no code, but requests
     646             :     // the following instruction gets an R_AARCH64_TLSDESC_CALL.
     647             :     MCInst TLSDescCall;
     648             :     TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
     649             :     TLSDescCall.addOperand(Sym);
     650          24 :     EmitToStreamer(*OutStreamer, TLSDescCall);
     651             : 
     652             :     MCInst Blr;
     653             :     Blr.setOpcode(AArch64::BLR);
     654          48 :     Blr.addOperand(MCOperand::createReg(AArch64::X1));
     655          24 :     EmitToStreamer(*OutStreamer, Blr);
     656             : 
     657             :     return;
     658             :   }
     659             : 
     660          75 :   case AArch64::FMOVH0:
     661             :   case AArch64::FMOVS0:
     662             :   case AArch64::FMOVD0:
     663          75 :     EmitFMov0(*MI);
     664          75 :     return;
     665             : 
     666          15 :   case TargetOpcode::STACKMAP:
     667          30 :     return LowerSTACKMAP(*OutStreamer, SM, *MI);
     668             : 
     669          46 :   case TargetOpcode::PATCHPOINT:
     670          92 :     return LowerPATCHPOINT(*OutStreamer, SM, *MI);
     671             : 
     672           3 :   case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
     673             :     LowerPATCHABLE_FUNCTION_ENTER(*MI);
     674             :     return;
     675             : 
     676           3 :   case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
     677             :     LowerPATCHABLE_FUNCTION_EXIT(*MI);
     678             :     return;
     679             : 
     680           0 :   case TargetOpcode::PATCHABLE_TAIL_CALL:
     681             :     LowerPATCHABLE_TAIL_CALL(*MI);
     682             :     return;
     683             :   }
     684             : 
     685             :   // Finally, do the automated lowerings for everything else.
     686             :   MCInst TmpInst;
     687       68356 :   MCInstLowering.Lower(MI, TmpInst);
     688      136712 :   EmitToStreamer(*OutStreamer, TmpInst);
     689             : }
     690             : 
     691             : // Force static initialization.
     692       53163 : extern "C" void LLVMInitializeAArch64AsmPrinter() {
     693       53163 :   RegisterAsmPrinter<AArch64AsmPrinter> X(getTheAArch64leTarget());
     694       53163 :   RegisterAsmPrinter<AArch64AsmPrinter> Y(getTheAArch64beTarget());
     695       53163 :   RegisterAsmPrinter<AArch64AsmPrinter> Z(getTheARM64Target());
     696       53163 : }

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