LCOV - code coverage report
Current view: top level - lib/Target/AArch64 - AArch64ConditionalCompares.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 214 241 88.8 %
Date: 2018-02-18 16:14:26 Functions: 23 24 95.8 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- AArch64ConditionalCompares.cpp --- CCMP formation for AArch64 -----===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements the AArch64ConditionalCompares pass which reduces
      11             : // branching and code size by using the conditional compare instructions CCMP,
      12             : // CCMN, and FCMP.
      13             : //
      14             : // The CFG transformations for forming conditional compares are very similar to
      15             : // if-conversion, and this pass should run immediately before the early
      16             : // if-conversion pass.
      17             : //
      18             : //===----------------------------------------------------------------------===//
      19             : 
      20             : #include "AArch64.h"
      21             : #include "llvm/ADT/DepthFirstIterator.h"
      22             : #include "llvm/ADT/SetVector.h"
      23             : #include "llvm/ADT/SmallPtrSet.h"
      24             : #include "llvm/ADT/Statistic.h"
      25             : #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
      26             : #include "llvm/CodeGen/MachineDominators.h"
      27             : #include "llvm/CodeGen/MachineFunction.h"
      28             : #include "llvm/CodeGen/MachineFunctionPass.h"
      29             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      30             : #include "llvm/CodeGen/MachineLoopInfo.h"
      31             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      32             : #include "llvm/CodeGen/MachineTraceMetrics.h"
      33             : #include "llvm/CodeGen/Passes.h"
      34             : #include "llvm/CodeGen/TargetInstrInfo.h"
      35             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      36             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      37             : #include "llvm/Support/CommandLine.h"
      38             : #include "llvm/Support/Debug.h"
      39             : #include "llvm/Support/raw_ostream.h"
      40             : 
      41             : using namespace llvm;
      42             : 
      43             : #define DEBUG_TYPE "aarch64-ccmp"
      44             : 
      45             : // Absolute maximum number of instructions allowed per speculated block.
      46             : // This bypasses all other heuristics, so it should be set fairly high.
      47       97323 : static cl::opt<unsigned> BlockInstrLimit(
      48      194646 :     "aarch64-ccmp-limit", cl::init(30), cl::Hidden,
      49      291969 :     cl::desc("Maximum number of instructions per speculated block."));
      50             : 
      51             : // Stress testing mode - disable heuristics.
      52       97323 : static cl::opt<bool> Stress("aarch64-stress-ccmp", cl::Hidden,
      53       97323 :                             cl::desc("Turn all knobs to 11"));
      54             : 
      55             : STATISTIC(NumConsidered, "Number of ccmps considered");
      56             : STATISTIC(NumPhiRejs, "Number of ccmps rejected (PHI)");
      57             : STATISTIC(NumPhysRejs, "Number of ccmps rejected (Physregs)");
      58             : STATISTIC(NumPhi2Rejs, "Number of ccmps rejected (PHI2)");
      59             : STATISTIC(NumHeadBranchRejs, "Number of ccmps rejected (Head branch)");
      60             : STATISTIC(NumCmpBranchRejs, "Number of ccmps rejected (CmpBB branch)");
      61             : STATISTIC(NumCmpTermRejs, "Number of ccmps rejected (CmpBB is cbz...)");
      62             : STATISTIC(NumImmRangeRejs, "Number of ccmps rejected (Imm out of range)");
      63             : STATISTIC(NumLiveDstRejs, "Number of ccmps rejected (Cmp dest live)");
      64             : STATISTIC(NumMultNZCVUses, "Number of ccmps rejected (NZCV used)");
      65             : STATISTIC(NumUnknNZCVDefs, "Number of ccmps rejected (NZCV def unknown)");
      66             : 
      67             : STATISTIC(NumSpeculateRejs, "Number of ccmps rejected (Can't speculate)");
      68             : 
      69             : STATISTIC(NumConverted, "Number of ccmp instructions created");
      70             : STATISTIC(NumCompBranches, "Number of cbz/cbnz branches converted");
      71             : 
      72             : //===----------------------------------------------------------------------===//
      73             : //                                 SSACCmpConv
      74             : //===----------------------------------------------------------------------===//
      75             : //
      76             : // The SSACCmpConv class performs ccmp-conversion on SSA form machine code
      77             : // after determining if it is possible. The class contains no heuristics;
      78             : // external code should be used to determine when ccmp-conversion is a good
      79             : // idea.
      80             : //
      81             : // CCmp-formation works on a CFG representing chained conditions, typically
      82             : // from C's short-circuit || and && operators:
      83             : //
      84             : //   From:         Head            To:         Head
      85             : //                 / |                         CmpBB
      86             : //                /  |                         / |
      87             : //               |  CmpBB                     /  |
      88             : //               |  / |                    Tail  |
      89             : //               | /  |                      |   |
      90             : //              Tail  |                      |   |
      91             : //                |   |                      |   |
      92             : //               ... ...                    ... ...
      93             : //
      94             : // The Head block is terminated by a br.cond instruction, and the CmpBB block
      95             : // contains compare + br.cond. Tail must be a successor of both.
      96             : //
      97             : // The cmp-conversion turns the compare instruction in CmpBB into a conditional
      98             : // compare, and merges CmpBB into Head, speculatively executing its
      99             : // instructions. The AArch64 conditional compare instructions have an immediate
     100             : // operand that specifies the NZCV flag values when the condition is false and
     101             : // the compare isn't executed. This makes it possible to chain compares with
     102             : // different condition codes.
     103             : //
     104             : // Example:
     105             : //
     106             : //    if (a == 5 || b == 17)
     107             : //      foo();
     108             : //
     109             : //    Head:
     110             : //       cmp  w0, #5
     111             : //       b.eq Tail
     112             : //    CmpBB:
     113             : //       cmp  w1, #17
     114             : //       b.eq Tail
     115             : //    ...
     116             : //    Tail:
     117             : //      bl _foo
     118             : //
     119             : //  Becomes:
     120             : //
     121             : //    Head:
     122             : //       cmp  w0, #5
     123             : //       ccmp w1, #17, 4, ne  ; 4 = nZcv
     124             : //       b.eq Tail
     125             : //    ...
     126             : //    Tail:
     127             : //      bl _foo
     128             : //
     129             : // The ccmp condition code is the one that would cause the Head terminator to
     130             : // branch to CmpBB.
     131             : //
     132             : // FIXME: It should also be possible to speculate a block on the critical edge
     133             : // between Head and Tail, just like if-converting a diamond.
     134             : //
     135             : // FIXME: Handle PHIs in Tail by turning them into selects (if-conversion).
     136             : 
     137             : namespace {
     138        1916 : class SSACCmpConv {
     139             :   MachineFunction *MF;
     140             :   const TargetInstrInfo *TII;
     141             :   const TargetRegisterInfo *TRI;
     142             :   MachineRegisterInfo *MRI;
     143             :   const MachineBranchProbabilityInfo *MBPI;
     144             : 
     145             : public:
     146             :   /// The first block containing a conditional branch, dominating everything
     147             :   /// else.
     148             :   MachineBasicBlock *Head;
     149             : 
     150             :   /// The block containing cmp+br.cond with a successor shared with Head.
     151             :   MachineBasicBlock *CmpBB;
     152             : 
     153             :   /// The common successor for Head and CmpBB.
     154             :   MachineBasicBlock *Tail;
     155             : 
     156             :   /// The compare instruction in CmpBB that can be converted to a ccmp.
     157             :   MachineInstr *CmpMI;
     158             : 
     159             : private:
     160             :   /// The branch condition in Head as determined by AnalyzeBranch.
     161             :   SmallVector<MachineOperand, 4> HeadCond;
     162             : 
     163             :   /// The condition code that makes Head branch to CmpBB.
     164             :   AArch64CC::CondCode HeadCmpBBCC;
     165             : 
     166             :   /// The branch condition in CmpBB.
     167             :   SmallVector<MachineOperand, 4> CmpBBCond;
     168             : 
     169             :   /// The condition code that makes CmpBB branch to Tail.
     170             :   AArch64CC::CondCode CmpBBTailCC;
     171             : 
     172             :   /// Check if the Tail PHIs are trivially convertible.
     173             :   bool trivialTailPHIs();
     174             : 
     175             :   /// Remove CmpBB from the Tail PHIs.
     176             :   void updateTailPHIs();
     177             : 
     178             :   /// Check if an operand defining DstReg is dead.
     179             :   bool isDeadDef(unsigned DstReg);
     180             : 
     181             :   /// Find the compare instruction in MBB that controls the conditional branch.
     182             :   /// Return NULL if a convertible instruction can't be found.
     183             :   MachineInstr *findConvertibleCompare(MachineBasicBlock *MBB);
     184             : 
     185             :   /// Return true if all non-terminator instructions in MBB can be safely
     186             :   /// speculated.
     187             :   bool canSpeculateInstrs(MachineBasicBlock *MBB, const MachineInstr *CmpMI);
     188             : 
     189             : public:
     190             :   /// runOnMachineFunction - Initialize per-function data structures.
     191             :   void runOnMachineFunction(MachineFunction &MF,
     192             :                             const MachineBranchProbabilityInfo *MBPI) {
     193       12649 :     this->MF = &MF;
     194       12649 :     this->MBPI = MBPI;
     195       12649 :     TII = MF.getSubtarget().getInstrInfo();
     196       12649 :     TRI = MF.getSubtarget().getRegisterInfo();
     197       12649 :     MRI = &MF.getRegInfo();
     198             :   }
     199             : 
     200             :   /// If the sub-CFG headed by MBB can be cmp-converted, initialize the
     201             :   /// internal state, and return true.
     202             :   bool canConvert(MachineBasicBlock *MBB);
     203             : 
     204             :   /// Cmo-convert the last block passed to canConvertCmp(), assuming
     205             :   /// it is possible. Add any erased blocks to RemovedBlocks.
     206             :   void convert(SmallVectorImpl<MachineBasicBlock *> &RemovedBlocks);
     207             : 
     208             :   /// Return the expected code size delta if the conversion into a
     209             :   /// conditional compare is performed.
     210             :   int expectedCodeSizeDelta() const;
     211             : };
     212             : } // end anonymous namespace
     213             : 
     214             : // Check that all PHIs in Tail are selecting the same value from Head and CmpBB.
     215             : // This means that no if-conversion is required when merging CmpBB into Head.
     216         112 : bool SSACCmpConv::trivialTailPHIs() {
     217         233 :   for (auto &I : *Tail) {
     218             :     if (!I.isPHI())
     219             :       break;
     220             :     unsigned HeadReg = 0, CmpBBReg = 0;
     221             :     // PHI operands come in (VReg, MBB) pairs.
     222         293 :     for (unsigned oi = 1, oe = I.getNumOperands(); oi != oe; oi += 2) {
     223         138 :       MachineBasicBlock *MBB = I.getOperand(oi + 1).getMBB();
     224             :       unsigned Reg = I.getOperand(oi).getReg();
     225         138 :       if (MBB == Head) {
     226             :         assert((!HeadReg || HeadReg == Reg) && "Inconsistent PHI operands");
     227             :         HeadReg = Reg;
     228             :       }
     229         138 :       if (MBB == CmpBB) {
     230             :         assert((!CmpBBReg || CmpBBReg == Reg) && "Inconsistent PHI operands");
     231             :         CmpBBReg = Reg;
     232             :       }
     233             :     }
     234          17 :     if (HeadReg != CmpBBReg)
     235           8 :       return false;
     236             :   }
     237         104 :   return true;
     238             : }
     239             : 
     240             : // Assuming that trivialTailPHIs() is true, update the Tail PHIs by simply
     241             : // removing the CmpBB operands. The Head operands will be identical.
     242          11 : void SSACCmpConv::updateTailPHIs() {
     243          22 :   for (auto &I : *Tail) {
     244             :     if (!I.isPHI())
     245             :       break;
     246             :     // I is a PHI. It can have multiple entries for CmpBB.
     247           0 :     for (unsigned oi = I.getNumOperands(); oi > 2; oi -= 2) {
     248             :       // PHI operands are (Reg, MBB) at (oi-2, oi-1).
     249           0 :       if (I.getOperand(oi - 1).getMBB() == CmpBB) {
     250           0 :         I.RemoveOperand(oi - 1);
     251           0 :         I.RemoveOperand(oi - 2);
     252             :       }
     253             :     }
     254             :   }
     255          11 : }
     256             : 
     257             : // This pass runs before the AArch64DeadRegisterDefinitions pass, so compares
     258             : // are still writing virtual registers without any uses.
     259          36 : bool SSACCmpConv::isDeadDef(unsigned DstReg) {
     260             :   // Writes to the zero register are dead.
     261          36 :   if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
     262             :     return true;
     263          35 :   if (!TargetRegisterInfo::isVirtualRegister(DstReg))
     264             :     return false;
     265             :   // A virtual register def without any uses will be marked dead later, and
     266             :   // eventually replaced by the zero register.
     267          35 :   return MRI->use_nodbg_empty(DstReg);
     268             : }
     269             : 
     270             : // Parse a condition code returned by AnalyzeBranch, and compute the CondCode
     271             : // corresponding to TBB.
     272             : // Return
     273             : static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
     274             :   // A normal br.cond simply has the condition code.
     275         189 :   if (Cond[0].getImm() != -1) {
     276             :     assert(Cond.size() == 1 && "Unknown Cond array format");
     277         142 :     CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
     278             :     return true;
     279             :   }
     280             :   // For tbz and cbz instruction, the opcode is next.
     281          47 :   switch (Cond[1].getImm()) {
     282             :   default:
     283             :     // This includes tbz / tbnz branches which can't be converted to
     284             :     // ccmp + br.cond.
     285             :     return false;
     286          18 :   case AArch64::CBZW:
     287             :   case AArch64::CBZX:
     288             :     assert(Cond.size() == 3 && "Unknown Cond array format");
     289          18 :     CC = AArch64CC::EQ;
     290             :     return true;
     291          12 :   case AArch64::CBNZW:
     292             :   case AArch64::CBNZX:
     293             :     assert(Cond.size() == 3 && "Unknown Cond array format");
     294          12 :     CC = AArch64CC::NE;
     295             :     return true;
     296             :   }
     297             : }
     298             : 
     299          83 : MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) {
     300          83 :   MachineBasicBlock::iterator I = MBB->getFirstTerminator();
     301          83 :   if (I == MBB->end())
     302             :     return nullptr;
     303             :   // The terminator must be controlled by the flags.
     304          83 :   if (!I->readsRegister(AArch64::NZCV)) {
     305          17 :     switch (I->getOpcode()) {
     306             :     case AArch64::CBZW:
     307             :     case AArch64::CBZX:
     308             :     case AArch64::CBNZW:
     309             :     case AArch64::CBNZX:
     310             :       // These can be converted into a ccmp against #0.
     311          17 :       return &*I;
     312             :     }
     313             :     ++NumCmpTermRejs;
     314             :     DEBUG(dbgs() << "Flags not used by terminator: " << *I);
     315             :     return nullptr;
     316             :   }
     317             : 
     318             :   // Now find the instruction controlling the terminator.
     319          66 :   for (MachineBasicBlock::iterator B = MBB->begin(); I != B;) {
     320             :     --I;
     321             :     assert(!I->isTerminator() && "Spurious terminator");
     322          66 :     switch (I->getOpcode()) {
     323             :     // cmp is an alias for subs with a dead destination register.
     324             :     case AArch64::SUBSWri:
     325             :     case AArch64::SUBSXri:
     326             :     // cmn is an alias for adds with a dead destination register.
     327             :     case AArch64::ADDSWri:
     328             :     case AArch64::ADDSXri:
     329             :       // Check that the immediate operand is within range, ccmp wants a uimm5.
     330             :       // Rd = SUBSri Rn, imm, shift
     331          31 :       if (I->getOperand(3).getImm() || !isUInt<5>(I->getOperand(2).getImm())) {
     332             :         DEBUG(dbgs() << "Immediate out of range for ccmp: " << *I);
     333             :         ++NumImmRangeRejs;
     334          66 :         return nullptr;
     335             :       }
     336             :       LLVM_FALLTHROUGH;
     337             :     case AArch64::SUBSWrr:
     338             :     case AArch64::SUBSXrr:
     339             :     case AArch64::ADDSWrr:
     340             :     case AArch64::ADDSXrr:
     341          36 :       if (isDeadDef(I->getOperand(0).getReg()))
     342          36 :         return &*I;
     343             :       DEBUG(dbgs() << "Can't convert compare with live destination: " << *I);
     344             :       ++NumLiveDstRejs;
     345             :       return nullptr;
     346             :     case AArch64::FCMPSrr:
     347             :     case AArch64::FCMPDrr:
     348             :     case AArch64::FCMPESrr:
     349             :     case AArch64::FCMPEDrr:
     350             :       return &*I;
     351             :     }
     352             : 
     353             :     // Check for flag reads and clobbers.
     354             :     MIOperands::PhysRegInfo PRI =
     355          16 :         MIOperands(*I).analyzePhysReg(AArch64::NZCV, TRI);
     356             : 
     357          16 :     if (PRI.Read) {
     358             :       // The ccmp doesn't produce exactly the same flags as the original
     359             :       // compare, so reject the transform if there are uses of the flags
     360             :       // besides the terminators.
     361             :       DEBUG(dbgs() << "Can't create ccmp with multiple uses: " << *I);
     362             :       ++NumMultNZCVUses;
     363             :       return nullptr;
     364             :     }
     365             : 
     366          16 :     if (PRI.Defined || PRI.Clobbered) {
     367             :       DEBUG(dbgs() << "Not convertible compare: " << *I);
     368             :       ++NumUnknNZCVDefs;
     369             :       return nullptr;
     370             :     }
     371             :   }
     372             :   DEBUG(dbgs() << "Flags not defined in " << printMBBReference(*MBB) << '\n');
     373             :   return nullptr;
     374             : }
     375             : 
     376             : /// Determine if all the instructions in MBB can safely
     377             : /// be speculated. The terminators are not considered.
     378             : ///
     379             : /// Only CmpMI is allowed to clobber the flags.
     380             : ///
     381          54 : bool SSACCmpConv::canSpeculateInstrs(MachineBasicBlock *MBB,
     382             :                                      const MachineInstr *CmpMI) {
     383             :   // Reject any live-in physregs. It's probably NZCV/EFLAGS, and very hard to
     384             :   // get right.
     385          54 :   if (!MBB->livein_empty()) {
     386             :     DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n");
     387             :     return false;
     388             :   }
     389             : 
     390             :   unsigned InstrCount = 0;
     391             : 
     392             :   // Check all instructions, except the terminators. It is assumed that
     393             :   // terminators never have side effects or define any used register values.
     394         167 :   for (auto &I : make_range(MBB->begin(), MBB->getFirstTerminator())) {
     395          82 :     if (I.isDebugValue())
     396           1 :       continue;
     397             : 
     398          81 :     if (++InstrCount > BlockInstrLimit && !Stress) {
     399             :       DEBUG(dbgs() << printMBBReference(*MBB) << " has more than "
     400             :                    << BlockInstrLimit << " instructions.\n");
     401          23 :       return false;
     402             :     }
     403             : 
     404             :     // There shouldn't normally be any phis in a single-predecessor block.
     405             :     if (I.isPHI()) {
     406             :       DEBUG(dbgs() << "Can't hoist: " << I);
     407             :       return false;
     408             :     }
     409             : 
     410             :     // Don't speculate loads. Note that it may be possible and desirable to
     411             :     // speculate GOT or constant pool loads that are guaranteed not to trap,
     412             :     // but we don't support that for now.
     413          81 :     if (I.mayLoad()) {
     414             :       DEBUG(dbgs() << "Won't speculate load: " << I);
     415             :       return false;
     416             :     }
     417             : 
     418             :     // We never speculate stores, so an AA pointer isn't necessary.
     419          63 :     bool DontMoveAcrossStore = true;
     420          63 :     if (!I.isSafeToMove(nullptr, DontMoveAcrossStore)) {
     421             :       DEBUG(dbgs() << "Can't speculate: " << I);
     422             :       return false;
     423             :     }
     424             : 
     425             :     // Only CmpMI is allowed to clobber the flags.
     426         100 :     if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) {
     427             :       DEBUG(dbgs() << "Clobbers flags: " << I);
     428             :       return false;
     429             :     }
     430             :   }
     431             :   return true;
     432             : }
     433             : 
     434             : /// Analyze the sub-cfg rooted in MBB, and return true if it is a potential
     435             : /// candidate for cmp-conversion. Fill out the internal state.
     436             : ///
     437       14824 : bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) {
     438       14824 :   Head = MBB;
     439       14824 :   Tail = CmpBB = nullptr;
     440             : 
     441       14824 :   if (Head->succ_size() != 2)
     442             :     return false;
     443        1026 :   MachineBasicBlock *Succ0 = Head->succ_begin()[0];
     444        1026 :   MachineBasicBlock *Succ1 = Head->succ_begin()[1];
     445             : 
     446             :   // CmpBB can only have a single predecessor. Tail is allowed many.
     447        1026 :   if (Succ0->pred_size() != 1)
     448             :     std::swap(Succ0, Succ1);
     449             : 
     450             :   // Succ0 is our candidate for CmpBB.
     451        1963 :   if (Succ0->pred_size() != 1 || Succ0->succ_size() != 2)
     452             :     return false;
     453             : 
     454         203 :   CmpBB = Succ0;
     455         203 :   Tail = Succ1;
     456             : 
     457         203 :   if (!CmpBB->isSuccessor(Tail))
     458             :     return false;
     459             : 
     460             :   // The CFG topology checks out.
     461             :   DEBUG(dbgs() << "\nTriangle: " << printMBBReference(*Head) << " -> "
     462             :                << printMBBReference(*CmpBB) << " -> "
     463             :                << printMBBReference(*Tail) << '\n');
     464             :   ++NumConsidered;
     465             : 
     466             :   // Tail is allowed to have many predecessors, but we can't handle PHIs yet.
     467             :   //
     468             :   // FIXME: Real PHIs could be if-converted as long as the CmpBB values are
     469             :   // defined before The CmpBB cmp clobbers the flags. Alternatively, it should
     470             :   // always be safe to sink the ccmp down to immediately before the CmpBB
     471             :   // terminators.
     472         112 :   if (!trivialTailPHIs()) {
     473             :     DEBUG(dbgs() << "Can't handle phis in Tail.\n");
     474             :     ++NumPhiRejs;
     475             :     return false;
     476             :   }
     477             : 
     478         104 :   if (!Tail->livein_empty()) {
     479             :     DEBUG(dbgs() << "Can't handle live-in physregs in Tail.\n");
     480             :     ++NumPhysRejs;
     481             :     return false;
     482             :   }
     483             : 
     484             :   // CmpBB should never have PHIs since Head is its only predecessor.
     485             :   // FIXME: Clean them up if it happens.
     486         208 :   if (!CmpBB->empty() && CmpBB->front().isPHI()) {
     487             :     DEBUG(dbgs() << "Can't handle phis in CmpBB.\n");
     488             :     ++NumPhi2Rejs;
     489             :     return false;
     490             :   }
     491             : 
     492         104 :   if (!CmpBB->livein_empty()) {
     493             :     DEBUG(dbgs() << "Can't handle live-in physregs in CmpBB.\n");
     494             :     ++NumPhysRejs;
     495             :     return false;
     496             :   }
     497             : 
     498             :   // The branch we're looking to eliminate must be analyzable.
     499         104 :   HeadCond.clear();
     500         104 :   MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
     501         104 :   if (TII->analyzeBranch(*Head, TBB, FBB, HeadCond)) {
     502             :     DEBUG(dbgs() << "Head branch not analyzable.\n");
     503             :     ++NumHeadBranchRejs;
     504             :     return false;
     505             :   }
     506             : 
     507             :   // This is weird, probably some sort of degenerate CFG, or an edge to a
     508             :   // landing pad.
     509         102 :   if (!TBB || HeadCond.empty()) {
     510             :     DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch in Head.\n");
     511             :     ++NumHeadBranchRejs;
     512             :     return false;
     513             :   }
     514             : 
     515             :   if (!parseCond(HeadCond, HeadCmpBBCC)) {
     516             :     DEBUG(dbgs() << "Unsupported branch type on Head\n");
     517             :     ++NumHeadBranchRejs;
     518             :     return false;
     519             :   }
     520             : 
     521             :   // Make sure the branch direction is right.
     522          89 :   if (TBB != CmpBB) {
     523             :     assert(TBB == Tail && "Unexpected TBB");
     524         178 :     HeadCmpBBCC = AArch64CC::getInvertedCondCode(HeadCmpBBCC);
     525             :   }
     526             : 
     527          89 :   CmpBBCond.clear();
     528          89 :   TBB = FBB = nullptr;
     529          89 :   if (TII->analyzeBranch(*CmpBB, TBB, FBB, CmpBBCond)) {
     530             :     DEBUG(dbgs() << "CmpBB branch not analyzable.\n");
     531             :     ++NumCmpBranchRejs;
     532             :     return false;
     533             :   }
     534             : 
     535          87 :   if (!TBB || CmpBBCond.empty()) {
     536             :     DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch in CmpBB.\n");
     537             :     ++NumCmpBranchRejs;
     538             :     return false;
     539             :   }
     540             : 
     541             :   if (!parseCond(CmpBBCond, CmpBBTailCC)) {
     542             :     DEBUG(dbgs() << "Unsupported branch type on CmpBB\n");
     543             :     ++NumCmpBranchRejs;
     544             :     return false;
     545             :   }
     546             : 
     547          83 :   if (TBB != Tail)
     548          54 :     CmpBBTailCC = AArch64CC::getInvertedCondCode(CmpBBTailCC);
     549             : 
     550             :   DEBUG(dbgs() << "Head->CmpBB on " << AArch64CC::getCondCodeName(HeadCmpBBCC)
     551             :                << ", CmpBB->Tail on " << AArch64CC::getCondCodeName(CmpBBTailCC)
     552             :                << '\n');
     553             : 
     554          83 :   CmpMI = findConvertibleCompare(CmpBB);
     555          83 :   if (!CmpMI)
     556             :     return false;
     557             : 
     558          54 :   if (!canSpeculateInstrs(CmpBB, CmpMI)) {
     559             :     ++NumSpeculateRejs;
     560             :     return false;
     561             :   }
     562          31 :   return true;
     563             : }
     564             : 
     565          11 : void SSACCmpConv::convert(SmallVectorImpl<MachineBasicBlock *> &RemovedBlocks) {
     566             :   DEBUG(dbgs() << "Merging " << printMBBReference(*CmpBB) << " into "
     567             :                << printMBBReference(*Head) << ":\n"
     568             :                << *CmpBB);
     569             : 
     570             :   // All CmpBB instructions are moved into Head, and CmpBB is deleted.
     571             :   // Update the CFG first.
     572          11 :   updateTailPHIs();
     573             : 
     574             :   // Save successor probabilties before removing CmpBB and Tail from their
     575             :   // parents.
     576          11 :   BranchProbability Head2CmpBB = MBPI->getEdgeProbability(Head, CmpBB);
     577          11 :   BranchProbability CmpBB2Tail = MBPI->getEdgeProbability(CmpBB, Tail);
     578             : 
     579          11 :   Head->removeSuccessor(CmpBB);
     580          11 :   CmpBB->removeSuccessor(Tail);
     581             : 
     582             :   // If Head and CmpBB had successor probabilties, udpate the probabilities to
     583             :   // reflect the ccmp-conversion.
     584          11 :   if (Head->hasSuccessorProbabilities() && CmpBB->hasSuccessorProbabilities()) {
     585             : 
     586             :     // Head is allowed two successors. We've removed CmpBB, so the remaining
     587             :     // successor is Tail. We need to increase the successor probability for
     588             :     // Tail to account for the CmpBB path we removed.
     589             :     //
     590             :     // Pr(Tail|Head) += Pr(CmpBB|Head) * Pr(Tail|CmpBB).
     591             :     assert(*Head->succ_begin() == Tail && "Head successor is not Tail");
     592          11 :     BranchProbability Head2Tail = MBPI->getEdgeProbability(Head, Tail);
     593          22 :     Head->setSuccProbability(Head->succ_begin(),
     594             :                              Head2Tail + Head2CmpBB * CmpBB2Tail);
     595             : 
     596             :     // We will transfer successors of CmpBB to Head in a moment without
     597             :     // normalizing the successor probabilities. Set the successor probabilites
     598             :     // before doing so.
     599             :     //
     600             :     // Pr(I|Head) = Pr(CmpBB|Head) * Pr(I|CmpBB).
     601          33 :     for (auto I = CmpBB->succ_begin(), E = CmpBB->succ_end(); I != E; ++I) {
     602          11 :       BranchProbability CmpBB2I = MBPI->getEdgeProbability(CmpBB, *I);
     603          22 :       CmpBB->setSuccProbability(I, Head2CmpBB * CmpBB2I);
     604             :     }
     605             :   }
     606             : 
     607          11 :   Head->transferSuccessorsAndUpdatePHIs(CmpBB);
     608          22 :   DebugLoc TermDL = Head->getFirstTerminator()->getDebugLoc();
     609          11 :   TII->removeBranch(*Head);
     610             : 
     611             :   // If the Head terminator was one of the cbz / tbz branches with built-in
     612             :   // compare, we need to insert an explicit compare instruction in its place.
     613          11 :   if (HeadCond[0].getImm() == -1) {
     614             :     ++NumCompBranches;
     615             :     unsigned Opc = 0;
     616           3 :     switch (HeadCond[1].getImm()) {
     617             :     case AArch64::CBZW:
     618             :     case AArch64::CBNZW:
     619             :       Opc = AArch64::SUBSWri;
     620             :       break;
     621           0 :     case AArch64::CBZX:
     622             :     case AArch64::CBNZX:
     623             :       Opc = AArch64::SUBSXri;
     624           0 :       break;
     625           0 :     default:
     626           0 :       llvm_unreachable("Cannot convert Head branch");
     627             :     }
     628           3 :     const MCInstrDesc &MCID = TII->get(Opc);
     629             :     // Create a dummy virtual register for the SUBS def.
     630             :     unsigned DestReg =
     631           3 :         MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF));
     632             :     // Insert a SUBS Rn, #0 instruction instead of the cbz / cbnz.
     633           9 :     BuildMI(*Head, Head->end(), TermDL, MCID)
     634           3 :         .addReg(DestReg, RegState::Define | RegState::Dead)
     635             :         .add(HeadCond[2])
     636             :         .addImm(0)
     637             :         .addImm(0);
     638             :     // SUBS uses the GPR*sp register classes.
     639           9 :     MRI->constrainRegClass(HeadCond[2].getReg(),
     640           3 :                            TII->getRegClass(MCID, 1, TRI, *MF));
     641             :   }
     642             : 
     643          11 :   Head->splice(Head->end(), CmpBB, CmpBB->begin(), CmpBB->end());
     644             : 
     645             :   // Now replace CmpMI with a ccmp instruction that also considers the incoming
     646             :   // flags.
     647             :   unsigned Opc = 0;
     648             :   unsigned FirstOp = 1;   // First CmpMI operand to copy.
     649             :   bool isZBranch = false; // CmpMI is a cbz/cbnz instruction.
     650          22 :   switch (CmpMI->getOpcode()) {
     651           0 :   default:
     652           0 :     llvm_unreachable("Unknown compare opcode");
     653             :   case AArch64::SUBSWri:    Opc = AArch64::CCMPWi; break;
     654           1 :   case AArch64::SUBSWrr:    Opc = AArch64::CCMPWr; break;
     655           0 :   case AArch64::SUBSXri:    Opc = AArch64::CCMPXi; break;
     656           1 :   case AArch64::SUBSXrr:    Opc = AArch64::CCMPXr; break;
     657           0 :   case AArch64::ADDSWri:    Opc = AArch64::CCMNWi; break;
     658           0 :   case AArch64::ADDSWrr:    Opc = AArch64::CCMNWr; break;
     659           0 :   case AArch64::ADDSXri:    Opc = AArch64::CCMNXi; break;
     660           0 :   case AArch64::ADDSXrr:    Opc = AArch64::CCMNXr; break;
     661           1 :   case AArch64::FCMPSrr:    Opc = AArch64::FCCMPSrr; FirstOp = 0; break;
     662           0 :   case AArch64::FCMPDrr:    Opc = AArch64::FCCMPDrr; FirstOp = 0; break;
     663           0 :   case AArch64::FCMPESrr:   Opc = AArch64::FCCMPESrr; FirstOp = 0; break;
     664           0 :   case AArch64::FCMPEDrr:   Opc = AArch64::FCCMPEDrr; FirstOp = 0; break;
     665           2 :   case AArch64::CBZW:
     666             :   case AArch64::CBNZW:
     667             :     Opc = AArch64::CCMPWi;
     668             :     FirstOp = 0;
     669             :     isZBranch = true;
     670           2 :     break;
     671           1 :   case AArch64::CBZX:
     672             :   case AArch64::CBNZX:
     673             :     Opc = AArch64::CCMPXi;
     674             :     FirstOp = 0;
     675             :     isZBranch = true;
     676           1 :     break;
     677             :   }
     678             : 
     679             :   // The ccmp instruction should set the flags according to the comparison when
     680             :   // Head would have branched to CmpBB.
     681             :   // The NZCV immediate operand should provide flags for the case where Head
     682             :   // would have branched to Tail. These flags should cause the new Head
     683             :   // terminator to branch to tail.
     684          11 :   unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(CmpBBTailCC);
     685          11 :   const MCInstrDesc &MCID = TII->get(Opc);
     686          33 :   MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(),
     687          11 :                          TII->getRegClass(MCID, 0, TRI, *MF));
     688          22 :   if (CmpMI->getOperand(FirstOp + 1).isReg())
     689           9 :     MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),
     690           3 :                            TII->getRegClass(MCID, 1, TRI, *MF));
     691          22 :   MachineInstrBuilder MIB = BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)
     692          11 :                                 .add(CmpMI->getOperand(FirstOp)); // Register Rn
     693          11 :   if (isZBranch)
     694             :     MIB.addImm(0); // cbz/cbnz Rn -> ccmp Rn, #0
     695             :   else
     696           8 :     MIB.add(CmpMI->getOperand(FirstOp + 1)); // Register Rm / Immediate
     697          22 :   MIB.addImm(NZCV).addImm(HeadCmpBBCC);
     698             : 
     699             :   // If CmpMI was a terminator, we need a new conditional branch to replace it.
     700             :   // This now becomes a Head terminator.
     701          11 :   if (isZBranch) {
     702           6 :     bool isNZ = CmpMI->getOpcode() == AArch64::CBNZW ||
     703             :                 CmpMI->getOpcode() == AArch64::CBNZX;
     704           6 :     BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), TII->get(AArch64::Bcc))
     705           3 :         .addImm(isNZ ? AArch64CC::NE : AArch64CC::EQ)
     706           3 :         .add(CmpMI->getOperand(1)); // Branch target.
     707             :   }
     708          11 :   CmpMI->eraseFromParent();
     709          11 :   Head->updateTerminator();
     710             : 
     711          11 :   RemovedBlocks.push_back(CmpBB);
     712          11 :   CmpBB->eraseFromParent();
     713             :   DEBUG(dbgs() << "Result:\n" << *Head);
     714             :   ++NumConverted;
     715          11 : }
     716             : 
     717             : int SSACCmpConv::expectedCodeSizeDelta() const {
     718             :   int delta = 0;
     719             :   // If the Head terminator was one of the cbz / tbz branches with built-in
     720             :   // compare, we need to insert an explicit compare instruction in its place
     721             :   // plus a branch instruction.
     722           0 :   if (HeadCond[0].getImm() == -1) {
     723           0 :     switch (HeadCond[1].getImm()) {
     724             :     case AArch64::CBZW:
     725             :     case AArch64::CBNZW:
     726             :     case AArch64::CBZX:
     727             :     case AArch64::CBNZX:
     728             :       // Therefore delta += 1
     729             :       delta = 1;
     730             :       break;
     731           0 :     default:
     732           0 :       llvm_unreachable("Cannot convert Head branch");
     733             :     }
     734             :   }
     735             :   // If the Cmp terminator was one of the cbz / tbz branches with
     736             :   // built-in compare, it will be turned into a compare instruction
     737             :   // into Head, but we do not save any instruction.
     738             :   // Otherwise, we save the branch instruction.
     739           0 :   switch (CmpMI->getOpcode()) {
     740           0 :   default:
     741           0 :     --delta;
     742             :     break;
     743             :   case AArch64::CBZW:
     744             :   case AArch64::CBNZW:
     745             :   case AArch64::CBZX:
     746             :   case AArch64::CBNZX:
     747             :     break;
     748             :   }
     749             :   return delta;
     750             : }
     751             : 
     752             : //===----------------------------------------------------------------------===//
     753             : //                       AArch64ConditionalCompares Pass
     754             : //===----------------------------------------------------------------------===//
     755             : 
     756             : namespace {
     757         958 : class AArch64ConditionalCompares : public MachineFunctionPass {
     758             :   const MachineBranchProbabilityInfo *MBPI;
     759             :   const TargetInstrInfo *TII;
     760             :   const TargetRegisterInfo *TRI;
     761             :   MCSchedModel SchedModel;
     762             :   // Does the proceeded function has Oz attribute.
     763             :   bool MinSize;
     764             :   MachineRegisterInfo *MRI;
     765             :   MachineDominatorTree *DomTree;
     766             :   MachineLoopInfo *Loops;
     767             :   MachineTraceMetrics *Traces;
     768             :   MachineTraceMetrics::Ensemble *MinInstr;
     769             :   SSACCmpConv CmpConv;
     770             : 
     771             : public:
     772             :   static char ID;
     773         967 :   AArch64ConditionalCompares() : MachineFunctionPass(ID) {
     774         967 :     initializeAArch64ConditionalComparesPass(*PassRegistry::getPassRegistry());
     775         967 :   }
     776             :   void getAnalysisUsage(AnalysisUsage &AU) const override;
     777             :   bool runOnMachineFunction(MachineFunction &MF) override;
     778         964 :   StringRef getPassName() const override {
     779         964 :     return "AArch64 Conditional Compares";
     780             :   }
     781             : 
     782             : private:
     783             :   bool tryConvert(MachineBasicBlock *);
     784             :   void updateDomTree(ArrayRef<MachineBasicBlock *> Removed);
     785             :   void updateLoops(ArrayRef<MachineBasicBlock *> Removed);
     786             :   void invalidateTraces();
     787             :   bool shouldConvert();
     788             : };
     789             : } // end anonymous namespace
     790             : 
     791             : char AArch64ConditionalCompares::ID = 0;
     792             : 
     793       75441 : INITIALIZE_PASS_BEGIN(AArch64ConditionalCompares, "aarch64-ccmp",
     794             :                       "AArch64 CCMP Pass", false, false)
     795       75441 : INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
     796       75441 : INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
     797       75441 : INITIALIZE_PASS_DEPENDENCY(MachineTraceMetrics)
     798      357464 : INITIALIZE_PASS_END(AArch64ConditionalCompares, "aarch64-ccmp",
     799             :                     "AArch64 CCMP Pass", false, false)
     800             : 
     801         966 : FunctionPass *llvm::createAArch64ConditionalCompares() {
     802         966 :   return new AArch64ConditionalCompares();
     803             : }
     804             : 
     805         957 : void AArch64ConditionalCompares::getAnalysisUsage(AnalysisUsage &AU) const {
     806             :   AU.addRequired<MachineBranchProbabilityInfo>();
     807             :   AU.addRequired<MachineDominatorTree>();
     808             :   AU.addPreserved<MachineDominatorTree>();
     809             :   AU.addRequired<MachineLoopInfo>();
     810             :   AU.addPreserved<MachineLoopInfo>();
     811             :   AU.addRequired<MachineTraceMetrics>();
     812             :   AU.addPreserved<MachineTraceMetrics>();
     813         957 :   MachineFunctionPass::getAnalysisUsage(AU);
     814         957 : }
     815             : 
     816             : /// Update the dominator tree after if-conversion erased some blocks.
     817          11 : void AArch64ConditionalCompares::updateDomTree(
     818             :     ArrayRef<MachineBasicBlock *> Removed) {
     819             :   // convert() removes CmpBB which was previously dominated by Head.
     820             :   // CmpBB children should be transferred to Head.
     821          11 :   MachineDomTreeNode *HeadNode = DomTree->getNode(CmpConv.Head);
     822          33 :   for (MachineBasicBlock *RemovedMBB : Removed) {
     823          11 :     MachineDomTreeNode *Node = DomTree->getNode(RemovedMBB);
     824             :     assert(Node != HeadNode && "Cannot erase the head node");
     825             :     assert(Node->getIDom() == HeadNode && "CmpBB should be dominated by Head");
     826          16 :     while (Node->getNumChildren())
     827           5 :       DomTree->changeImmediateDominator(Node->getChildren().back(), HeadNode);
     828          11 :     DomTree->eraseNode(RemovedMBB);
     829             :   }
     830          11 : }
     831             : 
     832             : /// Update LoopInfo after if-conversion.
     833             : void
     834          11 : AArch64ConditionalCompares::updateLoops(ArrayRef<MachineBasicBlock *> Removed) {
     835          11 :   if (!Loops)
     836             :     return;
     837          33 :   for (MachineBasicBlock *RemovedMBB : Removed)
     838          11 :     Loops->removeBlock(RemovedMBB);
     839             : }
     840             : 
     841             : /// Invalidate MachineTraceMetrics before if-conversion.
     842          11 : void AArch64ConditionalCompares::invalidateTraces() {
     843          11 :   Traces->invalidate(CmpConv.Head);
     844          11 :   Traces->invalidate(CmpConv.CmpBB);
     845          11 : }
     846             : 
     847             : /// Apply cost model and heuristics to the if-conversion in IfConv.
     848             : /// Return true if the conversion is a good idea.
     849             : ///
     850          31 : bool AArch64ConditionalCompares::shouldConvert() {
     851             :   // Stress testing mode disables all cost considerations.
     852          31 :   if (Stress)
     853             :     return true;
     854          21 :   if (!MinInstr)
     855          15 :     MinInstr = Traces->getEnsemble(MachineTraceMetrics::TS_MinInstrCount);
     856             : 
     857             :   // Head dominates CmpBB, so it is always included in its trace.
     858          21 :   MachineTraceMetrics::Trace Trace = MinInstr->getTrace(CmpConv.CmpBB);
     859             : 
     860             :   // If code size is the main concern
     861          21 :   if (MinSize) {
     862             :     int CodeSizeDelta = CmpConv.expectedCodeSizeDelta();
     863             :     DEBUG(dbgs() << "Code size delta:  " << CodeSizeDelta << '\n');
     864             :     // If we are minimizing the code size, do the conversion whatever
     865             :     // the cost is.
     866           0 :     if (CodeSizeDelta < 0)
     867             :       return true;
     868           0 :     if (CodeSizeDelta > 0) {
     869             :       DEBUG(dbgs() << "Code size is increasing, give up on this one.\n");
     870             :       return false;
     871             :     }
     872             :     // CodeSizeDelta == 0, continue with the regular heuristics
     873             :   }
     874             : 
     875             :   // Heuristic: The compare conversion delays the execution of the branch
     876             :   // instruction because we must wait for the inputs to the second compare as
     877             :   // well. The branch has no dependent instructions, but delaying it increases
     878             :   // the cost of a misprediction.
     879             :   //
     880             :   // Set a limit on the delay we will accept.
     881          21 :   unsigned DelayLimit = SchedModel.MispredictPenalty * 3 / 4;
     882             : 
     883             :   // Instruction depths can be computed for all trace instructions above CmpBB.
     884             :   unsigned HeadDepth =
     885          42 :       Trace.getInstrCycles(*CmpConv.Head->getFirstTerminator()).Depth;
     886             :   unsigned CmpBBDepth =
     887          42 :       Trace.getInstrCycles(*CmpConv.CmpBB->getFirstTerminator()).Depth;
     888             :   DEBUG(dbgs() << "Head depth:  " << HeadDepth
     889             :                << "\nCmpBB depth: " << CmpBBDepth << '\n');
     890          21 :   if (CmpBBDepth > HeadDepth + DelayLimit) {
     891             :     DEBUG(dbgs() << "Branch delay would be larger than " << DelayLimit
     892             :                  << " cycles.\n");
     893             :     return false;
     894             :   }
     895             : 
     896             :   // Check the resource depth at the bottom of CmpBB - these instructions will
     897             :   // be speculated.
     898          19 :   unsigned ResDepth = Trace.getResourceDepth(true);
     899             :   DEBUG(dbgs() << "Resources:   " << ResDepth << '\n');
     900             : 
     901             :   // Heuristic: The speculatively executed instructions must all be able to
     902             :   // merge into the Head block. The Head critical path should dominate the
     903             :   // resource cost of the speculated instructions.
     904          19 :   if (ResDepth > HeadDepth) {
     905             :     DEBUG(dbgs() << "Too many instructions to speculate.\n");
     906             :     return false;
     907             :   }
     908           1 :   return true;
     909             : }
     910             : 
     911       14813 : bool AArch64ConditionalCompares::tryConvert(MachineBasicBlock *MBB) {
     912             :   bool Changed = false;
     913       14835 :   while (CmpConv.canConvert(MBB) && shouldConvert()) {
     914          11 :     invalidateTraces();
     915             :     SmallVector<MachineBasicBlock *, 4> RemovedBlocks;
     916          11 :     CmpConv.convert(RemovedBlocks);
     917             :     Changed = true;
     918          11 :     updateDomTree(RemovedBlocks);
     919          11 :     updateLoops(RemovedBlocks);
     920             :   }
     921       14813 :   return Changed;
     922             : }
     923             : 
     924       12650 : bool AArch64ConditionalCompares::runOnMachineFunction(MachineFunction &MF) {
     925             :   DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n"
     926             :                << "********** Function: " << MF.getName() << '\n');
     927       12650 :   if (skipFunction(MF.getFunction()))
     928             :     return false;
     929             : 
     930       12649 :   TII = MF.getSubtarget().getInstrInfo();
     931       12649 :   TRI = MF.getSubtarget().getRegisterInfo();
     932       12649 :   SchedModel = MF.getSubtarget().getSchedModel();
     933       12649 :   MRI = &MF.getRegInfo();
     934       12649 :   DomTree = &getAnalysis<MachineDominatorTree>();
     935       12649 :   Loops = getAnalysisIfAvailable<MachineLoopInfo>();
     936       12649 :   MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
     937       12649 :   Traces = &getAnalysis<MachineTraceMetrics>();
     938       12649 :   MinInstr = nullptr;
     939       12649 :   MinSize = MF.getFunction().optForMinSize();
     940             : 
     941             :   bool Changed = false;
     942       12649 :   CmpConv.runOnMachineFunction(MF, MBPI);
     943             : 
     944             :   // Visit blocks in dominator tree pre-order. The pre-order enables multiple
     945             :   // cmp-conversions from the same head block.
     946             :   // Note that updateDomTree() modifies the children of the DomTree node
     947             :   // currently being visited. The df_iterator supports that; it doesn't look at
     948             :   // child_begin() / child_end() until after a node has been visited.
     949       52760 :   for (auto *I : depth_first(DomTree))
     950       14813 :     if (tryConvert(I->getBlock()))
     951             :       Changed = true;
     952             : 
     953       12649 :   return Changed;
     954      291969 : }

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