LCOV - code coverage report
Current view: top level - lib/Target/AArch64 - AArch64GenRegisterBankInfo.def (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 24 48 50.0 %
Date: 2017-09-14 15:23:50 Functions: 3 6 50.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- AArch64GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : /// \file
      10             : /// This file defines all the static objects used by AArch64RegisterBankInfo.
      11             : /// \todo This should be generated by TableGen.
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : namespace llvm {
      15             : RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{
      16             :     /* StartIdx, Length, RegBank */
      17             :     // 0: FPR 32-bit value.
      18             :     {0, 32, AArch64::FPRRegBank},
      19             :     // 1: FPR 64-bit value.
      20             :     {0, 64, AArch64::FPRRegBank},
      21             :     // 2: FPR 128-bit value.
      22             :     {0, 128, AArch64::FPRRegBank},
      23             :     // 3: FPR 256-bit value.
      24             :     {0, 256, AArch64::FPRRegBank},
      25             :     // 4: FPR 512-bit value.
      26             :     {0, 512, AArch64::FPRRegBank},
      27             :     // 5: GPR 32-bit value.
      28             :     {0, 32, AArch64::GPRRegBank},
      29             :     // 6: GPR 64-bit value.
      30             :     {0, 64, AArch64::GPRRegBank},
      31      578448 : };
      32             : 
      33             : // ValueMappings.
      34             : RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::ValMappings[]{
      35             :     /* BreakDown, NumBreakDowns */
      36             :     // 0: invalid
      37             :     {nullptr, 0},
      38             :     // 3-operands instructions (all binary operations should end up with one of
      39             :     // those mapping).
      40             :     // 1: FPR 32-bit value. <-- This must match First3OpsIdx.
      41             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
      42             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
      43             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
      44             :     // 4: FPR 64-bit value.
      45             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
      46             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
      47             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
      48             :     // 7: FPR 128-bit value.
      49             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
      50             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
      51             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
      52             :     // 10: FPR 256-bit value.
      53             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
      54             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
      55             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
      56             :     // 13: FPR 512-bit value.
      57             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
      58             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
      59             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
      60             :     // 16: GPR 32-bit value.
      61             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
      62             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
      63             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
      64             :     // 19: GPR 64-bit value. <-- This must match Last3OpsIdx.
      65             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
      66             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
      67             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
      68             :     // Cross register bank copies.
      69             :     // 22: FPR 32-bit value to GPR 32-bit value. <-- This must match
      70             :     //                                               FirstCrossRegCpyIdx.
      71             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
      72             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
      73             :     // 24: FPR 64-bit value to GPR 64-bit value.
      74             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
      75             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
      76             :     // 26: FPR 128-bit value to GPR 128-bit value (invalid)
      77             :     {nullptr, 1},
      78             :     {nullptr, 1},
      79             :     // 28: FPR 256-bit value to GPR 256-bit value (invalid)
      80             :     {nullptr, 1},
      81             :     {nullptr, 1},
      82             :     // 30: FPR 512-bit value to GPR 512-bit value (invalid)
      83             :     {nullptr, 1},
      84             :     {nullptr, 1},
      85             :     // 32: GPR 32-bit value to FPR 32-bit value.
      86             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
      87             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
      88             :     // 34: GPR 64-bit value to FPR 64-bit value. <-- This must match
      89             :     //                                               LastCrossRegCpyIdx.
      90             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
      91             :     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
      92     2675322 : };
      93             : 
      94           0 : bool AArch64GenRegisterBankInfo::checkPartialMap(unsigned Idx,
      95             :                                                  unsigned ValStartIdx,
      96             :                                                  unsigned ValLength,
      97             :                                                  const RegisterBank &RB) {
      98           0 :   const PartialMapping &Map = PartMappings[Idx - PartialMappingIdx::PMI_Min];
      99           0 :   return Map.StartIdx == ValStartIdx && Map.Length == ValLength &&
     100           0 :          Map.RegBank == &RB;
     101             : }
     102             : 
     103           0 : bool AArch64GenRegisterBankInfo::checkValueMapImpl(unsigned Idx,
     104             :                                                    unsigned FirstInBank,
     105             :                                                    unsigned Size,
     106             :                                                    unsigned Offset) {
     107           0 :   unsigned PartialMapBaseIdx = Idx - PartialMappingIdx::PMI_Min;
     108             :   const ValueMapping &Map =
     109           0 :       AArch64GenRegisterBankInfo::getValueMapping((PartialMappingIdx)FirstInBank, Size)[Offset];
     110           0 :   return Map.BreakDown == &PartMappings[PartialMapBaseIdx] &&
     111           0 :          Map.NumBreakDowns == 1;
     112             : }
     113             : 
     114           0 : bool AArch64GenRegisterBankInfo::checkPartialMappingIdx(
     115             :     PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias,
     116             :     ArrayRef<PartialMappingIdx> Order) {
     117           0 :   if (Order.front() != FirstAlias)
     118             :     return false;
     119           0 :   if (Order.back() != LastAlias)
     120             :     return false;
     121           0 :   if (Order.front() > Order.back())
     122             :     return false;
     123             : 
     124           0 :   PartialMappingIdx Previous = Order.front();
     125           0 :   bool First = true;
     126           0 :   for (const auto &Current : Order) {
     127           0 :     if (First) {
     128           0 :       First = false;
     129           0 :       continue;
     130             :     }
     131           0 :     if (Previous + 1 != Current)
     132             :       return false;
     133             :     Previous = Current;
     134             :   }
     135             :   return true;
     136             : }
     137             : 
     138        9843 : unsigned AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(unsigned RBIdx,
     139             :                                                              unsigned Size) {
     140        9843 :   if (RBIdx == PMI_FirstGPR) {
     141        4951 :     if (Size <= 32)
     142             :       return 0;
     143        2476 :     if (Size <= 64)
     144             :       return 1;
     145           0 :     return -1;
     146             :   }
     147        4892 :   if (RBIdx == PMI_FirstFPR) {
     148        4892 :     if (Size <= 32)
     149             :       return 0;
     150        2461 :     if (Size <= 64)
     151             :       return 1;
     152           8 :     if (Size <= 128)
     153             :       return 2;
     154           0 :     if (Size <= 256)
     155             :       return 3;
     156           0 :     if (Size <= 512)
     157             :       return 4;
     158           0 :     return -1;
     159             :   }
     160             :   return -1;
     161             : }
     162             : 
     163             : const RegisterBankInfo::ValueMapping *
     164        4995 : AArch64GenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx,
     165             :                                             unsigned Size) {
     166             :   assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that");
     167        4995 :   unsigned BaseIdxOffset = getRegBankBaseIdxOffset(RBIdx, Size);
     168        4995 :   if (BaseIdxOffset == -1u)
     169             :     return &ValMappings[InvalidIdx];
     170             : 
     171        4995 :   unsigned ValMappingIdx =
     172        4995 :       First3OpsIdx + (RBIdx - PartialMappingIdx::PMI_Min + BaseIdxOffset) *
     173             :                          ValueMappingIdx::DistanceBetweenRegBanks;
     174             :   assert(ValMappingIdx >= First3OpsIdx && ValMappingIdx <= Last3OpsIdx &&
     175             :          "Mapping out of bound");
     176             : 
     177        4995 :   return &ValMappings[ValMappingIdx];
     178             : }
     179             : 
     180             : AArch64GenRegisterBankInfo::PartialMappingIdx
     181             :     AArch64GenRegisterBankInfo::BankIDToCopyMapIdx[]{
     182             :         PMI_None,     // CCR
     183             :         PMI_FirstFPR, // FPR
     184             :         PMI_FirstGPR, // GPR
     185             :     };
     186             : 
     187             : const RegisterBankInfo::ValueMapping *
     188        9692 : AArch64GenRegisterBankInfo::getCopyMapping(unsigned DstBankID,
     189             :                                            unsigned SrcBankID, unsigned Size) {
     190             :   assert(DstBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
     191             :   assert(SrcBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
     192        9692 :   PartialMappingIdx DstRBIdx = BankIDToCopyMapIdx[DstBankID];
     193        9692 :   PartialMappingIdx SrcRBIdx = BankIDToCopyMapIdx[SrcBankID];
     194             :   assert(DstRBIdx != PMI_None && "No such mapping");
     195             :   assert(SrcRBIdx != PMI_None && "No such mapping");
     196             : 
     197        9692 :   if (DstRBIdx == SrcRBIdx)
     198        4844 :     return getValueMapping(DstRBIdx, Size);
     199             : 
     200             :   assert(Size <= 64 && "GPR cannot handle that size");
     201             :   unsigned ValMappingIdx =
     202             :       FirstCrossRegCpyIdx +
     203        4848 :       (DstRBIdx - PMI_Min + getRegBankBaseIdxOffset(DstRBIdx, Size)) *
     204        4848 :           ValueMappingIdx::DistanceBetweenCrossRegCpy;
     205             :   assert(ValMappingIdx >= FirstCrossRegCpyIdx &&
     206             :          ValMappingIdx <= LastCrossRegCpyIdx && "Mapping out of bound");
     207        4848 :   return &ValMappings[ValMappingIdx];
     208             : }
     209             : } // End llvm namespace.

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