LCOV - code coverage report
Current view: top level - lib/Target/AArch64 - AArch64ISelDAGToDAG.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 1631 1706 95.6 %
Date: 2018-06-17 00:07:59 Functions: 65 67 97.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file defines an instruction selector for the AArch64 target.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "AArch64TargetMachine.h"
      15             : #include "MCTargetDesc/AArch64AddressingModes.h"
      16             : #include "llvm/ADT/APSInt.h"
      17             : #include "llvm/CodeGen/SelectionDAGISel.h"
      18             : #include "llvm/IR/Function.h" // To access function attributes.
      19             : #include "llvm/IR/GlobalValue.h"
      20             : #include "llvm/IR/Intrinsics.h"
      21             : #include "llvm/Support/Debug.h"
      22             : #include "llvm/Support/ErrorHandling.h"
      23             : #include "llvm/Support/KnownBits.h"
      24             : #include "llvm/Support/MathExtras.h"
      25             : #include "llvm/Support/raw_ostream.h"
      26             : 
      27             : using namespace llvm;
      28             : 
      29             : #define DEBUG_TYPE "aarch64-isel"
      30             : 
      31             : //===--------------------------------------------------------------------===//
      32             : /// AArch64DAGToDAGISel - AArch64 specific code to select AArch64 machine
      33             : /// instructions for SelectionDAG operations.
      34             : ///
      35             : namespace {
      36             : 
      37        1111 : class AArch64DAGToDAGISel : public SelectionDAGISel {
      38             : 
      39             :   /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
      40             :   /// make the right decision when generating code for different targets.
      41             :   const AArch64Subtarget *Subtarget;
      42             : 
      43             :   bool ForCodeSize;
      44             : 
      45             : public:
      46             :   explicit AArch64DAGToDAGISel(AArch64TargetMachine &tm,
      47             :                                CodeGenOpt::Level OptLevel)
      48        1118 :       : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr),
      49        1118 :         ForCodeSize(false) {}
      50             : 
      51           8 :   StringRef getPassName() const override {
      52           8 :     return "AArch64 Instruction Selection";
      53             :   }
      54             : 
      55       13970 :   bool runOnMachineFunction(MachineFunction &MF) override {
      56       13970 :     ForCodeSize = MF.getFunction().optForSize();
      57       13970 :     Subtarget = &MF.getSubtarget<AArch64Subtarget>();
      58       13970 :     return SelectionDAGISel::runOnMachineFunction(MF);
      59             :   }
      60             : 
      61             :   void Select(SDNode *Node) override;
      62             : 
      63             :   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
      64             :   /// inline asm expressions.
      65             :   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
      66             :                                     unsigned ConstraintID,
      67             :                                     std::vector<SDValue> &OutOps) override;
      68             : 
      69             :   bool tryMLAV64LaneV128(SDNode *N);
      70             :   bool tryMULLV64LaneV128(unsigned IntNo, SDNode *N);
      71             :   bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift);
      72             :   bool SelectArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
      73             :   bool SelectNegArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
      74             :   bool SelectArithShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
      75        1964 :     return SelectShiftedRegister(N, false, Reg, Shift);
      76             :   }
      77             :   bool SelectLogicalShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
      78        1348 :     return SelectShiftedRegister(N, true, Reg, Shift);
      79             :   }
      80             :   bool SelectAddrModeIndexed7S8(SDValue N, SDValue &Base, SDValue &OffImm) {
      81             :     return SelectAddrModeIndexed7S(N, 1, Base, OffImm);
      82             :   }
      83             :   bool SelectAddrModeIndexed7S16(SDValue N, SDValue &Base, SDValue &OffImm) {
      84             :     return SelectAddrModeIndexed7S(N, 2, Base, OffImm);
      85             :   }
      86             :   bool SelectAddrModeIndexed7S32(SDValue N, SDValue &Base, SDValue &OffImm) {
      87          15 :     return SelectAddrModeIndexed7S(N, 4, Base, OffImm);
      88             :   }
      89             :   bool SelectAddrModeIndexed7S64(SDValue N, SDValue &Base, SDValue &OffImm) {
      90          18 :     return SelectAddrModeIndexed7S(N, 8, Base, OffImm);
      91             :   }
      92             :   bool SelectAddrModeIndexed7S128(SDValue N, SDValue &Base, SDValue &OffImm) {
      93             :     return SelectAddrModeIndexed7S(N, 16, Base, OffImm);
      94             :   }
      95             :   bool SelectAddrModeIndexed8(SDValue N, SDValue &Base, SDValue &OffImm) {
      96         424 :     return SelectAddrModeIndexed(N, 1, Base, OffImm);
      97             :   }
      98             :   bool SelectAddrModeIndexed16(SDValue N, SDValue &Base, SDValue &OffImm) {
      99         325 :     return SelectAddrModeIndexed(N, 2, Base, OffImm);
     100             :   }
     101             :   bool SelectAddrModeIndexed32(SDValue N, SDValue &Base, SDValue &OffImm) {
     102        1895 :     return SelectAddrModeIndexed(N, 4, Base, OffImm);
     103             :   }
     104             :   bool SelectAddrModeIndexed64(SDValue N, SDValue &Base, SDValue &OffImm) {
     105        4379 :     return SelectAddrModeIndexed(N, 8, Base, OffImm);
     106             :   }
     107             :   bool SelectAddrModeIndexed128(SDValue N, SDValue &Base, SDValue &OffImm) {
     108        1900 :     return SelectAddrModeIndexed(N, 16, Base, OffImm);
     109             :   }
     110             :   bool SelectAddrModeUnscaled8(SDValue N, SDValue &Base, SDValue &OffImm) {
     111          52 :     return SelectAddrModeUnscaled(N, 1, Base, OffImm);
     112             :   }
     113             :   bool SelectAddrModeUnscaled16(SDValue N, SDValue &Base, SDValue &OffImm) {
     114          69 :     return SelectAddrModeUnscaled(N, 2, Base, OffImm);
     115             :   }
     116             :   bool SelectAddrModeUnscaled32(SDValue N, SDValue &Base, SDValue &OffImm) {
     117         111 :     return SelectAddrModeUnscaled(N, 4, Base, OffImm);
     118             :   }
     119             :   bool SelectAddrModeUnscaled64(SDValue N, SDValue &Base, SDValue &OffImm) {
     120          99 :     return SelectAddrModeUnscaled(N, 8, Base, OffImm);
     121             :   }
     122             :   bool SelectAddrModeUnscaled128(SDValue N, SDValue &Base, SDValue &OffImm) {
     123          73 :     return SelectAddrModeUnscaled(N, 16, Base, OffImm);
     124             :   }
     125             : 
     126             :   template<int Width>
     127             :   bool SelectAddrModeWRO(SDValue N, SDValue &Base, SDValue &Offset,
     128             :                          SDValue &SignExtend, SDValue &DoShift) {
     129        9389 :     return SelectAddrModeWRO(N, Width / 8, Base, Offset, SignExtend, DoShift);
     130             :   }
     131             : 
     132             :   template<int Width>
     133             :   bool SelectAddrModeXRO(SDValue N, SDValue &Base, SDValue &Offset,
     134             :                          SDValue &SignExtend, SDValue &DoShift) {
     135        9287 :     return SelectAddrModeXRO(N, Width / 8, Base, Offset, SignExtend, DoShift);
     136             :   }
     137             : 
     138             : 
     139             :   /// Form sequences of consecutive 64/128-bit registers for use in NEON
     140             :   /// instructions making use of a vector-list (e.g. ldN, tbl). Vecs must have
     141             :   /// between 1 and 4 elements. If it contains a single element that is returned
     142             :   /// unchanged; otherwise a REG_SEQUENCE value is returned.
     143             :   SDValue createDTuple(ArrayRef<SDValue> Vecs);
     144             :   SDValue createQTuple(ArrayRef<SDValue> Vecs);
     145             : 
     146             :   /// Generic helper for the createDTuple/createQTuple
     147             :   /// functions. Those should almost always be called instead.
     148             :   SDValue createTuple(ArrayRef<SDValue> Vecs, const unsigned RegClassIDs[],
     149             :                       const unsigned SubRegs[]);
     150             : 
     151             :   void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
     152             : 
     153             :   bool tryIndexedLoad(SDNode *N);
     154             : 
     155             :   void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
     156             :                      unsigned SubRegIdx);
     157             :   void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
     158             :                          unsigned SubRegIdx);
     159             :   void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
     160             :   void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
     161             : 
     162             :   void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
     163             :   void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
     164             :   void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
     165             :   void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
     166             : 
     167             :   bool tryBitfieldExtractOp(SDNode *N);
     168             :   bool tryBitfieldExtractOpFromSExt(SDNode *N);
     169             :   bool tryBitfieldInsertOp(SDNode *N);
     170             :   bool tryBitfieldInsertInZeroOp(SDNode *N);
     171             :   bool tryShiftAmountMod(SDNode *N);
     172             : 
     173             :   bool tryReadRegister(SDNode *N);
     174             :   bool tryWriteRegister(SDNode *N);
     175             : 
     176             : // Include the pieces autogenerated from the target description.
     177             : #include "AArch64GenDAGISel.inc"
     178             : 
     179             : private:
     180             :   bool SelectShiftedRegister(SDValue N, bool AllowROR, SDValue &Reg,
     181             :                              SDValue &Shift);
     182             :   bool SelectAddrModeIndexed7S(SDValue N, unsigned Size, SDValue &Base,
     183             :                                SDValue &OffImm);
     184             :   bool SelectAddrModeIndexed(SDValue N, unsigned Size, SDValue &Base,
     185             :                              SDValue &OffImm);
     186             :   bool SelectAddrModeUnscaled(SDValue N, unsigned Size, SDValue &Base,
     187             :                               SDValue &OffImm);
     188             :   bool SelectAddrModeWRO(SDValue N, unsigned Size, SDValue &Base,
     189             :                          SDValue &Offset, SDValue &SignExtend,
     190             :                          SDValue &DoShift);
     191             :   bool SelectAddrModeXRO(SDValue N, unsigned Size, SDValue &Base,
     192             :                          SDValue &Offset, SDValue &SignExtend,
     193             :                          SDValue &DoShift);
     194             :   bool isWorthFolding(SDValue V) const;
     195             :   bool SelectExtendedSHL(SDValue N, unsigned Size, bool WantExtend,
     196             :                          SDValue &Offset, SDValue &SignExtend);
     197             : 
     198             :   template<unsigned RegWidth>
     199             :   bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos) {
     200          32 :     return SelectCVTFixedPosOperand(N, FixedPos, RegWidth);
     201             :   }
     202             : 
     203             :   bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos, unsigned Width);
     204             : 
     205             :   bool SelectCMP_SWAP(SDNode *N);
     206             : 
     207             : };
     208             : } // end anonymous namespace
     209             : 
     210             : /// isIntImmediate - This method tests to see if the node is a constant
     211             : /// operand. If so Imm will receive the 32-bit value.
     212             : static bool isIntImmediate(const SDNode *N, uint64_t &Imm) {
     213             :   if (const ConstantSDNode *C = dyn_cast<const ConstantSDNode>(N)) {
     214        1130 :     Imm = C->getZExtValue();
     215             :     return true;
     216             :   }
     217             :   return false;
     218             : }
     219             : 
     220             : // isIntImmediate - This method tests to see if a constant operand.
     221             : // If so Imm will receive the value.
     222             : static bool isIntImmediate(SDValue N, uint64_t &Imm) {
     223             :   return isIntImmediate(N.getNode(), Imm);
     224             : }
     225             : 
     226             : // isOpcWithIntImmediate - This method tests to see if the node is a specific
     227             : // opcode and that it has a immediate integer right operand.
     228             : // If so Imm will receive the 32 bit value.
     229             : static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc,
     230             :                                   uint64_t &Imm) {
     231        6422 :   return N->getOpcode() == Opc &&
     232        2581 :          isIntImmediate(N->getOperand(1).getNode(), Imm);
     233             : }
     234             : 
     235           2 : bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
     236             :     const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
     237             :   switch(ConstraintID) {
     238           0 :   default:
     239           0 :     llvm_unreachable("Unexpected asm memory constraint");
     240           2 :   case InlineAsm::Constraint_i:
     241             :   case InlineAsm::Constraint_m:
     242             :   case InlineAsm::Constraint_Q:
     243             :     // We need to make sure that this one operand does not end up in XZR, thus
     244             :     // require the address to be in a PointerRegClass register.
     245           2 :     const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
     246           2 :     const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF);
     247             :     SDLoc dl(Op);
     248           6 :     SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64);
     249             :     SDValue NewOp =
     250           4 :         SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
     251             :                                        dl, Op.getValueType(),
     252             :                                        Op, RC), 0);
     253           2 :     OutOps.push_back(NewOp);
     254             :     return false;
     255             :   }
     256             :   return true;
     257             : }
     258             : 
     259             : /// SelectArithImmed - Select an immediate value that can be represented as
     260             : /// a 12-bit value shifted left by either 0 or 12.  If so, return true with
     261             : /// Val set to the 12-bit value and Shift set to the shifter operand.
     262        3698 : bool AArch64DAGToDAGISel::SelectArithImmed(SDValue N, SDValue &Val,
     263             :                                            SDValue &Shift) {
     264             :   // This function is called from the addsub_shifted_imm ComplexPattern,
     265             :   // which lists [imm] as the list of opcode it's interested in, however
     266             :   // we still need to check whether the operand is actually an immediate
     267             :   // here because the ComplexPattern opcode list is only used in
     268             :   // root-level opcode matching.
     269             :   if (!isa<ConstantSDNode>(N.getNode()))
     270             :     return false;
     271             : 
     272        1345 :   uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
     273             :   unsigned ShiftAmt;
     274             : 
     275        1345 :   if (Immed >> 12 == 0) {
     276             :     ShiftAmt = 0;
     277         252 :   } else if ((Immed & 0xfff) == 0 && Immed >> 24 == 0) {
     278             :     ShiftAmt = 12;
     279             :     Immed = Immed >> 12;
     280             :   } else
     281             :     return false;
     282             : 
     283             :   unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
     284             :   SDLoc dl(N);
     285        2226 :   Val = CurDAG->getTargetConstant(Immed, dl, MVT::i32);
     286        2226 :   Shift = CurDAG->getTargetConstant(ShVal, dl, MVT::i32);
     287             :   return true;
     288             : }
     289             : 
     290             : /// SelectNegArithImmed - As above, but negates the value before trying to
     291             : /// select it.
     292        2615 : bool AArch64DAGToDAGISel::SelectNegArithImmed(SDValue N, SDValue &Val,
     293             :                                               SDValue &Shift) {
     294             :   // This function is called from the addsub_shifted_imm ComplexPattern,
     295             :   // which lists [imm] as the list of opcode it's interested in, however
     296             :   // we still need to check whether the operand is actually an immediate
     297             :   // here because the ComplexPattern opcode list is only used in
     298             :   // root-level opcode matching.
     299             :   if (!isa<ConstantSDNode>(N.getNode()))
     300             :     return false;
     301             : 
     302             :   // The immediate operand must be a 24-bit zero-extended immediate.
     303         611 :   uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
     304             : 
     305             :   // This negation is almost always valid, but "cmp wN, #0" and "cmn wN, #0"
     306             :   // have the opposite effect on the C flag, so this pattern mustn't match under
     307             :   // those circumstances.
     308         611 :   if (Immed == 0)
     309             :     return false;
     310             : 
     311             :   if (N.getValueType() == MVT::i32)
     312         309 :     Immed = ~((uint32_t)Immed) + 1;
     313             :   else
     314         197 :     Immed = ~Immed + 1ULL;
     315         506 :   if (Immed & 0xFFFFFFFFFF000000ULL)
     316             :     return false;
     317             : 
     318         218 :   Immed &= 0xFFFFFFULL;
     319         654 :   return SelectArithImmed(CurDAG->getConstant(Immed, SDLoc(N), MVT::i32), Val,
     320         218 :                           Shift);
     321             : }
     322             : 
     323             : /// getShiftTypeForNode - Translate a shift node to the corresponding
     324             : /// ShiftType value.
     325             : static AArch64_AM::ShiftExtendType getShiftTypeForNode(SDValue N) {
     326             :   switch (N.getOpcode()) {
     327             :   default:
     328             :     return AArch64_AM::InvalidShiftExtend;
     329             :   case ISD::SHL:
     330             :     return AArch64_AM::LSL;
     331             :   case ISD::SRL:
     332             :     return AArch64_AM::LSR;
     333             :   case ISD::SRA:
     334             :     return AArch64_AM::ASR;
     335             :   case ISD::ROTR:
     336             :     return AArch64_AM::ROR;
     337             :   }
     338             : }
     339             : 
     340             : /// Determine whether it is worth it to fold SHL into the addressing
     341             : /// mode.
     342          10 : static bool isWorthFoldingSHL(SDValue V) {
     343             :   assert(V.getOpcode() == ISD::SHL && "invalid opcode");
     344             :   // It is worth folding logical shift of up to three places.
     345             :   auto *CSD = dyn_cast<ConstantSDNode>(V.getOperand(1));
     346             :   if (!CSD)
     347             :     return false;
     348          20 :   unsigned ShiftVal = CSD->getZExtValue();
     349          10 :   if (ShiftVal > 3)
     350             :     return false;
     351             : 
     352             :   // Check if this particular node is reused in any non-memory related
     353             :   // operation.  If yes, do not try to fold this node into the address
     354             :   // computation, since the computation will be kept.
     355             :   const SDNode *Node = V.getNode();
     356          25 :   for (SDNode *UI : Node->uses())
     357          16 :     if (!isa<MemSDNode>(*UI))
     358          37 :       for (SDNode *UII : UI->uses())
     359          22 :         if (!isa<MemSDNode>(*UII))
     360             :           return false;
     361             :   return true;
     362             : }
     363             : 
     364             : /// Determine whether it is worth to fold V into an extended register.
     365        1418 : bool AArch64DAGToDAGISel::isWorthFolding(SDValue V) const {
     366             :   // Trivial if we are optimizing for code size or if there is only
     367             :   // one use of the value.
     368        2543 :   if (ForCodeSize || V.hasOneUse())
     369             :     return true;
     370             :   // If a subtarget has a fastpath LSL we can fold a logical shift into
     371             :   // the addressing mode and save a cycle.
     372         117 :   if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::SHL &&
     373           4 :       isWorthFoldingSHL(V))
     374             :     return true;
     375         107 :   if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::ADD) {
     376           6 :     const SDValue LHS = V.getOperand(0);
     377           6 :     const SDValue RHS = V.getOperand(1);
     378           6 :     if (LHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(LHS))
     379             :       return true;
     380           6 :     if (RHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(RHS))
     381             :       return true;
     382             :   }
     383             : 
     384             :   // It hurts otherwise, since the value will be reused.
     385             :   return false;
     386             : }
     387             : 
     388             : /// SelectShiftedRegister - Select a "shifted register" operand.  If the value
     389             : /// is not shifted, set the Shift operand to default of "LSL 0".  The logical
     390             : /// instructions allow the shifted register to be rotated, but the arithmetic
     391             : /// instructions do not.  The AllowROR parameter specifies whether ROR is
     392             : /// supported.
     393        3312 : bool AArch64DAGToDAGISel::SelectShiftedRegister(SDValue N, bool AllowROR,
     394             :                                                 SDValue &Reg, SDValue &Shift) {
     395        3312 :   AArch64_AM::ShiftExtendType ShType = getShiftTypeForNode(N);
     396         257 :   if (ShType == AArch64_AM::InvalidShiftExtend)
     397             :     return false;
     398         257 :   if (!AllowROR && ShType == AArch64_AM::ROR)
     399             :     return false;
     400             : 
     401             :   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
     402         217 :     unsigned BitSize = N.getValueSizeInBits();
     403         434 :     unsigned Val = RHS->getZExtValue() & (BitSize - 1);
     404             :     unsigned ShVal = AArch64_AM::getShifterImm(ShType, Val);
     405             : 
     406         434 :     Reg = N.getOperand(0);
     407         868 :     Shift = CurDAG->getTargetConstant(ShVal, SDLoc(N), MVT::i32);
     408         217 :     return isWorthFolding(N);
     409             :   }
     410             : 
     411             :   return false;
     412             : }
     413             : 
     414             : /// getExtendTypeForNode - Translate an extend node to the corresponding
     415             : /// ExtendType value.
     416             : static AArch64_AM::ShiftExtendType
     417        3706 : getExtendTypeForNode(SDValue N, bool IsLoadStore = false) {
     418        3706 :   if (N.getOpcode() == ISD::SIGN_EXTEND ||
     419             :       N.getOpcode() == ISD::SIGN_EXTEND_INREG) {
     420             :     EVT SrcVT;
     421         172 :     if (N.getOpcode() == ISD::SIGN_EXTEND_INREG)
     422             :       SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT();
     423             :     else
     424         119 :       SrcVT = N.getOperand(0).getValueType();
     425             : 
     426         172 :     if (!IsLoadStore && SrcVT == MVT::i8)
     427             :       return AArch64_AM::SXTB;
     428         153 :     else if (!IsLoadStore && SrcVT == MVT::i16)
     429             :       return AArch64_AM::SXTH;
     430             :     else if (SrcVT == MVT::i32)
     431             :       return AArch64_AM::SXTW;
     432             :     assert(SrcVT != MVT::i64 && "extend from 64-bits?");
     433             : 
     434           0 :     return AArch64_AM::InvalidShiftExtend;
     435        7009 :   } else if (N.getOpcode() == ISD::ZERO_EXTEND ||
     436             :              N.getOpcode() == ISD::ANY_EXTEND) {
     437          59 :     EVT SrcVT = N.getOperand(0).getValueType();
     438          59 :     if (!IsLoadStore && SrcVT == MVT::i8)
     439             :       return AArch64_AM::UXTB;
     440          59 :     else if (!IsLoadStore && SrcVT == MVT::i16)
     441             :       return AArch64_AM::UXTH;
     442             :     else if (SrcVT == MVT::i32)
     443             :       return AArch64_AM::UXTW;
     444             :     assert(SrcVT != MVT::i64 && "extend from 64-bits?");
     445             : 
     446           0 :     return AArch64_AM::InvalidShiftExtend;
     447        3475 :   } else if (N.getOpcode() == ISD::AND) {
     448             :     ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
     449             :     if (!CSD)
     450             :       return AArch64_AM::InvalidShiftExtend;
     451         132 :     uint64_t AndMask = CSD->getZExtValue();
     452             : 
     453         132 :     switch (AndMask) {
     454             :     default:
     455             :       return AArch64_AM::InvalidShiftExtend;
     456          33 :     case 0xFF:
     457          33 :       return !IsLoadStore ? AArch64_AM::UXTB : AArch64_AM::InvalidShiftExtend;
     458          25 :     case 0xFFFF:
     459          25 :       return !IsLoadStore ? AArch64_AM::UXTH : AArch64_AM::InvalidShiftExtend;
     460          12 :     case 0xFFFFFFFF:
     461          12 :       return AArch64_AM::UXTW;
     462             :     }
     463             :   }
     464             : 
     465             :   return AArch64_AM::InvalidShiftExtend;
     466             : }
     467             : 
     468             : // Helper for SelectMLAV64LaneV128 - Recognize high lane extracts.
     469         536 : static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) {
     470        1072 :   if (DL->getOpcode() != AArch64ISD::DUPLANE16 &&
     471             :       DL->getOpcode() != AArch64ISD::DUPLANE32)
     472             :     return false;
     473             : 
     474         109 :   SDValue SV = DL->getOperand(0);
     475         109 :   if (SV.getOpcode() != ISD::INSERT_SUBVECTOR)
     476             :     return false;
     477             : 
     478          52 :   SDValue EV = SV.getOperand(1);
     479          52 :   if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR)
     480             :     return false;
     481             : 
     482           0 :   ConstantSDNode *DLidx = cast<ConstantSDNode>(DL->getOperand(1).getNode());
     483           0 :   ConstantSDNode *EVidx = cast<ConstantSDNode>(EV.getOperand(1).getNode());
     484           0 :   LaneIdx = DLidx->getSExtValue() + EVidx->getSExtValue();
     485           0 :   LaneOp = EV.getOperand(0);
     486             : 
     487           0 :   return true;
     488             : }
     489             : 
     490             : // Helper for SelectOpcV64LaneV128 - Recognize operations where one operand is a
     491             : // high lane extract.
     492         268 : static bool checkV64LaneV128(SDValue Op0, SDValue Op1, SDValue &StdOp,
     493             :                              SDValue &LaneOp, int &LaneIdx) {
     494             : 
     495         268 :   if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) {
     496             :     std::swap(Op0, Op1);
     497         268 :     if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx))
     498             :       return false;
     499             :   }
     500           0 :   StdOp = Op1;
     501             :   return true;
     502             : }
     503             : 
     504             : /// SelectMLAV64LaneV128 - AArch64 supports vector MLAs where one multiplicand
     505             : /// is a lane in the upper half of a 128-bit vector.  Recognize and select this
     506             : /// so that we don't emit unnecessary lane extracts.
     507        2464 : bool AArch64DAGToDAGISel::tryMLAV64LaneV128(SDNode *N) {
     508             :   SDLoc dl(N);
     509        2464 :   SDValue Op0 = N->getOperand(0);
     510        2464 :   SDValue Op1 = N->getOperand(1);
     511        2464 :   SDValue MLAOp1;   // Will hold ordinary multiplicand for MLA.
     512        2464 :   SDValue MLAOp2;   // Will hold lane-accessed multiplicand for MLA.
     513        2464 :   int LaneIdx = -1; // Will hold the lane index.
     514             : 
     515        2518 :   if (Op1.getOpcode() != ISD::MUL ||
     516          54 :       !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
     517             :                         LaneIdx)) {
     518             :     std::swap(Op0, Op1);
     519        2532 :     if (Op1.getOpcode() != ISD::MUL ||
     520          68 :         !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
     521             :                           LaneIdx))
     522             :       return false;
     523             :   }
     524             : 
     525           0 :   SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64);
     526             : 
     527           0 :   SDValue Ops[] = { Op0, MLAOp1, MLAOp2, LaneIdxVal };
     528             : 
     529             :   unsigned MLAOpc = ~0U;
     530             : 
     531           0 :   switch (N->getSimpleValueType(0).SimpleTy) {
     532           0 :   default:
     533           0 :     llvm_unreachable("Unrecognized MLA.");
     534             :   case MVT::v4i16:
     535             :     MLAOpc = AArch64::MLAv4i16_indexed;
     536             :     break;
     537           0 :   case MVT::v8i16:
     538             :     MLAOpc = AArch64::MLAv8i16_indexed;
     539           0 :     break;
     540           0 :   case MVT::v2i32:
     541             :     MLAOpc = AArch64::MLAv2i32_indexed;
     542           0 :     break;
     543           0 :   case MVT::v4i32:
     544             :     MLAOpc = AArch64::MLAv4i32_indexed;
     545           0 :     break;
     546             :   }
     547             : 
     548           0 :   ReplaceNode(N, CurDAG->getMachineNode(MLAOpc, dl, N->getValueType(0), Ops));
     549           0 :   return true;
     550             : }
     551             : 
     552         146 : bool AArch64DAGToDAGISel::tryMULLV64LaneV128(unsigned IntNo, SDNode *N) {
     553             :   SDLoc dl(N);
     554         146 :   SDValue SMULLOp0;
     555         146 :   SDValue SMULLOp1;
     556             :   int LaneIdx;
     557             : 
     558         146 :   if (!checkV64LaneV128(N->getOperand(1), N->getOperand(2), SMULLOp0, SMULLOp1,
     559             :                         LaneIdx))
     560             :     return false;
     561             : 
     562           0 :   SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64);
     563             : 
     564           0 :   SDValue Ops[] = { SMULLOp0, SMULLOp1, LaneIdxVal };
     565             : 
     566             :   unsigned SMULLOpc = ~0U;
     567             : 
     568           0 :   if (IntNo == Intrinsic::aarch64_neon_smull) {
     569           0 :     switch (N->getSimpleValueType(0).SimpleTy) {
     570           0 :     default:
     571           0 :       llvm_unreachable("Unrecognized SMULL.");
     572             :     case MVT::v4i32:
     573             :       SMULLOpc = AArch64::SMULLv4i16_indexed;
     574             :       break;
     575           0 :     case MVT::v2i64:
     576             :       SMULLOpc = AArch64::SMULLv2i32_indexed;
     577           0 :       break;
     578             :     }
     579           0 :   } else if (IntNo == Intrinsic::aarch64_neon_umull) {
     580           0 :     switch (N->getSimpleValueType(0).SimpleTy) {
     581           0 :     default:
     582           0 :       llvm_unreachable("Unrecognized SMULL.");
     583             :     case MVT::v4i32:
     584             :       SMULLOpc = AArch64::UMULLv4i16_indexed;
     585             :       break;
     586           0 :     case MVT::v2i64:
     587             :       SMULLOpc = AArch64::UMULLv2i32_indexed;
     588           0 :       break;
     589             :     }
     590             :   } else
     591           0 :     llvm_unreachable("Unrecognized intrinsic.");
     592             : 
     593           0 :   ReplaceNode(N, CurDAG->getMachineNode(SMULLOpc, dl, N->getValueType(0), Ops));
     594           0 :   return true;
     595             : }
     596             : 
     597             : /// Instructions that accept extend modifiers like UXTW expect the register
     598             : /// being extended to be a GPR32, but the incoming DAG might be acting on a
     599             : /// GPR64 (either via SEXT_INREG or AND). Extract the appropriate low bits if
     600             : /// this is the case.
     601         295 : static SDValue narrowIfNeeded(SelectionDAG *CurDAG, SDValue N) {
     602             :   if (N.getValueType() == MVT::i32)
     603         250 :     return N;
     604             : 
     605             :   SDLoc dl(N);
     606          45 :   SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
     607          45 :   MachineSDNode *Node = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
     608          45 :                                                dl, MVT::i32, N, SubReg);
     609          45 :   return SDValue(Node, 0);
     610             : }
     611             : 
     612             : 
     613             : /// SelectArithExtendedRegister - Select a "extended register" operand.  This
     614             : /// operand folds in an extend followed by an optional left shift.
     615        2768 : bool AArch64DAGToDAGISel::SelectArithExtendedRegister(SDValue N, SDValue &Reg,
     616             :                                                       SDValue &Shift) {
     617             :   unsigned ShiftVal = 0;
     618             :   AArch64_AM::ShiftExtendType Ext;
     619             : 
     620        2768 :   if (N.getOpcode() == ISD::SHL) {
     621             :     ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
     622             :     if (!CSD)
     623             :       return false;
     624         292 :     ShiftVal = CSD->getZExtValue();
     625         146 :     if (ShiftVal > 4)
     626             :       return false;
     627             : 
     628         124 :     Ext = getExtendTypeForNode(N.getOperand(0));
     629         124 :     if (Ext == AArch64_AM::InvalidShiftExtend)
     630             :       return false;
     631             : 
     632         114 :     Reg = N.getOperand(0).getOperand(0);
     633             :   } else {
     634        2618 :     Ext = getExtendTypeForNode(N);
     635        2618 :     if (Ext == AArch64_AM::InvalidShiftExtend)
     636             :       return false;
     637             : 
     638         119 :     Reg = N.getOperand(0);
     639             : 
     640             :     // Don't match if free 32-bit -> 64-bit zext can be used instead.
     641          22 :     if (Ext == AArch64_AM::UXTW &&
     642         254 :         Reg->getValueType(0).getSizeInBits() == 32 && isDef32(*Reg.getNode()))
     643             :       return false;
     644             :   }
     645             : 
     646             :   // AArch64 mandates that the RHS of the operation must use the smallest
     647             :   // register class that could contain the size being extended from.  Thus,
     648             :   // if we're folding a (sext i8), we need the RHS to be a GPR32, even though
     649             :   // there might not be an actual 32-bit value in the program.  We can
     650             :   // (harmlessly) synthesize one by injected an EXTRACT_SUBREG here.
     651             :   assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX);
     652         170 :   Reg = narrowIfNeeded(CurDAG, Reg);
     653         510 :   Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N),
     654         170 :                                     MVT::i32);
     655         170 :   return isWorthFolding(N);
     656             : }
     657             : 
     658             : /// If there's a use of this ADDlow that's not itself a load/store then we'll
     659             : /// need to create a real ADD instruction from it anyway and there's no point in
     660             : /// folding it into the mem op. Theoretically, it shouldn't matter, but there's
     661             : /// a single pseudo-instruction for an ADRP/ADD pair so over-aggressive folding
     662             : /// leads to duplicated ADRP instructions.
     663        1565 : static bool isWorthFoldingADDlow(SDValue N) {
     664        7996 :   for (auto Use : N->uses()) {
     665        7286 :     if (Use->getOpcode() != ISD::LOAD && Use->getOpcode() != ISD::STORE &&
     666        5062 :         Use->getOpcode() != ISD::ATOMIC_LOAD &&
     667             :         Use->getOpcode() != ISD::ATOMIC_STORE)
     668             :       return false;
     669             : 
     670             :     // ldar and stlr have much more restrictive addressing modes (just a
     671             :     // register).
     672        9732 :     if (isStrongerThanMonotonic(cast<MemSDNode>(Use)->getOrdering()))
     673             :       return false;
     674             :   }
     675             : 
     676             :   return true;
     677             : }
     678             : 
     679             : /// SelectAddrModeIndexed7S - Select a "register plus scaled signed 7-bit
     680             : /// immediate" address.  The "Size" argument is the size in bytes of the memory
     681             : /// reference, which determines the scale.
     682          33 : bool AArch64DAGToDAGISel::SelectAddrModeIndexed7S(SDValue N, unsigned Size,
     683             :                                                   SDValue &Base,
     684             :                                                   SDValue &OffImm) {
     685             :   SDLoc dl(N);
     686          33 :   const DataLayout &DL = CurDAG->getDataLayout();
     687             :   const TargetLowering *TLI = getTargetLowering();
     688          33 :   if (N.getOpcode() == ISD::FrameIndex) {
     689           1 :     int FI = cast<FrameIndexSDNode>(N)->getIndex();
     690           2 :     Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
     691           2 :     OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
     692             :     return true;
     693             :   }
     694             : 
     695             :   // As opposed to the (12-bit) Indexed addressing mode below, the 7-bit signed
     696             :   // selected here doesn't support labels/immediates, only base+offset.
     697             : 
     698          32 :   if (CurDAG->isBaseWithConstantOffset(N)) {
     699             :     if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
     700          19 :       int64_t RHSC = RHS->getSExtValue();
     701             :       unsigned Scale = Log2_32(Size);
     702          33 :       if ((RHSC & (Size - 1)) == 0 && RHSC >= -(0x40 << Scale) &&
     703          14 :           RHSC < (0x40 << Scale)) {
     704          12 :         Base = N.getOperand(0);
     705          24 :         if (Base.getOpcode() == ISD::FrameIndex) {
     706           1 :           int FI = cast<FrameIndexSDNode>(Base)->getIndex();
     707           2 :           Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
     708             :         }
     709          24 :         OffImm = CurDAG->getTargetConstant(RHSC >> Scale, dl, MVT::i64);
     710             :         return true;
     711             :       }
     712             :     }
     713             :   }
     714             : 
     715             :   // Base only. The address will be materialized into a register before
     716             :   // the memory is accessed.
     717             :   //    add x0, Xbase, #offset
     718             :   //    stp x1, x2, [x0]
     719          20 :   Base = N;
     720          40 :   OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
     721             :   return true;
     722             : }
     723             : 
     724             : /// SelectAddrModeIndexed - Select a "register plus scaled unsigned 12-bit
     725             : /// immediate" address.  The "Size" argument is the size in bytes of the memory
     726             : /// reference, which determines the scale.
     727        8923 : bool AArch64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size,
     728             :                                               SDValue &Base, SDValue &OffImm) {
     729             :   SDLoc dl(N);
     730        8923 :   const DataLayout &DL = CurDAG->getDataLayout();
     731             :   const TargetLowering *TLI = getTargetLowering();
     732        8923 :   if (N.getOpcode() == ISD::FrameIndex) {
     733         859 :     int FI = cast<FrameIndexSDNode>(N)->getIndex();
     734        1718 :     Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
     735        1718 :     OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
     736         859 :     return true;
     737             :   }
     738             : 
     739        8064 :   if (N.getOpcode() == AArch64ISD::ADDlow && isWorthFoldingADDlow(N)) {
     740             :     GlobalAddressSDNode *GAN =
     741        1469 :         dyn_cast<GlobalAddressSDNode>(N.getOperand(1).getNode());
     742        1469 :     Base = N.getOperand(0);
     743        1469 :     OffImm = N.getOperand(1);
     744        1469 :     if (!GAN)
     745             :       return true;
     746             : 
     747        1348 :     if (GAN->getOffset() % Size == 0) {
     748        1347 :       const GlobalValue *GV = GAN->getGlobal();
     749        1347 :       unsigned Alignment = GV->getAlignment();
     750        1347 :       Type *Ty = GV->getValueType();
     751        1347 :       if (Alignment == 0 && Ty->isSized())
     752        1119 :         Alignment = DL.getABITypeAlignment(Ty);
     753             : 
     754        1347 :       if (Alignment >= Size)
     755             :         return true;
     756             :     }
     757             :   }
     758             : 
     759        6618 :   if (CurDAG->isBaseWithConstantOffset(N)) {
     760             :     if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
     761        5506 :       int64_t RHSC = (int64_t)RHS->getZExtValue();
     762             :       unsigned Scale = Log2_32(Size);
     763        2753 :       if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 && RHSC < (0x1000 << Scale)) {
     764        2330 :         Base = N.getOperand(0);
     765        4660 :         if (Base.getOpcode() == ISD::FrameIndex) {
     766         313 :           int FI = cast<FrameIndexSDNode>(Base)->getIndex();
     767         626 :           Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
     768             :         }
     769        4660 :         OffImm = CurDAG->getTargetConstant(RHSC >> Scale, dl, MVT::i64);
     770        2330 :         return true;
     771             :       }
     772             :     }
     773             :   }
     774             : 
     775             :   // Before falling back to our general case, check if the unscaled
     776             :   // instructions can handle this. If so, that's preferable.
     777        4288 :   if (SelectAddrModeUnscaled(N, Size, Base, OffImm))
     778             :     return false;
     779             : 
     780             :   // Base only. The address will be materialized into a register before
     781             :   // the memory is accessed.
     782             :   //    add x0, Xbase, #offset
     783             :   //    ldr x0, [x0]
     784        3884 :   Base = N;
     785        7768 :   OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
     786        3884 :   return true;
     787             : }
     788             : 
     789             : /// SelectAddrModeUnscaled - Select a "register plus unscaled signed 9-bit
     790             : /// immediate" address.  This should only match when there is an offset that
     791             : /// is not valid for a scaled immediate addressing mode.  The "Size" argument
     792             : /// is the size in bytes of the memory reference, which is needed here to know
     793             : /// what is valid for a scaled immediate.
     794        4692 : bool AArch64DAGToDAGISel::SelectAddrModeUnscaled(SDValue N, unsigned Size,
     795             :                                                  SDValue &Base,
     796             :                                                  SDValue &OffImm) {
     797        4692 :   if (!CurDAG->isBaseWithConstantOffset(N))
     798             :     return false;
     799             :   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
     800         827 :     int64_t RHSC = RHS->getSExtValue();
     801             :     // If the offset is valid as a scaled immediate, don't match here.
     802         836 :     if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 &&
     803           9 :         RHSC < (0x1000 << Log2_32(Size)))
     804             :       return false;
     805         827 :     if (RHSC >= -256 && RHSC < 256) {
     806         808 :       Base = N.getOperand(0);
     807        1616 :       if (Base.getOpcode() == ISD::FrameIndex) {
     808           6 :         int FI = cast<FrameIndexSDNode>(Base)->getIndex();
     809             :         const TargetLowering *TLI = getTargetLowering();
     810          12 :         Base = CurDAG->getTargetFrameIndex(
     811           6 :             FI, TLI->getPointerTy(CurDAG->getDataLayout()));
     812             :       }
     813        2424 :       OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i64);
     814             :       return true;
     815             :     }
     816             :   }
     817             :   return false;
     818             : }
     819             : 
     820          11 : static SDValue Widen(SelectionDAG *CurDAG, SDValue N) {
     821             :   SDLoc dl(N);
     822          11 :   SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
     823             :   SDValue ImpDef = SDValue(
     824          22 :       CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::i64), 0);
     825          11 :   MachineSDNode *Node = CurDAG->getMachineNode(
     826          11 :       TargetOpcode::INSERT_SUBREG, dl, MVT::i64, ImpDef, N, SubReg);
     827          22 :   return SDValue(Node, 0);
     828             : }
     829             : 
     830             : /// Check if the given SHL node (\p N), can be used to form an
     831             : /// extended register for an addressing mode.
     832         467 : bool AArch64DAGToDAGISel::SelectExtendedSHL(SDValue N, unsigned Size,
     833             :                                             bool WantExtend, SDValue &Offset,
     834             :                                             SDValue &SignExtend) {
     835             :   assert(N.getOpcode() == ISD::SHL && "Invalid opcode.");
     836             :   ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
     837         934 :   if (!CSD || (CSD->getZExtValue() & 0x7) != CSD->getZExtValue())
     838             :     return false;
     839             : 
     840             :   SDLoc dl(N);
     841         467 :   if (WantExtend) {
     842             :     AArch64_AM::ShiftExtendType Ext =
     843         263 :         getExtendTypeForNode(N.getOperand(0), true);
     844         263 :     if (Ext == AArch64_AM::InvalidShiftExtend)
     845             :       return false;
     846             : 
     847         122 :     Offset = narrowIfNeeded(CurDAG, N.getOperand(0).getOperand(0));
     848         122 :     SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl,
     849          61 :                                            MVT::i32);
     850             :   } else {
     851         204 :     Offset = N.getOperand(0);
     852         408 :     SignExtend = CurDAG->getTargetConstant(0, dl, MVT::i32);
     853             :   }
     854             : 
     855             :   unsigned LegalShiftVal = Log2_32(Size);
     856         530 :   unsigned ShiftVal = CSD->getZExtValue();
     857             : 
     858         265 :   if (ShiftVal != 0 && ShiftVal != LegalShiftVal)
     859             :     return false;
     860             : 
     861         240 :   return isWorthFolding(N);
     862             : }
     863             : 
     864        9389 : bool AArch64DAGToDAGISel::SelectAddrModeWRO(SDValue N, unsigned Size,
     865             :                                             SDValue &Base, SDValue &Offset,
     866             :                                             SDValue &SignExtend,
     867             :                                             SDValue &DoShift) {
     868        9389 :   if (N.getOpcode() != ISD::ADD)
     869             :     return false;
     870        3222 :   SDValue LHS = N.getOperand(0);
     871        3222 :   SDValue RHS = N.getOperand(1);
     872             :   SDLoc dl(N);
     873             : 
     874             :   // We don't want to match immediate adds here, because they are better lowered
     875             :   // to the register-immediate addressing modes.
     876             :   if (isa<ConstantSDNode>(LHS) || isa<ConstantSDNode>(RHS))
     877             :     return false;
     878             : 
     879             :   // Check if this particular node is reused in any non-memory related
     880             :   // operation.  If yes, do not try to fold this node into the address
     881             :   // computation, since the computation will be kept.
     882             :   const SDNode *Node = N.getNode();
     883         870 :   for (SDNode *UI : Node->uses()) {
     884         461 :     if (!isa<MemSDNode>(*UI))
     885             :       return false;
     886             :   }
     887             : 
     888             :   // Remember if it is worth folding N when it produces extended register.
     889         409 :   bool IsExtendedRegisterWorthFolding = isWorthFolding(N);
     890             : 
     891             :   // Try to match a shifted extend on the RHS.
     892        1040 :   if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
     893         223 :       SelectExtendedSHL(RHS, Size, true, Offset, SignExtend)) {
     894          50 :     Base = LHS;
     895         100 :     DoShift = CurDAG->getTargetConstant(true, dl, MVT::i32);
     896             :     return true;
     897             :   }
     898             : 
     899             :   // Try to match a shifted extend on the LHS.
     900         757 :   if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
     901          40 :       SelectExtendedSHL(LHS, Size, true, Offset, SignExtend)) {
     902           7 :     Base = RHS;
     903          14 :     DoShift = CurDAG->getTargetConstant(true, dl, MVT::i32);
     904             :     return true;
     905             :   }
     906             : 
     907             :   // There was no shift, whatever else we find.
     908         704 :   DoShift = CurDAG->getTargetConstant(false, dl, MVT::i32);
     909             : 
     910             :   AArch64_AM::ShiftExtendType Ext = AArch64_AM::InvalidShiftExtend;
     911             :   // Try to match an unshifted extend on the LHS.
     912         703 :   if (IsExtendedRegisterWorthFolding &&
     913             :       (Ext = getExtendTypeForNode(LHS, true)) !=
     914             :           AArch64_AM::InvalidShiftExtend) {
     915           1 :     Base = RHS;
     916           1 :     Offset = narrowIfNeeded(CurDAG, LHS.getOperand(0));
     917           2 :     SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl,
     918           1 :                                            MVT::i32);
     919           1 :     if (isWorthFolding(LHS))
     920             :       return true;
     921             :   }
     922             : 
     923             :   // Try to match an unshifted extend on the RHS.
     924         351 :   if (IsExtendedRegisterWorthFolding &&
     925             :       (Ext = getExtendTypeForNode(RHS, true)) !=
     926             :           AArch64_AM::InvalidShiftExtend) {
     927          49 :     Base = LHS;
     928          49 :     Offset = narrowIfNeeded(CurDAG, RHS.getOperand(0));
     929          98 :     SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl,
     930          49 :                                            MVT::i32);
     931          49 :     if (isWorthFolding(RHS))
     932             :       return true;
     933             :   }
     934             : 
     935             :   return false;
     936             : }
     937             : 
     938             : // Check if the given immediate is preferred by ADD. If an immediate can be
     939             : // encoded in an ADD, or it can be encoded in an "ADD LSL #12" and can not be
     940             : // encoded by one MOVZ, return true.
     941             : static bool isPreferredADD(int64_t ImmOff) {
     942             :   // Constant in [0x0, 0xfff] can be encoded in ADD.
     943         798 :   if ((ImmOff & 0xfffffffffffff000LL) == 0x0LL)
     944             :     return true;
     945             :   // Check if it can be encoded in an "ADD LSL #12".
     946         373 :   if ((ImmOff & 0xffffffffff000fffLL) == 0x0LL)
     947             :     // As a single MOVZ is faster than a "ADD of LSL #12", ignore such constant.
     948          31 :     return (ImmOff & 0xffffffffff00ffffLL) != 0x0LL &&
     949          15 :            (ImmOff & 0xffffffffffff0fffLL) != 0x0LL;
     950             :   return false;
     951             : }
     952             : 
     953        9287 : bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
     954             :                                             SDValue &Base, SDValue &Offset,
     955             :                                             SDValue &SignExtend,
     956             :                                             SDValue &DoShift) {
     957        9287 :   if (N.getOpcode() != ISD::ADD)
     958             :     return false;
     959        3120 :   SDValue LHS = N.getOperand(0);
     960        3120 :   SDValue RHS = N.getOperand(1);
     961             :   SDLoc DL(N);
     962             : 
     963             :   // Check if this particular node is reused in any non-memory related
     964             :   // operation.  If yes, do not try to fold this node into the address
     965             :   // computation, since the computation will be kept.
     966             :   const SDNode *Node = N.getNode();
     967        6529 :   for (SDNode *UI : Node->uses()) {
     968        3458 :     if (!isa<MemSDNode>(*UI))
     969             :       return false;
     970             :   }
     971             : 
     972             :   // Watch out if RHS is a wide immediate, it can not be selected into
     973             :   // [BaseReg+Imm] addressing mode. Also it may not be able to be encoded into
     974             :   // ADD/SUB. Instead it will use [BaseReg + 0] address mode and generate
     975             :   // instructions like:
     976             :   //     MOV  X0, WideImmediate
     977             :   //     ADD  X1, BaseReg, X0
     978             :   //     LDR  X2, [X1, 0]
     979             :   // For such situation, using [BaseReg, XReg] addressing mode can save one
     980             :   // ADD/SUB:
     981             :   //     MOV  X0, WideImmediate
     982             :   //     LDR  X2, [BaseReg, X0]
     983             :   if (isa<ConstantSDNode>(RHS)) {
     984        5528 :     int64_t ImmOff = (int64_t)cast<ConstantSDNode>(RHS)->getZExtValue();
     985             :     unsigned Scale = Log2_32(Size);
     986             :     // Skip the immediate can be selected by load/store addressing mode.
     987             :     // Also skip the immediate can be encoded by a single ADD (SUB is also
     988             :     // checked by using -ImmOff).
     989        5390 :     if ((ImmOff % Size == 0 && ImmOff >= 0 && ImmOff < (0x1000 << Scale)) ||
     990        3102 :         isPreferredADD(ImmOff) || isPreferredADD(-ImmOff))
     991        2739 :       return false;
     992             : 
     993          25 :     SDValue Ops[] = { RHS };
     994             :     SDNode *MOVI =
     995          50 :         CurDAG->getMachineNode(AArch64::MOVi64imm, DL, MVT::i64, Ops);
     996             :     SDValue MOVIV = SDValue(MOVI, 0);
     997             :     // This ADD of two X register will be selected into [Reg+Reg] mode.
     998          50 :     N = CurDAG->getNode(ISD::ADD, DL, MVT::i64, LHS, MOVIV);
     999             :   }
    1000             : 
    1001             :   // Remember if it is worth folding N when it produces extended register.
    1002         332 :   bool IsExtendedRegisterWorthFolding = isWorthFolding(N);
    1003             : 
    1004             :   // Try to match a shifted extend on the RHS.
    1005         811 :   if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
    1006         173 :       SelectExtendedSHL(RHS, Size, false, Offset, SignExtend)) {
    1007         118 :     Base = LHS;
    1008         236 :     DoShift = CurDAG->getTargetConstant(true, DL, MVT::i32);
    1009             :     return true;
    1010             :   }
    1011             : 
    1012             :   // Try to match a shifted extend on the LHS.
    1013         433 :   if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
    1014          31 :       SelectExtendedSHL(LHS, Size, false, Offset, SignExtend)) {
    1015          31 :     Base = RHS;
    1016          62 :     DoShift = CurDAG->getTargetConstant(true, DL, MVT::i32);
    1017             :     return true;
    1018             :   }
    1019             : 
    1020             :   // Match any non-shifted, non-extend, non-immediate add expression.
    1021         183 :   Base = LHS;
    1022         183 :   Offset = RHS;
    1023         366 :   SignExtend = CurDAG->getTargetConstant(false, DL, MVT::i32);
    1024         366 :   DoShift = CurDAG->getTargetConstant(false, DL, MVT::i32);
    1025             :   // Reg1 + Reg2 is free: no check needed.
    1026             :   return true;
    1027             : }
    1028             : 
    1029             : SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) {
    1030             :   static const unsigned RegClassIDs[] = {
    1031             :       AArch64::DDRegClassID, AArch64::DDDRegClassID, AArch64::DDDDRegClassID};
    1032             :   static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1,
    1033             :                                      AArch64::dsub2, AArch64::dsub3};
    1034             : 
    1035         149 :   return createTuple(Regs, RegClassIDs, SubRegs);
    1036             : }
    1037             : 
    1038             : SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) {
    1039             :   static const unsigned RegClassIDs[] = {
    1040             :       AArch64::QQRegClassID, AArch64::QQQRegClassID, AArch64::QQQQRegClassID};
    1041             :   static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1,
    1042             :                                      AArch64::qsub2, AArch64::qsub3};
    1043             : 
    1044         385 :   return createTuple(Regs, RegClassIDs, SubRegs);
    1045             : }
    1046             : 
    1047         534 : SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs,
    1048             :                                          const unsigned RegClassIDs[],
    1049             :                                          const unsigned SubRegs[]) {
    1050             :   // There's no special register-class for a vector-list of 1 element: it's just
    1051             :   // a vector.
    1052         534 :   if (Regs.size() == 1)
    1053          22 :     return Regs[0];
    1054             : 
    1055             :   assert(Regs.size() >= 2 && Regs.size() <= 4);
    1056             : 
    1057             :   SDLoc DL(Regs[0]);
    1058             : 
    1059             :   SmallVector<SDValue, 4> Ops;
    1060             : 
    1061             :   // First operand of REG_SEQUENCE is the desired RegClass.
    1062         512 :   Ops.push_back(
    1063        1536 :       CurDAG->getTargetConstant(RegClassIDs[Regs.size() - 2], DL, MVT::i32));
    1064             : 
    1065             :   // Then we get pairs of source & subregister-position for the components.
    1066        3554 :   for (unsigned i = 0; i < Regs.size(); ++i) {
    1067        1521 :     Ops.push_back(Regs[i]);
    1068        3042 :     Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], DL, MVT::i32));
    1069             :   }
    1070             : 
    1071             :   SDNode *N =
    1072        1024 :       CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::Untyped, Ops);
    1073         512 :   return SDValue(N, 0);
    1074             : }
    1075             : 
    1076          14 : void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc,
    1077             :                                       bool isExt) {
    1078             :   SDLoc dl(N);
    1079          28 :   EVT VT = N->getValueType(0);
    1080             : 
    1081          14 :   unsigned ExtOff = isExt;
    1082             : 
    1083             :   // Form a REG_SEQUENCE to force register allocation.
    1084          14 :   unsigned Vec0Off = ExtOff + 1;
    1085          14 :   SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off,
    1086          28 :                                N->op_begin() + Vec0Off + NumVecs);
    1087          14 :   SDValue RegSeq = createQTuple(Regs);
    1088             : 
    1089             :   SmallVector<SDValue, 6> Ops;
    1090          14 :   if (isExt)
    1091          12 :     Ops.push_back(N->getOperand(1));
    1092          14 :   Ops.push_back(RegSeq);
    1093          28 :   Ops.push_back(N->getOperand(NumVecs + ExtOff + 1));
    1094          28 :   ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, Ops));
    1095          14 : }
    1096             : 
    1097        5707 : bool AArch64DAGToDAGISel::tryIndexedLoad(SDNode *N) {
    1098             :   LoadSDNode *LD = cast<LoadSDNode>(N);
    1099        5707 :   if (LD->isUnindexed())
    1100             :     return false;
    1101          49 :   EVT VT = LD->getMemoryVT();
    1102          98 :   EVT DstVT = N->getValueType(0);
    1103             :   ISD::MemIndexedMode AM = LD->getAddressingMode();
    1104          49 :   bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
    1105             : 
    1106             :   // We're not doing validity checking here. That was done when checking
    1107             :   // if we should mark the load as indexed or not. We're just selecting
    1108             :   // the right instruction.
    1109             :   unsigned Opcode = 0;
    1110             : 
    1111             :   ISD::LoadExtType ExtType = LD->getExtensionType();
    1112             :   bool InsertTo64 = false;
    1113             :   if (VT == MVT::i64)
    1114           3 :     Opcode = IsPre ? AArch64::LDRXpre : AArch64::LDRXpost;
    1115             :   else if (VT == MVT::i32) {
    1116           8 :     if (ExtType == ISD::NON_EXTLOAD)
    1117           7 :       Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost;
    1118           1 :     else if (ExtType == ISD::SEXTLOAD)
    1119           1 :       Opcode = IsPre ? AArch64::LDRSWpre : AArch64::LDRSWpost;
    1120             :     else {
    1121           0 :       Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost;
    1122             :       InsertTo64 = true;
    1123             :       // The result of the load is only i32. It's the subreg_to_reg that makes
    1124             :       // it into an i64.
    1125           0 :       DstVT = MVT::i32;
    1126             :     }
    1127             :   } else if (VT == MVT::i16) {
    1128           4 :     if (ExtType == ISD::SEXTLOAD) {
    1129             :       if (DstVT == MVT::i64)
    1130           1 :         Opcode = IsPre ? AArch64::LDRSHXpre : AArch64::LDRSHXpost;
    1131             :       else
    1132           1 :         Opcode = IsPre ? AArch64::LDRSHWpre : AArch64::LDRSHWpost;
    1133             :     } else {
    1134           2 :       Opcode = IsPre ? AArch64::LDRHHpre : AArch64::LDRHHpost;
    1135             :       InsertTo64 = DstVT == MVT::i64;
    1136             :       // The result of the load is only i32. It's the subreg_to_reg that makes
    1137             :       // it into an i64.
    1138           2 :       DstVT = MVT::i32;
    1139             :     }
    1140             :   } else if (VT == MVT::i8) {
    1141           5 :     if (ExtType == ISD::SEXTLOAD) {
    1142             :       if (DstVT == MVT::i64)
    1143           1 :         Opcode = IsPre ? AArch64::LDRSBXpre : AArch64::LDRSBXpost;
    1144             :       else
    1145           1 :         Opcode = IsPre ? AArch64::LDRSBWpre : AArch64::LDRSBWpost;
    1146             :     } else {
    1147           3 :       Opcode = IsPre ? AArch64::LDRBBpre : AArch64::LDRBBpost;
    1148             :       InsertTo64 = DstVT == MVT::i64;
    1149             :       // The result of the load is only i32. It's the subreg_to_reg that makes
    1150             :       // it into an i64.
    1151           3 :       DstVT = MVT::i32;
    1152             :     }
    1153             :   } else if (VT == MVT::f16) {
    1154           1 :     Opcode = IsPre ? AArch64::LDRHpre : AArch64::LDRHpost;
    1155             :   } else if (VT == MVT::f32) {
    1156           1 :     Opcode = IsPre ? AArch64::LDRSpre : AArch64::LDRSpost;
    1157          25 :   } else if (VT == MVT::f64 || VT.is64BitVector()) {
    1158          14 :     Opcode = IsPre ? AArch64::LDRDpre : AArch64::LDRDpost;
    1159          13 :   } else if (VT.is128BitVector()) {
    1160          13 :     Opcode = IsPre ? AArch64::LDRQpre : AArch64::LDRQpost;
    1161             :   } else
    1162             :     return false;
    1163          49 :   SDValue Chain = LD->getChain();
    1164          49 :   SDValue Base = LD->getBasePtr();
    1165             :   ConstantSDNode *OffsetOp = cast<ConstantSDNode>(LD->getOffset());
    1166          98 :   int OffsetVal = (int)OffsetOp->getZExtValue();
    1167             :   SDLoc dl(N);
    1168          49 :   SDValue Offset = CurDAG->getTargetConstant(OffsetVal, dl, MVT::i64);
    1169          49 :   SDValue Ops[] = { Base, Offset, Chain };
    1170          98 :   SDNode *Res = CurDAG->getMachineNode(Opcode, dl, MVT::i64, DstVT,
    1171          49 :                                        MVT::Other, Ops);
    1172             :   // Either way, we're replacing the node, so tell the caller that.
    1173             :   SDValue LoadedVal = SDValue(Res, 1);
    1174          49 :   if (InsertTo64) {
    1175           4 :     SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
    1176             :     LoadedVal =
    1177           4 :         SDValue(CurDAG->getMachineNode(
    1178             :                     AArch64::SUBREG_TO_REG, dl, MVT::i64,
    1179             :                     CurDAG->getTargetConstant(0, dl, MVT::i64), LoadedVal,
    1180             :                     SubReg),
    1181             :                 0);
    1182             :   }
    1183             : 
    1184          49 :   ReplaceUses(SDValue(N, 0), LoadedVal);
    1185          49 :   ReplaceUses(SDValue(N, 1), SDValue(Res, 0));
    1186          49 :   ReplaceUses(SDValue(N, 2), SDValue(Res, 2));
    1187          49 :   CurDAG->RemoveDeadNode(N);
    1188             :   return true;
    1189             : }
    1190             : 
    1191         120 : void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
    1192             :                                      unsigned SubRegIdx) {
    1193             :   SDLoc dl(N);
    1194         240 :   EVT VT = N->getValueType(0);
    1195         120 :   SDValue Chain = N->getOperand(0);
    1196             : 
    1197             :   SDValue Ops[] = {N->getOperand(2), // Mem operand;
    1198         120 :                    Chain};
    1199             : 
    1200         120 :   const EVT ResTys[] = {MVT::Untyped, MVT::Other};
    1201             : 
    1202         240 :   SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
    1203             :   SDValue SuperReg = SDValue(Ld, 0);
    1204         830 :   for (unsigned i = 0; i < NumVecs; ++i)
    1205         355 :     ReplaceUses(SDValue(N, i),
    1206         355 :         CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
    1207             : 
    1208         120 :   ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
    1209             : 
    1210             :   // Transfer memoperands.
    1211         120 :   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
    1212         120 :   MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
    1213         120 :   cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
    1214             : 
    1215         120 :   CurDAG->RemoveDeadNode(N);
    1216         120 : }
    1217             : 
    1218         236 : void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs,
    1219             :                                          unsigned Opc, unsigned SubRegIdx) {
    1220             :   SDLoc dl(N);
    1221         472 :   EVT VT = N->getValueType(0);
    1222         236 :   SDValue Chain = N->getOperand(0);
    1223             : 
    1224             :   SDValue Ops[] = {N->getOperand(1), // Mem operand
    1225             :                    N->getOperand(2), // Incremental
    1226         236 :                    Chain};
    1227             : 
    1228         236 :   const EVT ResTys[] = {MVT::i64, // Type of the write back register
    1229             :                         MVT::Untyped, MVT::Other};
    1230             : 
    1231         472 :   SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
    1232             : 
    1233             :   // Update uses of write back register
    1234         236 :   ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
    1235             : 
    1236             :   // Update uses of vector list
    1237             :   SDValue SuperReg = SDValue(Ld, 1);
    1238         236 :   if (NumVecs == 1)
    1239          20 :     ReplaceUses(SDValue(N, 0), SuperReg);
    1240             :   else
    1241        1512 :     for (unsigned i = 0; i < NumVecs; ++i)
    1242         648 :       ReplaceUses(SDValue(N, i),
    1243         648 :           CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
    1244             : 
    1245             :   // Update the chain
    1246         236 :   ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
    1247         236 :   CurDAG->RemoveDeadNode(N);
    1248         236 : }
    1249             : 
    1250         149 : void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
    1251             :                                       unsigned Opc) {
    1252             :   SDLoc dl(N);
    1253         298 :   EVT VT = N->getOperand(2)->getValueType(0);
    1254             : 
    1255             :   // Form a REG_SEQUENCE to force register allocation.
    1256         149 :   bool Is128Bit = VT.getSizeInBits() == 128;
    1257         149 :   SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
    1258         149 :   SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
    1259             : 
    1260         298 :   SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)};
    1261         447 :   SDNode *St = CurDAG->getMachineNode(Opc, dl, N->getValueType(0), Ops);
    1262             : 
    1263             :   // Transfer memoperands.
    1264         149 :   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
    1265         149 :   MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
    1266         149 :   cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
    1267             : 
    1268         149 :   ReplaceNode(N, St);
    1269         149 : }
    1270             : 
    1271         144 : void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs,
    1272             :                                           unsigned Opc) {
    1273             :   SDLoc dl(N);
    1274         288 :   EVT VT = N->getOperand(2)->getValueType(0);
    1275         144 :   const EVT ResTys[] = {MVT::i64,    // Type of the write back register
    1276             :                         MVT::Other}; // Type for the Chain
    1277             : 
    1278             :   // Form a REG_SEQUENCE to force register allocation.
    1279         144 :   bool Is128Bit = VT.getSizeInBits() == 128;
    1280         144 :   SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
    1281         144 :   SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
    1282             : 
    1283             :   SDValue Ops[] = {RegSeq,
    1284         144 :                    N->getOperand(NumVecs + 1), // base register
    1285         144 :                    N->getOperand(NumVecs + 2), // Incremental
    1286         432 :                    N->getOperand(0)};          // Chain
    1287         288 :   SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
    1288             : 
    1289         144 :   ReplaceNode(N, St);
    1290         144 : }
    1291             : 
    1292             : namespace {
    1293             : /// WidenVector - Given a value in the V64 register class, produce the
    1294             : /// equivalent value in the V128 register class.
    1295             : class WidenVector {
    1296             :   SelectionDAG &DAG;
    1297             : 
    1298             : public:
    1299          85 :   WidenVector(SelectionDAG &DAG) : DAG(DAG) {}
    1300             : 
    1301         250 :   SDValue operator()(SDValue V64Reg) {
    1302         250 :     EVT VT = V64Reg.getValueType();
    1303         250 :     unsigned NarrowSize = VT.getVectorNumElements();
    1304         250 :     MVT EltTy = VT.getVectorElementType().getSimpleVT();
    1305         250 :     MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
    1306             :     SDLoc DL(V64Reg);
    1307             : 
    1308             :     SDValue Undef =
    1309         750 :         SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, WideTy), 0);
    1310         750 :     return DAG.getTargetInsertSubreg(AArch64::dsub, DL, WideTy, Undef, V64Reg);
    1311             :   }
    1312             : };
    1313             : } // namespace
    1314             : 
    1315             : /// NarrowVector - Given a value in the V128 register class, produce the
    1316             : /// equivalent value in the V64 register class.
    1317         122 : static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
    1318         122 :   EVT VT = V128Reg.getValueType();
    1319         122 :   unsigned WideSize = VT.getVectorNumElements();
    1320         122 :   MVT EltTy = VT.getVectorElementType().getSimpleVT();
    1321         122 :   MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
    1322             : 
    1323         122 :   return DAG.getTargetExtractSubreg(AArch64::dsub, SDLoc(V128Reg), NarrowTy,
    1324         244 :                                     V128Reg);
    1325             : }
    1326             : 
    1327          26 : void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,
    1328             :                                          unsigned Opc) {
    1329             :   SDLoc dl(N);
    1330          52 :   EVT VT = N->getValueType(0);
    1331          26 :   bool Narrow = VT.getSizeInBits() == 64;
    1332             : 
    1333             :   // Form a REG_SEQUENCE to force register allocation.
    1334          26 :   SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
    1335             : 
    1336          26 :   if (Narrow)
    1337           5 :     transform(Regs, Regs.begin(),
    1338           5 :                    WidenVector(*CurDAG));
    1339             : 
    1340             :   SDValue RegSeq = createQTuple(Regs);
    1341             : 
    1342          26 :   const EVT ResTys[] = {MVT::Untyped, MVT::Other};
    1343             : 
    1344             :   unsigned LaneNo =
    1345          52 :       cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
    1346             : 
    1347          26 :   SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
    1348          78 :                    N->getOperand(NumVecs + 3), N->getOperand(0)};
    1349          52 :   SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
    1350             :   SDValue SuperReg = SDValue(Ld, 0);
    1351             : 
    1352          52 :   EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
    1353             :   static const unsigned QSubs[] = { AArch64::qsub0, AArch64::qsub1,
    1354             :                                     AArch64::qsub2, AArch64::qsub3 };
    1355         178 :   for (unsigned i = 0; i < NumVecs; ++i) {
    1356          76 :     SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg);
    1357          76 :     if (Narrow)
    1358          13 :       NV = NarrowVector(NV, *CurDAG);
    1359          76 :     ReplaceUses(SDValue(N, i), NV);
    1360             :   }
    1361             : 
    1362          26 :   ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
    1363          26 :   CurDAG->RemoveDeadNode(N);
    1364          26 : }
    1365             : 
    1366          94 : void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,
    1367             :                                              unsigned Opc) {
    1368             :   SDLoc dl(N);
    1369         188 :   EVT VT = N->getValueType(0);
    1370          94 :   bool Narrow = VT.getSizeInBits() == 64;
    1371             : 
    1372             :   // Form a REG_SEQUENCE to force register allocation.
    1373          94 :   SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
    1374             : 
    1375          94 :   if (Narrow)
    1376          37 :     transform(Regs, Regs.begin(),
    1377          37 :                    WidenVector(*CurDAG));
    1378             : 
    1379             :   SDValue RegSeq = createQTuple(Regs);
    1380             : 
    1381             :   const EVT ResTys[] = {MVT::i64, // Type of the write back register
    1382         188 :                         RegSeq->getValueType(0), MVT::Other};
    1383             : 
    1384             :   unsigned LaneNo =
    1385         188 :       cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
    1386             : 
    1387             :   SDValue Ops[] = {RegSeq,
    1388          94 :                    CurDAG->getTargetConstant(LaneNo, dl,
    1389             :                                              MVT::i64),         // Lane Number
    1390          94 :                    N->getOperand(NumVecs + 2),                  // Base register
    1391          94 :                    N->getOperand(NumVecs + 3),                  // Incremental
    1392         376 :                    N->getOperand(0)};
    1393         188 :   SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
    1394             : 
    1395             :   // Update uses of the write back register
    1396          94 :   ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
    1397             : 
    1398             :   // Update uses of the vector list
    1399             :   SDValue SuperReg = SDValue(Ld, 1);
    1400          94 :   if (NumVecs == 1) {
    1401          23 :     ReplaceUses(SDValue(N, 0),
    1402           1 :                 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg);
    1403             :   } else {
    1404         144 :     EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
    1405             :     static const unsigned QSubs[] = { AArch64::qsub0, AArch64::qsub1,
    1406             :                                       AArch64::qsub2, AArch64::qsub3 };
    1407         504 :     for (unsigned i = 0; i < NumVecs; ++i) {
    1408         216 :       SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT,
    1409         216 :                                                   SuperReg);
    1410         216 :       if (Narrow)
    1411         108 :         NV = NarrowVector(NV, *CurDAG);
    1412         216 :       ReplaceUses(SDValue(N, i), NV);
    1413             :     }
    1414             :   }
    1415             : 
    1416             :   // Update the Chain
    1417          94 :   ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
    1418          94 :   CurDAG->RemoveDeadNode(N);
    1419          94 : }
    1420             : 
    1421          35 : void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,
    1422             :                                           unsigned Opc) {
    1423             :   SDLoc dl(N);
    1424          70 :   EVT VT = N->getOperand(2)->getValueType(0);
    1425          35 :   bool Narrow = VT.getSizeInBits() == 64;
    1426             : 
    1427             :   // Form a REG_SEQUENCE to force register allocation.
    1428          35 :   SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
    1429             : 
    1430          35 :   if (Narrow)
    1431           7 :     transform(Regs, Regs.begin(),
    1432           7 :                    WidenVector(*CurDAG));
    1433             : 
    1434             :   SDValue RegSeq = createQTuple(Regs);
    1435             : 
    1436             :   unsigned LaneNo =
    1437          70 :       cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
    1438             : 
    1439          35 :   SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
    1440         105 :                    N->getOperand(NumVecs + 3), N->getOperand(0)};
    1441          70 :   SDNode *St = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops);
    1442             : 
    1443             :   // Transfer memoperands.
    1444          35 :   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
    1445          35 :   MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
    1446          35 :   cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
    1447             : 
    1448          35 :   ReplaceNode(N, St);
    1449          35 : }
    1450             : 
    1451          72 : void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
    1452             :                                               unsigned Opc) {
    1453             :   SDLoc dl(N);
    1454         144 :   EVT VT = N->getOperand(2)->getValueType(0);
    1455          72 :   bool Narrow = VT.getSizeInBits() == 64;
    1456             : 
    1457             :   // Form a REG_SEQUENCE to force register allocation.
    1458          72 :   SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
    1459             : 
    1460          72 :   if (Narrow)
    1461          36 :     transform(Regs, Regs.begin(),
    1462          36 :                    WidenVector(*CurDAG));
    1463             : 
    1464             :   SDValue RegSeq = createQTuple(Regs);
    1465             : 
    1466          72 :   const EVT ResTys[] = {MVT::i64, // Type of the write back register
    1467             :                         MVT::Other};
    1468             : 
    1469             :   unsigned LaneNo =
    1470         144 :       cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
    1471             : 
    1472          72 :   SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
    1473          72 :                    N->getOperand(NumVecs + 2), // Base Register
    1474          72 :                    N->getOperand(NumVecs + 3), // Incremental
    1475         288 :                    N->getOperand(0)};
    1476         144 :   SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
    1477             : 
    1478             :   // Transfer memoperands.
    1479          72 :   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
    1480          72 :   MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
    1481          72 :   cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
    1482             : 
    1483          72 :   ReplaceNode(N, St);
    1484          72 : }
    1485             : 
    1486        1083 : static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,
    1487             :                                        unsigned &Opc, SDValue &Opd0,
    1488             :                                        unsigned &LSB, unsigned &MSB,
    1489             :                                        unsigned NumberOfIgnoredLowBits,
    1490             :                                        bool BiggerPattern) {
    1491             :   assert(N->getOpcode() == ISD::AND &&
    1492             :          "N must be a AND operation to call this function");
    1493             : 
    1494        2166 :   EVT VT = N->getValueType(0);
    1495             : 
    1496             :   // Here we can test the type of VT and return false when the type does not
    1497             :   // match, but since it is done prior to that call in the current context
    1498             :   // we turned that into an assert to avoid redundant code.
    1499             :   assert((VT == MVT::i32 || VT == MVT::i64) &&
    1500             :          "Type checking must have been done before calling this function");
    1501             : 
    1502             :   // FIXME: simplify-demanded-bits in DAGCombine will probably have
    1503             :   // changed the AND node to a 32-bit mask operation. We'll have to
    1504             :   // undo that as part of the transform here if we want to catch all
    1505             :   // the opportunities.
    1506             :   // Currently the NumberOfIgnoredLowBits argument helps to recover
    1507             :   // form these situations when matching bigger pattern (bitfield insert).
    1508             : 
    1509             :   // For unsigned extracts, check for a shift right and mask
    1510             :   uint64_t AndImm = 0;
    1511        1083 :   if (!isOpcWithIntImmediate(N, ISD::AND, AndImm))
    1512             :     return false;
    1513             : 
    1514         783 :   const SDNode *Op0 = N->getOperand(0).getNode();
    1515             : 
    1516             :   // Because of simplify-demanded-bits in DAGCombine, the mask may have been
    1517             :   // simplified. Try to undo that
    1518         783 :   AndImm |= maskTrailingOnes<uint64_t>(NumberOfIgnoredLowBits);
    1519             : 
    1520             :   // The immediate is a mask of the low bits iff imm & (imm+1) == 0
    1521         783 :   if (AndImm & (AndImm + 1))
    1522             :     return false;
    1523             : 
    1524             :   bool ClampMSB = false;
    1525             :   uint64_t SrlImm = 0;
    1526             :   // Handle the SRL + ANY_EXTEND case.
    1527          76 :   if (VT == MVT::i64 && Op0->getOpcode() == ISD::ANY_EXTEND &&
    1528          23 :       isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, SrlImm)) {
    1529             :     // Extend the incoming operand of the SRL to 64-bit.
    1530          10 :     Opd0 = Widen(CurDAG, Op0->getOperand(0).getOperand(0));
    1531             :     // Make sure to clamp the MSB so that we preserve the semantics of the
    1532             :     // original operations.
    1533             :     ClampMSB = true;
    1534         360 :   } else if (VT == MVT::i32 && Op0->getOpcode() == ISD::TRUNCATE &&
    1535           5 :              isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL,
    1536             :                                    SrlImm)) {
    1537             :     // If the shift result was truncated, we can still combine them.
    1538           4 :     Opd0 = Op0->getOperand(0).getOperand(0);
    1539             : 
    1540             :     // Use the type of SRL node.
    1541           8 :     VT = Opd0->getValueType(0);
    1542             :   } else if (isOpcWithIntImmediate(Op0, ISD::SRL, SrlImm)) {
    1543          26 :     Opd0 = Op0->getOperand(0);
    1544         396 :   } else if (BiggerPattern) {
    1545             :     // Let's pretend a 0 shift right has been performed.
    1546             :     // The resulting code will be at least as good as the original one
    1547             :     // plus it may expose more opportunities for bitfield insert pattern.
    1548             :     // FIXME: Currently we limit this to the bigger pattern, because
    1549             :     // some optimizations expect AND and not UBFM.
    1550          12 :     Opd0 = N->getOperand(0);
    1551             :   } else
    1552             :     return false;
    1553             : 
    1554             :   // Bail out on large immediates. This happens when no proper
    1555             :   // combining/constant folding was performed.
    1556          52 :   if (!BiggerPattern && (SrlImm <= 0 || SrlImm >= VT.getSizeInBits())) {
    1557             :     LLVM_DEBUG(
    1558             :         (dbgs() << N
    1559             :                 << ": Found large shift immediate, this should not happen\n"));
    1560             :     return false;
    1561             :   }
    1562             : 
    1563          52 :   LSB = SrlImm;
    1564         126 :   MSB = SrlImm + (VT == MVT::i32 ? countTrailingOnes<uint32_t>(AndImm)
    1565          52 :                                  : countTrailingOnes<uint64_t>(AndImm)) -
    1566             :         1;
    1567          52 :   if (ClampMSB)
    1568             :     // Since we're moving the extend before the right shift operation, we need
    1569             :     // to clamp the MSB to make sure we don't shift in undefined bits instead of
    1570             :     // the zeros which would get shifted in with the original right shift
    1571             :     // operation.
    1572          10 :     MSB = MSB > 31 ? 31 : MSB;
    1573             : 
    1574          52 :   Opc = VT == MVT::i32 ? AArch64::UBFMWri : AArch64::UBFMXri;
    1575          52 :   return true;
    1576             : }
    1577             : 
    1578         241 : static bool isBitfieldExtractOpFromSExtInReg(SDNode *N, unsigned &Opc,
    1579             :                                              SDValue &Opd0, unsigned &Immr,
    1580             :                                              unsigned &Imms) {
    1581             :   assert(N->getOpcode() == ISD::SIGN_EXTEND_INREG);
    1582             : 
    1583         482 :   EVT VT = N->getValueType(0);
    1584         241 :   unsigned BitWidth = VT.getSizeInBits();
    1585             :   assert((VT == MVT::i32 || VT == MVT::i64) &&
    1586             :          "Type checking must have been done before calling this function");
    1587             : 
    1588         241 :   SDValue Op = N->getOperand(0);
    1589         241 :   if (Op->getOpcode() == ISD::TRUNCATE) {
    1590          11 :     Op = Op->getOperand(0);
    1591          22 :     VT = Op->getValueType(0);
    1592          11 :     BitWidth = VT.getSizeInBits();
    1593             :   }
    1594             : 
    1595             :   uint64_t ShiftImm;
    1596         475 :   if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) &&
    1597             :       !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
    1598             :     return false;
    1599             : 
    1600           7 :   unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
    1601           7 :   if (ShiftImm + Width > BitWidth)
    1602             :     return false;
    1603             : 
    1604           7 :   Opc = (VT == MVT::i32) ? AArch64::SBFMWri : AArch64::SBFMXri;
    1605           7 :   Opd0 = Op.getOperand(0);
    1606           7 :   Immr = ShiftImm;
    1607           7 :   Imms = ShiftImm + Width - 1;
    1608           7 :   return true;
    1609             : }
    1610             : 
    1611         221 : static bool isSeveralBitsExtractOpFromShr(SDNode *N, unsigned &Opc,
    1612             :                                           SDValue &Opd0, unsigned &LSB,
    1613             :                                           unsigned &MSB) {
    1614             :   // We are looking for the following pattern which basically extracts several
    1615             :   // continuous bits from the source value and places it from the LSB of the
    1616             :   // destination value, all other bits of the destination value or set to zero:
    1617             :   //
    1618             :   // Value2 = AND Value, MaskImm
    1619             :   // SRL Value2, ShiftImm
    1620             :   //
    1621             :   // with MaskImm >> ShiftImm to search for the bit width.
    1622             :   //
    1623             :   // This gets selected into a single UBFM:
    1624             :   //
    1625             :   // UBFM Value, ShiftImm, BitWide + SrlImm -1
    1626             :   //
    1627             : 
    1628         221 :   if (N->getOpcode() != ISD::SRL)
    1629             :     return false;
    1630             : 
    1631             :   uint64_t AndMask = 0;
    1632         316 :   if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, AndMask))
    1633             :     return false;
    1634             : 
    1635           9 :   Opd0 = N->getOperand(0).getOperand(0);
    1636             : 
    1637             :   uint64_t SrlImm = 0;
    1638          18 :   if (!isIntImmediate(N->getOperand(1), SrlImm))
    1639             :     return false;
    1640             : 
    1641             :   // Check whether we really have several bits extract here.
    1642          12 :   unsigned BitWide = 64 - countLeadingOnes(~(AndMask >> SrlImm));
    1643           6 :   if (BitWide && isMask_64(AndMask >> SrlImm)) {
    1644           5 :     if (N->getValueType(0) == MVT::i32)
    1645           5 :       Opc = AArch64::UBFMWri;
    1646             :     else
    1647           0 :       Opc = AArch64::UBFMXri;
    1648             : 
    1649           5 :     LSB = SrlImm;
    1650           5 :     MSB = BitWide + SrlImm - 1;
    1651           5 :     return true;
    1652             :   }
    1653             : 
    1654             :   return false;
    1655             : }
    1656             : 
    1657         221 : static bool isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0,
    1658             :                                        unsigned &Immr, unsigned &Imms,
    1659             :                                        bool BiggerPattern) {
    1660             :   assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
    1661             :          "N must be a SHR/SRA operation to call this function");
    1662             : 
    1663         442 :   EVT VT = N->getValueType(0);
    1664             : 
    1665             :   // Here we can test the type of VT and return false when the type does not
    1666             :   // match, but since it is done prior to that call in the current context
    1667             :   // we turned that into an assert to avoid redundant code.
    1668             :   assert((VT == MVT::i32 || VT == MVT::i64) &&
    1669             :          "Type checking must have been done before calling this function");
    1670             : 
    1671             :   // Check for AND + SRL doing several bits extract.
    1672         221 :   if (isSeveralBitsExtractOpFromShr(N, Opc, Opd0, Immr, Imms))
    1673             :     return true;
    1674             : 
    1675             :   // We're looking for a shift of a shift.
    1676             :   uint64_t ShlImm = 0;
    1677             :   uint64_t TruncBits = 0;
    1678         216 :   if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, ShlImm)) {
    1679          14 :     Opd0 = N->getOperand(0).getOperand(0);
    1680          68 :   } else if (VT == MVT::i32 && N->getOpcode() == ISD::SRL &&
    1681             :              N->getOperand(0).getNode()->getOpcode() == ISD::TRUNCATE) {
    1682             :     // We are looking for a shift of truncate. Truncate from i64 to i32 could
    1683             :     // be considered as setting high 32 bits as zero. Our strategy here is to
    1684             :     // always generate 64bit UBFM. This consistency will help the CSE pass
    1685             :     // later find more redundancy.
    1686           2 :     Opd0 = N->getOperand(0).getOperand(0);
    1687           4 :     TruncBits = Opd0->getValueType(0).getSizeInBits() - VT.getSizeInBits();
    1688           4 :     VT = Opd0.getValueType();
    1689             :     assert(VT == MVT::i64 && "the promoted type should be i64");
    1690         200 :   } else if (BiggerPattern) {
    1691             :     // Let's pretend a 0 shift left has been performed.
    1692             :     // FIXME: Currently we limit this to the bigger pattern case,
    1693             :     // because some optimizations expect AND and not UBFM
    1694           5 :     Opd0 = N->getOperand(0);
    1695             :   } else
    1696             :     return false;
    1697             : 
    1698             :   // Missing combines/constant folding may have left us with strange
    1699             :   // constants.
    1700          21 :   if (ShlImm >= VT.getSizeInBits()) {
    1701             :     LLVM_DEBUG(
    1702             :         (dbgs() << N
    1703             :                 << ": Found large shift immediate, this should not happen\n"));
    1704             :     return false;
    1705             :   }
    1706             : 
    1707             :   uint64_t SrlImm = 0;
    1708          42 :   if (!isIntImmediate(N->getOperand(1), SrlImm))
    1709             :     return false;
    1710             : 
    1711             :   assert(SrlImm > 0 && SrlImm < VT.getSizeInBits() &&
    1712             :          "bad amount in shift node!");
    1713          18 :   int immr = SrlImm - ShlImm;
    1714          18 :   Immr = immr < 0 ? immr + VT.getSizeInBits() : immr;
    1715          18 :   Imms = VT.getSizeInBits() - ShlImm - TruncBits - 1;
    1716             :   // SRA requires a signed extraction
    1717             :   if (VT == MVT::i32)
    1718           9 :     Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMWri : AArch64::UBFMWri;
    1719             :   else
    1720          18 :     Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMXri : AArch64::UBFMXri;
    1721             :   return true;
    1722             : }
    1723             : 
    1724          89 : bool AArch64DAGToDAGISel::tryBitfieldExtractOpFromSExt(SDNode *N) {
    1725             :   assert(N->getOpcode() == ISD::SIGN_EXTEND);
    1726             : 
    1727         178 :   EVT VT = N->getValueType(0);
    1728         178 :   EVT NarrowVT = N->getOperand(0)->getValueType(0);
    1729             :   if (VT != MVT::i64 || NarrowVT != MVT::i32)
    1730             :     return false;
    1731             : 
    1732             :   uint64_t ShiftImm;
    1733             :   SDValue Op = N->getOperand(0);
    1734          31 :   if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
    1735             :     return false;
    1736             : 
    1737             :   SDLoc dl(N);
    1738             :   // Extend the incoming operand of the shift to 64-bits.
    1739           1 :   SDValue Opd0 = Widen(CurDAG, Op.getOperand(0));
    1740             :   unsigned Immr = ShiftImm;
    1741           1 :   unsigned Imms = NarrowVT.getSizeInBits() - 1;
    1742           1 :   SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, VT),
    1743           3 :                    CurDAG->getTargetConstant(Imms, dl, VT)};
    1744           2 :   CurDAG->SelectNodeTo(N, AArch64::SBFMXri, VT, Ops);
    1745             :   return true;
    1746             : }
    1747             : 
    1748        2038 : static bool isBitfieldExtractOp(SelectionDAG *CurDAG, SDNode *N, unsigned &Opc,
    1749             :                                 SDValue &Opd0, unsigned &Immr, unsigned &Imms,
    1750             :                                 unsigned NumberOfIgnoredLowBits = 0,
    1751             :                                 bool BiggerPattern = false) {
    1752        2038 :   if (N->getValueType(0) != MVT::i32 && N->getValueType(0) != MVT::i64)
    1753             :     return false;
    1754             : 
    1755        3920 :   switch (N->getOpcode()) {
    1756         415 :   default:
    1757         415 :     if (!N->isMachineOpcode())
    1758             :       return false;
    1759             :     break;
    1760        1083 :   case ISD::AND:
    1761        1083 :     return isBitfieldExtractOpFromAnd(CurDAG, N, Opc, Opd0, Immr, Imms,
    1762        1083 :                                       NumberOfIgnoredLowBits, BiggerPattern);
    1763         221 :   case ISD::SRL:
    1764             :   case ISD::SRA:
    1765         221 :     return isBitfieldExtractOpFromShr(N, Opc, Opd0, Immr, Imms, BiggerPattern);
    1766             : 
    1767         241 :   case ISD::SIGN_EXTEND_INREG:
    1768         241 :     return isBitfieldExtractOpFromSExtInReg(N, Opc, Opd0, Immr, Imms);
    1769             :   }
    1770             : 
    1771             :   unsigned NOpc = N->getMachineOpcode();
    1772           6 :   switch (NOpc) {
    1773             :   default:
    1774             :     return false;
    1775           0 :   case AArch64::SBFMWri:
    1776             :   case AArch64::UBFMWri:
    1777             :   case AArch64::SBFMXri:
    1778             :   case AArch64::UBFMXri:
    1779           0 :     Opc = NOpc;
    1780           0 :     Opd0 = N->getOperand(0);
    1781           0 :     Immr = cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
    1782           0 :     Imms = cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
    1783           0 :     return true;
    1784             :   }
    1785             :   // Unreachable
    1786             :   return false;
    1787             : }
    1788             : 
    1789        1256 : bool AArch64DAGToDAGISel::tryBitfieldExtractOp(SDNode *N) {
    1790             :   unsigned Opc, Immr, Imms;
    1791        1256 :   SDValue Opd0;
    1792        1256 :   if (!isBitfieldExtractOp(CurDAG, N, Opc, Opd0, Immr, Imms))
    1793             :     return false;
    1794             : 
    1795          96 :   EVT VT = N->getValueType(0);
    1796             :   SDLoc dl(N);
    1797             : 
    1798             :   // If the bit extract operation is 64bit but the original type is 32bit, we
    1799             :   // need to add one EXTRACT_SUBREG.
    1800          48 :   if ((Opc == AArch64::SBFMXri || Opc == AArch64::UBFMXri) && VT == MVT::i32) {
    1801           7 :     SDValue Ops64[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, MVT::i64),
    1802          21 :                        CurDAG->getTargetConstant(Imms, dl, MVT::i64)};
    1803             : 
    1804          14 :     SDNode *BFM = CurDAG->getMachineNode(Opc, dl, MVT::i64, Ops64);
    1805          14 :     SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
    1806          14 :     ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
    1807             :                                           MVT::i32, SDValue(BFM, 0), SubReg));
    1808             :     return true;
    1809             :   }
    1810             : 
    1811          41 :   SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, VT),
    1812         123 :                    CurDAG->getTargetConstant(Imms, dl, VT)};
    1813          82 :   CurDAG->SelectNodeTo(N, Opc, VT, Ops);
    1814          41 :   return true;
    1815             : }
    1816             : 
    1817             : /// Does DstMask form a complementary pair with the mask provided by
    1818             : /// BitsToBeInserted, suitable for use in a BFI instruction. Roughly speaking,
    1819             : /// this asks whether DstMask zeroes precisely those bits that will be set by
    1820             : /// the other half.
    1821          39 : static bool isBitfieldDstMask(uint64_t DstMask, const APInt &BitsToBeInserted,
    1822             :                               unsigned NumberOfIgnoredHighBits, EVT VT) {
    1823             :   assert((VT == MVT::i32 || VT == MVT::i64) &&
    1824             :          "i32 or i64 mask type expected!");
    1825          39 :   unsigned BitWidth = VT.getSizeInBits() - NumberOfIgnoredHighBits;
    1826             : 
    1827             :   APInt SignificantDstMask = APInt(BitWidth, DstMask);
    1828          39 :   APInt SignificantBitsToBeInserted = BitsToBeInserted.zextOrTrunc(BitWidth);
    1829             : 
    1830         156 :   return (SignificantDstMask & SignificantBitsToBeInserted) == 0 &&
    1831         156 :          (SignificantDstMask | SignificantBitsToBeInserted).isAllOnesValue();
    1832             : }
    1833             : 
    1834             : // Look for bits that will be useful for later uses.
    1835             : // A bit is consider useless as soon as it is dropped and never used
    1836             : // before it as been dropped.
    1837             : // E.g., looking for useful bit of x
    1838             : // 1. y = x & 0x7
    1839             : // 2. z = y >> 2
    1840             : // After #1, x useful bits are 0x7, then the useful bits of x, live through
    1841             : // y.
    1842             : // After #2, the useful bits of x are 0x4.
    1843             : // However, if x is used on an unpredicatable instruction, then all its bits
    1844             : // are useful.
    1845             : // E.g.
    1846             : // 1. y = x & 0x7
    1847             : // 2. z = y >> 2
    1848             : // 3. str x, [@x]
    1849             : static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth = 0);
    1850             : 
    1851          10 : static void getUsefulBitsFromAndWithImmediate(SDValue Op, APInt &UsefulBits,
    1852             :                                               unsigned Depth) {
    1853             :   uint64_t Imm =
    1854          20 :       cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
    1855          10 :   Imm = AArch64_AM::decodeLogicalImmediate(Imm, UsefulBits.getBitWidth());
    1856          10 :   UsefulBits &= APInt(UsefulBits.getBitWidth(), Imm);
    1857          10 :   getUsefulBits(Op, UsefulBits, Depth + 1);
    1858          10 : }
    1859             : 
    1860          20 : static void getUsefulBitsFromBitfieldMoveOpd(SDValue Op, APInt &UsefulBits,
    1861             :                                              uint64_t Imm, uint64_t MSB,
    1862             :                                              unsigned Depth) {
    1863             :   // inherit the bitwidth value
    1864             :   APInt OpUsefulBits(UsefulBits);
    1865          20 :   OpUsefulBits = 1;
    1866             : 
    1867          20 :   if (MSB >= Imm) {
    1868           8 :     OpUsefulBits <<= MSB - Imm + 1;
    1869           8 :     --OpUsefulBits;
    1870             :     // The interesting part will be in the lower part of the result
    1871           8 :     getUsefulBits(Op, OpUsefulBits, Depth + 1);
    1872             :     // The interesting part was starting at Imm in the argument
    1873           8 :     OpUsefulBits <<= Imm;
    1874             :   } else {
    1875          12 :     OpUsefulBits <<= MSB + 1;
    1876          12 :     --OpUsefulBits;
    1877             :     // The interesting part will be shifted in the result
    1878          12 :     OpUsefulBits <<= OpUsefulBits.getBitWidth() - Imm;
    1879          12 :     getUsefulBits(Op, OpUsefulBits, Depth + 1);
    1880             :     // The interesting part was at zero in the argument
    1881          12 :     OpUsefulBits.lshrInPlace(OpUsefulBits.getBitWidth() - Imm);
    1882             :   }
    1883             : 
    1884             :   UsefulBits &= OpUsefulBits;
    1885          20 : }
    1886             : 
    1887          20 : static void getUsefulBitsFromUBFM(SDValue Op, APInt &UsefulBits,
    1888             :                                   unsigned Depth) {
    1889             :   uint64_t Imm =
    1890          20 :       cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
    1891             :   uint64_t MSB =
    1892          20 :       cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
    1893             : 
    1894          20 :   getUsefulBitsFromBitfieldMoveOpd(Op, UsefulBits, Imm, MSB, Depth);
    1895          20 : }
    1896             : 
    1897           0 : static void getUsefulBitsFromOrWithShiftedReg(SDValue Op, APInt &UsefulBits,
    1898             :                                               unsigned Depth) {
    1899             :   uint64_t ShiftTypeAndValue =
    1900           0 :       cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
    1901             :   APInt Mask(UsefulBits);
    1902           0 :   Mask.clearAllBits();
    1903           0 :   Mask.flipAllBits();
    1904             : 
    1905           0 :   if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSL) {
    1906             :     // Shift Left
    1907             :     uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
    1908           0 :     Mask <<= ShiftAmt;
    1909           0 :     getUsefulBits(Op, Mask, Depth + 1);
    1910             :     Mask.lshrInPlace(ShiftAmt);
    1911           0 :   } else if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSR) {
    1912             :     // Shift Right
    1913             :     // We do not handle AArch64_AM::ASR, because the sign will change the
    1914             :     // number of useful bits
    1915             :     uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
    1916             :     Mask.lshrInPlace(ShiftAmt);
    1917           0 :     getUsefulBits(Op, Mask, Depth + 1);
    1918           0 :     Mask <<= ShiftAmt;
    1919             :   } else
    1920             :     return;
    1921             : 
    1922             :   UsefulBits &= Mask;
    1923             : }
    1924             : 
    1925          25 : static void getUsefulBitsFromBFM(SDValue Op, SDValue Orig, APInt &UsefulBits,
    1926             :                                  unsigned Depth) {
    1927             :   uint64_t Imm =
    1928          25 :       cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
    1929             :   uint64_t MSB =
    1930          25 :       cast<const ConstantSDNode>(Op.getOperand(3).getNode())->getZExtValue();
    1931             : 
    1932             :   APInt OpUsefulBits(UsefulBits);
    1933          25 :   OpUsefulBits = 1;
    1934             : 
    1935          25 :   APInt ResultUsefulBits(UsefulBits.getBitWidth(), 0);
    1936          25 :   ResultUsefulBits.flipAllBits();
    1937          25 :   APInt Mask(UsefulBits.getBitWidth(), 0);
    1938             : 
    1939          25 :   getUsefulBits(Op, ResultUsefulBits, Depth + 1);
    1940             : 
    1941          25 :   if (MSB >= Imm) {
    1942             :     // The instruction is a BFXIL.
    1943           2 :     uint64_t Width = MSB - Imm + 1;
    1944             :     uint64_t LSB = Imm;
    1945             : 
    1946           2 :     OpUsefulBits <<= Width;
    1947           2 :     --OpUsefulBits;
    1948             : 
    1949             :     if (Op.getOperand(1) == Orig) {
    1950             :       // Copy the low bits from the result to bits starting from LSB.
    1951           0 :       Mask = ResultUsefulBits & OpUsefulBits;
    1952           0 :       Mask <<= LSB;
    1953             :     }
    1954             : 
    1955             :     if (Op.getOperand(0) == Orig)
    1956             :       // Bits starting from LSB in the input contribute to the result.
    1957           6 :       Mask |= (ResultUsefulBits & ~OpUsefulBits);
    1958             :   } else {
    1959             :     // The instruction is a BFI.
    1960          23 :     uint64_t Width = MSB + 1;
    1961          23 :     uint64_t LSB = UsefulBits.getBitWidth() - Imm;
    1962             : 
    1963          23 :     OpUsefulBits <<= Width;
    1964          23 :     --OpUsefulBits;
    1965          23 :     OpUsefulBits <<= LSB;
    1966             : 
    1967             :     if (Op.getOperand(1) == Orig) {
    1968             :       // Copy the bits from the result to the zero bits.
    1969          10 :       Mask = ResultUsefulBits & OpUsefulBits;
    1970             :       Mask.lshrInPlace(LSB);
    1971             :     }
    1972             : 
    1973             :     if (Op.getOperand(0) == Orig)
    1974          51 :       Mask |= (ResultUsefulBits & ~OpUsefulBits);
    1975             :   }
    1976             : 
    1977             :   UsefulBits &= Mask;
    1978          25 : }
    1979             : 
    1980         468 : static void getUsefulBitsForUse(SDNode *UserNode, APInt &UsefulBits,
    1981             :                                 SDValue Orig, unsigned Depth) {
    1982             : 
    1983             :   // Users of this node should have already been instruction selected
    1984             :   // FIXME: Can we turn that into an assert?
    1985         468 :   if (!UserNode->isMachineOpcode())
    1986             :     return;
    1987             : 
    1988         203 :   switch (UserNode->getMachineOpcode()) {
    1989             :   default:
    1990             :     return;
    1991             :   case AArch64::ANDSWri:
    1992             :   case AArch64::ANDSXri:
    1993             :   case AArch64::ANDWri:
    1994             :   case AArch64::ANDXri:
    1995             :     // We increment Depth only when we call the getUsefulBits
    1996          10 :     return getUsefulBitsFromAndWithImmediate(SDValue(UserNode, 0), UsefulBits,
    1997          10 :                                              Depth);
    1998             :   case AArch64::UBFMWri:
    1999             :   case AArch64::UBFMXri:
    2000          20 :     return getUsefulBitsFromUBFM(SDValue(UserNode, 0), UsefulBits, Depth);
    2001             : 
    2002           6 :   case AArch64::ORRWrs:
    2003             :   case AArch64::ORRXrs:
    2004           6 :     if (UserNode->getOperand(1) != Orig)
    2005             :       return;
    2006           0 :     return getUsefulBitsFromOrWithShiftedReg(SDValue(UserNode, 0), UsefulBits,
    2007           0 :                                              Depth);
    2008             :   case AArch64::BFMWri:
    2009             :   case AArch64::BFMXri:
    2010          25 :     return getUsefulBitsFromBFM(SDValue(UserNode, 0), Orig, UsefulBits, Depth);
    2011             : 
    2012           6 :   case AArch64::STRBBui:
    2013             :   case AArch64::STURBBi:
    2014           6 :     if (UserNode->getOperand(0) != Orig)
    2015             :       return;
    2016          12 :     UsefulBits &= APInt(UsefulBits.getBitWidth(), 0xff);
    2017           6 :     return;
    2018             : 
    2019           5 :   case AArch64::STRHHui:
    2020             :   case AArch64::STURHHi:
    2021           5 :     if (UserNode->getOperand(0) != Orig)
    2022             :       return;
    2023          10 :     UsefulBits &= APInt(UsefulBits.getBitWidth(), 0xffff);
    2024           5 :     return;
    2025             :   }
    2026             : }
    2027             : 
    2028         459 : static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth) {
    2029         459 :   if (Depth >= 6)
    2030           0 :     return;
    2031             :   // Initialize UsefulBits
    2032         459 :   if (!Depth) {
    2033         404 :     unsigned Bitwidth = Op.getScalarValueSizeInBits();
    2034             :     // At the beginning, assume every produced bits is useful
    2035         404 :     UsefulBits = APInt(Bitwidth, 0);
    2036         404 :     UsefulBits.flipAllBits();
    2037             :   }
    2038         459 :   APInt UsersUsefulBits(UsefulBits.getBitWidth(), 0);
    2039             : 
    2040        1386 :   for (SDNode *Node : Op.getNode()->uses()) {
    2041             :     // A use cannot produce useful bits
    2042             :     APInt UsefulBitsForUse = APInt(UsefulBits);
    2043         468 :     getUsefulBitsForUse(Node, UsefulBitsForUse, Op, Depth);
    2044             :     UsersUsefulBits |= UsefulBitsForUse;
    2045             :   }
    2046             :   // UsefulBits contains the produced bits that are meaningful for the
    2047             :   // current definition, thus a user cannot make a bit meaningful at
    2048             :   // this point
    2049             :   UsefulBits &= UsersUsefulBits;
    2050             : }
    2051             : 
    2052             : /// Create a machine node performing a notional SHL of Op by ShlAmount. If
    2053             : /// ShlAmount is negative, do a (logical) right-shift instead. If ShlAmount is
    2054             : /// 0, return Op unchanged.
    2055          76 : static SDValue getLeftShift(SelectionDAG *CurDAG, SDValue Op, int ShlAmount) {
    2056          76 :   if (ShlAmount == 0)
    2057          75 :     return Op;
    2058             : 
    2059           1 :   EVT VT = Op.getValueType();
    2060             :   SDLoc dl(Op);
    2061           1 :   unsigned BitWidth = VT.getSizeInBits();
    2062           1 :   unsigned UBFMOpc = BitWidth == 32 ? AArch64::UBFMWri : AArch64::UBFMXri;
    2063             : 
    2064             :   SDNode *ShiftNode;
    2065           1 :   if (ShlAmount > 0) {
    2066             :     // LSL wD, wN, #Amt == UBFM wD, wN, #32-Amt, #31-Amt
    2067           0 :     ShiftNode = CurDAG->getMachineNode(
    2068             :         UBFMOpc, dl, VT, Op,
    2069             :         CurDAG->getTargetConstant(BitWidth - ShlAmount, dl, VT),
    2070           0 :         CurDAG->getTargetConstant(BitWidth - 1 - ShlAmount, dl, VT));
    2071             :   } else {
    2072             :     // LSR wD, wN, #Amt == UBFM wD, wN, #Amt, #32-1
    2073             :     assert(ShlAmount < 0 && "expected right shift");
    2074           1 :     int ShrAmount = -ShlAmount;
    2075           3 :     ShiftNode = CurDAG->getMachineNode(
    2076             :         UBFMOpc, dl, VT, Op, CurDAG->getTargetConstant(ShrAmount, dl, VT),
    2077           1 :         CurDAG->getTargetConstant(BitWidth - 1, dl, VT));
    2078             :   }
    2079             : 
    2080           1 :   return SDValue(ShiftNode, 0);
    2081             : }
    2082             : 
    2083             : /// Does this tree qualify as an attempt to move a bitfield into position,
    2084             : /// essentially "(and (shl VAL, N), Mask)".
    2085        1460 : static bool isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op,
    2086             :                                     bool BiggerPattern,
    2087             :                                     SDValue &Src, int &ShiftAmount,
    2088             :                                     int &MaskWidth) {
    2089        1460 :   EVT VT = Op.getValueType();
    2090             :   unsigned BitWidth = VT.getSizeInBits();
    2091             :   (void)BitWidth;
    2092             :   assert(BitWidth == 32 || BitWidth == 64);
    2093             : 
    2094        1460 :   KnownBits Known;
    2095        1460 :   CurDAG->computeKnownBits(Op, Known);
    2096             : 
    2097             :   // Non-zero in the sense that they're not provably zero, which is the key
    2098             :   // point if we want to use this value
    2099        1460 :   uint64_t NonZeroBits = (~Known.Zero).getZExtValue();
    2100             : 
    2101             :   // Discard a constant AND mask if present. It's safe because the node will
    2102             :   // already have been factored into the computeKnownBits calculation above.
    2103             :   uint64_t AndImm;
    2104             :   if (isOpcWithIntImmediate(Op.getNode(), ISD::AND, AndImm)) {
    2105             :     assert((~APInt(BitWidth, AndImm) & ~Known.Zero) == 0);
    2106         731 :     Op = Op.getOperand(0);
    2107             :   }
    2108             : 
    2109             :   // Don't match if the SHL has more than one use, since then we'll end up
    2110             :   // generating SHL+UBFIZ instead of just keeping SHL+AND.
    2111        2604 :   if (!BiggerPattern && !Op.hasOneUse())
    2112             :     return false;
    2113             : 
    2114             :   uint64_t ShlImm;
    2115        1349 :   if (!isOpcWithIntImmediate(Op.getNode(), ISD::SHL, ShlImm))
    2116             :     return false;
    2117          83 :   Op = Op.getOperand(0);
    2118             : 
    2119             :   if (!isShiftedMask_64(NonZeroBits))
    2120             :     return false;
    2121             : 
    2122          77 :   ShiftAmount = countTrailingZeros(NonZeroBits);
    2123         154 :   MaskWidth = countTrailingOnes(NonZeroBits >> ShiftAmount);
    2124             : 
    2125             :   // BFI encompasses sufficiently many nodes that it's worth inserting an extra
    2126             :   // LSL/LSR if the mask in NonZeroBits doesn't quite match up with the ISD::SHL
    2127             :   // amount.  BiggerPattern is true when this pattern is being matched for BFI,
    2128             :   // BiggerPattern is false when this pattern is being matched for UBFIZ, in
    2129             :   // which case it is not profitable to insert an extra shift.
    2130          77 :   if (ShlImm - ShiftAmount != 0 && !BiggerPattern)
    2131             :     return false;
    2132          76 :   Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount);
    2133             : 
    2134          76 :   return true;
    2135             : }
    2136             : 
    2137             : static bool isShiftedMask(uint64_t Mask, EVT VT) {
    2138             :   assert(VT == MVT::i32 || VT == MVT::i64);
    2139             :   if (VT == MVT::i32)
    2140          27 :     return isShiftedMask_32(Mask);
    2141             :   return isShiftedMask_64(Mask);
    2142             : }
    2143             : 
    2144             : // Generate a BFI/BFXIL from 'or (and X, MaskImm), OrImm' iff the value being
    2145             : // inserted only sets known zero bits.
    2146         317 : static bool tryBitfieldInsertOpFromOrAndImm(SDNode *N, SelectionDAG *CurDAG) {
    2147             :   assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
    2148             : 
    2149         634 :   EVT VT = N->getValueType(0);
    2150             :   if (VT != MVT::i32 && VT != MVT::i64)
    2151             :     return false;
    2152             : 
    2153         150 :   unsigned BitWidth = VT.getSizeInBits();
    2154             : 
    2155             :   uint64_t OrImm;
    2156         150 :   if (!isOpcWithIntImmediate(N, ISD::OR, OrImm))
    2157             :     return false;
    2158             : 
    2159             :   // Skip this transformation if the ORR immediate can be encoded in the ORR.
    2160             :   // Otherwise, we'll trade an AND+ORR for ORR+BFI/BFXIL, which is most likely
    2161             :   // performance neutral.
    2162          34 :   if (AArch64_AM::isLogicalImmediate(OrImm, BitWidth))
    2163             :     return false;
    2164             : 
    2165             :   uint64_t MaskImm;
    2166           9 :   SDValue And = N->getOperand(0);
    2167             :   // Must be a single use AND with an immediate operand.
    2168           9 :   if (!And.hasOneUse() ||
    2169             :       !isOpcWithIntImmediate(And.getNode(), ISD::AND, MaskImm))
    2170             :     return false;
    2171             : 
    2172             :   // Compute the Known Zero for the AND as this allows us to catch more general
    2173             :   // cases than just looking for AND with imm.
    2174           7 :   KnownBits Known;
    2175           7 :   CurDAG->computeKnownBits(And, Known);
    2176             : 
    2177             :   // Non-zero in the sense that they're not provably zero, which is the key
    2178             :   // point if we want to use this value.
    2179           7 :   uint64_t NotKnownZero = (~Known.Zero).getZExtValue();
    2180             : 
    2181             :   // The KnownZero mask must be a shifted mask (e.g., 1110..011, 11100..00).
    2182           7 :   if (!isShiftedMask(Known.Zero.getZExtValue(), VT))
    2183             :     return false;
    2184             : 
    2185             :   // The bits being inserted must only set those bits that are known to be zero.
    2186           7 :   if ((OrImm & NotKnownZero) != 0) {
    2187             :     // FIXME:  It's okay if the OrImm sets NotKnownZero bits to 1, but we don't
    2188             :     // currently handle this case.
    2189             :     return false;
    2190             :   }
    2191             : 
    2192             :   // BFI/BFXIL dst, src, #lsb, #width.
    2193           7 :   int LSB = countTrailingOnes(NotKnownZero);
    2194          14 :   int Width = BitWidth - APInt(BitWidth, NotKnownZero).countPopulation();
    2195             : 
    2196             :   // BFI/BFXIL is an alias of BFM, so translate to BFM operands.
    2197           7 :   unsigned ImmR = (BitWidth - LSB) % BitWidth;
    2198           7 :   unsigned ImmS = Width - 1;
    2199             : 
    2200             :   // If we're creating a BFI instruction avoid cases where we need more
    2201             :   // instructions to materialize the BFI constant as compared to the original
    2202             :   // ORR.  A BFXIL will use the same constant as the original ORR, so the code
    2203             :   // should be no worse in this case.
    2204             :   bool IsBFI = LSB != 0;
    2205           7 :   uint64_t BFIImm = OrImm >> LSB;
    2206          11 :   if (IsBFI && !AArch64_AM::isLogicalImmediate(BFIImm, BitWidth)) {
    2207             :     // We have a BFI instruction and we know the constant can't be materialized
    2208             :     // with a ORR-immediate with the zero register.
    2209             :     unsigned OrChunks = 0, BFIChunks = 0;
    2210          28 :     for (unsigned Shift = 0; Shift < BitWidth; Shift += 16) {
    2211          12 :       if (((OrImm >> Shift) & 0xFFFF) != 0)
    2212           6 :         ++OrChunks;
    2213          12 :       if (((BFIImm >> Shift) & 0xFFFF) != 0)
    2214           7 :         ++BFIChunks;
    2215             :     }
    2216           4 :     if (BFIChunks > OrChunks)
    2217             :       return false;
    2218             :   }
    2219             : 
    2220             :   // Materialize the constant to be inserted.
    2221             :   SDLoc DL(N);
    2222             :   unsigned MOVIOpc = VT == MVT::i32 ? AArch64::MOVi32imm : AArch64::MOVi64imm;
    2223             :   SDNode *MOVI = CurDAG->getMachineNode(
    2224           6 :       MOVIOpc, DL, VT, CurDAG->getTargetConstant(BFIImm, DL, VT));
    2225             : 
    2226             :   // Create the BFI/BFXIL instruction.
    2227             :   SDValue Ops[] = {And.getOperand(0), SDValue(MOVI, 0),
    2228           6 :                    CurDAG->getTargetConstant(ImmR, DL, VT),
    2229          18 :                    CurDAG->getTargetConstant(ImmS, DL, VT)};
    2230             :   unsigned Opc = (VT == MVT::i32) ? AArch64::BFMWri : AArch64::BFMXri;
    2231           6 :   CurDAG->SelectNodeTo(N, Opc, VT, Ops);
    2232             :   return true;
    2233             : }
    2234             : 
    2235         403 : static bool tryBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits,
    2236             :                                       SelectionDAG *CurDAG) {
    2237             :   assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
    2238             : 
    2239         806 :   EVT VT = N->getValueType(0);
    2240             :   if (VT != MVT::i32 && VT != MVT::i64)
    2241             :     return false;
    2242             : 
    2243         236 :   unsigned BitWidth = VT.getSizeInBits();
    2244             : 
    2245             :   // Because of simplify-demanded-bits in DAGCombine, involved masks may not
    2246             :   // have the expected shape. Try to undo that.
    2247             : 
    2248         236 :   unsigned NumberOfIgnoredLowBits = UsefulBits.countTrailingZeros();
    2249         236 :   unsigned NumberOfIgnoredHighBits = UsefulBits.countLeadingZeros();
    2250             : 
    2251             :   // Given a OR operation, check if we have the following pattern
    2252             :   // ubfm c, b, imm, imm2 (or something that does the same jobs, see
    2253             :   //                       isBitfieldExtractOp)
    2254             :   // d = e & mask2 ; where mask is a binary sequence of 1..10..0 and
    2255             :   //                 countTrailingZeros(mask2) == imm2 - imm + 1
    2256             :   // f = d | c
    2257             :   // if yes, replace the OR instruction with:
    2258             :   // f = BFM Opd0, Opd1, LSB, MSB ; where LSB = imm, and MSB = imm2
    2259             : 
    2260             :   // OR is commutative, check all combinations of operand order and values of
    2261             :   // BiggerPattern, i.e.
    2262             :   //     Opd0, Opd1, BiggerPattern=false
    2263             :   //     Opd1, Opd0, BiggerPattern=false
    2264             :   //     Opd0, Opd1, BiggerPattern=true
    2265             :   //     Opd1, Opd0, BiggerPattern=true
    2266             :   // Several of these combinations may match, so check with BiggerPattern=false
    2267             :   // first since that will produce better results by matching more instructions
    2268             :   // and/or inserting fewer extra instructions.
    2269        1644 :   for (int I = 0; I < 4; ++I) {
    2270             : 
    2271         782 :     SDValue Dst, Src;
    2272             :     unsigned ImmR, ImmS;
    2273         782 :     bool BiggerPattern = I / 2;
    2274        1564 :     SDValue OrOpd0Val = N->getOperand(I % 2);
    2275             :     SDNode *OrOpd0 = OrOpd0Val.getNode();
    2276        1564 :     SDValue OrOpd1Val = N->getOperand((I + 1) % 2);
    2277             :     SDNode *OrOpd1 = OrOpd1Val.getNode();
    2278             : 
    2279             :     unsigned BFXOpc;
    2280             :     int DstLSB, Width;
    2281         782 :     if (isBitfieldExtractOp(CurDAG, OrOpd0, BFXOpc, Src, ImmR, ImmS,
    2282             :                             NumberOfIgnoredLowBits, BiggerPattern)) {
    2283             :       // Check that the returned opcode is compatible with the pattern,
    2284             :       // i.e., same type and zero extended (U and not S)
    2285          70 :       if ((BFXOpc != AArch64::UBFMXri && VT == MVT::i64) ||
    2286             :           (BFXOpc != AArch64::UBFMWri && VT == MVT::i32))
    2287         706 :         continue;
    2288             : 
    2289             :       // Compute the width of the bitfield insertion
    2290          32 :       DstLSB = 0;
    2291          32 :       Width = ImmS - ImmR + 1;
    2292             :       // FIXME: This constraint is to catch bitfield insertion we may
    2293             :       // want to widen the pattern if we want to grab general bitfied
    2294             :       // move case
    2295          32 :       if (Width <= 0)
    2296           0 :         continue;
    2297             : 
    2298             :       // If the mask on the insertee is correct, we have a BFXIL operation. We
    2299             :       // can share the ImmR and ImmS values from the already-computed UBFM.
    2300        1422 :     } else if (isBitfieldPositioningOp(CurDAG, OrOpd0Val,
    2301             :                                        BiggerPattern,
    2302             :                                        Src, DstLSB, Width)) {
    2303          74 :       ImmR = (BitWidth - DstLSB) % BitWidth;
    2304          74 :       ImmS = Width - 1;
    2305             :     } else
    2306         674 :       continue;
    2307             : 
    2308             :     // Check the second part of the pattern
    2309         106 :     EVT VT = OrOpd1Val.getValueType();
    2310             :     assert((VT == MVT::i32 || VT == MVT::i64) && "unexpected OR operand");
    2311             : 
    2312             :     // Compute the Known Zero for the candidate of the first operand.
    2313             :     // This allows to catch more general case than just looking for
    2314             :     // AND with imm. Indeed, simplify-demanded-bits may have removed
    2315             :     // the AND instruction because it proves it was useless.
    2316             :     KnownBits Known;
    2317         106 :     CurDAG->computeKnownBits(OrOpd1Val, Known);
    2318             : 
    2319             :     // Check if there is enough room for the second operand to appear
    2320             :     // in the first one
    2321             :     APInt BitsToBeInserted =
    2322         212 :         APInt::getBitsSet(Known.getBitWidth(), DstLSB, DstLSB + Width);
    2323             : 
    2324         318 :     if ((BitsToBeInserted & ~Known.Zero) != 0)
    2325             :       continue;
    2326             : 
    2327             :     // Set the first operand
    2328             :     uint64_t Imm;
    2329          39 :     if (isOpcWithIntImmediate(OrOpd1, ISD::AND, Imm) &&
    2330          39 :         isBitfieldDstMask(Imm, BitsToBeInserted, NumberOfIgnoredHighBits, VT))
    2331             :       // In that case, we can eliminate the AND
    2332          29 :       Dst = OrOpd1->getOperand(0);
    2333             :     else
    2334             :       // Maybe the AND has been removed by simplify-demanded-bits
    2335             :       // or is useful because it discards more bits
    2336             :       Dst = OrOpd1Val;
    2337             : 
    2338             :     // both parts match
    2339             :     SDLoc DL(N);
    2340          78 :     SDValue Ops[] = {Dst, Src, CurDAG->getTargetConstant(ImmR, DL, VT),
    2341         234 :                      CurDAG->getTargetConstant(ImmS, DL, VT)};
    2342             :     unsigned Opc = (VT == MVT::i32) ? AArch64::BFMWri : AArch64::BFMXri;
    2343          78 :     CurDAG->SelectNodeTo(N, Opc, VT, Ops);
    2344             :     return true;
    2345             :   }
    2346             : 
    2347             :   // Generate a BFXIL from 'or (and X, Mask0Imm), (and Y, Mask1Imm)' iff
    2348             :   // Mask0Imm and ~Mask1Imm are equivalent and one of the MaskImms is a shifted
    2349             :   // mask (e.g., 0x000ffff0).
    2350             :   uint64_t Mask0Imm, Mask1Imm;
    2351         158 :   SDValue And0 = N->getOperand(0);
    2352         158 :   SDValue And1 = N->getOperand(1);
    2353         283 :   if (And0.hasOneUse() && And1.hasOneUse() &&
    2354             :       isOpcWithIntImmediate(And0.getNode(), ISD::AND, Mask0Imm) &&
    2355          21 :       isOpcWithIntImmediate(And1.getNode(), ISD::AND, Mask1Imm) &&
    2356         790 :       APInt(BitWidth, Mask0Imm) == ~APInt(BitWidth, Mask1Imm) &&
    2357          15 :       (isShiftedMask(Mask0Imm, VT) || isShiftedMask(Mask1Imm, VT))) {
    2358             : 
    2359             :     // ORR is commutative, so canonicalize to the form 'or (and X, Mask0Imm),
    2360             :     // (and Y, Mask1Imm)' where Mask1Imm is the shifted mask masking off the
    2361             :     // bits to be inserted.
    2362           8 :     if (isShiftedMask(Mask0Imm, VT)) {
    2363             :       std::swap(And0, And1);
    2364             :       std::swap(Mask0Imm, Mask1Imm);
    2365             :     }
    2366             : 
    2367           8 :     SDValue Src = And1->getOperand(0);
    2368           8 :     SDValue Dst = And0->getOperand(0);
    2369           8 :     unsigned LSB = countTrailingZeros(Mask1Imm);
    2370          16 :     int Width = BitWidth - APInt(BitWidth, Mask0Imm).countPopulation();
    2371             : 
    2372             :     // The BFXIL inserts the low-order bits from a source register, so right
    2373             :     // shift the needed bits into place.
    2374             :     SDLoc DL(N);
    2375             :     unsigned ShiftOpc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
    2376           8 :     SDNode *LSR = CurDAG->getMachineNode(
    2377             :         ShiftOpc, DL, VT, Src, CurDAG->getTargetConstant(LSB, DL, VT),
    2378          16 :         CurDAG->getTargetConstant(BitWidth - 1, DL, VT));
    2379             : 
    2380             :     // BFXIL is an alias of BFM, so translate to BFM operands.
    2381           8 :     unsigned ImmR = (BitWidth - LSB) % BitWidth;
    2382           8 :     unsigned ImmS = Width - 1;
    2383             : 
    2384             :     // Create the BFXIL instruction.
    2385             :     SDValue Ops[] = {Dst, SDValue(LSR, 0),
    2386           8 :                      CurDAG->getTargetConstant(ImmR, DL, VT),
    2387          24 :                      CurDAG->getTargetConstant(ImmS, DL, VT)};
    2388             :     unsigned Opc = (VT == MVT::i32) ? AArch64::BFMWri : AArch64::BFMXri;
    2389           8 :     CurDAG->SelectNodeTo(N, Opc, VT, Ops);
    2390             :     return true;
    2391             :   }
    2392             : 
    2393             :   return false;
    2394             : }
    2395             : 
    2396         404 : bool AArch64DAGToDAGISel::tryBitfieldInsertOp(SDNode *N) {
    2397         404 :   if (N->getOpcode() != ISD::OR)
    2398             :     return false;
    2399             : 
    2400             :   APInt NUsefulBits;
    2401         404 :   getUsefulBits(SDValue(N, 0), NUsefulBits);
    2402             : 
    2403             :   // If all bits are not useful, just return UNDEF.
    2404         404 :   if (!NUsefulBits) {
    2405           2 :     CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF, N->getValueType(0));
    2406             :     return true;
    2407             :   }
    2408             : 
    2409         403 :   if (tryBitfieldInsertOpFromOr(N, NUsefulBits, CurDAG))
    2410             :     return true;
    2411             : 
    2412         317 :   return tryBitfieldInsertOpFromOrAndImm(N, CurDAG);
    2413             : }
    2414             : 
    2415             : /// SelectBitfieldInsertInZeroOp - Match a UBFIZ instruction that is the
    2416             : /// equivalent of a left shift by a constant amount followed by an and masking
    2417             : /// out a contiguous set of bits.
    2418        1208 : bool AArch64DAGToDAGISel::tryBitfieldInsertInZeroOp(SDNode *N) {
    2419        1208 :   if (N->getOpcode() != ISD::AND)
    2420             :     return false;
    2421             : 
    2422        1572 :   EVT VT = N->getValueType(0);
    2423             :   if (VT != MVT::i32 && VT != MVT::i64)
    2424             :     return false;
    2425             : 
    2426         712 :   SDValue Op0;
    2427             :   int DstLSB, Width;
    2428         712 :   if (!isBitfieldPositioningOp(CurDAG, SDValue(N, 0), /*BiggerPattern=*/false,
    2429             :                                Op0, DstLSB, Width))
    2430             :     return false;
    2431             : 
    2432             :   // ImmR is the rotate right amount.
    2433           2 :   unsigned ImmR = (VT.getSizeInBits() - DstLSB) % VT.getSizeInBits();
    2434             :   // ImmS is the most significant bit of the source to be moved.
    2435           2 :   unsigned ImmS = Width - 1;
    2436             : 
    2437             :   SDLoc DL(N);
    2438           2 :   SDValue Ops[] = {Op0, CurDAG->getTargetConstant(ImmR, DL, VT),
    2439           6 :                    CurDAG->getTargetConstant(ImmS, DL, VT)};
    2440             :   unsigned Opc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
    2441           4 :   CurDAG->SelectNodeTo(N, Opc, VT, Ops);
    2442             :   return true;
    2443             : }
    2444             : 
    2445             : /// tryShiftAmountMod - Take advantage of built-in mod of shift amount in
    2446             : /// variable shift/rotate instructions.
    2447        1636 : bool AArch64DAGToDAGISel::tryShiftAmountMod(SDNode *N) {
    2448        3272 :   EVT VT = N->getValueType(0);
    2449             : 
    2450             :   unsigned Opc;
    2451        3272 :   switch (N->getOpcode()) {
    2452             :   case ISD::ROTR:
    2453             :     Opc = (VT == MVT::i32) ? AArch64::RORVWr : AArch64::RORVXr;
    2454             :     break;
    2455             :   case ISD::SHL:
    2456             :     Opc = (VT == MVT::i32) ? AArch64::LSLVWr : AArch64::LSLVXr;
    2457             :     break;
    2458             :   case ISD::SRL:
    2459             :     Opc = (VT == MVT::i32) ? AArch64::LSRVWr : AArch64::LSRVXr;
    2460             :     break;
    2461             :   case ISD::SRA:
    2462             :     Opc = (VT == MVT::i32) ? AArch64::ASRVWr : AArch64::ASRVXr;
    2463             :     break;
    2464             :   default:
    2465             :     return false;
    2466             :   }
    2467             : 
    2468             :   uint64_t Size;
    2469             :   uint64_t Bits;
    2470             :   if (VT == MVT::i32) {
    2471             :     Bits = 5;
    2472             :     Size = 32;
    2473             :   } else if (VT == MVT::i64) {
    2474             :     Bits = 6;
    2475             :     Size = 64;
    2476             :   } else
    2477             :     return false;
    2478             : 
    2479         618 :   SDValue ShiftAmt = N->getOperand(1);
    2480             :   SDLoc DL(N);
    2481             :   SDValue NewShiftAmt;
    2482             : 
    2483             :   // Skip over an extend of the shift amount.
    2484        1236 :   if (ShiftAmt->getOpcode() == ISD::ZERO_EXTEND ||
    2485             :       ShiftAmt->getOpcode() == ISD::ANY_EXTEND)
    2486          45 :     ShiftAmt = ShiftAmt->getOperand(0);
    2487             : 
    2488        1236 :   if (ShiftAmt->getOpcode() == ISD::ADD || ShiftAmt->getOpcode() == ISD::SUB) {
    2489          27 :     SDValue Add0 = ShiftAmt->getOperand(0);
    2490          27 :     SDValue Add1 = ShiftAmt->getOperand(1);
    2491             :     uint64_t Add0Imm;
    2492             :     uint64_t Add1Imm;
    2493             :     // If we are shifting by X+/-N where N == 0 mod Size, then just shift by X
    2494             :     // to avoid the ADD/SUB.
    2495           8 :     if (isIntImmediate(Add1, Add1Imm) && (Add1Imm % Size == 0))
    2496             :       NewShiftAmt = Add0;
    2497             :     // If we are shifting by N-X where N == 0 mod Size, then just shift by -X to
    2498             :     // generate a NEG instead of a SUB of a constant.
    2499             :     else if (ShiftAmt->getOpcode() == ISD::SUB &&
    2500          61 :              isIntImmediate(Add0, Add0Imm) && Add0Imm != 0 &&
    2501          19 :              (Add0Imm % Size == 0)) {
    2502             :       unsigned NegOpc;
    2503             :       unsigned ZeroReg;
    2504          36 :       EVT SubVT = ShiftAmt->getValueType(0);
    2505             :       if (SubVT == MVT::i32) {
    2506             :         NegOpc = AArch64::SUBWrr;
    2507             :         ZeroReg = AArch64::WZR;
    2508             :       } else {
    2509             :         assert(SubVT == MVT::i64);
    2510             :         NegOpc = AArch64::SUBXrr;
    2511             :         ZeroReg = AArch64::XZR;
    2512             :       }
    2513             :       SDValue Zero =
    2514          36 :           CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT);
    2515             :       MachineSDNode *Neg =
    2516          18 :           CurDAG->getMachineNode(NegOpc, DL, SubVT, Zero, Add1);
    2517             :       NewShiftAmt = SDValue(Neg, 0);
    2518             :     } else
    2519           5 :       return false;
    2520             :   } else {
    2521             :     // If the shift amount is masked with an AND, check that the mask covers the
    2522             :     // bits that are implicitly ANDed off by the above opcodes and if so, skip
    2523             :     // the AND.
    2524             :     uint64_t MaskImm;
    2525         591 :     if (!isOpcWithIntImmediate(ShiftAmt.getNode(), ISD::AND, MaskImm))
    2526             :       return false;
    2527             : 
    2528          14 :     if (countTrailingOnes(MaskImm) < Bits)
    2529             :       return false;
    2530             : 
    2531          13 :     NewShiftAmt = ShiftAmt->getOperand(0);
    2532             :   }
    2533             : 
    2534             :   // Narrow/widen the shift amount to match the size of the shift operation.
    2535             :   if (VT == MVT::i32)
    2536          14 :     NewShiftAmt = narrowIfNeeded(CurDAG, NewShiftAmt);
    2537          21 :   else if (VT == MVT::i64 && NewShiftAmt->getValueType(0) == MVT::i32) {
    2538           2 :     SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, DL, MVT::i32);
    2539           1 :     MachineSDNode *Ext = CurDAG->getMachineNode(
    2540             :         AArch64::SUBREG_TO_REG, DL, VT,
    2541           1 :         CurDAG->getTargetConstant(0, DL, MVT::i64), NewShiftAmt, SubReg);
    2542             :     NewShiftAmt = SDValue(Ext, 0);
    2543             :   }
    2544             : 
    2545          35 :   SDValue Ops[] = {N->getOperand(0), NewShiftAmt};
    2546          70 :   CurDAG->SelectNodeTo(N, Opc, VT, Ops);
    2547             :   return true;
    2548             : }
    2549             : 
    2550             : bool
    2551          32 : AArch64DAGToDAGISel::SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos,
    2552             :                                               unsigned RegWidth) {
    2553          32 :   APFloat FVal(0.0);
    2554             :   if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
    2555           0 :     FVal = CN->getValueAPF();
    2556             :   else if (LoadSDNode *LN = dyn_cast<LoadSDNode>(N)) {
    2557             :     // Some otherwise illegal constants are allowed in this case.
    2558          64 :     if (LN->getOperand(1).getOpcode() != AArch64ISD::ADDlow ||
    2559          32 :         !isa<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1)))
    2560             :       return false;
    2561             : 
    2562             :     ConstantPoolSDNode *CN =
    2563             :         dyn_cast<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1));
    2564          32 :     FVal = cast<ConstantFP>(CN->getConstVal())->getValueAPF();
    2565             :   } else
    2566             :     return false;
    2567             : 
    2568             :   // An FCVT[SU] instruction performs: convertToInt(Val * 2^fbits) where fbits
    2569             :   // is between 1 and 32 for a destination w-register, or 1 and 64 for an
    2570             :   // x-register.
    2571             :   //
    2572             :   // By this stage, we've detected (fp_to_[su]int (fmul Val, THIS_NODE)) so we
    2573             :   // want THIS_NODE to be 2^fbits. This is much easier to deal with using
    2574             :   // integers.
    2575             :   bool IsExact;
    2576             : 
    2577             :   // fbits is between 1 and 64 in the worst-case, which means the fmul
    2578             :   // could have 2^64 as an actual operand. Need 65 bits of precision.
    2579             :   APSInt IntVal(65, true);
    2580          32 :   FVal.convertToInteger(IntVal, APFloat::rmTowardZero, &IsExact);
    2581             : 
    2582             :   // N.b. isPowerOf2 also checks for > 0.
    2583          32 :   if (!IsExact || !IntVal.isPowerOf2()) return false;
    2584             :   unsigned FBits = IntVal.logBase2();
    2585             : 
    2586             :   // Checks above should have guaranteed that we haven't lost information in
    2587             :   // finding FBits, but it must still be in range.
    2588          32 :   if (FBits == 0 || FBits > RegWidth) return false;
    2589             : 
    2590         128 :   FixedPos = CurDAG->getTargetConstant(FBits, SDLoc(N), MVT::i32);
    2591             :   return true;
    2592             : }
    2593             : 
    2594             : // Inspects a register string of the form o0:op1:CRn:CRm:op2 gets the fields
    2595             : // of the string and obtains the integer values from them and combines these
    2596             : // into a single value to be used in the MRS/MSR instruction.
    2597          15 : static int getIntOperandFromRegisterString(StringRef RegString) {
    2598             :   SmallVector<StringRef, 5> Fields;
    2599          15 :   RegString.split(Fields, ':');
    2600             : 
    2601          15 :   if (Fields.size() == 1)
    2602             :     return -1;
    2603             : 
    2604             :   assert(Fields.size() == 5
    2605             :             && "Invalid number of fields in read register string");
    2606             : 
    2607             :   SmallVector<int, 5> Ops;
    2608             :   bool AllIntFields = true;
    2609             : 
    2610          22 :   for (StringRef Field : Fields) {
    2611             :     unsigned IntField;
    2612             :     AllIntFields &= !Field.getAsInteger(10, IntField);
    2613          10 :     Ops.push_back(IntField);
    2614             :   }
    2615             : 
    2616             :   assert(AllIntFields &&
    2617             :           "Unexpected non-integer value in special register string.");
    2618             : 
    2619             :   // Need to combine the integer fields of the string into a single value
    2620             :   // based on the bit encoding of MRS/MSR instruction.
    2621           4 :   return (Ops[0] << 14) | (Ops[1] << 11) | (Ops[2] << 7) |
    2622           4 :          (Ops[3] << 3) | (Ops[4]);
    2623             : }
    2624             : 
    2625             : // Lower the read_register intrinsic to an MRS instruction node if the special
    2626             : // register string argument is either of the form detailed in the ALCE (the
    2627             : // form described in getIntOperandsFromRegsterString) or is a named register
    2628             : // known by the MRS SysReg mapper.
    2629           7 : bool AArch64DAGToDAGISel::tryReadRegister(SDNode *N) {
    2630           7 :   const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(N->getOperand(1));
    2631           7 :   const MDString *RegString = dyn_cast<MDString>(MD->getMD()->getOperand(0));
    2632             :   SDLoc DL(N);
    2633             : 
    2634           7 :   int Reg = getIntOperandFromRegisterString(RegString->getString());
    2635           7 :   if (Reg != -1) {
    2636           3 :     ReplaceNode(N, CurDAG->getMachineNode(
    2637             :                        AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other,
    2638             :                        CurDAG->getTargetConstant(Reg, DL, MVT::i32),
    2639           1 :                        N->getOperand(0)));
    2640           1 :     return true;
    2641             :   }
    2642             : 
    2643             :   // Use the sysreg mapper to map the remaining possible strings to the
    2644             :   // value for the register to be used for the instruction operand.
    2645           6 :   auto TheReg = AArch64SysReg::lookupSysRegByName(RegString->getString());
    2646           7 :   if (TheReg && TheReg->Readable &&
    2647           1 :       TheReg->haveFeatures(Subtarget->getFeatureBits()))
    2648           1 :     Reg = TheReg->Encoding;
    2649             :   else
    2650           5 :     Reg = AArch64SysReg::parseGenericRegister(RegString->getString());
    2651             : 
    2652           6 :   if (Reg != -1) {
    2653           3 :     ReplaceNode(N, CurDAG->getMachineNode(
    2654             :                        AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other,
    2655             :                        CurDAG->getTargetConstant(Reg, DL, MVT::i32),
    2656           1 :                        N->getOperand(0)));
    2657           1 :     return true;
    2658             :   }
    2659             : 
    2660             :   return false;
    2661             : }
    2662             : 
    2663             : // Lower the write_register intrinsic to an MSR instruction node if the special
    2664             : // register string argument is either of the form detailed in the ALCE (the
    2665             : // form described in getIntOperandsFromRegsterString) or is a named register
    2666             : // known by the MSR SysReg mapper.
    2667           8 : bool AArch64DAGToDAGISel::tryWriteRegister(SDNode *N) {
    2668           8 :   const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(N->getOperand(1));
    2669           8 :   const MDString *RegString = dyn_cast<MDString>(MD->getMD()->getOperand(0));
    2670             :   SDLoc DL(N);
    2671             : 
    2672           8 :   int Reg = getIntOperandFromRegisterString(RegString->getString());
    2673           8 :   if (Reg != -1) {
    2674           1 :     ReplaceNode(
    2675           4 :         N, CurDAG->getMachineNode(AArch64::MSR, DL, MVT::Other,
    2676             :                                   CurDAG->getTargetConstant(Reg, DL, MVT::i32),
    2677           1 :                                   N->getOperand(2), N->getOperand(0)));
    2678           1 :     return true;
    2679             :   }
    2680             : 
    2681             :   // Check if the register was one of those allowed as the pstatefield value in
    2682             :   // the MSR (immediate) instruction. To accept the values allowed in the
    2683             :   // pstatefield for the MSR (immediate) instruction, we also require that an
    2684             :   // immediate value has been provided as an argument, we know that this is
    2685             :   // the case as it has been ensured by semantic checking.
    2686           7 :   auto PMapper = AArch64PState::lookupPStateByName(RegString->getString());
    2687           7 :   if (PMapper) {
    2688             :     assert (isa<ConstantSDNode>(N->getOperand(2))
    2689             :               && "Expected a constant integer expression.");
    2690           1 :     unsigned Reg = PMapper->Encoding;
    2691           2 :     uint64_t Immed = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
    2692             :     unsigned State;
    2693           1 :     if (Reg == AArch64PState::PAN || Reg == AArch64PState::UAO) {
    2694             :       assert(Immed < 2 && "Bad imm");
    2695             :       State = AArch64::MSRpstateImm1;
    2696             :     } else {
    2697             :       assert(Immed < 16 && "Bad imm");
    2698             :       State = AArch64::MSRpstateImm4;
    2699             :     }
    2700           3 :     ReplaceNode(N, CurDAG->getMachineNode(
    2701             :                        State, DL, MVT::Other,
    2702           1 :                        CurDAG->getTargetConstant(Reg, DL, MVT::i32),
    2703             :                        CurDAG->getTargetConstant(Immed, DL, MVT::i16),
    2704             :                        N->getOperand(0)));
    2705           1 :     return true;
    2706             :   }
    2707             : 
    2708             :   // Use the sysreg mapper to attempt to map the remaining possible strings
    2709             :   // to the value for the register to be used for the MSR (register)
    2710             :   // instruction operand.
    2711           6 :   auto TheReg = AArch64SysReg::lookupSysRegByName(RegString->getString());
    2712           7 :   if (TheReg && TheReg->Writeable &&
    2713           1 :       TheReg->haveFeatures(Subtarget->getFeatureBits()))
    2714           1 :     Reg = TheReg->Encoding;
    2715             :   else
    2716           5 :     Reg = AArch64SysReg::parseGenericRegister(RegString->getString());
    2717           6 :   if (Reg != -1) {
    2718           3 :     ReplaceNode(N, CurDAG->getMachineNode(
    2719             :                        AArch64::MSR, DL, MVT::Other,
    2720             :                        CurDAG->getTargetConstant(Reg, DL, MVT::i32),
    2721           1 :                        N->getOperand(2), N->getOperand(0)));
    2722           1 :     return true;
    2723             :   }
    2724             : 
    2725             :   return false;
    2726             : }
    2727             : 
    2728             : /// We've got special pseudo-instructions for these
    2729          76 : bool AArch64DAGToDAGISel::SelectCMP_SWAP(SDNode *N) {
    2730             :   unsigned Opcode;
    2731             :   EVT MemTy = cast<MemSDNode>(N)->getMemoryVT();
    2732             : 
    2733             :   // Leave IR for LSE if subtarget supports it.
    2734          76 :   if (Subtarget->hasLSE()) return false;
    2735             : 
    2736             :   if (MemTy == MVT::i8)
    2737             :     Opcode = AArch64::CMP_SWAP_8;
    2738             :   else if (MemTy == MVT::i16)
    2739             :     Opcode = AArch64::CMP_SWAP_16;
    2740             :   else if (MemTy == MVT::i32)
    2741             :     Opcode = AArch64::CMP_SWAP_32;
    2742             :   else if (MemTy == MVT::i64)
    2743             :     Opcode = AArch64::CMP_SWAP_64;
    2744             :   else
    2745           0 :     llvm_unreachable("Unknown AtomicCmpSwap type");
    2746             : 
    2747             :   MVT RegTy = MemTy == MVT::i64 ? MVT::i64 : MVT::i32;
    2748           4 :   SDValue Ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3),
    2749           4 :                    N->getOperand(0)};
    2750          12 :   SDNode *CmpSwap = CurDAG->getMachineNode(
    2751           4 :       Opcode, SDLoc(N),
    2752           4 :       CurDAG->getVTList(RegTy, MVT::i32, MVT::Other), Ops);
    2753             : 
    2754           4 :   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
    2755           4 :   MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
    2756           4 :   cast<MachineSDNode>(CmpSwap)->setMemRefs(MemOp, MemOp + 1);
    2757             : 
    2758           4 :   ReplaceUses(SDValue(N, 0), SDValue(CmpSwap, 0));
    2759           4 :   ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 2));
    2760           4 :   CurDAG->RemoveDeadNode(N);
    2761             : 
    2762           4 :   return true;
    2763             : }
    2764             : 
    2765      183842 : void AArch64DAGToDAGISel::Select(SDNode *Node) {
    2766             :   // If we have a custom node, we already have selected!
    2767      183842 :   if (Node->isMachineOpcode()) {
    2768             :     LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
    2769             :     Node->setNodeId(-1);
    2770        3057 :     return;
    2771             :   }
    2772             : 
    2773             :   // Few custom selection stuff.
    2774      366690 :   EVT VT = Node->getValueType(0);
    2775             : 
    2776      183345 :   switch (Node->getOpcode()) {
    2777             :   default:
    2778             :     break;
    2779             : 
    2780          76 :   case ISD::ATOMIC_CMP_SWAP:
    2781          76 :     if (SelectCMP_SWAP(Node))
    2782             :       return;
    2783             :     break;
    2784             : 
    2785           7 :   case ISD::READ_REGISTER:
    2786           7 :     if (tryReadRegister(Node))
    2787             :       return;
    2788             :     break;
    2789             : 
    2790           8 :   case ISD::WRITE_REGISTER:
    2791           8 :     if (tryWriteRegister(Node))
    2792             :       return;
    2793             :     break;
    2794             : 
    2795        2464 :   case ISD::ADD:
    2796        2464 :     if (tryMLAV64LaneV128(Node))
    2797             :       return;
    2798             :     break;
    2799             : 
    2800        5707 :   case ISD::LOAD: {
    2801             :     // Try to select as an indexed load. Fall through to normal processing
    2802             :     // if we can't.
    2803        5707 :     if (tryIndexedLoad(Node))
    2804             :       return;
    2805             :     break;
    2806             :   }
    2807             : 
    2808        1256 :   case ISD::SRL:
    2809             :   case ISD::AND:
    2810             :   case ISD::SRA:
    2811             :   case ISD::SIGN_EXTEND_INREG:
    2812        1256 :     if (tryBitfieldExtractOp(Node))
    2813             :       return;
    2814        1208 :     if (tryBitfieldInsertInZeroOp(Node))
    2815             :       return;
    2816             :     LLVM_FALLTHROUGH;
    2817             :   case ISD::ROTR:
    2818             :   case ISD::SHL:
    2819        1636 :     if (tryShiftAmountMod(Node))
    2820             :       return;
    2821             :     break;
    2822             : 
    2823          89 :   case ISD::SIGN_EXTEND:
    2824          89 :     if (tryBitfieldExtractOpFromSExt(Node))
    2825             :       return;
    2826             :     break;
    2827             : 
    2828         404 :   case ISD::OR:
    2829         404 :     if (tryBitfieldInsertOp(Node))
    2830             :       return;
    2831             :     break;
    2832             : 
    2833        1505 :   case ISD::EXTRACT_VECTOR_ELT: {
    2834             :     // Extracting lane zero is a special case where we can just use a plain
    2835             :     // EXTRACT_SUBREG instruction, which will become FMOV. This is easier for
    2836             :     // the rest of the compiler, especially the register allocator and copyi
    2837             :     // propagation, to reason about, so is preferred when it's possible to
    2838             :     // use it.
    2839        1505 :     ConstantSDNode *LaneNode = cast<ConstantSDNode>(Node->getOperand(1));
    2840             :     // Bail and use the default Select() for non-zero lanes.
    2841        3010 :     if (LaneNode->getZExtValue() != 0)
    2842             :       break;
    2843             :     // If the element type is not the same as the result type, likewise
    2844             :     // bail and use the default Select(), as there's more to do than just
    2845             :     // a cross-class COPY. This catches extracts of i8 and i16 elements
    2846             :     // since they will need an explicit zext.
    2847        1785 :     if (VT != Node->getOperand(0).getValueType().getVectorElementType())
    2848             :       break;
    2849             :     unsigned SubReg;
    2850         904 :     switch (Node->getOperand(0)
    2851        1356 :                 .getValueType()
    2852         904 :                 .getVectorElementType()
    2853         452 :                 .getSizeInBits()) {
    2854           0 :     default:
    2855           0 :       llvm_unreachable("Unexpected vector element type!");
    2856             :     case 64:
    2857             :       SubReg = AArch64::dsub;
    2858             :       break;
    2859         155 :     case 32:
    2860             :       SubReg = AArch64::ssub;
    2861         155 :       break;
    2862         129 :     case 16:
    2863             :       SubReg = AArch64::hsub;
    2864         129 :       break;
    2865           0 :     case 8:
    2866           0 :       llvm_unreachable("unexpected zext-requiring extract element!");
    2867             :     }
    2868         904 :     SDValue Extract = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(Node), VT,
    2869         904 :                                                      Node->getOperand(0));
    2870             :     LLVM_DEBUG(dbgs() << "ISEL: Custom selection!\n=> ");
    2871             :     LLVM_DEBUG(Extract->dumpr(CurDAG));
    2872             :     LLVM_DEBUG(dbgs() << "\n");
    2873         452 :     ReplaceNode(Node, Extract.getNode());
    2874         452 :     return;
    2875             :   }
    2876             :   case ISD::Constant: {
    2877             :     // Materialize zero constants as copies from WZR/XZR.  This allows
    2878             :     // the coalescer to propagate these into other instructions.
    2879             :     ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);
    2880        4026 :     if (ConstNode->isNullValue()) {
    2881             :       if (VT == MVT::i32) {
    2882         498 :         SDValue New = CurDAG->getCopyFromReg(
    2883        1494 :             CurDAG->getEntryNode(), SDLoc(Node), AArch64::WZR, MVT::i32);
    2884         498 :         ReplaceNode(Node, New.getNode());
    2885             :         return;
    2886             :       } else if (VT == MVT::i64) {
    2887         178 :         SDValue New = CurDAG->getCopyFromReg(
    2888         534 :             CurDAG->getEntryNode(), SDLoc(Node), AArch64::XZR, MVT::i64);
    2889         178 :         ReplaceNode(Node, New.getNode());
    2890             :         return;
    2891             :       }
    2892             :     }
    2893             :     break;
    2894             :   }
    2895       16506 :   case ISD::CopyToReg: {
    2896             :     // Special case for copy of zero to avoid a double copy.
    2897       16506 :     SDNode *CopyVal = Node->getOperand(2).getNode();
    2898             :     ConstantSDNode *CopyValConst = dyn_cast<ConstantSDNode>(CopyVal);
    2899        2264 :     if (!CopyValConst || !CopyValConst->isNullValue())
    2900             :       break;
    2901             :     const SDValue &Dest = Node->getOperand(1);
    2902         772 :     if (!TargetRegisterInfo::isVirtualRegister(
    2903             :             cast<RegisterSDNode>(Dest)->getReg()))
    2904             :       break;
    2905             :     unsigned ZeroReg;
    2906         266 :     EVT ZeroVT = CopyValConst->getValueType(0);
    2907             :     if (ZeroVT == MVT::i32)
    2908             :       ZeroReg = AArch64::WZR;
    2909             :     else if (ZeroVT == MVT::i64)
    2910             :       ZeroReg = AArch64::XZR;
    2911             :     else
    2912             :       break;
    2913         133 :     unsigned NumOperands = Node->getNumOperands();
    2914         133 :     SDValue ZeroRegVal = CurDAG->getRegister(ZeroReg, ZeroVT);
    2915             :     // Replace the source operand (#0) with ZeroRegVal.
    2916         133 :     SDValue Ops[] = {Node->getOperand(0), Node->getOperand(1), ZeroRegVal,
    2917         133 :                      (NumOperands == 4) ? Node->getOperand(3) : SDValue()};
    2918             :     SDValue New =
    2919         266 :         CurDAG->getNode(ISD::CopyToReg, SDLoc(Node), Node->getVTList(),
    2920         266 :                         makeArrayRef(Ops, NumOperands));
    2921         133 :     ReplaceNode(Node, New.getNode());
    2922         133 :     return;
    2923             :   }
    2924             :   case ISD::FrameIndex: {
    2925             :     // Selects to ADDXri FI, 0 which in turn will become ADDXri SP, imm.
    2926         140 :     int FI = cast<FrameIndexSDNode>(Node)->getIndex();
    2927             :     unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
    2928             :     const TargetLowering *TLI = getTargetLowering();
    2929         140 :     SDValue TFI = CurDAG->getTargetFrameIndex(
    2930         140 :         FI, TLI->getPointerTy(CurDAG->getDataLayout()));
    2931             :     SDLoc DL(Node);
    2932         140 :     SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, DL, MVT::i32),
    2933         420 :                       CurDAG->getTargetConstant(Shifter, DL, MVT::i32) };
    2934         280 :     CurDAG->SelectNodeTo(Node, AArch64::ADDXri, MVT::i64, Ops);
    2935             :     return;
    2936             :   }
    2937         400 :   case ISD::INTRINSIC_W_CHAIN: {
    2938        1200 :     unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
    2939         400 :     switch (IntNo) {
    2940             :     default:
    2941             :       break;
    2942          16 :     case Intrinsic::aarch64_ldaxp:
    2943             :     case Intrinsic::aarch64_ldxp: {
    2944             :       unsigned Op =
    2945          16 :           IntNo == Intrinsic::aarch64_ldaxp ? AArch64::LDAXPX : AArch64::LDXPX;
    2946          16 :       SDValue MemAddr = Node->getOperand(2);
    2947             :       SDLoc DL(Node);
    2948          16 :       SDValue Chain = Node->getOperand(0);
    2949             : 
    2950          32 :       SDNode *Ld = CurDAG->getMachineNode(Op, DL, MVT::i64, MVT::i64,
    2951          16 :                                           MVT::Other, MemAddr, Chain);
    2952             : 
    2953             :       // Transfer memoperands.
    2954          16 :       MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
    2955          16 :       MemOp[0] = cast<MemIntrinsicSDNode>(Node)->getMemOperand();
    2956          16 :       cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
    2957          16 :       ReplaceNode(Node, Ld);
    2958             :       return;
    2959             :     }
    2960          16 :     case Intrinsic::aarch64_stlxp:
    2961             :     case Intrinsic::aarch64_stxp: {
    2962             :       unsigned Op =
    2963          16 :           IntNo == Intrinsic::aarch64_stlxp ? AArch64::STLXPX : AArch64::STXPX;
    2964             :       SDLoc DL(Node);
    2965          16 :       SDValue Chain = Node->getOperand(0);
    2966          16 :       SDValue ValLo = Node->getOperand(2);
    2967          16 :       SDValue ValHi = Node->getOperand(3);
    2968          16 :       SDValue MemAddr = Node->getOperand(4);
    2969             : 
    2970             :       // Place arguments in the right order.
    2971          16 :       SDValue Ops[] = {ValLo, ValHi, MemAddr, Chain};
    2972             : 
    2973          32 :       SDNode *St = CurDAG->getMachineNode(Op, DL, MVT::i32, MVT::Other, Ops);
    2974             :       // Transfer memoperands.
    2975          16 :       MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
    2976          16 :       MemOp[0] = cast<MemIntrinsicSDNode>(Node)->getMemOperand();
    2977          16 :       cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
    2978             : 
    2979          16 :       ReplaceNode(Node, St);
    2980             :       return;
    2981             :     }
    2982             :     case Intrinsic::aarch64_neon_ld1x2:
    2983             :       if (VT == MVT::v8i8) {
    2984           1 :         SelectLoad(Node, 2, AArch64::LD1Twov8b, AArch64::dsub0);
    2985           1 :         return;
    2986             :       } else if (VT == MVT::v16i8) {
    2987           1 :         SelectLoad(Node, 2, AArch64::LD1Twov16b, AArch64::qsub0);
    2988           1 :         return;
    2989             :       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    2990           2 :         SelectLoad(Node, 2, AArch64::LD1Twov4h, AArch64::dsub0);
    2991           2 :         return;
    2992             :       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    2993           2 :         SelectLoad(Node, 2, AArch64::LD1Twov8h, AArch64::qsub0);
    2994           2 :         return;
    2995             :       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    2996           2 :         SelectLoad(Node, 2, AArch64::LD1Twov2s, AArch64::dsub0);
    2997           2 :         return;
    2998             :       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    2999           2 :         SelectLoad(Node, 2, AArch64::LD1Twov4s, AArch64::qsub0);
    3000           2 :         return;
    3001             :       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3002           2 :         SelectLoad(Node, 2, AArch64::LD1Twov1d, AArch64::dsub0);
    3003           2 :         return;
    3004             :       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3005           2 :         SelectLoad(Node, 2, AArch64::LD1Twov2d, AArch64::qsub0);
    3006           2 :         return;
    3007             :       }
    3008             :       break;
    3009             :     case Intrinsic::aarch64_neon_ld1x3:
    3010             :       if (VT == MVT::v8i8) {
    3011           1 :         SelectLoad(Node, 3, AArch64::LD1Threev8b, AArch64::dsub0);
    3012           1 :         return;
    3013             :       } else if (VT == MVT::v16i8) {
    3014           1 :         SelectLoad(Node, 3, AArch64::LD1Threev16b, AArch64::qsub0);
    3015           1 :         return;
    3016             :       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3017           2 :         SelectLoad(Node, 3, AArch64::LD1Threev4h, AArch64::dsub0);
    3018           2 :         return;
    3019             :       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3020           2 :         SelectLoad(Node, 3, AArch64::LD1Threev8h, AArch64::qsub0);
    3021           2 :         return;
    3022             :       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3023           2 :         SelectLoad(Node, 3, AArch64::LD1Threev2s, AArch64::dsub0);
    3024           2 :         return;
    3025             :       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3026           2 :         SelectLoad(Node, 3, AArch64::LD1Threev4s, AArch64::qsub0);
    3027           2 :         return;
    3028             :       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3029           2 :         SelectLoad(Node, 3, AArch64::LD1Threev1d, AArch64::dsub0);
    3030           2 :         return;
    3031             :       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3032           2 :         SelectLoad(Node, 3, AArch64::LD1Threev2d, AArch64::qsub0);
    3033           2 :         return;
    3034             :       }
    3035             :       break;
    3036             :     case Intrinsic::aarch64_neon_ld1x4:
    3037             :       if (VT == MVT::v8i8) {
    3038           1 :         SelectLoad(Node, 4, AArch64::LD1Fourv8b, AArch64::dsub0);
    3039           1 :         return;
    3040             :       } else if (VT == MVT::v16i8) {
    3041           1 :         SelectLoad(Node, 4, AArch64::LD1Fourv16b, AArch64::qsub0);
    3042           1 :         return;
    3043             :       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3044           2 :         SelectLoad(Node, 4, AArch64::LD1Fourv4h, AArch64::dsub0);
    3045           2 :         return;
    3046             :       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3047           2 :         SelectLoad(Node, 4, AArch64::LD1Fourv8h, AArch64::qsub0);
    3048           2 :         return;
    3049             :       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3050           2 :         SelectLoad(Node, 4, AArch64::LD1Fourv2s, AArch64::dsub0);
    3051           2 :         return;
    3052             :       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3053           2 :         SelectLoad(Node, 4, AArch64::LD1Fourv4s, AArch64::qsub0);
    3054           2 :         return;
    3055             :       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3056           2 :         SelectLoad(Node, 4, AArch64::LD1Fourv1d, AArch64::dsub0);
    3057           2 :         return;
    3058             :       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3059           2 :         SelectLoad(Node, 4, AArch64::LD1Fourv2d, AArch64::qsub0);
    3060           2 :         return;
    3061             :       }
    3062             :       break;
    3063             :     case Intrinsic::aarch64_neon_ld2:
    3064             :       if (VT == MVT::v8i8) {
    3065           5 :         SelectLoad(Node, 2, AArch64::LD2Twov8b, AArch64::dsub0);
    3066           5 :         return;
    3067             :       } else if (VT == MVT::v16i8) {
    3068           1 :         SelectLoad(Node, 2, AArch64::LD2Twov16b, AArch64::qsub0);
    3069           1 :         return;
    3070             :       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3071           2 :         SelectLoad(Node, 2, AArch64::LD2Twov4h, AArch64::dsub0);
    3072           2 :         return;
    3073             :       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3074           2 :         SelectLoad(Node, 2, AArch64::LD2Twov8h, AArch64::qsub0);
    3075           2 :         return;
    3076             :       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3077           2 :         SelectLoad(Node, 2, AArch64::LD2Twov2s, AArch64::dsub0);
    3078           2 :         return;
    3079             :       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3080           4 :         SelectLoad(Node, 2, AArch64::LD2Twov4s, AArch64::qsub0);
    3081           4 :         return;
    3082             :       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3083           2 :         SelectLoad(Node, 2, AArch64::LD1Twov1d, AArch64::dsub0);
    3084           2 :         return;
    3085             :       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3086           1 :         SelectLoad(Node, 2, AArch64::LD2Twov2d, AArch64::qsub0);
    3087           1 :         return;
    3088             :       }
    3089             :       break;
    3090             :     case Intrinsic::aarch64_neon_ld3:
    3091             :       if (VT == MVT::v8i8) {
    3092           2 :         SelectLoad(Node, 3, AArch64::LD3Threev8b, AArch64::dsub0);
    3093           2 :         return;
    3094             :       } else if (VT == MVT::v16i8) {
    3095           2 :         SelectLoad(Node, 3, AArch64::LD3Threev16b, AArch64::qsub0);
    3096           2 :         return;
    3097             :       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3098           3 :         SelectLoad(Node, 3, AArch64::LD3Threev4h, AArch64::dsub0);
    3099           3 :         return;
    3100             :       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3101           2 :         SelectLoad(Node, 3, AArch64::LD3Threev8h, AArch64::qsub0);
    3102           2 :         return;
    3103             :       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3104           1 :         SelectLoad(Node, 3, AArch64::LD3Threev2s, AArch64::dsub0);
    3105           1 :         return;
    3106             :       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3107           2 :         SelectLoad(Node, 3, AArch64::LD3Threev4s, AArch64::qsub0);
    3108           2 :         return;
    3109             :       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3110           2 :         SelectLoad(Node, 3, AArch64::LD1Threev1d, AArch64::dsub0);
    3111           2 :         return;
    3112             :       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3113           1 :         SelectLoad(Node, 3, AArch64::LD3Threev2d, AArch64::qsub0);
    3114           1 :         return;
    3115             :       }
    3116             :       break;
    3117             :     case Intrinsic::aarch64_neon_ld4:
    3118             :       if (VT == MVT::v8i8) {
    3119           1 :         SelectLoad(Node, 4, AArch64::LD4Fourv8b, AArch64::dsub0);
    3120           1 :         return;
    3121             :       } else if (VT == MVT::v16i8) {
    3122           3 :         SelectLoad(Node, 4, AArch64::LD4Fourv16b, AArch64::qsub0);
    3123           3 :         return;
    3124             :       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3125           3 :         SelectLoad(Node, 4, AArch64::LD4Fourv4h, AArch64::dsub0);
    3126           3 :         return;
    3127             :       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3128           2 :         SelectLoad(Node, 4, AArch64::LD4Fourv8h, AArch64::qsub0);
    3129           2 :         return;
    3130             :       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3131           1 :         SelectLoad(Node, 4, AArch64::LD4Fourv2s, AArch64::dsub0);
    3132           1 :         return;
    3133             :       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3134           1 :         SelectLoad(Node, 4, AArch64::LD4Fourv4s, AArch64::qsub0);
    3135           1 :         return;
    3136             :       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3137           2 :         SelectLoad(Node, 4, AArch64::LD1Fourv1d, AArch64::dsub0);
    3138           2 :         return;
    3139             :       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3140           1 :         SelectLoad(Node, 4, AArch64::LD4Fourv2d, AArch64::qsub0);
    3141           1 :         return;
    3142             :       }
    3143             :       break;
    3144             :     case Intrinsic::aarch64_neon_ld2r:
    3145             :       if (VT == MVT::v8i8) {
    3146           1 :         SelectLoad(Node, 2, AArch64::LD2Rv8b, AArch64::dsub0);
    3147           1 :         return;
    3148             :       } else if (VT == MVT::v16i8) {
    3149           1 :         SelectLoad(Node, 2, AArch64::LD2Rv16b, AArch64::qsub0);
    3150           1 :         return;
    3151             :       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3152           2 :         SelectLoad(Node, 2, AArch64::LD2Rv4h, AArch64::dsub0);
    3153           2 :         return;
    3154             :       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3155           2 :         SelectLoad(Node, 2, AArch64::LD2Rv8h, AArch64::qsub0);
    3156           2 :         return;
    3157             :       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3158           1 :         SelectLoad(Node, 2, AArch64::LD2Rv2s, AArch64::dsub0);
    3159           1 :         return;
    3160             :       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3161           1 :         SelectLoad(Node, 2, AArch64::LD2Rv4s, AArch64::qsub0);
    3162           1 :         return;
    3163             :       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3164           1 :         SelectLoad(Node, 2, AArch64::LD2Rv1d, AArch64::dsub0);
    3165           1 :         return;
    3166             :       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3167           1 :         SelectLoad(Node, 2, AArch64::LD2Rv2d, AArch64::qsub0);
    3168           1 :         return;
    3169             :       }
    3170             :       break;
    3171             :     case Intrinsic::aarch64_neon_ld3r:
    3172             :       if (VT == MVT::v8i8) {
    3173           1 :         SelectLoad(Node, 3, AArch64::LD3Rv8b, AArch64::dsub0);
    3174           1 :         return;
    3175             :       } else if (VT == MVT::v16i8) {
    3176           1 :         SelectLoad(Node, 3, AArch64::LD3Rv16b, AArch64::qsub0);
    3177           1 :         return;
    3178             :       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3179           2 :         SelectLoad(Node, 3, AArch64::LD3Rv4h, AArch64::dsub0);
    3180           2 :         return;
    3181             :       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3182           2 :         SelectLoad(Node, 3, AArch64::LD3Rv8h, AArch64::qsub0);
    3183           2 :         return;
    3184             :       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3185           1 :         SelectLoad(Node, 3, AArch64::LD3Rv2s, AArch64::dsub0);
    3186           1 :         return;
    3187             :       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3188           1 :         SelectLoad(Node, 3, AArch64::LD3Rv4s, AArch64::qsub0);
    3189           1 :         return;
    3190             :       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3191           1 :         SelectLoad(Node, 3, AArch64::LD3Rv1d, AArch64::dsub0);
    3192           1 :         return;
    3193             :       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3194           1 :         SelectLoad(Node, 3, AArch64::LD3Rv2d, AArch64::qsub0);
    3195           1 :         return;
    3196             :       }
    3197             :       break;
    3198             :     case Intrinsic::aarch64_neon_ld4r:
    3199             :       if (VT == MVT::v8i8) {
    3200           1 :         SelectLoad(Node, 4, AArch64::LD4Rv8b, AArch64::dsub0);
    3201           1 :         return;
    3202             :       } else if (VT == MVT::v16i8) {
    3203           1 :         SelectLoad(Node, 4, AArch64::LD4Rv16b, AArch64::qsub0);
    3204           1 :         return;
    3205             :       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3206           2 :         SelectLoad(Node, 4, AArch64::LD4Rv4h, AArch64::dsub0);
    3207           2 :         return;
    3208             :       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3209           2 :         SelectLoad(Node, 4, AArch64::LD4Rv8h, AArch64::qsub0);
    3210           2 :         return;
    3211             :       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3212           1 :         SelectLoad(Node, 4, AArch64::LD4Rv2s, AArch64::dsub0);
    3213           1 :         return;
    3214             :       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3215           1 :         SelectLoad(Node, 4, AArch64::LD4Rv4s, AArch64::qsub0);
    3216           1 :         return;
    3217             :       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3218           1 :         SelectLoad(Node, 4, AArch64::LD4Rv1d, AArch64::dsub0);
    3219           1 :         return;
    3220             :       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3221           1 :         SelectLoad(Node, 4, AArch64::LD4Rv2d, AArch64::qsub0);
    3222           1 :         return;
    3223             :       }
    3224             :       break;
    3225             :     case Intrinsic::aarch64_neon_ld2lane:
    3226             :       if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    3227           1 :         SelectLoadLane(Node, 2, AArch64::LD2i8);
    3228           1 :         return;
    3229             :       } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
    3230             :                  VT == MVT::v8f16) {
    3231           3 :         SelectLoadLane(Node, 2, AArch64::LD2i16);
    3232           3 :         return;
    3233             :       } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
    3234             :                  VT == MVT::v2f32) {
    3235           3 :         SelectLoadLane(Node, 2, AArch64::LD2i32);
    3236           3 :         return;
    3237             :       } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
    3238             :                  VT == MVT::v1f64) {
    3239           3 :         SelectLoadLane(Node, 2, AArch64::LD2i64);
    3240           3 :         return;
    3241             :       }
    3242             :       break;
    3243             :     case Intrinsic::aarch64_neon_ld3lane:
    3244             :       if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    3245           1 :         SelectLoadLane(Node, 3, AArch64::LD3i8);
    3246           1 :         return;
    3247             :       } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
    3248             :                  VT == MVT::v8f16) {
    3249           3 :         SelectLoadLane(Node, 3, AArch64::LD3i16);
    3250           3 :         return;
    3251             :       } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
    3252             :                  VT == MVT::v2f32) {
    3253           3 :         SelectLoadLane(Node, 3, AArch64::LD3i32);
    3254           3 :         return;
    3255             :       } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
    3256             :                  VT == MVT::v1f64) {
    3257           1 :         SelectLoadLane(Node, 3, AArch64::LD3i64);
    3258           1 :         return;
    3259             :       }
    3260             :       break;
    3261             :     case Intrinsic::aarch64_neon_ld4lane:
    3262             :       if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    3263           1 :         SelectLoadLane(Node, 4, AArch64::LD4i8);
    3264           1 :         return;
    3265             :       } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
    3266             :                  VT == MVT::v8f16) {
    3267           3 :         SelectLoadLane(Node, 4, AArch64::LD4i16);
    3268           3 :         return;
    3269             :       } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
    3270             :                  VT == MVT::v2f32) {
    3271           3 :         SelectLoadLane(Node, 4, AArch64::LD4i32);
    3272           3 :         return;
    3273             :       } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
    3274             :                  VT == MVT::v1f64) {
    3275           1 :         SelectLoadLane(Node, 4, AArch64::LD4i64);
    3276           1 :         return;
    3277             :       }
    3278             :       break;
    3279             :     }
    3280             :   } break;
    3281        1788 :   case ISD::INTRINSIC_WO_CHAIN: {
    3282        5364 :     unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
    3283        1788 :     switch (IntNo) {
    3284             :     default:
    3285             :       break;
    3286             :     case Intrinsic::aarch64_neon_tbl2:
    3287           4 :       SelectTable(Node, 2,
    3288             :                   VT == MVT::v8i8 ? AArch64::TBLv8i8Two : AArch64::TBLv16i8Two,
    3289             :                   false);
    3290           4 :       return;
    3291             :     case Intrinsic::aarch64_neon_tbl3:
    3292           2 :       SelectTable(Node, 3, VT == MVT::v8i8 ? AArch64::TBLv8i8Three
    3293             :                                            : AArch64::TBLv16i8Three,
    3294             :                   false);
    3295           2 :       return;
    3296             :     case Intrinsic::aarch64_neon_tbl4:
    3297           2 :       SelectTable(Node, 4, VT == MVT::v8i8 ? AArch64::TBLv8i8Four
    3298             :                                            : AArch64::TBLv16i8Four,
    3299             :                   false);
    3300           2 :       return;
    3301             :     case Intrinsic::aarch64_neon_tbx2:
    3302           2 :       SelectTable(Node, 2,
    3303             :                   VT == MVT::v8i8 ? AArch64::TBXv8i8Two : AArch64::TBXv16i8Two,
    3304             :                   true);
    3305           2 :       return;
    3306             :     case Intrinsic::aarch64_neon_tbx3:
    3307           2 :       SelectTable(Node, 3, VT == MVT::v8i8 ? AArch64::TBXv8i8Three
    3308             :                                            : AArch64::TBXv16i8Three,
    3309             :                   true);
    3310           2 :       return;
    3311             :     case Intrinsic::aarch64_neon_tbx4:
    3312           2 :       SelectTable(Node, 4, VT == MVT::v8i8 ? AArch64::TBXv8i8Four
    3313             :                                            : AArch64::TBXv16i8Four,
    3314             :                   true);
    3315           2 :       return;
    3316         146 :     case Intrinsic::aarch64_neon_smull:
    3317             :     case Intrinsic::aarch64_neon_umull:
    3318         146 :       if (tryMULLV64LaneV128(IntNo, Node))
    3319             :         return;
    3320             :       break;
    3321             :     }
    3322             :     break;
    3323             :   }
    3324         217 :   case ISD::INTRINSIC_VOID: {
    3325         651 :     unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
    3326         217 :     if (Node->getNumOperands() >= 3)
    3327         199 :       VT = Node->getOperand(2)->getValueType(0);
    3328         217 :     switch (IntNo) {
    3329             :     default:
    3330             :       break;
    3331             :     case Intrinsic::aarch64_neon_st1x2: {
    3332             :       if (VT == MVT::v8i8) {
    3333           2 :         SelectStore(Node, 2, AArch64::ST1Twov8b);
    3334           2 :         return;
    3335             :       } else if (VT == MVT::v16i8) {
    3336           2 :         SelectStore(Node, 2, AArch64::ST1Twov16b);
    3337           2 :         return;
    3338             :       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3339           3 :         SelectStore(Node, 2, AArch64::ST1Twov4h);
    3340           3 :         return;
    3341             :       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3342           3 :         SelectStore(Node, 2, AArch64::ST1Twov8h);
    3343           3 :         return;
    3344             :       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3345           4 :         SelectStore(Node, 2, AArch64::ST1Twov2s);
    3346           4 :         return;
    3347             :       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3348           4 :         SelectStore(Node, 2, AArch64::ST1Twov4s);
    3349           4 :         return;
    3350             :       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3351           4 :         SelectStore(Node, 2, AArch64::ST1Twov2d);
    3352           4 :         return;
    3353             :       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3354           4 :         SelectStore(Node, 2, AArch64::ST1Twov1d);
    3355           4 :         return;
    3356             :       }
    3357             :       break;
    3358             :     }
    3359             :     case Intrinsic::aarch64_neon_st1x3: {
    3360             :       if (VT == MVT::v8i8) {
    3361           2 :         SelectStore(Node, 3, AArch64::ST1Threev8b);
    3362           2 :         return;
    3363             :       } else if (VT == MVT::v16i8) {
    3364           2 :         SelectStore(Node, 3, AArch64::ST1Threev16b);
    3365           2 :         return;
    3366             :       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3367           3 :         SelectStore(Node, 3, AArch64::ST1Threev4h);
    3368           3 :         return;
    3369             :       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3370           3 :         SelectStore(Node, 3, AArch64::ST1Threev8h);
    3371           3 :         return;
    3372             :       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3373           4 :         SelectStore(Node, 3, AArch64::ST1Threev2s);
    3374           4 :         return;
    3375             :       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3376           4 :         SelectStore(Node, 3, AArch64::ST1Threev4s);
    3377           4 :         return;
    3378             :       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3379           4 :         SelectStore(Node, 3, AArch64::ST1Threev2d);
    3380           4 :         return;
    3381             :       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3382           4 :         SelectStore(Node, 3, AArch64::ST1Threev1d);
    3383           4 :         return;
    3384             :       }
    3385             :       break;
    3386             :     }
    3387             :     case Intrinsic::aarch64_neon_st1x4: {
    3388             :       if (VT == MVT::v8i8) {
    3389           2 :         SelectStore(Node, 4, AArch64::ST1Fourv8b);
    3390           2 :         return;
    3391             :       } else if (VT == MVT::v16i8) {
    3392           2 :         SelectStore(Node, 4, AArch64::ST1Fourv16b);
    3393           2 :         return;
    3394             :       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3395           3 :         SelectStore(Node, 4, AArch64::ST1Fourv4h);
    3396           3 :         return;
    3397             :       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3398           3 :         SelectStore(Node, 4, AArch64::ST1Fourv8h);
    3399           3 :         return;
    3400             :       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3401           4 :         SelectStore(Node, 4, AArch64::ST1Fourv2s);
    3402           4 :         return;
    3403             :       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3404           4 :         SelectStore(Node, 4, AArch64::ST1Fourv4s);
    3405           4 :         return;
    3406             :       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3407           4 :         SelectStore(Node, 4, AArch64::ST1Fourv2d);
    3408           4 :         return;
    3409             :       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3410           4 :         SelectStore(Node, 4, AArch64::ST1Fourv1d);
    3411           4 :         return;
    3412             :       }
    3413             :       break;
    3414             :     }
    3415             :     case Intrinsic::aarch64_neon_st2: {
    3416             :       if (VT == MVT::v8i8) {
    3417          10 :         SelectStore(Node, 2, AArch64::ST2Twov8b);
    3418          10 :         return;
    3419             :       } else if (VT == MVT::v16i8) {
    3420           2 :         SelectStore(Node, 2, AArch64::ST2Twov16b);
    3421           2 :         return;
    3422             :       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3423           3 :         SelectStore(Node, 2, AArch64::ST2Twov4h);
    3424           3 :         return;
    3425             :       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3426           3 :         SelectStore(Node, 2, AArch64::ST2Twov8h);
    3427           3 :         return;
    3428             :       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3429           2 :         SelectStore(Node, 2, AArch64::ST2Twov2s);
    3430           2 :         return;
    3431             :       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3432           4 :         SelectStore(Node, 2, AArch64::ST2Twov4s);
    3433           4 :         return;
    3434             :       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3435           2 :         SelectStore(Node, 2, AArch64::ST2Twov2d);
    3436           2 :         return;
    3437             :       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3438           3 :         SelectStore(Node, 2, AArch64::ST1Twov1d);
    3439           3 :         return;
    3440             :       }
    3441             :       break;
    3442             :     }
    3443             :     case Intrinsic::aarch64_neon_st3: {
    3444             :       if (VT == MVT::v8i8) {
    3445           4 :         SelectStore(Node, 3, AArch64::ST3Threev8b);
    3446           4 :         return;
    3447             :       } else if (VT == MVT::v16i8) {
    3448           4 :         SelectStore(Node, 3, AArch64::ST3Threev16b);
    3449           4 :         return;
    3450             :       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3451           3 :         SelectStore(Node, 3, AArch64::ST3Threev4h);
    3452           3 :         return;
    3453             :       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3454           3 :         SelectStore(Node, 3, AArch64::ST3Threev8h);
    3455           3 :         return;
    3456             :       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3457           2 :         SelectStore(Node, 3, AArch64::ST3Threev2s);
    3458           2 :         return;
    3459             :       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3460           2 :         SelectStore(Node, 3, AArch64::ST3Threev4s);
    3461           2 :         return;
    3462             :       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3463           2 :         SelectStore(Node, 3, AArch64::ST3Threev2d);
    3464           2 :         return;
    3465             :       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3466           2 :         SelectStore(Node, 3, AArch64::ST1Threev1d);
    3467           2 :         return;
    3468             :       }
    3469             :       break;
    3470             :     }
    3471             :     case Intrinsic::aarch64_neon_st4: {
    3472             :       if (VT == MVT::v8i8) {
    3473           2 :         SelectStore(Node, 4, AArch64::ST4Fourv8b);
    3474           2 :         return;
    3475             :       } else if (VT == MVT::v16i8) {
    3476           4 :         SelectStore(Node, 4, AArch64::ST4Fourv16b);
    3477           4 :         return;
    3478             :       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3479           3 :         SelectStore(Node, 4, AArch64::ST4Fourv4h);
    3480           3 :         return;
    3481             :       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3482           3 :         SelectStore(Node, 4, AArch64::ST4Fourv8h);
    3483           3 :         return;
    3484             :       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3485           2 :         SelectStore(Node, 4, AArch64::ST4Fourv2s);
    3486           2 :         return;
    3487             :       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3488           2 :         SelectStore(Node, 4, AArch64::ST4Fourv4s);
    3489           2 :         return;
    3490             :       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3491           2 :         SelectStore(Node, 4, AArch64::ST4Fourv2d);
    3492           2 :         return;
    3493             :       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3494           2 :         SelectStore(Node, 4, AArch64::ST1Fourv1d);
    3495           2 :         return;
    3496             :       }
    3497             :       break;
    3498             :     }
    3499             :     case Intrinsic::aarch64_neon_st2lane: {
    3500             :       if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    3501           2 :         SelectStoreLane(Node, 2, AArch64::ST2i8);
    3502           2 :         return;
    3503             :       } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
    3504             :                  VT == MVT::v8f16) {
    3505           4 :         SelectStoreLane(Node, 2, AArch64::ST2i16);
    3506           4 :         return;
    3507             :       } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
    3508             :                  VT == MVT::v2f32) {
    3509           2 :         SelectStoreLane(Node, 2, AArch64::ST2i32);
    3510           2 :         return;
    3511             :       } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
    3512             :                  VT == MVT::v1f64) {
    3513           5 :         SelectStoreLane(Node, 2, AArch64::ST2i64);
    3514           5 :         return;
    3515             :       }
    3516             :       break;
    3517             :     }
    3518             :     case Intrinsic::aarch64_neon_st3lane: {
    3519             :       if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    3520           2 :         SelectStoreLane(Node, 3, AArch64::ST3i8);
    3521           2 :         return;
    3522             :       } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
    3523             :                  VT == MVT::v8f16) {
    3524           4 :         SelectStoreLane(Node, 3, AArch64::ST3i16);
    3525           4 :         return;
    3526             :       } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
    3527             :                  VT == MVT::v2f32) {
    3528           2 :         SelectStoreLane(Node, 3, AArch64::ST3i32);
    3529           2 :         return;
    3530             :       } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
    3531             :                  VT == MVT::v1f64) {
    3532           3 :         SelectStoreLane(Node, 3, AArch64::ST3i64);
    3533           3 :         return;
    3534             :       }
    3535             :       break;
    3536             :     }
    3537             :     case Intrinsic::aarch64_neon_st4lane: {
    3538             :       if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    3539           2 :         SelectStoreLane(Node, 4, AArch64::ST4i8);
    3540           2 :         return;
    3541             :       } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
    3542             :                  VT == MVT::v8f16) {
    3543           4 :         SelectStoreLane(Node, 4, AArch64::ST4i16);
    3544           4 :         return;
    3545             :       } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
    3546             :                  VT == MVT::v2f32) {
    3547           2 :         SelectStoreLane(Node, 4, AArch64::ST4i32);
    3548           2 :         return;
    3549             :       } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
    3550             :                  VT == MVT::v1f64) {
    3551           3 :         SelectStoreLane(Node, 4, AArch64::ST4i64);
    3552           3 :         return;
    3553             :       }
    3554             :       break;
    3555             :     }
    3556             :     }
    3557             :     break;
    3558             :   }
    3559             :   case AArch64ISD::LD2post: {
    3560             :     if (VT == MVT::v8i8) {
    3561           2 :       SelectPostLoad(Node, 2, AArch64::LD2Twov8b_POST, AArch64::dsub0);
    3562           2 :       return;
    3563             :     } else if (VT == MVT::v16i8) {
    3564           2 :       SelectPostLoad(Node, 2, AArch64::LD2Twov16b_POST, AArch64::qsub0);
    3565           2 :       return;
    3566             :     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3567           2 :       SelectPostLoad(Node, 2, AArch64::LD2Twov4h_POST, AArch64::dsub0);
    3568           2 :       return;
    3569             :     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3570           2 :       SelectPostLoad(Node, 2, AArch64::LD2Twov8h_POST, AArch64::qsub0);
    3571           2 :       return;
    3572             :     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3573           4 :       SelectPostLoad(Node, 2, AArch64::LD2Twov2s_POST, AArch64::dsub0);
    3574           4 :       return;
    3575             :     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3576           4 :       SelectPostLoad(Node, 2, AArch64::LD2Twov4s_POST, AArch64::qsub0);
    3577           4 :       return;
    3578             :     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3579           4 :       SelectPostLoad(Node, 2, AArch64::LD1Twov1d_POST, AArch64::dsub0);
    3580           4 :       return;
    3581             :     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3582           4 :       SelectPostLoad(Node, 2, AArch64::LD2Twov2d_POST, AArch64::qsub0);
    3583           4 :       return;
    3584             :     }
    3585             :     break;
    3586             :   }
    3587             :   case AArch64ISD::LD3post: {
    3588             :     if (VT == MVT::v8i8) {
    3589           2 :       SelectPostLoad(Node, 3, AArch64::LD3Threev8b_POST, AArch64::dsub0);
    3590           2 :       return;
    3591             :     } else if (VT == MVT::v16i8) {
    3592           2 :       SelectPostLoad(Node, 3, AArch64::LD3Threev16b_POST, AArch64::qsub0);
    3593           2 :       return;
    3594             :     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3595           2 :       SelectPostLoad(Node, 3, AArch64::LD3Threev4h_POST, AArch64::dsub0);
    3596           2 :       return;
    3597             :     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3598           2 :       SelectPostLoad(Node, 3, AArch64::LD3Threev8h_POST, AArch64::qsub0);
    3599           2 :       return;
    3600             :     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3601           4 :       SelectPostLoad(Node, 3, AArch64::LD3Threev2s_POST, AArch64::dsub0);
    3602           4 :       return;
    3603             :     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3604           4 :       SelectPostLoad(Node, 3, AArch64::LD3Threev4s_POST, AArch64::qsub0);
    3605           4 :       return;
    3606             :     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3607           4 :       SelectPostLoad(Node, 3, AArch64::LD1Threev1d_POST, AArch64::dsub0);
    3608           4 :       return;
    3609             :     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3610           4 :       SelectPostLoad(Node, 3, AArch64::LD3Threev2d_POST, AArch64::qsub0);
    3611           4 :       return;
    3612             :     }
    3613             :     break;
    3614             :   }
    3615             :   case AArch64ISD::LD4post: {
    3616             :     if (VT == MVT::v8i8) {
    3617           2 :       SelectPostLoad(Node, 4, AArch64::LD4Fourv8b_POST, AArch64::dsub0);
    3618           2 :       return;
    3619             :     } else if (VT == MVT::v16i8) {
    3620           2 :       SelectPostLoad(Node, 4, AArch64::LD4Fourv16b_POST, AArch64::qsub0);
    3621           2 :       return;
    3622             :     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3623           2 :       SelectPostLoad(Node, 4, AArch64::LD4Fourv4h_POST, AArch64::dsub0);
    3624           2 :       return;
    3625             :     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3626           2 :       SelectPostLoad(Node, 4, AArch64::LD4Fourv8h_POST, AArch64::qsub0);
    3627           2 :       return;
    3628             :     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3629           4 :       SelectPostLoad(Node, 4, AArch64::LD4Fourv2s_POST, AArch64::dsub0);
    3630           4 :       return;
    3631             :     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3632           4 :       SelectPostLoad(Node, 4, AArch64::LD4Fourv4s_POST, AArch64::qsub0);
    3633           4 :       return;
    3634             :     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3635           4 :       SelectPostLoad(Node, 4, AArch64::LD1Fourv1d_POST, AArch64::dsub0);
    3636           4 :       return;
    3637             :     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3638           4 :       SelectPostLoad(Node, 4, AArch64::LD4Fourv2d_POST, AArch64::qsub0);
    3639           4 :       return;
    3640             :     }
    3641             :     break;
    3642             :   }
    3643             :   case AArch64ISD::LD1x2post: {
    3644             :     if (VT == MVT::v8i8) {
    3645           2 :       SelectPostLoad(Node, 2, AArch64::LD1Twov8b_POST, AArch64::dsub0);
    3646           2 :       return;
    3647             :     } else if (VT == MVT::v16i8) {
    3648           2 :       SelectPostLoad(Node, 2, AArch64::LD1Twov16b_POST, AArch64::qsub0);
    3649           2 :       return;
    3650             :     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3651           2 :       SelectPostLoad(Node, 2, AArch64::LD1Twov4h_POST, AArch64::dsub0);
    3652           2 :       return;
    3653             :     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3654           2 :       SelectPostLoad(Node, 2, AArch64::LD1Twov8h_POST, AArch64::qsub0);
    3655           2 :       return;
    3656             :     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3657           4 :       SelectPostLoad(Node, 2, AArch64::LD1Twov2s_POST, AArch64::dsub0);
    3658           4 :       return;
    3659             :     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3660           4 :       SelectPostLoad(Node, 2, AArch64::LD1Twov4s_POST, AArch64::qsub0);
    3661           4 :       return;
    3662             :     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3663           4 :       SelectPostLoad(Node, 2, AArch64::LD1Twov1d_POST, AArch64::dsub0);
    3664           4 :       return;
    3665             :     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3666           4 :       SelectPostLoad(Node, 2, AArch64::LD1Twov2d_POST, AArch64::qsub0);
    3667           4 :       return;
    3668             :     }
    3669             :     break;
    3670             :   }
    3671             :   case AArch64ISD::LD1x3post: {
    3672             :     if (VT == MVT::v8i8) {
    3673           2 :       SelectPostLoad(Node, 3, AArch64::LD1Threev8b_POST, AArch64::dsub0);
    3674           2 :       return;
    3675             :     } else if (VT == MVT::v16i8) {
    3676           2 :       SelectPostLoad(Node, 3, AArch64::LD1Threev16b_POST, AArch64::qsub0);
    3677           2 :       return;
    3678             :     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3679           2 :       SelectPostLoad(Node, 3, AArch64::LD1Threev4h_POST, AArch64::dsub0);
    3680           2 :       return;
    3681             :     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3682           2 :       SelectPostLoad(Node, 3, AArch64::LD1Threev8h_POST, AArch64::qsub0);
    3683           2 :       return;
    3684             :     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3685           4 :       SelectPostLoad(Node, 3, AArch64::LD1Threev2s_POST, AArch64::dsub0);
    3686           4 :       return;
    3687             :     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3688           4 :       SelectPostLoad(Node, 3, AArch64::LD1Threev4s_POST, AArch64::qsub0);
    3689           4 :       return;
    3690             :     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3691           4 :       SelectPostLoad(Node, 3, AArch64::LD1Threev1d_POST, AArch64::dsub0);
    3692           4 :       return;
    3693             :     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3694           4 :       SelectPostLoad(Node, 3, AArch64::LD1Threev2d_POST, AArch64::qsub0);
    3695           4 :       return;
    3696             :     }
    3697             :     break;
    3698             :   }
    3699             :   case AArch64ISD::LD1x4post: {
    3700             :     if (VT == MVT::v8i8) {
    3701           2 :       SelectPostLoad(Node, 4, AArch64::LD1Fourv8b_POST, AArch64::dsub0);
    3702           2 :       return;
    3703             :     } else if (VT == MVT::v16i8) {
    3704           2 :       SelectPostLoad(Node, 4, AArch64::LD1Fourv16b_POST, AArch64::qsub0);
    3705           2 :       return;
    3706             :     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3707           2 :       SelectPostLoad(Node, 4, AArch64::LD1Fourv4h_POST, AArch64::dsub0);
    3708           2 :       return;
    3709             :     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3710           2 :       SelectPostLoad(Node, 4, AArch64::LD1Fourv8h_POST, AArch64::qsub0);
    3711           2 :       return;
    3712             :     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3713           4 :       SelectPostLoad(Node, 4, AArch64::LD1Fourv2s_POST, AArch64::dsub0);
    3714           4 :       return;
    3715             :     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3716           4 :       SelectPostLoad(Node, 4, AArch64::LD1Fourv4s_POST, AArch64::qsub0);
    3717           4 :       return;
    3718             :     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3719           4 :       SelectPostLoad(Node, 4, AArch64::LD1Fourv1d_POST, AArch64::dsub0);
    3720           4 :       return;
    3721             :     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3722           4 :       SelectPostLoad(Node, 4, AArch64::LD1Fourv2d_POST, AArch64::qsub0);
    3723           4 :       return;
    3724             :     }
    3725             :     break;
    3726             :   }
    3727             :   case AArch64ISD::LD1DUPpost: {
    3728             :     if (VT == MVT::v8i8) {
    3729           2 :       SelectPostLoad(Node, 1, AArch64::LD1Rv8b_POST, AArch64::dsub0);
    3730           2 :       return;
    3731             :     } else if (VT == MVT::v16i8) {
    3732           2 :       SelectPostLoad(Node, 1, AArch64::LD1Rv16b_POST, AArch64::qsub0);
    3733           2 :       return;
    3734             :     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3735           2 :       SelectPostLoad(Node, 1, AArch64::LD1Rv4h_POST, AArch64::dsub0);
    3736           2 :       return;
    3737             :     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3738           2 :       SelectPostLoad(Node, 1, AArch64::LD1Rv8h_POST, AArch64::qsub0);
    3739           2 :       return;
    3740             :     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3741           4 :       SelectPostLoad(Node, 1, AArch64::LD1Rv2s_POST, AArch64::dsub0);
    3742           4 :       return;
    3743             :     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3744           4 :       SelectPostLoad(Node, 1, AArch64::LD1Rv4s_POST, AArch64::qsub0);
    3745           4 :       return;
    3746             :     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3747           0 :       SelectPostLoad(Node, 1, AArch64::LD1Rv1d_POST, AArch64::dsub0);
    3748           0 :       return;
    3749             :     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3750           4 :       SelectPostLoad(Node, 1, AArch64::LD1Rv2d_POST, AArch64::qsub0);
    3751           4 :       return;
    3752             :     }
    3753             :     break;
    3754             :   }
    3755             :   case AArch64ISD::LD2DUPpost: {
    3756             :     if (VT == MVT::v8i8) {
    3757           2 :       SelectPostLoad(Node, 2, AArch64::LD2Rv8b_POST, AArch64::dsub0);
    3758           2 :       return;
    3759             :     } else if (VT == MVT::v16i8) {
    3760           2 :       SelectPostLoad(Node, 2, AArch64::LD2Rv16b_POST, AArch64::qsub0);
    3761           2 :       return;
    3762             :     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3763           2 :       SelectPostLoad(Node, 2, AArch64::LD2Rv4h_POST, AArch64::dsub0);
    3764           2 :       return;
    3765             :     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3766           2 :       SelectPostLoad(Node, 2, AArch64::LD2Rv8h_POST, AArch64::qsub0);
    3767           2 :       return;
    3768             :     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3769           4 :       SelectPostLoad(Node, 2, AArch64::LD2Rv2s_POST, AArch64::dsub0);
    3770           4 :       return;
    3771             :     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3772           4 :       SelectPostLoad(Node, 2, AArch64::LD2Rv4s_POST, AArch64::qsub0);
    3773           4 :       return;
    3774             :     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3775           4 :       SelectPostLoad(Node, 2, AArch64::LD2Rv1d_POST, AArch64::dsub0);
    3776           4 :       return;
    3777             :     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3778           4 :       SelectPostLoad(Node, 2, AArch64::LD2Rv2d_POST, AArch64::qsub0);
    3779           4 :       return;
    3780             :     }
    3781             :     break;
    3782             :   }
    3783             :   case AArch64ISD::LD3DUPpost: {
    3784             :     if (VT == MVT::v8i8) {
    3785           2 :       SelectPostLoad(Node, 3, AArch64::LD3Rv8b_POST, AArch64::dsub0);
    3786           2 :       return;
    3787             :     } else if (VT == MVT::v16i8) {
    3788           2 :       SelectPostLoad(Node, 3, AArch64::LD3Rv16b_POST, AArch64::qsub0);
    3789           2 :       return;
    3790             :     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3791           2 :       SelectPostLoad(Node, 3, AArch64::LD3Rv4h_POST, AArch64::dsub0);
    3792           2 :       return;
    3793             :     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3794           2 :       SelectPostLoad(Node, 3, AArch64::LD3Rv8h_POST, AArch64::qsub0);
    3795           2 :       return;
    3796             :     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3797           4 :       SelectPostLoad(Node, 3, AArch64::LD3Rv2s_POST, AArch64::dsub0);
    3798           4 :       return;
    3799             :     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3800           4 :       SelectPostLoad(Node, 3, AArch64::LD3Rv4s_POST, AArch64::qsub0);
    3801           4 :       return;
    3802             :     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3803           4 :       SelectPostLoad(Node, 3, AArch64::LD3Rv1d_POST, AArch64::dsub0);
    3804           4 :       return;
    3805             :     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3806           4 :       SelectPostLoad(Node, 3, AArch64::LD3Rv2d_POST, AArch64::qsub0);
    3807           4 :       return;
    3808             :     }
    3809             :     break;
    3810             :   }
    3811             :   case AArch64ISD::LD4DUPpost: {
    3812             :     if (VT == MVT::v8i8) {
    3813           2 :       SelectPostLoad(Node, 4, AArch64::LD4Rv8b_POST, AArch64::dsub0);
    3814           2 :       return;
    3815             :     } else if (VT == MVT::v16i8) {
    3816           2 :       SelectPostLoad(Node, 4, AArch64::LD4Rv16b_POST, AArch64::qsub0);
    3817           2 :       return;
    3818             :     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3819           2 :       SelectPostLoad(Node, 4, AArch64::LD4Rv4h_POST, AArch64::dsub0);
    3820           2 :       return;
    3821             :     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3822           2 :       SelectPostLoad(Node, 4, AArch64::LD4Rv8h_POST, AArch64::qsub0);
    3823           2 :       return;
    3824             :     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3825           4 :       SelectPostLoad(Node, 4, AArch64::LD4Rv2s_POST, AArch64::dsub0);
    3826           4 :       return;
    3827             :     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3828           4 :       SelectPostLoad(Node, 4, AArch64::LD4Rv4s_POST, AArch64::qsub0);
    3829           4 :       return;
    3830             :     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3831           4 :       SelectPostLoad(Node, 4, AArch64::LD4Rv1d_POST, AArch64::dsub0);
    3832           4 :       return;
    3833             :     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3834           4 :       SelectPostLoad(Node, 4, AArch64::LD4Rv2d_POST, AArch64::qsub0);
    3835           4 :       return;
    3836             :     }
    3837             :     break;
    3838             :   }
    3839             :   case AArch64ISD::LD1LANEpost: {
    3840             :     if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    3841           4 :       SelectPostLoadLane(Node, 1, AArch64::LD1i8_POST);
    3842           4 :       return;
    3843             :     } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
    3844             :                VT == MVT::v8f16) {
    3845           5 :       SelectPostLoadLane(Node, 1, AArch64::LD1i16_POST);
    3846           5 :       return;
    3847             :     } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
    3848             :                VT == MVT::v2f32) {
    3849           8 :       SelectPostLoadLane(Node, 1, AArch64::LD1i32_POST);
    3850           8 :       return;
    3851             :     } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
    3852             :                VT == MVT::v1f64) {
    3853           5 :       SelectPostLoadLane(Node, 1, AArch64::LD1i64_POST);
    3854           5 :       return;
    3855             :     }
    3856             :     break;
    3857             :   }
    3858             :   case AArch64ISD::LD2LANEpost: {
    3859             :     if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    3860           4 :       SelectPostLoadLane(Node, 2, AArch64::LD2i8_POST);
    3861           4 :       return;
    3862             :     } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
    3863             :                VT == MVT::v8f16) {
    3864           4 :       SelectPostLoadLane(Node, 2, AArch64::LD2i16_POST);
    3865           4 :       return;
    3866             :     } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
    3867             :                VT == MVT::v2f32) {
    3868           8 :       SelectPostLoadLane(Node, 2, AArch64::LD2i32_POST);
    3869           8 :       return;
    3870             :     } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
    3871             :                VT == MVT::v1f64) {
    3872           8 :       SelectPostLoadLane(Node, 2, AArch64::LD2i64_POST);
    3873           8 :       return;
    3874             :     }
    3875             :     break;
    3876             :   }
    3877             :   case AArch64ISD::LD3LANEpost: {
    3878             :     if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    3879           4 :       SelectPostLoadLane(Node, 3, AArch64::LD3i8_POST);
    3880           4 :       return;
    3881             :     } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
    3882             :                VT == MVT::v8f16) {
    3883           4 :       SelectPostLoadLane(Node, 3, AArch64::LD3i16_POST);
    3884           4 :       return;
    3885             :     } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
    3886             :                VT == MVT::v2f32) {
    3887           8 :       SelectPostLoadLane(Node, 3, AArch64::LD3i32_POST);
    3888           8 :       return;
    3889             :     } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
    3890             :                VT == MVT::v1f64) {
    3891           8 :       SelectPostLoadLane(Node, 3, AArch64::LD3i64_POST);
    3892           8 :       return;
    3893             :     }
    3894             :     break;
    3895             :   }
    3896             :   case AArch64ISD::LD4LANEpost: {
    3897             :     if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    3898           4 :       SelectPostLoadLane(Node, 4, AArch64::LD4i8_POST);
    3899           4 :       return;
    3900             :     } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
    3901             :                VT == MVT::v8f16) {
    3902           4 :       SelectPostLoadLane(Node, 4, AArch64::LD4i16_POST);
    3903           4 :       return;
    3904             :     } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
    3905             :                VT == MVT::v2f32) {
    3906           8 :       SelectPostLoadLane(Node, 4, AArch64::LD4i32_POST);
    3907           8 :       return;
    3908             :     } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
    3909             :                VT == MVT::v1f64) {
    3910           8 :       SelectPostLoadLane(Node, 4, AArch64::LD4i64_POST);
    3911           8 :       return;
    3912             :     }
    3913             :     break;
    3914             :   }
    3915          24 :   case AArch64ISD::ST2post: {
    3916          24 :     VT = Node->getOperand(1).getValueType();
    3917             :     if (VT == MVT::v8i8) {
    3918           2 :       SelectPostStore(Node, 2, AArch64::ST2Twov8b_POST);
    3919           2 :       return;
    3920             :     } else if (VT == MVT::v16i8) {
    3921           2 :       SelectPostStore(Node, 2, AArch64::ST2Twov16b_POST);
    3922           2 :       return;
    3923             :     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3924           2 :       SelectPostStore(Node, 2, AArch64::ST2Twov4h_POST);
    3925           2 :       return;
    3926             :     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3927           2 :       SelectPostStore(Node, 2, AArch64::ST2Twov8h_POST);
    3928           2 :       return;
    3929             :     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3930           4 :       SelectPostStore(Node, 2, AArch64::ST2Twov2s_POST);
    3931           4 :       return;
    3932             :     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3933           4 :       SelectPostStore(Node, 2, AArch64::ST2Twov4s_POST);
    3934           4 :       return;
    3935             :     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3936           4 :       SelectPostStore(Node, 2, AArch64::ST2Twov2d_POST);
    3937           4 :       return;
    3938             :     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3939           4 :       SelectPostStore(Node, 2, AArch64::ST1Twov1d_POST);
    3940           4 :       return;
    3941             :     }
    3942             :     break;
    3943             :   }
    3944          24 :   case AArch64ISD::ST3post: {
    3945          24 :     VT = Node->getOperand(1).getValueType();
    3946             :     if (VT == MVT::v8i8) {
    3947           2 :       SelectPostStore(Node, 3, AArch64::ST3Threev8b_POST);
    3948           2 :       return;
    3949             :     } else if (VT == MVT::v16i8) {
    3950           2 :       SelectPostStore(Node, 3, AArch64::ST3Threev16b_POST);
    3951           2 :       return;
    3952             :     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3953           2 :       SelectPostStore(Node, 3, AArch64::ST3Threev4h_POST);
    3954           2 :       return;
    3955             :     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3956           2 :       SelectPostStore(Node, 3, AArch64::ST3Threev8h_POST);
    3957           2 :       return;
    3958             :     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3959           4 :       SelectPostStore(Node, 3, AArch64::ST3Threev2s_POST);
    3960           4 :       return;
    3961             :     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3962           4 :       SelectPostStore(Node, 3, AArch64::ST3Threev4s_POST);
    3963           4 :       return;
    3964             :     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3965           4 :       SelectPostStore(Node, 3, AArch64::ST3Threev2d_POST);
    3966           4 :       return;
    3967             :     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3968           4 :       SelectPostStore(Node, 3, AArch64::ST1Threev1d_POST);
    3969           4 :       return;
    3970             :     }
    3971             :     break;
    3972             :   }
    3973          24 :   case AArch64ISD::ST4post: {
    3974          24 :     VT = Node->getOperand(1).getValueType();
    3975             :     if (VT == MVT::v8i8) {
    3976           2 :       SelectPostStore(Node, 4, AArch64::ST4Fourv8b_POST);
    3977           2 :       return;
    3978             :     } else if (VT == MVT::v16i8) {
    3979           2 :       SelectPostStore(Node, 4, AArch64::ST4Fourv16b_POST);
    3980           2 :       return;
    3981             :     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    3982           2 :       SelectPostStore(Node, 4, AArch64::ST4Fourv4h_POST);
    3983           2 :       return;
    3984             :     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    3985           2 :       SelectPostStore(Node, 4, AArch64::ST4Fourv8h_POST);
    3986           2 :       return;
    3987             :     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    3988           4 :       SelectPostStore(Node, 4, AArch64::ST4Fourv2s_POST);
    3989           4 :       return;
    3990             :     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    3991           4 :       SelectPostStore(Node, 4, AArch64::ST4Fourv4s_POST);
    3992           4 :       return;
    3993             :     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    3994           4 :       SelectPostStore(Node, 4, AArch64::ST4Fourv2d_POST);
    3995           4 :       return;
    3996             :     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    3997           4 :       SelectPostStore(Node, 4, AArch64::ST1Fourv1d_POST);
    3998           4 :       return;
    3999             :     }
    4000             :     break;
    4001             :   }
    4002          24 :   case AArch64ISD::ST1x2post: {
    4003          24 :     VT = Node->getOperand(1).getValueType();
    4004             :     if (VT == MVT::v8i8) {
    4005           2 :       SelectPostStore(Node, 2, AArch64::ST1Twov8b_POST);
    4006           2 :       return;
    4007             :     } else if (VT == MVT::v16i8) {
    4008           2 :       SelectPostStore(Node, 2, AArch64::ST1Twov16b_POST);
    4009           2 :       return;
    4010             :     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    4011           2 :       SelectPostStore(Node, 2, AArch64::ST1Twov4h_POST);
    4012           2 :       return;
    4013             :     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    4014           2 :       SelectPostStore(Node, 2, AArch64::ST1Twov8h_POST);
    4015           2 :       return;
    4016             :     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    4017           4 :       SelectPostStore(Node, 2, AArch64::ST1Twov2s_POST);
    4018           4 :       return;
    4019             :     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    4020           4 :       SelectPostStore(Node, 2, AArch64::ST1Twov4s_POST);
    4021           4 :       return;
    4022             :     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    4023           4 :       SelectPostStore(Node, 2, AArch64::ST1Twov1d_POST);
    4024           4 :       return;
    4025             :     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    4026           4 :       SelectPostStore(Node, 2, AArch64::ST1Twov2d_POST);
    4027           4 :       return;
    4028             :     }
    4029             :     break;
    4030             :   }
    4031          24 :   case AArch64ISD::ST1x3post: {
    4032          24 :     VT = Node->getOperand(1).getValueType();
    4033             :     if (VT == MVT::v8i8) {
    4034           2 :       SelectPostStore(Node, 3, AArch64::ST1Threev8b_POST);
    4035           2 :       return;
    4036             :     } else if (VT == MVT::v16i8) {
    4037           2 :       SelectPostStore(Node, 3, AArch64::ST1Threev16b_POST);
    4038           2 :       return;
    4039             :     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    4040           2 :       SelectPostStore(Node, 3, AArch64::ST1Threev4h_POST);
    4041           2 :       return;
    4042             :     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    4043           2 :       SelectPostStore(Node, 3, AArch64::ST1Threev8h_POST);
    4044           2 :       return;
    4045             :     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    4046           4 :       SelectPostStore(Node, 3, AArch64::ST1Threev2s_POST);
    4047           4 :       return;
    4048             :     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    4049           4 :       SelectPostStore(Node, 3, AArch64::ST1Threev4s_POST);
    4050           4 :       return;
    4051             :     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    4052           4 :       SelectPostStore(Node, 3, AArch64::ST1Threev1d_POST);
    4053           4 :       return;
    4054             :     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    4055           4 :       SelectPostStore(Node, 3, AArch64::ST1Threev2d_POST);
    4056           4 :       return;
    4057             :     }
    4058             :     break;
    4059             :   }
    4060          24 :   case AArch64ISD::ST1x4post: {
    4061          24 :     VT = Node->getOperand(1).getValueType();
    4062             :     if (VT == MVT::v8i8) {
    4063           2 :       SelectPostStore(Node, 4, AArch64::ST1Fourv8b_POST);
    4064           2 :       return;
    4065             :     } else if (VT == MVT::v16i8) {
    4066           2 :       SelectPostStore(Node, 4, AArch64::ST1Fourv16b_POST);
    4067           2 :       return;
    4068             :     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
    4069           2 :       SelectPostStore(Node, 4, AArch64::ST1Fourv4h_POST);
    4070           2 :       return;
    4071             :     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
    4072           2 :       SelectPostStore(Node, 4, AArch64::ST1Fourv8h_POST);
    4073           2 :       return;
    4074             :     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
    4075           4 :       SelectPostStore(Node, 4, AArch64::ST1Fourv2s_POST);
    4076           4 :       return;
    4077             :     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
    4078           4 :       SelectPostStore(Node, 4, AArch64::ST1Fourv4s_POST);
    4079           4 :       return;
    4080             :     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
    4081           4 :       SelectPostStore(Node, 4, AArch64::ST1Fourv1d_POST);
    4082           4 :       return;
    4083             :     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
    4084           4 :       SelectPostStore(Node, 4, AArch64::ST1Fourv2d_POST);
    4085           4 :       return;
    4086             :     }
    4087             :     break;
    4088             :   }
    4089          24 :   case AArch64ISD::ST2LANEpost: {
    4090          24 :     VT = Node->getOperand(1).getValueType();
    4091             :     if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    4092           4 :       SelectPostStoreLane(Node, 2, AArch64::ST2i8_POST);
    4093           4 :       return;
    4094             :     } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
    4095             :                VT == MVT::v8f16) {
    4096           4 :       SelectPostStoreLane(Node, 2, AArch64::ST2i16_POST);
    4097           4 :       return;
    4098             :     } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
    4099             :                VT == MVT::v2f32) {
    4100           8 :       SelectPostStoreLane(Node, 2, AArch64::ST2i32_POST);
    4101           8 :       return;
    4102             :     } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
    4103             :                VT == MVT::v1f64) {
    4104           8 :       SelectPostStoreLane(Node, 2, AArch64::ST2i64_POST);
    4105           8 :       return;
    4106             :     }
    4107             :     break;
    4108             :   }
    4109          24 :   case AArch64ISD::ST3LANEpost: {
    4110          24 :     VT = Node->getOperand(1).getValueType();
    4111             :     if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    4112           4 :       SelectPostStoreLane(Node, 3, AArch64::ST3i8_POST);
    4113           4 :       return;
    4114             :     } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
    4115             :                VT == MVT::v8f16) {
    4116           4 :       SelectPostStoreLane(Node, 3, AArch64::ST3i16_POST);
    4117           4 :       return;
    4118             :     } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
    4119             :                VT == MVT::v2f32) {
    4120           8 :       SelectPostStoreLane(Node, 3, AArch64::ST3i32_POST);
    4121           8 :       return;
    4122             :     } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
    4123             :                VT == MVT::v1f64) {
    4124           8 :       SelectPostStoreLane(Node, 3, AArch64::ST3i64_POST);
    4125           8 :       return;
    4126             :     }
    4127             :     break;
    4128             :   }
    4129          24 :   case AArch64ISD::ST4LANEpost: {
    4130          24 :     VT = Node->getOperand(1).getValueType();
    4131             :     if (VT == MVT::v16i8 || VT == MVT::v8i8) {
    4132           4 :       SelectPostStoreLane(Node, 4, AArch64::ST4i8_POST);
    4133           4 :       return;
    4134             :     } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
    4135             :                VT == MVT::v8f16) {
    4136           4 :       SelectPostStoreLane(Node, 4, AArch64::ST4i16_POST);
    4137           4 :       return;
    4138             :     } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
    4139             :                VT == MVT::v2f32) {
    4140           8 :       SelectPostStoreLane(Node, 4, AArch64::ST4i32_POST);
    4141           8 :       return;
    4142             :     } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
    4143             :                VT == MVT::v1f64) {
    4144           8 :       SelectPostStoreLane(Node, 4, AArch64::ST4i64_POST);
    4145           8 :       return;
    4146             :     }
    4147             :     break;
    4148             :   }
    4149             :   }
    4150             : 
    4151             :   // Select the default instruction
    4152             :   SelectCode(Node);
    4153             : }
    4154             : 
    4155             : /// createAArch64ISelDag - This pass converts a legalized DAG into a
    4156             : /// AArch64-specific DAG, ready for instruction scheduling.
    4157        1118 : FunctionPass *llvm::createAArch64ISelDag(AArch64TargetMachine &TM,
    4158             :                                          CodeGenOpt::Level OptLevel) {
    4159        2236 :   return new AArch64DAGToDAGISel(TM, OptLevel);
    4160             : }

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