LCOV - code coverage report
Current view: top level - lib/Target/AArch64 - AArch64RedundantCopyElimination.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 176 178 98.9 %
Date: 2017-09-14 15:23:50 Functions: 12 12 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //=- AArch64RedundantCopyElimination.cpp - Remove useless copy for AArch64 -=//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : // This pass removes unnecessary copies/moves in BBs based on a dominating
       9             : // condition.
      10             : //
      11             : // We handle three cases:
      12             : // 1. For BBs that are targets of CBZ/CBNZ instructions, we know the value of
      13             : //    the CBZ/CBNZ source register is zero on the taken/not-taken path. For
      14             : //    instance, the copy instruction in the code below can be removed because
      15             : //    the CBZW jumps to BB#2 when w0 is zero.
      16             : //
      17             : //  BB#1:
      18             : //    cbz w0, .LBB0_2
      19             : //  .LBB0_2:
      20             : //    mov w0, wzr  ; <-- redundant
      21             : //
      22             : // 2. If the flag setting instruction defines a register other than WZR/XZR, we
      23             : //    can remove a zero copy in some cases.
      24             : //
      25             : //  BB#0:
      26             : //    subs w0, w1, w2
      27             : //    str w0, [x1]
      28             : //    b.ne .LBB0_2
      29             : //  BB#1:
      30             : //    mov w0, wzr  ; <-- redundant
      31             : //    str w0, [x2]
      32             : //  .LBB0_2
      33             : //
      34             : // 3. Finally, if the flag setting instruction is a comparison against a
      35             : //    constant (i.e., ADDS[W|X]ri, SUBS[W|X]ri), we can remove a mov immediate
      36             : //    in some cases.
      37             : //
      38             : //  BB#0:
      39             : //    subs xzr, x0, #1
      40             : //    b.eq .LBB0_1
      41             : //  .LBB0_1:
      42             : //    orr x0, xzr, #0x1  ; <-- redundant
      43             : //
      44             : // This pass should be run after register allocation.
      45             : //
      46             : // FIXME: This could also be extended to check the whole dominance subtree below
      47             : // the comparison if the compile time regression is acceptable.
      48             : //
      49             : // FIXME: Add support for handling CCMP instructions.
      50             : // FIXME: If the known register value is zero, we should be able to rewrite uses
      51             : //        to use WZR/XZR directly in some cases.
      52             : //===----------------------------------------------------------------------===//
      53             : #include "AArch64.h"
      54             : #include "llvm/ADT/Optional.h"
      55             : #include "llvm/ADT/SetVector.h"
      56             : #include "llvm/ADT/Statistic.h"
      57             : #include "llvm/ADT/iterator_range.h"
      58             : #include "llvm/CodeGen/MachineFunctionPass.h"
      59             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      60             : #include "llvm/Support/Debug.h"
      61             : 
      62             : using namespace llvm;
      63             : 
      64             : #define DEBUG_TYPE "aarch64-copyelim"
      65             : 
      66             : STATISTIC(NumCopiesRemoved, "Number of copies removed.");
      67             : 
      68             : namespace {
      69        3636 : class AArch64RedundantCopyElimination : public MachineFunctionPass {
      70             :   const MachineRegisterInfo *MRI;
      71             :   const TargetRegisterInfo *TRI;
      72             : 
      73             :   // DomBBClobberedRegs is used when computing known values in the dominating
      74             :   // BB.
      75             :   BitVector DomBBClobberedRegs;
      76             : 
      77             :   // OptBBClobberedRegs is used when optimizing away redundant copies/moves.
      78             :   BitVector OptBBClobberedRegs;
      79             : 
      80             : public:
      81             :   static char ID;
      82        2748 :   AArch64RedundantCopyElimination() : MachineFunctionPass(ID) {
      83         916 :     initializeAArch64RedundantCopyEliminationPass(
      84         916 :         *PassRegistry::getPassRegistry());
      85         916 :   }
      86             : 
      87             :   struct RegImm {
      88             :     MCPhysReg Reg;
      89             :     int32_t Imm;
      90         378 :     RegImm(MCPhysReg Reg, int32_t Imm) : Reg(Reg), Imm(Imm) {}
      91             :   };
      92             : 
      93             :   bool knownRegValInBlock(MachineInstr &CondBr, MachineBasicBlock *MBB,
      94             :                           SmallVectorImpl<RegImm> &KnownRegs,
      95             :                           MachineBasicBlock::iterator &FirstUse);
      96             :   bool optimizeBlock(MachineBasicBlock *MBB);
      97             :   bool runOnMachineFunction(MachineFunction &MF) override;
      98         907 :   MachineFunctionProperties getRequiredProperties() const override {
      99        2721 :     return MachineFunctionProperties().set(
     100        2721 :         MachineFunctionProperties::Property::NoVRegs);
     101             :   }
     102         913 :   StringRef getPassName() const override {
     103         913 :     return "AArch64 Redundant Copy Elimination";
     104             :   }
     105             : };
     106             : char AArch64RedundantCopyElimination::ID = 0;
     107             : }
     108             : 
     109      315301 : INITIALIZE_PASS(AArch64RedundantCopyElimination, "aarch64-copyelim",
     110             :                 "AArch64 redundant copy elimination pass", false, false)
     111             : 
     112             : /// Remember what registers the specified instruction modifies.
     113         809 : static void trackRegDefs(const MachineInstr &MI, BitVector &ClobberedRegs,
     114             :                          const TargetRegisterInfo *TRI) {
     115        3473 :   for (const MachineOperand &MO : MI.operands()) {
     116        2675 :     if (MO.isRegMask()) {
     117          22 :       ClobberedRegs.setBitsNotInMask(MO.getRegMask());
     118          11 :       continue;
     119             :     }
     120             : 
     121        2653 :     if (!MO.isReg())
     122         882 :       continue;
     123        1771 :     unsigned Reg = MO.getReg();
     124        1771 :     if (!Reg)
     125           0 :       continue;
     126        1771 :     if (!MO.isDef())
     127        1220 :       continue;
     128             : 
     129       11950 :     for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
     130       10848 :       ClobberedRegs.set(*AI);
     131             :   }
     132         809 : }
     133             : 
     134             : /// It's possible to determine the value of a register based on a dominating
     135             : /// condition.  To do so, this function checks to see if the basic block \p MBB
     136             : /// is the target of a conditional branch \p CondBr with an equality comparison.
     137             : /// If the branch is a CBZ/CBNZ, we know the value of its source operand is zero
     138             : /// in \p MBB for some cases.  Otherwise, we find and inspect the NZCV setting
     139             : /// instruction (e.g., SUBS, ADDS).  If this instruction defines a register
     140             : /// other than WZR/XZR, we know the value of the destination register is zero in
     141             : /// \p MMB for some cases.  In addition, if the NZCV setting instruction is
     142             : /// comparing against a constant we know the other source register is equal to
     143             : /// the constant in \p MBB for some cases.  If we find any constant values, push
     144             : /// a physical register and constant value pair onto the KnownRegs vector and
     145             : /// return true.  Otherwise, return false if no known values were found.
     146        3156 : bool AArch64RedundantCopyElimination::knownRegValInBlock(
     147             :     MachineInstr &CondBr, MachineBasicBlock *MBB,
     148             :     SmallVectorImpl<RegImm> &KnownRegs, MachineBasicBlock::iterator &FirstUse) {
     149        6312 :   unsigned Opc = CondBr.getOpcode();
     150             : 
     151             :   // Check if the current basic block is the target block to which the
     152             :   // CBZ/CBNZ instruction jumps when its Wt/Xt is zero.
     153        3267 :   if (((Opc == AArch64::CBZW || Opc == AArch64::CBZX) &&
     154        6265 :        MBB == CondBr.getOperand(1).getMBB()) ||
     155        3342 :       ((Opc == AArch64::CBNZW || Opc == AArch64::CBNZX) &&
     156         233 :        MBB != CondBr.getOperand(1).getMBB())) {
     157         228 :     FirstUse = CondBr;
     158         456 :     KnownRegs.push_back(RegImm(CondBr.getOperand(0).getReg(), 0));
     159         228 :     return true;
     160             :   }
     161             : 
     162             :   // Otherwise, must be a conditional branch.
     163        2928 :   if (Opc != AArch64::Bcc)
     164             :     return false;
     165             : 
     166             :   // Must be an equality check (i.e., == or !=).
     167         748 :   AArch64CC::CondCode CC = (AArch64CC::CondCode)CondBr.getOperand(0).getImm();
     168         748 :   if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
     169             :     return false;
     170             : 
     171         368 :   MachineBasicBlock *BrTarget = CondBr.getOperand(1).getMBB();
     172         659 :   if ((CC == AArch64CC::EQ && BrTarget != MBB) ||
     173         291 :       (CC == AArch64CC::NE && BrTarget == MBB))
     174             :     return false;
     175             : 
     176             :   // Stop if we get to the beginning of PredMBB.
     177         240 :   MachineBasicBlock *PredMBB = *MBB->pred_begin();
     178             :   assert(PredMBB == CondBr.getParent() &&
     179             :          "Conditional branch not in predecessor block!");
     180         480 :   if (CondBr == PredMBB->begin())
     181             :     return false;
     182             : 
     183             :   // Registers clobbered in PredMBB between CondBr instruction and current
     184             :   // instruction being checked in loop.
     185         480 :   DomBBClobberedRegs.reset();
     186             : 
     187             :   // Find compare instruction that sets NZCV used by CondBr.
     188         720 :   MachineBasicBlock::reverse_iterator RIt = CondBr.getReverseIterator();
     189        1486 :   for (MachineInstr &PredI : make_range(std::next(RIt), PredMBB->rend())) {
     190             : 
     191         383 :     bool IsCMN = false;
     192         383 :     switch (PredI.getOpcode()) {
     193             :     default:
     194             :       break;
     195             : 
     196             :     // CMN is an alias for ADDS with a dead destination register.
     197             :     case AArch64::ADDSWri:
     198             :     case AArch64::ADDSXri:
     199             :       IsCMN = true;
     200             :       LLVM_FALLTHROUGH;
     201             :     // CMP is an alias for SUBS with a dead destination register.
     202         107 :     case AArch64::SUBSWri:
     203             :     case AArch64::SUBSXri: {
     204         107 :       MCPhysReg DstReg = PredI.getOperand(0).getReg();
     205         107 :       MCPhysReg SrcReg = PredI.getOperand(1).getReg();
     206             : 
     207         107 :       bool Res = false;
     208             :       // If we're comparing against a non-symbolic immediate and the source
     209             :       // register of the compare is not modified (including a self-clobbering
     210             :       // compare) between the compare and conditional branch we known the value
     211             :       // of the 1st source operand.
     212         428 :       if (PredI.getOperand(2).isImm() && !DomBBClobberedRegs[SrcReg] &&
     213             :           SrcReg != DstReg) {
     214             :         // We've found the instruction that sets NZCV.
     215          61 :         int32_t KnownImm = PredI.getOperand(2).getImm();
     216          61 :         int32_t Shift = PredI.getOperand(3).getImm();
     217          61 :         KnownImm <<= Shift;
     218          61 :         if (IsCMN)
     219           5 :           KnownImm = -KnownImm;
     220          61 :         FirstUse = PredI;
     221         122 :         KnownRegs.push_back(RegImm(SrcReg, KnownImm));
     222          61 :         Res = true;
     223             :       }
     224             : 
     225             :       // If this instructions defines something other than WZR/XZR, we know it's
     226             :       // result is zero in some cases.
     227         107 :       if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
     228         240 :         return Res;
     229             : 
     230             :       // The destination register must not be modified between the NZCV setting
     231             :       // instruction and the conditional branch.
     232         141 :       if (DomBBClobberedRegs[DstReg])
     233             :         return Res;
     234             : 
     235          47 :       FirstUse = PredI;
     236          94 :       KnownRegs.push_back(RegImm(DstReg, 0));
     237          47 :       return true;
     238             :     }
     239             : 
     240             :     // Look for NZCV setting instructions that define something other than
     241             :     // WZR/XZR.
     242         111 :     case AArch64::ADCSWr:
     243             :     case AArch64::ADCSXr:
     244             :     case AArch64::ADDSWrr:
     245             :     case AArch64::ADDSWrs:
     246             :     case AArch64::ADDSWrx:
     247             :     case AArch64::ADDSXrr:
     248             :     case AArch64::ADDSXrs:
     249             :     case AArch64::ADDSXrx:
     250             :     case AArch64::ADDSXrx64:
     251             :     case AArch64::ANDSWri:
     252             :     case AArch64::ANDSWrr:
     253             :     case AArch64::ANDSWrs:
     254             :     case AArch64::ANDSXri:
     255             :     case AArch64::ANDSXrr:
     256             :     case AArch64::ANDSXrs:
     257             :     case AArch64::BICSWrr:
     258             :     case AArch64::BICSWrs:
     259             :     case AArch64::BICSXrs:
     260             :     case AArch64::BICSXrr:
     261             :     case AArch64::SBCSWr:
     262             :     case AArch64::SBCSXr:
     263             :     case AArch64::SUBSWrr:
     264             :     case AArch64::SUBSWrs:
     265             :     case AArch64::SUBSWrx:
     266             :     case AArch64::SUBSXrr:
     267             :     case AArch64::SUBSXrs:
     268             :     case AArch64::SUBSXrx:
     269             :     case AArch64::SUBSXrx64: {
     270         111 :       MCPhysReg DstReg = PredI.getOperand(0).getReg();
     271         111 :       if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
     272             :         return false;
     273             : 
     274             :       // The destination register of the NZCV setting instruction must not be
     275             :       // modified before the conditional branch.
     276          54 :       if (DomBBClobberedRegs[DstReg])
     277             :         return false;
     278             : 
     279             :       // We've found the instruction that sets NZCV whose DstReg == 0.
     280          16 :       FirstUse = PredI;
     281          32 :       KnownRegs.push_back(RegImm(DstReg, 0));
     282          16 :       return true;
     283             :     }
     284             :     }
     285             : 
     286             :     // Bail if we see an instruction that defines NZCV that we don't handle.
     287         165 :     if (PredI.definesRegister(AArch64::NZCV))
     288             :       return false;
     289             : 
     290             :     // Track clobbered registers.
     291         143 :     trackRegDefs(PredI, DomBBClobberedRegs, TRI);
     292             :   }
     293           0 :   return false;
     294             : }
     295             : 
     296       13289 : bool AArch64RedundantCopyElimination::optimizeBlock(MachineBasicBlock *MBB) {
     297             :   // Check if the current basic block has a single predecessor.
     298       13289 :   if (MBB->pred_size() != 1)
     299             :     return false;
     300             : 
     301             :   // Check if the predecessor has two successors, implying the block ends in a
     302             :   // conditional branch.
     303        1589 :   MachineBasicBlock *PredMBB = *MBB->pred_begin();
     304        1589 :   if (PredMBB->succ_size() != 2)
     305             :     return false;
     306             : 
     307        1372 :   MachineBasicBlock::iterator CondBr = PredMBB->getLastNonDebugInstr();
     308        2744 :   if (CondBr == PredMBB->end())
     309             :     return false;
     310             : 
     311             :   // Keep track of the earliest point in the PredMBB block where kill markers
     312             :   // need to be removed if a COPY is removed.
     313        1372 :   MachineBasicBlock::iterator FirstUse;
     314             :   // After calling knownRegValInBlock, FirstUse will either point to a CBZ/CBNZ
     315             :   // or a compare (i.e., SUBS).  In the latter case, we must take care when
     316             :   // updating FirstUse when scanning for COPY instructions.  In particular, if
     317             :   // there's a COPY in between the compare and branch the COPY should not
     318             :   // update FirstUse.
     319        1372 :   bool SeenFirstUse = false;
     320             :   // Registers that contain a known value at the start of MBB.
     321        1372 :   SmallVector<RegImm, 4> KnownRegs;
     322             : 
     323        1372 :   MachineBasicBlock::iterator Itr = std::next(CondBr);
     324             :   do {
     325        3156 :     --Itr;
     326             : 
     327        3156 :     if (!knownRegValInBlock(*Itr, MBB, KnownRegs, FirstUse))
     328             :       continue;
     329             : 
     330             :     // Reset the clobber list.
     331         700 :     OptBBClobberedRegs.reset();
     332             : 
     333             :     // Look backward in PredMBB for COPYs from the known reg to find other
     334             :     // registers that are known to be a constant value.
     335         350 :     for (auto PredI = Itr;; --PredI) {
     336         845 :       if (FirstUse == PredI)
     337         350 :         SeenFirstUse = true;
     338             : 
     339        1690 :       if (PredI->isCopy()) {
     340          35 :         MCPhysReg CopyDstReg = PredI->getOperand(0).getReg();
     341          35 :         MCPhysReg CopySrcReg = PredI->getOperand(1).getReg();
     342         116 :         for (auto &KnownReg : KnownRegs) {
     343         111 :           if (OptBBClobberedRegs[KnownReg.Reg])
     344           2 :             continue;
     345             :           // If we have X = COPY Y, and Y is known to be zero, then now X is
     346             :           // known to be zero.
     347          41 :           if (CopySrcReg == KnownReg.Reg && !OptBBClobberedRegs[CopyDstReg]) {
     348           4 :             KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm));
     349           2 :             if (SeenFirstUse)
     350           1 :               FirstUse = PredI;
     351             :             break;
     352             :           }
     353             :           // If we have X = COPY Y, and X is known to be zero, then now Y is
     354             :           // known to be zero.
     355         114 :           if (CopyDstReg == KnownReg.Reg && !OptBBClobberedRegs[CopySrcReg]) {
     356          48 :             KnownRegs.push_back(RegImm(CopySrcReg, KnownReg.Imm));
     357          24 :             if (SeenFirstUse)
     358          24 :               FirstUse = PredI;
     359             :             break;
     360             :           }
     361             :         }
     362             :       }
     363             : 
     364             :       // Stop if we get to the beginning of PredMBB.
     365        1690 :       if (PredI == PredMBB->begin())
     366             :         break;
     367             : 
     368        1332 :       trackRegDefs(*PredI, OptBBClobberedRegs, TRI);
     369             :       // Stop if all of the known-zero regs have been clobbered.
     370        1332 :       if (all_of(KnownRegs, [&](RegImm KnownReg) {
     371         685 :             return OptBBClobberedRegs[KnownReg.Reg];
     372         685 :           }))
     373             :         break;
     374             :     }
     375         350 :     break;
     376             : 
     377       10020 :   } while (Itr != PredMBB->begin() && Itr->isTerminator());
     378             : 
     379             :   // We've not found a registers with a known value, time to bail out.
     380        1372 :   if (KnownRegs.empty())
     381             :     return false;
     382             : 
     383         350 :   bool Changed = false;
     384             :   // UsedKnownRegs is the set of KnownRegs that have had uses added to MBB.
     385         350 :   SmallSetVector<unsigned, 4> UsedKnownRegs;
     386         350 :   MachineBasicBlock::iterator LastChange = MBB->begin();
     387             :   // Remove redundant copy/move instructions unless KnownReg is modified.
     388        1649 :   for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;) {
     389         681 :     MachineInstr *MI = &*I;
     390         681 :     ++I;
     391         681 :     bool RemovedMI = false;
     392         681 :     bool IsCopy = MI->isCopy();
     393         681 :     bool IsMoveImm = MI->isMoveImmediate();
     394         681 :     if (IsCopy || IsMoveImm) {
     395         213 :       MCPhysReg DefReg = MI->getOperand(0).getReg();
     396         213 :       MCPhysReg SrcReg = IsCopy ? MI->getOperand(1).getReg() : 0;
     397         213 :       int64_t SrcImm = IsMoveImm ? MI->getOperand(1).getImm() : 0;
     398         426 :       if (!MRI->isReserved(DefReg) &&
     399         166 :           ((IsCopy && (SrcReg == AArch64::XZR || SrcReg == AArch64::WZR)) ||
     400             :            IsMoveImm)) {
     401         416 :         for (RegImm &KnownReg : KnownRegs) {
     402         266 :           if (KnownReg.Reg != DefReg &&
     403          73 :               !TRI->isSuperRegister(DefReg, KnownReg.Reg))
     404          64 :             continue;
     405             : 
     406             :           // For a copy, the known value must be a zero.
     407         102 :           if (IsCopy && KnownReg.Imm != 0)
     408           6 :             continue;
     409             : 
     410          59 :           if (IsMoveImm) {
     411             :             // For a move immediate, the known immediate must match the source
     412             :             // immediate.
     413          28 :             if (KnownReg.Imm != SrcImm)
     414          15 :               continue;
     415             : 
     416             :             // Don't remove a move immediate that implicitly defines the upper
     417             :             // bits when only the lower 32 bits are known.
     418          13 :             MCPhysReg CmpReg = KnownReg.Reg;
     419          39 :             if (any_of(MI->implicit_operands(), [CmpReg](MachineOperand &O) {
     420           8 :                   return !O.isDead() && O.isReg() && O.isDef() &&
     421           2 :                          O.getReg() != CmpReg;
     422             :                 }))
     423           1 :               continue;
     424             :           }
     425             : 
     426             :           if (IsCopy)
     427             :             DEBUG(dbgs() << "Remove redundant Copy : " << *MI);
     428             :           else
     429             :             DEBUG(dbgs() << "Remove redundant Move : " << *MI);
     430             : 
     431          43 :           MI->eraseFromParent();
     432          43 :           Changed = true;
     433          43 :           LastChange = I;
     434          43 :           NumCopiesRemoved++;
     435          43 :           UsedKnownRegs.insert(KnownReg.Reg);
     436          43 :           RemovedMI = true;
     437             :           break;
     438             :         }
     439             :       }
     440             :     }
     441             : 
     442             :     // Skip to the next instruction if we removed the COPY/MovImm.
     443          43 :     if (RemovedMI)
     444          43 :       continue;
     445             : 
     446             :     // Remove any regs the MI clobbers from the KnownConstRegs set.
     447        2640 :     for (unsigned RI = 0; RI < KnownRegs.size();)
     448        2046 :       if (MI->modifiesRegister(KnownRegs[RI].Reg, TRI)) {
     449         360 :         std::swap(KnownRegs[RI], KnownRegs[KnownRegs.size() - 1]);
     450             :         KnownRegs.pop_back();
     451             :         // Don't increment RI since we need to now check the swapped-in
     452             :         // KnownRegs[RI].
     453             :       } else {
     454         592 :         ++RI;
     455             :       }
     456             : 
     457             :     // Continue until the KnownRegs set is empty.
     458         638 :     if (KnownRegs.empty())
     459             :       break;
     460             :   }
     461             : 
     462         350 :   if (!Changed)
     463             :     return false;
     464             : 
     465             :   // Add newly used regs to the block's live-in list if they aren't there
     466             :   // already.
     467         169 :   for (MCPhysReg KnownReg : UsedKnownRegs)
     468          43 :     if (!MBB->isLiveIn(KnownReg))
     469          42 :       MBB->addLiveIn(KnownReg);
     470             : 
     471             :   // Clear kills in the range where changes were made.  This is conservative,
     472             :   // but should be okay since kill markers are being phased out.
     473             :   DEBUG(dbgs() << "Clearing kill flags.\n\tFirstUse: " << *FirstUse
     474             :                << "\tLastChange: " << *LastChange);
     475         388 :   for (MachineInstr &MMI : make_range(FirstUse, PredMBB->end()))
     476         131 :     MMI.clearKillInfo();
     477         134 :   for (MachineInstr &MMI : make_range(MBB->begin(), LastChange))
     478           4 :     MMI.clearKillInfo();
     479             : 
     480          42 :   return true;
     481             : }
     482             : 
     483       11046 : bool AArch64RedundantCopyElimination::runOnMachineFunction(
     484             :     MachineFunction &MF) {
     485       11046 :   if (skipFunction(*MF.getFunction()))
     486             :     return false;
     487       11045 :   TRI = MF.getSubtarget().getRegisterInfo();
     488       11045 :   MRI = &MF.getRegInfo();
     489             : 
     490             :   // Resize the clobber register bitfield trackers.  We do this once per
     491             :   // function.
     492       11045 :   DomBBClobberedRegs.resize(TRI->getNumRegs());
     493       11045 :   OptBBClobberedRegs.resize(TRI->getNumRegs());
     494             : 
     495       11045 :   bool Changed = false;
     496       46424 :   for (MachineBasicBlock &MBB : MF)
     497       13289 :     Changed |= optimizeBlock(&MBB);
     498             :   return Changed;
     499             : }
     500             : 
     501         914 : FunctionPass *llvm::createAArch64RedundantCopyEliminationPass() {
     502         914 :   return new AArch64RedundantCopyElimination();
     503             : }

Generated by: LCOV version 1.13