LCOV - code coverage report
Current view: top level - lib/Target/AArch64 - AArch64RegisterInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 151 154 98.1 %
Date: 2017-09-14 15:23:50 Functions: 27 27 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains the AArch64 implementation of the TargetRegisterInfo
      11             : // class.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "AArch64RegisterInfo.h"
      16             : #include "AArch64FrameLowering.h"
      17             : #include "AArch64InstrInfo.h"
      18             : #include "AArch64MachineFunctionInfo.h"
      19             : #include "AArch64Subtarget.h"
      20             : #include "MCTargetDesc/AArch64AddressingModes.h"
      21             : #include "llvm/ADT/BitVector.h"
      22             : #include "llvm/ADT/Triple.h"
      23             : #include "llvm/CodeGen/MachineFrameInfo.h"
      24             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      25             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      26             : #include "llvm/CodeGen/RegisterScavenging.h"
      27             : #include "llvm/IR/Function.h"
      28             : #include "llvm/Support/raw_ostream.h"
      29             : #include "llvm/Target/TargetFrameLowering.h"
      30             : #include "llvm/Target/TargetOptions.h"
      31             : 
      32             : using namespace llvm;
      33             : 
      34             : #define GET_REGINFO_TARGET_DESC
      35             : #include "AArch64GenRegisterInfo.inc"
      36             : 
      37        1217 : AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
      38        1217 :     : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {
      39        1217 :   AArch64_MC::initLLVMToCVRegMapping(this);
      40        1217 : }
      41             : 
      42             : const MCPhysReg *
      43      173249 : AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
      44             :   assert(MF && "Invalid MachineFunction pointer.");
      45      346498 :   if (MF->getFunction()->getCallingConv() == CallingConv::GHC)
      46             :     // GHC set of callee saved regs is empty as all those regs are
      47             :     // used for passing STG regs around
      48             :     return CSR_AArch64_NoRegs_SaveList;
      49      346450 :   if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg)
      50             :     return CSR_AArch64_AllRegs_SaveList;
      51      346450 :   if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS)
      52         100 :     return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
      53             :            CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
      54             :            CSR_AArch64_CXX_TLS_Darwin_SaveList;
      55      346250 :   if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering()
      56      346250 :           ->supportSwiftError() &&
      57      173501 :       MF->getFunction()->getAttributes().hasAttrSomewhere(
      58             :           Attribute::SwiftError))
      59             :     return CSR_AArch64_AAPCS_SwiftError_SaveList;
      60      345498 :   if (MF->getFunction()->getCallingConv() == CallingConv::PreserveMost)
      61             :     return CSR_AArch64_RT_MostRegs_SaveList;
      62             :   else
      63      172722 :     return CSR_AArch64_AAPCS_SaveList;
      64             : }
      65             : 
      66       10579 : const MCPhysReg *AArch64RegisterInfo::getCalleeSavedRegsViaCopy(
      67             :     const MachineFunction *MF) const {
      68             :   assert(MF && "Invalid MachineFunction pointer.");
      69       21175 :   if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
      70          17 :       MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())
      71             :     return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList;
      72             :   return nullptr;
      73             : }
      74             : 
      75             : const uint32_t *
      76        2076 : AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
      77             :                                           CallingConv::ID CC) const {
      78        2076 :   if (CC == CallingConv::GHC)
      79             :     // This is academic because all GHC calls are (supposed to be) tail calls
      80             :     return CSR_AArch64_NoRegs_RegMask;
      81        2072 :   if (CC == CallingConv::AnyReg)
      82             :     return CSR_AArch64_AllRegs_RegMask;
      83        2059 :   if (CC == CallingConv::CXX_FAST_TLS)
      84             :     return CSR_AArch64_CXX_TLS_Darwin_RegMask;
      85        4106 :   if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering()
      86        4106 :           ->supportSwiftError() &&
      87        2079 :       MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
      88             :     return CSR_AArch64_AAPCS_SwiftError_RegMask;
      89        2027 :   if (CC == CallingConv::PreserveMost)
      90             :     return CSR_AArch64_RT_MostRegs_RegMask;
      91             :   else
      92        2023 :     return CSR_AArch64_AAPCS_RegMask;
      93             : }
      94             : 
      95          24 : const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const {
      96          24 :   if (TT.isOSDarwin())
      97             :     return CSR_AArch64_TLS_Darwin_RegMask;
      98             : 
      99             :   assert(TT.isOSBinFormatELF() && "Invalid target");
     100             :   return CSR_AArch64_TLS_ELF_RegMask;
     101             : }
     102             : 
     103             : const uint32_t *
     104          10 : AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
     105             :                                                 CallingConv::ID CC) const {
     106             :   // This should return a register mask that is the same as that returned by
     107             :   // getCallPreservedMask but that additionally preserves the register used for
     108             :   // the first i64 argument (which must also be the register used to return a
     109             :   // single i64 return value)
     110             :   //
     111             :   // In case that the calling convention does not use the same register for
     112             :   // both, the function should return NULL (does not currently apply)
     113             :   assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
     114          10 :   return CSR_AArch64_AAPCS_ThisReturn_RegMask;
     115             : }
     116             : 
     117             : BitVector
     118       24122 : AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
     119       24122 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     120             : 
     121             :   // FIXME: avoid re-calculating this every time.
     122       24122 :   BitVector Reserved(getNumRegs());
     123       24122 :   markSuperRegs(Reserved, AArch64::WSP);
     124       24122 :   markSuperRegs(Reserved, AArch64::WZR);
     125             : 
     126       24122 :   if (TFI->hasFP(MF) || TT.isOSDarwin())
     127        5142 :     markSuperRegs(Reserved, AArch64::W29);
     128             : 
     129       24122 :   if (MF.getSubtarget<AArch64Subtarget>().isX18Reserved())
     130        4986 :     markSuperRegs(Reserved, AArch64::W18); // Platform register
     131             : 
     132       24122 :   if (hasBasePointer(MF))
     133          24 :     markSuperRegs(Reserved, AArch64::W19);
     134             : 
     135             :   assert(checkAllSuperRegsMarked(Reserved));
     136       24122 :   return Reserved;
     137             : }
     138             : 
     139      139497 : bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
     140             :                                       unsigned Reg) const {
     141      139497 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     142             : 
     143      139497 :   switch (Reg) {
     144             :   default:
     145             :     break;
     146             :   case AArch64::SP:
     147             :   case AArch64::XZR:
     148             :   case AArch64::WSP:
     149             :   case AArch64::WZR:
     150             :     return true;
     151           0 :   case AArch64::X18:
     152             :   case AArch64::W18:
     153           0 :     return MF.getSubtarget<AArch64Subtarget>().isX18Reserved();
     154       11528 :   case AArch64::FP:
     155             :   case AArch64::W29:
     156       11528 :     return TFI->hasFP(MF) || TT.isOSDarwin();
     157       11484 :   case AArch64::W19:
     158             :   case AArch64::X19:
     159       11484 :     return hasBasePointer(MF);
     160             :   }
     161             : 
     162      116485 :   return false;
     163             : }
     164             : 
     165      102102 : bool AArch64RegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
     166      102102 :   return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
     167             : }
     168             : 
     169             : const TargetRegisterClass *
     170          24 : AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
     171             :                                       unsigned Kind) const {
     172          24 :   return &AArch64::GPR64spRegClass;
     173             : }
     174             : 
     175             : const TargetRegisterClass *
     176           3 : AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
     177           3 :   if (RC == &AArch64::CCRRegClass)
     178             :     return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
     179           0 :   return RC;
     180             : }
     181             : 
     182          43 : unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
     183             : 
     184       52148 : bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
     185       52148 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
     186             : 
     187             :   // In the presence of variable sized objects, if the fixed stack size is
     188             :   // large enough that referencing from the FP won't result in things being
     189             :   // in range relatively often, we can use a base pointer to allow access
     190             :   // from the other direction like the SP normally works.
     191             :   // Furthermore, if both variable sized objects are present, and the
     192             :   // stack needs to be dynamically re-aligned, the base pointer is the only
     193             :   // reliable way to reference the locals.
     194       52148 :   if (MFI.hasVarSizedObjects()) {
     195         262 :     if (needsStackRealignment(MF))
     196             :       return true;
     197             :     // Conservatively estimate whether the negative offset from the frame
     198             :     // pointer will be sufficient to reach. If a function has a smallish
     199             :     // frame, it's less likely to have lots of spills and callee saved
     200             :     // space, so it's all more likely to be within range of the frame pointer.
     201             :     // If it's wrong, we'll materialize the constant and still get to the
     202             :     // object; it's just suboptimal. Negative offsets use the unscaled
     203             :     // load/store instructions, which have a 9-bit signed immediate.
     204         200 :     return MFI.getLocalFrameSize() >= 256;
     205             :   }
     206             : 
     207             :   return false;
     208             : }
     209             : 
     210             : unsigned
     211        1337 : AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
     212        1337 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     213        1337 :   return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
     214             : }
     215             : 
     216       34289 : bool AArch64RegisterInfo::requiresRegisterScavenging(
     217             :     const MachineFunction &MF) const {
     218       34289 :   return true;
     219             : }
     220             : 
     221       11660 : bool AArch64RegisterInfo::requiresVirtualBaseRegisters(
     222             :     const MachineFunction &MF) const {
     223       11660 :   return true;
     224             : }
     225             : 
     226             : bool
     227         276 : AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
     228         276 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
     229             :   // AArch64FrameLowering::resolveFrameIndexReference() can always fall back
     230             :   // to the stack pointer, so only put the emergency spill slot next to the
     231             :   // FP when there's no better way to access it (SP or base pointer).
     232         276 :   return MFI.hasVarSizedObjects() && !hasBasePointer(MF);
     233             : }
     234             : 
     235       11661 : bool AArch64RegisterInfo::requiresFrameIndexScavenging(
     236             :     const MachineFunction &MF) const {
     237       11661 :   return true;
     238             : }
     239             : 
     240             : bool
     241       10663 : AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
     242       10663 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
     243       10663 :   if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack())
     244             :     return true;
     245       10663 :   return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
     246             : }
     247             : 
     248             : /// needsFrameBaseReg - Returns true if the instruction's frame index
     249             : /// reference would be better served by a base register other than FP
     250             : /// or SP. Used by LocalStackFrameAllocation to determine which frame index
     251             : /// references it should create new base registers for.
     252         986 : bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI,
     253             :                                             int64_t Offset) const {
     254        4934 :   for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
     255             :     assert(i < MI->getNumOperands() &&
     256             :            "Instr doesn't have FrameIndex operand!");
     257             : 
     258             :   // It's the load/store FI references that cause issues, as it can be difficult
     259             :   // to materialize the offset if it won't fit in the literal field. Estimate
     260             :   // based on the size of the local frame and some conservative assumptions
     261             :   // about the rest of the stack frame (note, this is pre-regalloc, so
     262             :   // we don't know everything for certain yet) whether this offset is likely
     263             :   // to be out of range of the immediate. Return true if so.
     264             : 
     265             :   // We only generate virtual base registers for loads and stores, so
     266             :   // return false for everything else.
     267         986 :   if (!MI->mayLoad() && !MI->mayStore())
     268             :     return false;
     269             : 
     270             :   // Without a virtual base register, if the function has variable sized
     271             :   // objects, all fixed-size local references will be via the frame pointer,
     272             :   // Approximate the offset and see if it's legal for the instruction.
     273             :   // Note that the incoming offset is based on the SP value at function entry,
     274             :   // so it'll be negative.
     275         846 :   MachineFunction &MF = *MI->getParent()->getParent();
     276         846 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     277         846 :   MachineFrameInfo &MFI = MF.getFrameInfo();
     278             : 
     279             :   // Estimate an offset from the frame pointer.
     280             :   // Conservatively assume all GPR callee-saved registers get pushed.
     281             :   // FP, LR, X19-X28, D8-D15. 64-bits each.
     282         846 :   int64_t FPOffset = Offset - 16 * 20;
     283             :   // Estimate an offset from the stack pointer.
     284             :   // The incoming offset is relating to the SP at the start of the function,
     285             :   // but when we access the local it'll be relative to the SP after local
     286             :   // allocation, so adjust our SP-relative offset by that allocation size.
     287         846 :   Offset += MFI.getLocalFrameSize();
     288             :   // Assume that we'll have at least some spill slots allocated.
     289             :   // FIXME: This is a total SWAG number. We should run some statistics
     290             :   //        and pick a real one.
     291         846 :   Offset += 128; // 128 bytes of spill slots
     292             : 
     293             :   // If there is a frame pointer, try using it.
     294             :   // The FP is only available if there is no dynamic realignment. We
     295             :   // don't know for sure yet whether we'll need that, so we guess based
     296             :   // on whether there are any local variables that would trigger it.
     297         846 :   if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
     298             :     return false;
     299             : 
     300             :   // If we can reference via the stack pointer or base pointer, try that.
     301             :   // FIXME: This (and the code that resolves the references) can be improved
     302             :   //        to only disallow SP relative references in the live range of
     303             :   //        the VLA(s). In practice, it's unclear how much difference that
     304             :   //        would make, but it may be worth doing.
     305         846 :   if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
     306             :     return false;
     307             : 
     308             :   // The offset likely isn't legal; we want to allocate a virtual base register.
     309           4 :   return true;
     310             : }
     311             : 
     312        1021 : bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
     313             :                                              unsigned BaseReg,
     314             :                                              int64_t Offset) const {
     315             :   assert(Offset <= INT_MAX && "Offset too big to fit in int.");
     316             :   assert(MI && "Unable to get the legal offset for nil instruction.");
     317        1021 :   int SaveOffset = Offset;
     318        1021 :   return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
     319             : }
     320             : 
     321             : /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
     322             : /// at the beginning of the basic block.
     323           1 : void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
     324             :                                                        unsigned BaseReg,
     325             :                                                        int FrameIdx,
     326             :                                                        int64_t Offset) const {
     327           1 :   MachineBasicBlock::iterator Ins = MBB->begin();
     328           2 :   DebugLoc DL; // Defaults to "unknown"
     329           2 :   if (Ins != MBB->end())
     330           1 :     DL = Ins->getDebugLoc();
     331           1 :   const MachineFunction &MF = *MBB->getParent();
     332             :   const AArch64InstrInfo *TII =
     333           1 :       MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
     334           2 :   const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
     335           1 :   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
     336           1 :   MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
     337           1 :   unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
     338             : 
     339           2 :   BuildMI(*MBB, Ins, DL, MCID, BaseReg)
     340           1 :       .addFrameIndex(FrameIdx)
     341           1 :       .addImm(Offset)
     342           2 :       .addImm(Shifter);
     343           1 : }
     344             : 
     345           2 : void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
     346             :                                             int64_t Offset) const {
     347           2 :   int Off = Offset; // ARM doesn't need the general 64-bit offsets
     348           2 :   unsigned i = 0;
     349             : 
     350          14 :   while (!MI.getOperand(i).isFI()) {
     351           2 :     ++i;
     352             :     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
     353             :   }
     354           2 :   const MachineFunction *MF = MI.getParent()->getParent();
     355             :   const AArch64InstrInfo *TII =
     356           4 :       MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
     357           2 :   bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
     358             :   assert(Done && "Unable to resolve frame index!");
     359             :   (void)Done;
     360           2 : }
     361             : 
     362        3179 : void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
     363             :                                               int SPAdj, unsigned FIOperandNum,
     364             :                                               RegScavenger *RS) const {
     365             :   assert(SPAdj == 0 && "Unexpected");
     366             : 
     367        3179 :   MachineInstr &MI = *II;
     368        3179 :   MachineBasicBlock &MBB = *MI.getParent();
     369        3179 :   MachineFunction &MF = *MBB.getParent();
     370             :   const AArch64InstrInfo *TII =
     371        6358 :       MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
     372        3179 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     373             : 
     374        6358 :   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
     375             :   unsigned FrameReg;
     376             :   int Offset;
     377             : 
     378             :   // Special handling of dbg_value, stackmap and patchpoint instructions.
     379        6358 :   if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
     380             :       MI.getOpcode() == TargetOpcode::PATCHPOINT) {
     381          29 :     Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
     382             :                                              /*PreferFP=*/true);
     383          58 :     Offset += MI.getOperand(FIOperandNum + 1).getImm();
     384          58 :     MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
     385          58 :     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
     386          29 :     return;
     387             :   }
     388             : 
     389             :   // Modify MI as necessary to handle as much of 'Offset' as possible
     390        3150 :   Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
     391        3150 :   if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
     392             :     return;
     393             : 
     394             :   assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
     395             :          "Emergency spill slot is out of reach");
     396             : 
     397             :   // If we get here, the immediate doesn't fit into the instruction.  We folded
     398             :   // as much as possible above.  Handle the rest, providing a register that is
     399             :   // SP+LargeImm.
     400             :   unsigned ScratchReg =
     401          22 :       MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
     402          44 :   emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
     403          44 :   MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
     404             : }
     405             : 
     406         810 : unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
     407             :                                                   MachineFunction &MF) const {
     408         810 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     409             : 
     410        1620 :   switch (RC->getID()) {
     411             :   default:
     412             :     return 0;
     413         120 :   case AArch64::GPR32RegClassID:
     414             :   case AArch64::GPR32spRegClassID:
     415             :   case AArch64::GPR32allRegClassID:
     416             :   case AArch64::GPR64spRegClassID:
     417             :   case AArch64::GPR64allRegClassID:
     418             :   case AArch64::GPR64RegClassID:
     419             :   case AArch64::GPR32commonRegClassID:
     420             :   case AArch64::GPR64commonRegClassID:
     421             :     return 32 - 1                                   // XZR/SP
     422         240 :               - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
     423         240 :               - MF.getSubtarget<AArch64Subtarget>()
     424         120 :                     .isX18Reserved() // X18 reserved as platform register
     425         120 :               - hasBasePointer(MF);  // X19
     426          75 :   case AArch64::FPR8RegClassID:
     427             :   case AArch64::FPR16RegClassID:
     428             :   case AArch64::FPR32RegClassID:
     429             :   case AArch64::FPR64RegClassID:
     430             :   case AArch64::FPR128RegClassID:
     431          75 :     return 32;
     432             : 
     433          90 :   case AArch64::DDRegClassID:
     434             :   case AArch64::DDDRegClassID:
     435             :   case AArch64::DDDDRegClassID:
     436             :   case AArch64::QQRegClassID:
     437             :   case AArch64::QQQRegClassID:
     438             :   case AArch64::QQQQRegClassID:
     439          90 :     return 32;
     440             : 
     441          15 :   case AArch64::FPR128_loRegClassID:
     442          15 :     return 16;
     443             :   }
     444      216918 : }

Generated by: LCOV version 1.13