LCOV - code coverage report
Current view: top level - lib/Target/AArch64 - AArch64RegisterInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 144 147 98.0 %
Date: 2018-02-23 05:02:05 Functions: 26 26 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains the AArch64 implementation of the TargetRegisterInfo
      11             : // class.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "AArch64RegisterInfo.h"
      16             : #include "AArch64FrameLowering.h"
      17             : #include "AArch64InstrInfo.h"
      18             : #include "AArch64MachineFunctionInfo.h"
      19             : #include "AArch64Subtarget.h"
      20             : #include "MCTargetDesc/AArch64AddressingModes.h"
      21             : #include "llvm/ADT/BitVector.h"
      22             : #include "llvm/ADT/Triple.h"
      23             : #include "llvm/CodeGen/MachineFrameInfo.h"
      24             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      25             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      26             : #include "llvm/CodeGen/RegisterScavenging.h"
      27             : #include "llvm/IR/Function.h"
      28             : #include "llvm/Support/raw_ostream.h"
      29             : #include "llvm/CodeGen/TargetFrameLowering.h"
      30             : #include "llvm/Target/TargetOptions.h"
      31             : 
      32             : using namespace llvm;
      33             : 
      34             : #define GET_REGINFO_TARGET_DESC
      35             : #include "AArch64GenRegisterInfo.inc"
      36             : 
      37        1325 : AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
      38        1325 :     : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {
      39        1325 :   AArch64_MC::initLLVMToCVRegMapping(this);
      40        1325 : }
      41             : 
      42             : const MCPhysReg *
      43      201314 : AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
      44             :   assert(MF && "Invalid MachineFunction pointer.");
      45      402628 :   if (MF->getFunction().getCallingConv() == CallingConv::GHC)
      46             :     // GHC set of callee saved regs is empty as all those regs are
      47             :     // used for passing STG regs around
      48             :     return CSR_AArch64_NoRegs_SaveList;
      49      201290 :   if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)
      50             :     return CSR_AArch64_AllRegs_SaveList;
      51      201290 :   if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS)
      52         100 :     return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
      53             :            CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
      54             :            CSR_AArch64_CXX_TLS_Darwin_SaveList;
      55      201190 :   if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering()
      56      402380 :           ->supportSwiftError() &&
      57      201575 :       MF->getFunction().getAttributes().hasAttrSomewhere(
      58             :           Attribute::SwiftError))
      59             :     return CSR_AArch64_AAPCS_SwiftError_SaveList;
      60      401610 :   if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost)
      61             :     return CSR_AArch64_RT_MostRegs_SaveList;
      62             :   else
      63      200778 :     return CSR_AArch64_AAPCS_SaveList;
      64             : }
      65             : 
      66       12219 : const MCPhysReg *AArch64RegisterInfo::getCalleeSavedRegsViaCopy(
      67             :     const MachineFunction *MF) const {
      68             :   assert(MF && "Invalid MachineFunction pointer.");
      69       24455 :   if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
      70          17 :       MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())
      71             :     return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList;
      72             :   return nullptr;
      73             : }
      74             : 
      75             : const uint32_t *
      76        2209 : AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
      77             :                                           CallingConv::ID CC) const {
      78        2209 :   if (CC == CallingConv::GHC)
      79             :     // This is academic because all GHC calls are (supposed to be) tail calls
      80             :     return CSR_AArch64_NoRegs_RegMask;
      81        2205 :   if (CC == CallingConv::AnyReg)
      82             :     return CSR_AArch64_AllRegs_RegMask;
      83        2192 :   if (CC == CallingConv::CXX_FAST_TLS)
      84             :     return CSR_AArch64_CXX_TLS_Darwin_RegMask;
      85        2186 :   if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering()
      86        4372 :           ->supportSwiftError() &&
      87        2213 :       MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
      88             :     return CSR_AArch64_AAPCS_SwiftError_RegMask;
      89        2159 :   if (CC == CallingConv::PreserveMost)
      90             :     return CSR_AArch64_RT_MostRegs_RegMask;
      91             :   else
      92        2155 :     return CSR_AArch64_AAPCS_RegMask;
      93             : }
      94             : 
      95          24 : const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const {
      96          24 :   if (TT.isOSDarwin())
      97             :     return CSR_AArch64_TLS_Darwin_RegMask;
      98             : 
      99             :   assert(TT.isOSBinFormatELF() && "Invalid target");
     100             :   return CSR_AArch64_TLS_ELF_RegMask;
     101             : }
     102             : 
     103             : const uint32_t *
     104          10 : AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
     105             :                                                 CallingConv::ID CC) const {
     106             :   // This should return a register mask that is the same as that returned by
     107             :   // getCallPreservedMask but that additionally preserves the register used for
     108             :   // the first i64 argument (which must also be the register used to return a
     109             :   // single i64 return value)
     110             :   //
     111             :   // In case that the calling convention does not use the same register for
     112             :   // both, the function should return NULL (does not currently apply)
     113             :   assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
     114          10 :   return CSR_AArch64_AAPCS_ThisReturn_RegMask;
     115             : }
     116             : 
     117           3 : const uint32_t *AArch64RegisterInfo::getWindowsStackProbePreservedMask() const {
     118           3 :   return CSR_AArch64_StackProbe_Windows_RegMask;
     119             : }
     120             : 
     121             : BitVector
     122       27656 : AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
     123       27656 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     124             : 
     125             :   // FIXME: avoid re-calculating this every time.
     126       27656 :   BitVector Reserved(getNumRegs());
     127       27656 :   markSuperRegs(Reserved, AArch64::WSP);
     128       27656 :   markSuperRegs(Reserved, AArch64::WZR);
     129             : 
     130       27656 :   if (TFI->hasFP(MF) || TT.isOSDarwin())
     131        5919 :     markSuperRegs(Reserved, AArch64::W29);
     132             : 
     133       27656 :   if (MF.getSubtarget<AArch64Subtarget>().isX18Reserved())
     134        5087 :     markSuperRegs(Reserved, AArch64::W18); // Platform register
     135             : 
     136       27656 :   if (hasBasePointer(MF))
     137          24 :     markSuperRegs(Reserved, AArch64::W19);
     138             : 
     139             :   assert(checkAllSuperRegsMarked(Reserved));
     140       27656 :   return Reserved;
     141             : }
     142             : 
     143      159802 : bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
     144             :                                       unsigned Reg) const {
     145      159802 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     146             : 
     147      159802 :   switch (Reg) {
     148             :   default:
     149             :     break;
     150             :   case AArch64::SP:
     151             :   case AArch64::XZR:
     152             :   case AArch64::WSP:
     153             :   case AArch64::WZR:
     154             :     return true;
     155           0 :   case AArch64::X18:
     156             :   case AArch64::W18:
     157           0 :     return MF.getSubtarget<AArch64Subtarget>().isX18Reserved();
     158       13220 :   case AArch64::FP:
     159             :   case AArch64::W29:
     160       13220 :     return TFI->hasFP(MF) || TT.isOSDarwin();
     161       13177 :   case AArch64::W19:
     162             :   case AArch64::X19:
     163       13177 :     return hasBasePointer(MF);
     164             :   }
     165             : 
     166      133405 :   return false;
     167             : }
     168             : 
     169      115423 : bool AArch64RegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
     170      115423 :   return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
     171             : }
     172             : 
     173             : const TargetRegisterClass *
     174          24 : AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
     175             :                                       unsigned Kind) const {
     176          24 :   return &AArch64::GPR64spRegClass;
     177             : }
     178             : 
     179             : const TargetRegisterClass *
     180           3 : AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
     181           3 :   if (RC == &AArch64::CCRRegClass)
     182             :     return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
     183           0 :   return RC;
     184             : }
     185             : 
     186          43 : unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
     187             : 
     188       59102 : bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
     189       59102 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
     190             : 
     191             :   // In the presence of variable sized objects, if the fixed stack size is
     192             :   // large enough that referencing from the FP won't result in things being
     193             :   // in range relatively often, we can use a base pointer to allow access
     194             :   // from the other direction like the SP normally works.
     195             :   // Furthermore, if both variable sized objects are present, and the
     196             :   // stack needs to be dynamically re-aligned, the base pointer is the only
     197             :   // reliable way to reference the locals.
     198       59102 :   if (MFI.hasVarSizedObjects()) {
     199         237 :     if (needsStackRealignment(MF))
     200             :       return true;
     201             :     // Conservatively estimate whether the negative offset from the frame
     202             :     // pointer will be sufficient to reach. If a function has a smallish
     203             :     // frame, it's less likely to have lots of spills and callee saved
     204             :     // space, so it's all more likely to be within range of the frame pointer.
     205             :     // If it's wrong, we'll materialize the constant and still get to the
     206             :     // object; it's just suboptimal. Negative offsets use the unscaled
     207             :     // load/store instructions, which have a 9-bit signed immediate.
     208         185 :     return MFI.getLocalFrameSize() >= 256;
     209             :   }
     210             : 
     211             :   return false;
     212             : }
     213             : 
     214             : unsigned
     215        1401 : AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
     216        1401 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     217        1401 :   return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
     218             : }
     219             : 
     220       39298 : bool AArch64RegisterInfo::requiresRegisterScavenging(
     221             :     const MachineFunction &MF) const {
     222       39298 :   return true;
     223             : }
     224             : 
     225       13336 : bool AArch64RegisterInfo::requiresVirtualBaseRegisters(
     226             :     const MachineFunction &MF) const {
     227       13336 :   return true;
     228             : }
     229             : 
     230             : bool
     231         279 : AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
     232             :   // This function indicates whether the emergency spillslot should be placed
     233             :   // close to the beginning of the stackframe (closer to FP) or the end
     234             :   // (closer to SP).
     235             :   //
     236             :   // The beginning works most reliably if we have a frame pointer.
     237         279 :   const AArch64FrameLowering &TFI = *getFrameLowering(MF);
     238         279 :   return TFI.hasFP(MF);
     239             : }
     240             : 
     241       13337 : bool AArch64RegisterInfo::requiresFrameIndexScavenging(
     242             :     const MachineFunction &MF) const {
     243       13337 :   return true;
     244             : }
     245             : 
     246             : bool
     247       12315 : AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
     248       12315 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
     249       12315 :   if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack())
     250             :     return true;
     251       12315 :   return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
     252             : }
     253             : 
     254             : /// needsFrameBaseReg - Returns true if the instruction's frame index
     255             : /// reference would be better served by a base register other than FP
     256             : /// or SP. Used by LocalStackFrameAllocation to determine which frame index
     257             : /// references it should create new base registers for.
     258         975 : bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI,
     259             :                                             int64_t Offset) const {
     260        3904 :   for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
     261             :     assert(i < MI->getNumOperands() &&
     262             :            "Instr doesn't have FrameIndex operand!");
     263             : 
     264             :   // It's the load/store FI references that cause issues, as it can be difficult
     265             :   // to materialize the offset if it won't fit in the literal field. Estimate
     266             :   // based on the size of the local frame and some conservative assumptions
     267             :   // about the rest of the stack frame (note, this is pre-regalloc, so
     268             :   // we don't know everything for certain yet) whether this offset is likely
     269             :   // to be out of range of the immediate. Return true if so.
     270             : 
     271             :   // We only generate virtual base registers for loads and stores, so
     272             :   // return false for everything else.
     273         975 :   if (!MI->mayLoad() && !MI->mayStore())
     274             :     return false;
     275             : 
     276             :   // Without a virtual base register, if the function has variable sized
     277             :   // objects, all fixed-size local references will be via the frame pointer,
     278             :   // Approximate the offset and see if it's legal for the instruction.
     279             :   // Note that the incoming offset is based on the SP value at function entry,
     280             :   // so it'll be negative.
     281         833 :   MachineFunction &MF = *MI->getParent()->getParent();
     282         833 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     283         833 :   MachineFrameInfo &MFI = MF.getFrameInfo();
     284             : 
     285             :   // Estimate an offset from the frame pointer.
     286             :   // Conservatively assume all GPR callee-saved registers get pushed.
     287             :   // FP, LR, X19-X28, D8-D15. 64-bits each.
     288         833 :   int64_t FPOffset = Offset - 16 * 20;
     289             :   // Estimate an offset from the stack pointer.
     290             :   // The incoming offset is relating to the SP at the start of the function,
     291             :   // but when we access the local it'll be relative to the SP after local
     292             :   // allocation, so adjust our SP-relative offset by that allocation size.
     293         833 :   Offset += MFI.getLocalFrameSize();
     294             :   // Assume that we'll have at least some spill slots allocated.
     295             :   // FIXME: This is a total SWAG number. We should run some statistics
     296             :   //        and pick a real one.
     297         833 :   Offset += 128; // 128 bytes of spill slots
     298             : 
     299             :   // If there is a frame pointer, try using it.
     300             :   // The FP is only available if there is no dynamic realignment. We
     301             :   // don't know for sure yet whether we'll need that, so we guess based
     302             :   // on whether there are any local variables that would trigger it.
     303         833 :   if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
     304             :     return false;
     305             : 
     306             :   // If we can reference via the stack pointer or base pointer, try that.
     307             :   // FIXME: This (and the code that resolves the references) can be improved
     308             :   //        to only disallow SP relative references in the live range of
     309             :   //        the VLA(s). In practice, it's unclear how much difference that
     310             :   //        would make, but it may be worth doing.
     311         833 :   if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
     312             :     return false;
     313             : 
     314             :   // The offset likely isn't legal; we want to allocate a virtual base register.
     315           4 :   return true;
     316             : }
     317             : 
     318        1008 : bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
     319             :                                              unsigned BaseReg,
     320             :                                              int64_t Offset) const {
     321             :   assert(Offset <= INT_MAX && "Offset too big to fit in int.");
     322             :   assert(MI && "Unable to get the legal offset for nil instruction.");
     323        1008 :   int SaveOffset = Offset;
     324        1008 :   return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
     325             : }
     326             : 
     327             : /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
     328             : /// at the beginning of the basic block.
     329           1 : void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
     330             :                                                        unsigned BaseReg,
     331             :                                                        int FrameIdx,
     332             :                                                        int64_t Offset) const {
     333             :   MachineBasicBlock::iterator Ins = MBB->begin();
     334           1 :   DebugLoc DL; // Defaults to "unknown"
     335           1 :   if (Ins != MBB->end())
     336             :     DL = Ins->getDebugLoc();
     337           1 :   const MachineFunction &MF = *MBB->getParent();
     338             :   const AArch64InstrInfo *TII =
     339           1 :       MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
     340           1 :   const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
     341           1 :   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
     342           1 :   MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
     343             :   unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
     344             : 
     345           1 :   BuildMI(*MBB, Ins, DL, MCID, BaseReg)
     346             :       .addFrameIndex(FrameIdx)
     347             :       .addImm(Offset)
     348             :       .addImm(Shifter);
     349           1 : }
     350             : 
     351           2 : void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
     352             :                                             int64_t Offset) const {
     353           2 :   int Off = Offset; // ARM doesn't need the general 64-bit offsets
     354             :   unsigned i = 0;
     355             : 
     356          10 :   while (!MI.getOperand(i).isFI()) {
     357           2 :     ++i;
     358             :     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
     359             :   }
     360           2 :   const MachineFunction *MF = MI.getParent()->getParent();
     361             :   const AArch64InstrInfo *TII =
     362           2 :       MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
     363           2 :   bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
     364             :   assert(Done && "Unable to resolve frame index!");
     365             :   (void)Done;
     366           2 : }
     367             : 
     368        3200 : void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
     369             :                                               int SPAdj, unsigned FIOperandNum,
     370             :                                               RegScavenger *RS) const {
     371             :   assert(SPAdj == 0 && "Unexpected");
     372             : 
     373             :   MachineInstr &MI = *II;
     374        3200 :   MachineBasicBlock &MBB = *MI.getParent();
     375        3200 :   MachineFunction &MF = *MBB.getParent();
     376             :   const AArch64InstrInfo *TII =
     377        3200 :       MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
     378        3200 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     379             : 
     380        6400 :   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
     381             :   unsigned FrameReg;
     382             :   int Offset;
     383             : 
     384             :   // Special handling of dbg_value, stackmap and patchpoint instructions.
     385        6400 :   if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
     386             :       MI.getOpcode() == TargetOpcode::PATCHPOINT) {
     387          29 :     Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
     388             :                                              /*PreferFP=*/true);
     389          58 :     Offset += MI.getOperand(FIOperandNum + 1).getImm();
     390          29 :     MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
     391          58 :     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
     392          29 :     return;
     393             :   }
     394             : 
     395             :   // Modify MI as necessary to handle as much of 'Offset' as possible
     396        3171 :   Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
     397        3171 :   if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
     398             :     return;
     399             : 
     400             :   assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
     401             :          "Emergency spill slot is out of reach");
     402             : 
     403             :   // If we get here, the immediate doesn't fit into the instruction.  We folded
     404             :   // as much as possible above.  Handle the rest, providing a register that is
     405             :   // SP+LargeImm.
     406             :   unsigned ScratchReg =
     407          22 :       MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
     408          44 :   emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
     409          44 :   MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
     410             : }
     411             : 
     412         870 : unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
     413             :                                                   MachineFunction &MF) const {
     414         870 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     415             : 
     416        1740 :   switch (RC->getID()) {
     417             :   default:
     418             :     return 0;
     419         120 :   case AArch64::GPR32RegClassID:
     420             :   case AArch64::GPR32spRegClassID:
     421             :   case AArch64::GPR32allRegClassID:
     422             :   case AArch64::GPR64spRegClassID:
     423             :   case AArch64::GPR64allRegClassID:
     424             :   case AArch64::GPR64RegClassID:
     425             :   case AArch64::GPR32commonRegClassID:
     426             :   case AArch64::GPR64commonRegClassID:
     427             :     return 32 - 1                                   // XZR/SP
     428         240 :               - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
     429         240 :               - MF.getSubtarget<AArch64Subtarget>()
     430         120 :                     .isX18Reserved() // X18 reserved as platform register
     431         120 :               - hasBasePointer(MF);  // X19
     432          75 :   case AArch64::FPR8RegClassID:
     433             :   case AArch64::FPR16RegClassID:
     434             :   case AArch64::FPR32RegClassID:
     435             :   case AArch64::FPR64RegClassID:
     436             :   case AArch64::FPR128RegClassID:
     437          75 :     return 32;
     438             : 
     439          90 :   case AArch64::DDRegClassID:
     440             :   case AArch64::DDDRegClassID:
     441             :   case AArch64::DDDDRegClassID:
     442             :   case AArch64::QQRegClassID:
     443             :   case AArch64::QQQRegClassID:
     444             :   case AArch64::QQQQRegClassID:
     445          90 :     return 32;
     446             : 
     447          15 :   case AArch64::FPR128_loRegClassID:
     448          15 :     return 16;
     449             :   }
     450             : }

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