LCOV - code coverage report
Current view: top level - lib/Target/AArch64 - AArch64RegisterInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 156 159 98.1 %
Date: 2018-06-17 00:07:59 Functions: 26 26 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains the AArch64 implementation of the TargetRegisterInfo
      11             : // class.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "AArch64RegisterInfo.h"
      16             : #include "AArch64FrameLowering.h"
      17             : #include "AArch64InstrInfo.h"
      18             : #include "AArch64MachineFunctionInfo.h"
      19             : #include "AArch64Subtarget.h"
      20             : #include "MCTargetDesc/AArch64AddressingModes.h"
      21             : #include "llvm/ADT/BitVector.h"
      22             : #include "llvm/ADT/Triple.h"
      23             : #include "llvm/CodeGen/MachineFrameInfo.h"
      24             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      25             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      26             : #include "llvm/CodeGen/RegisterScavenging.h"
      27             : #include "llvm/IR/Function.h"
      28             : #include "llvm/Support/raw_ostream.h"
      29             : #include "llvm/CodeGen/TargetFrameLowering.h"
      30             : #include "llvm/Target/TargetOptions.h"
      31             : 
      32             : using namespace llvm;
      33             : 
      34             : #define GET_REGINFO_TARGET_DESC
      35             : #include "AArch64GenRegisterInfo.inc"
      36             : 
      37        1438 : AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
      38        1438 :     : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {
      39        1438 :   AArch64_MC::initLLVMToCVRegMapping(this);
      40        1438 : }
      41             : 
      42             : const MCPhysReg *
      43      208430 : AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
      44             :   assert(MF && "Invalid MachineFunction pointer.");
      45      416860 :   if (MF->getFunction().getCallingConv() == CallingConv::GHC)
      46             :     // GHC set of callee saved regs is empty as all those regs are
      47             :     // used for passing STG regs around
      48             :     return CSR_AArch64_NoRegs_SaveList;
      49      208374 :   if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)
      50             :     return CSR_AArch64_AllRegs_SaveList;
      51      208374 :   if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS)
      52         100 :     return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
      53             :            CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
      54             :            CSR_AArch64_CXX_TLS_Darwin_SaveList;
      55      208274 :   if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering()
      56      416548 :           ->supportSwiftError() &&
      57      208659 :       MF->getFunction().getAttributes().hasAttrSomewhere(
      58             :           Attribute::SwiftError))
      59             :     return CSR_AArch64_AAPCS_SwiftError_SaveList;
      60      415778 :   if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost)
      61             :     return CSR_AArch64_RT_MostRegs_SaveList;
      62             :   else
      63      207862 :     return CSR_AArch64_AAPCS_SaveList;
      64             : }
      65             : 
      66       12839 : const MCPhysReg *AArch64RegisterInfo::getCalleeSavedRegsViaCopy(
      67             :     const MachineFunction *MF) const {
      68             :   assert(MF && "Invalid MachineFunction pointer.");
      69       25695 :   if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
      70          17 :       MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())
      71             :     return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList;
      72             :   return nullptr;
      73             : }
      74             : 
      75             : const uint32_t *
      76        2266 : AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
      77             :                                           CallingConv::ID CC) const {
      78        2266 :   bool SCS = MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
      79        2266 :   if (CC == CallingConv::GHC)
      80             :     // This is academic because all GHC calls are (supposed to be) tail calls
      81           4 :     return SCS ? CSR_AArch64_NoRegs_SCS_RegMask : CSR_AArch64_NoRegs_RegMask;
      82        2262 :   if (CC == CallingConv::AnyReg)
      83          13 :     return SCS ? CSR_AArch64_AllRegs_SCS_RegMask : CSR_AArch64_AllRegs_RegMask;
      84        2249 :   if (CC == CallingConv::CXX_FAST_TLS)
      85             :     return SCS ? CSR_AArch64_CXX_TLS_Darwin_SCS_RegMask
      86           6 :                : CSR_AArch64_CXX_TLS_Darwin_RegMask;
      87        2243 :   if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering()
      88        4486 :           ->supportSwiftError() &&
      89        4486 :       MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
      90             :     return SCS ? CSR_AArch64_AAPCS_SwiftError_SCS_RegMask
      91          27 :                : CSR_AArch64_AAPCS_SwiftError_RegMask;
      92        2216 :   if (CC == CallingConv::PreserveMost)
      93             :     return SCS ? CSR_AArch64_RT_MostRegs_SCS_RegMask
      94           4 :                : CSR_AArch64_RT_MostRegs_RegMask;
      95             :   else
      96        2212 :     return SCS ? CSR_AArch64_AAPCS_SCS_RegMask : CSR_AArch64_AAPCS_RegMask;
      97             : }
      98             : 
      99          27 : const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const {
     100          27 :   if (TT.isOSDarwin())
     101             :     return CSR_AArch64_TLS_Darwin_RegMask;
     102             : 
     103             :   assert(TT.isOSBinFormatELF() && "Invalid target");
     104             :   return CSR_AArch64_TLS_ELF_RegMask;
     105             : }
     106             : 
     107             : const uint32_t *
     108          10 : AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
     109             :                                                 CallingConv::ID CC) const {
     110             :   // This should return a register mask that is the same as that returned by
     111             :   // getCallPreservedMask but that additionally preserves the register used for
     112             :   // the first i64 argument (which must also be the register used to return a
     113             :   // single i64 return value)
     114             :   //
     115             :   // In case that the calling convention does not use the same register for
     116             :   // both, the function should return NULL (does not currently apply)
     117             :   assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
     118          10 :   return CSR_AArch64_AAPCS_ThisReturn_RegMask;
     119             : }
     120             : 
     121           3 : const uint32_t *AArch64RegisterInfo::getWindowsStackProbePreservedMask() const {
     122           3 :   return CSR_AArch64_StackProbe_Windows_RegMask;
     123             : }
     124             : 
     125             : BitVector
     126       29321 : AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
     127       29321 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     128             : 
     129             :   // FIXME: avoid re-calculating this every time.
     130       29321 :   BitVector Reserved(getNumRegs());
     131       29321 :   markSuperRegs(Reserved, AArch64::WSP);
     132       29321 :   markSuperRegs(Reserved, AArch64::WZR);
     133             : 
     134       29321 :   if (TFI->hasFP(MF) || TT.isOSDarwin())
     135        6368 :     markSuperRegs(Reserved, AArch64::W29);
     136             : 
     137       29321 :   if (MF.getSubtarget<AArch64Subtarget>().isX18Reserved())
     138        5540 :     markSuperRegs(Reserved, AArch64::W18); // Platform register
     139             : 
     140       29321 :   if (MF.getSubtarget<AArch64Subtarget>().isX20Reserved())
     141           4 :     markSuperRegs(Reserved, AArch64::W20); // Platform register
     142             : 
     143       29321 :   if (hasBasePointer(MF))
     144          25 :     markSuperRegs(Reserved, AArch64::W19);
     145             : 
     146             :   assert(checkAllSuperRegsMarked(Reserved));
     147       29321 :   return Reserved;
     148             : }
     149             : 
     150      167432 : bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
     151             :                                       unsigned Reg) const {
     152      167432 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     153             : 
     154      167432 :   switch (Reg) {
     155             :   default:
     156             :     break;
     157             :   case AArch64::SP:
     158             :   case AArch64::XZR:
     159             :   case AArch64::WSP:
     160             :   case AArch64::WZR:
     161             :     return true;
     162           0 :   case AArch64::X18:
     163             :   case AArch64::W18:
     164           0 :     return MF.getSubtarget<AArch64Subtarget>().isX18Reserved();
     165       13804 :   case AArch64::X19:
     166             :   case AArch64::W19:
     167       13804 :     return hasBasePointer(MF);
     168       13983 :   case AArch64::X20:
     169             :   case AArch64::W20:
     170       13983 :     return MF.getSubtarget<AArch64Subtarget>().isX20Reserved();
     171       13853 :   case AArch64::FP:
     172             :   case AArch64::W29:
     173       13853 :     return TFI->hasFP(MF) || TT.isOSDarwin();
     174             :   }
     175             : 
     176      125792 :   return false;
     177             : }
     178             : 
     179      171482 : bool AArch64RegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
     180      171482 :   return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
     181             : }
     182             : 
     183             : const TargetRegisterClass *
     184          28 : AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
     185             :                                       unsigned Kind) const {
     186          28 :   return &AArch64::GPR64spRegClass;
     187             : }
     188             : 
     189             : const TargetRegisterClass *
     190           3 : AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
     191           3 :   if (RC == &AArch64::CCRRegClass)
     192             :     return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
     193           0 :   return RC;
     194             : }
     195             : 
     196          41 : unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
     197             : 
     198       61655 : bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
     199       61655 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
     200             : 
     201             :   // In the presence of variable sized objects, if the fixed stack size is
     202             :   // large enough that referencing from the FP won't result in things being
     203             :   // in range relatively often, we can use a base pointer to allow access
     204             :   // from the other direction like the SP normally works.
     205             :   // Furthermore, if both variable sized objects are present, and the
     206             :   // stack needs to be dynamically re-aligned, the base pointer is the only
     207             :   // reliable way to reference the locals.
     208       61655 :   if (MFI.hasVarSizedObjects()) {
     209         241 :     if (needsStackRealignment(MF))
     210             :       return true;
     211             :     // Conservatively estimate whether the negative offset from the frame
     212             :     // pointer will be sufficient to reach. If a function has a smallish
     213             :     // frame, it's less likely to have lots of spills and callee saved
     214             :     // space, so it's all more likely to be within range of the frame pointer.
     215             :     // If it's wrong, we'll materialize the constant and still get to the
     216             :     // object; it's just suboptimal. Negative offsets use the unscaled
     217             :     // load/store instructions, which have a 9-bit signed immediate.
     218         195 :     return MFI.getLocalFrameSize() >= 256;
     219             :   }
     220             : 
     221             :   return false;
     222             : }
     223             : 
     224             : unsigned
     225        1441 : AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
     226        1441 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     227        1441 :   return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
     228             : }
     229             : 
     230       41212 : bool AArch64RegisterInfo::requiresRegisterScavenging(
     231             :     const MachineFunction &MF) const {
     232       41212 :   return true;
     233             : }
     234             : 
     235       13965 : bool AArch64RegisterInfo::requiresVirtualBaseRegisters(
     236             :     const MachineFunction &MF) const {
     237       13965 :   return true;
     238             : }
     239             : 
     240             : bool
     241         291 : AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
     242             :   // This function indicates whether the emergency spillslot should be placed
     243             :   // close to the beginning of the stackframe (closer to FP) or the end
     244             :   // (closer to SP).
     245             :   //
     246             :   // The beginning works most reliably if we have a frame pointer.
     247         291 :   const AArch64FrameLowering &TFI = *getFrameLowering(MF);
     248         291 :   return TFI.hasFP(MF);
     249             : }
     250             : 
     251       13980 : bool AArch64RegisterInfo::requiresFrameIndexScavenging(
     252             :     const MachineFunction &MF) const {
     253       13980 :   return true;
     254             : }
     255             : 
     256             : bool
     257       12903 : AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
     258       12903 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
     259       12903 :   if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack())
     260             :     return true;
     261       12903 :   return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
     262             : }
     263             : 
     264             : /// needsFrameBaseReg - Returns true if the instruction's frame index
     265             : /// reference would be better served by a base register other than FP
     266             : /// or SP. Used by LocalStackFrameAllocation to determine which frame index
     267             : /// references it should create new base registers for.
     268        1084 : bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI,
     269             :                                             int64_t Offset) const {
     270        4340 :   for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
     271             :     assert(i < MI->getNumOperands() &&
     272             :            "Instr doesn't have FrameIndex operand!");
     273             : 
     274             :   // It's the load/store FI references that cause issues, as it can be difficult
     275             :   // to materialize the offset if it won't fit in the literal field. Estimate
     276             :   // based on the size of the local frame and some conservative assumptions
     277             :   // about the rest of the stack frame (note, this is pre-regalloc, so
     278             :   // we don't know everything for certain yet) whether this offset is likely
     279             :   // to be out of range of the immediate. Return true if so.
     280             : 
     281             :   // We only generate virtual base registers for loads and stores, so
     282             :   // return false for everything else.
     283        1084 :   if (!MI->mayLoad() && !MI->mayStore())
     284             :     return false;
     285             : 
     286             :   // Without a virtual base register, if the function has variable sized
     287             :   // objects, all fixed-size local references will be via the frame pointer,
     288             :   // Approximate the offset and see if it's legal for the instruction.
     289             :   // Note that the incoming offset is based on the SP value at function entry,
     290             :   // so it'll be negative.
     291         938 :   MachineFunction &MF = *MI->getParent()->getParent();
     292         938 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     293         938 :   MachineFrameInfo &MFI = MF.getFrameInfo();
     294             : 
     295             :   // Estimate an offset from the frame pointer.
     296             :   // Conservatively assume all GPR callee-saved registers get pushed.
     297             :   // FP, LR, X19-X28, D8-D15. 64-bits each.
     298         938 :   int64_t FPOffset = Offset - 16 * 20;
     299             :   // Estimate an offset from the stack pointer.
     300             :   // The incoming offset is relating to the SP at the start of the function,
     301             :   // but when we access the local it'll be relative to the SP after local
     302             :   // allocation, so adjust our SP-relative offset by that allocation size.
     303         938 :   Offset += MFI.getLocalFrameSize();
     304             :   // Assume that we'll have at least some spill slots allocated.
     305             :   // FIXME: This is a total SWAG number. We should run some statistics
     306             :   //        and pick a real one.
     307         938 :   Offset += 128; // 128 bytes of spill slots
     308             : 
     309             :   // If there is a frame pointer, try using it.
     310             :   // The FP is only available if there is no dynamic realignment. We
     311             :   // don't know for sure yet whether we'll need that, so we guess based
     312             :   // on whether there are any local variables that would trigger it.
     313         938 :   if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
     314             :     return false;
     315             : 
     316             :   // If we can reference via the stack pointer or base pointer, try that.
     317             :   // FIXME: This (and the code that resolves the references) can be improved
     318             :   //        to only disallow SP relative references in the live range of
     319             :   //        the VLA(s). In practice, it's unclear how much difference that
     320             :   //        would make, but it may be worth doing.
     321         938 :   if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
     322             :     return false;
     323             : 
     324             :   // The offset likely isn't legal; we want to allocate a virtual base register.
     325           4 :   return true;
     326             : }
     327             : 
     328        1113 : bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
     329             :                                              unsigned BaseReg,
     330             :                                              int64_t Offset) const {
     331             :   assert(Offset <= INT_MAX && "Offset too big to fit in int.");
     332             :   assert(MI && "Unable to get the legal offset for nil instruction.");
     333        1113 :   int SaveOffset = Offset;
     334        1113 :   return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
     335             : }
     336             : 
     337             : /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
     338             : /// at the beginning of the basic block.
     339           1 : void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
     340             :                                                        unsigned BaseReg,
     341             :                                                        int FrameIdx,
     342             :                                                        int64_t Offset) const {
     343             :   MachineBasicBlock::iterator Ins = MBB->begin();
     344           1 :   DebugLoc DL; // Defaults to "unknown"
     345           1 :   if (Ins != MBB->end())
     346             :     DL = Ins->getDebugLoc();
     347           1 :   const MachineFunction &MF = *MBB->getParent();
     348             :   const AArch64InstrInfo *TII =
     349           1 :       MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
     350           1 :   const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
     351           1 :   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
     352           1 :   MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
     353             :   unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
     354             : 
     355           1 :   BuildMI(*MBB, Ins, DL, MCID, BaseReg)
     356             :       .addFrameIndex(FrameIdx)
     357             :       .addImm(Offset)
     358             :       .addImm(Shifter);
     359           1 : }
     360             : 
     361           2 : void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
     362             :                                             int64_t Offset) const {
     363           2 :   int Off = Offset; // ARM doesn't need the general 64-bit offsets
     364             :   unsigned i = 0;
     365             : 
     366          10 :   while (!MI.getOperand(i).isFI()) {
     367           2 :     ++i;
     368             :     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
     369             :   }
     370           2 :   const MachineFunction *MF = MI.getParent()->getParent();
     371             :   const AArch64InstrInfo *TII =
     372           2 :       MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
     373           2 :   bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
     374             :   assert(Done && "Unable to resolve frame index!");
     375             :   (void)Done;
     376           2 : }
     377             : 
     378        3286 : void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
     379             :                                               int SPAdj, unsigned FIOperandNum,
     380             :                                               RegScavenger *RS) const {
     381             :   assert(SPAdj == 0 && "Unexpected");
     382             : 
     383             :   MachineInstr &MI = *II;
     384        3286 :   MachineBasicBlock &MBB = *MI.getParent();
     385        3286 :   MachineFunction &MF = *MBB.getParent();
     386             :   const AArch64InstrInfo *TII =
     387        3286 :       MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
     388        3286 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     389             : 
     390        6572 :   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
     391             :   unsigned FrameReg;
     392             :   int Offset;
     393             : 
     394             :   // Special handling of dbg_value, stackmap and patchpoint instructions.
     395        6572 :   if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
     396             :       MI.getOpcode() == TargetOpcode::PATCHPOINT) {
     397          29 :     Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
     398             :                                              /*PreferFP=*/true);
     399          58 :     Offset += MI.getOperand(FIOperandNum + 1).getImm();
     400          29 :     MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
     401          58 :     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
     402          29 :     return;
     403             :   }
     404             : 
     405             :   // Modify MI as necessary to handle as much of 'Offset' as possible
     406        3257 :   Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
     407        3257 :   if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
     408             :     return;
     409             : 
     410             :   assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
     411             :          "Emergency spill slot is out of reach");
     412             : 
     413             :   // If we get here, the immediate doesn't fit into the instruction.  We folded
     414             :   // as much as possible above.  Handle the rest, providing a register that is
     415             :   // SP+LargeImm.
     416             :   unsigned ScratchReg =
     417          32 :       MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
     418          32 :   emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
     419          32 :   MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
     420             : }
     421             : 
     422        1200 : unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
     423             :                                                   MachineFunction &MF) const {
     424        1200 :   const AArch64FrameLowering *TFI = getFrameLowering(MF);
     425             : 
     426        2400 :   switch (RC->getID()) {
     427             :   default:
     428             :     return 0;
     429         120 :   case AArch64::GPR32RegClassID:
     430             :   case AArch64::GPR32spRegClassID:
     431             :   case AArch64::GPR32allRegClassID:
     432             :   case AArch64::GPR64spRegClassID:
     433             :   case AArch64::GPR64allRegClassID:
     434             :   case AArch64::GPR64RegClassID:
     435             :   case AArch64::GPR32commonRegClassID:
     436             :   case AArch64::GPR64commonRegClassID:
     437             :     return 32 - 1                                   // XZR/SP
     438         240 :               - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
     439         240 :               - MF.getSubtarget<AArch64Subtarget>()
     440         120 :                     .isX18Reserved() // X18 reserved as platform register
     441         120 :               - MF.getSubtarget<AArch64Subtarget>()
     442         120 :                     .isX20Reserved() // X20 reserved as platform register
     443         120 :               - hasBasePointer(MF);  // X19
     444          75 :   case AArch64::FPR8RegClassID:
     445             :   case AArch64::FPR16RegClassID:
     446             :   case AArch64::FPR32RegClassID:
     447             :   case AArch64::FPR64RegClassID:
     448             :   case AArch64::FPR128RegClassID:
     449          75 :     return 32;
     450             : 
     451          90 :   case AArch64::DDRegClassID:
     452             :   case AArch64::DDDRegClassID:
     453             :   case AArch64::DDDDRegClassID:
     454             :   case AArch64::QQRegClassID:
     455             :   case AArch64::QQQRegClassID:
     456             :   case AArch64::QQQQRegClassID:
     457          90 :     return 32;
     458             : 
     459          15 :   case AArch64::FPR128_loRegClassID:
     460          15 :     return 16;
     461             :   }
     462             : }

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