LCOV - code coverage report
Current view: top level - lib/Target/AArch64 - AArch64Subtarget.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 24 25 96.0 %
Date: 2018-06-17 00:07:59 Functions: 10 11 90.9 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file declares the AArch64 specific subclass of TargetSubtarget.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
      15             : #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
      16             : 
      17             : #include "AArch64FrameLowering.h"
      18             : #include "AArch64ISelLowering.h"
      19             : #include "AArch64InstrInfo.h"
      20             : #include "AArch64RegisterInfo.h"
      21             : #include "AArch64SelectionDAGInfo.h"
      22             : #include "llvm/CodeGen/GlobalISel/CallLowering.h"
      23             : #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
      24             : #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
      25             : #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
      26             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      27             : #include "llvm/IR/DataLayout.h"
      28             : #include <string>
      29             : 
      30             : #define GET_SUBTARGETINFO_HEADER
      31             : #include "AArch64GenSubtargetInfo.inc"
      32             : 
      33             : namespace llvm {
      34             : class GlobalValue;
      35             : class StringRef;
      36             : class Triple;
      37             : 
      38        4212 : class AArch64Subtarget final : public AArch64GenSubtargetInfo {
      39             : public:
      40             :   enum ARMProcFamilyEnum : uint8_t {
      41             :     Others,
      42             :     CortexA35,
      43             :     CortexA53,
      44             :     CortexA55,
      45             :     CortexA57,
      46             :     CortexA72,
      47             :     CortexA73,
      48             :     CortexA75,
      49             :     Cyclone,
      50             :     ExynosM1,
      51             :     ExynosM3,
      52             :     Falkor,
      53             :     Kryo,
      54             :     Saphira,
      55             :     ThunderX2T99,
      56             :     ThunderX,
      57             :     ThunderXT81,
      58             :     ThunderXT83,
      59             :     ThunderXT88
      60             :   };
      61             : 
      62             : protected:
      63             :   /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
      64             :   ARMProcFamilyEnum ARMProcFamily = Others;
      65             : 
      66             :   bool HasV8_1aOps = false;
      67             :   bool HasV8_2aOps = false;
      68             :   bool HasV8_3aOps = false;
      69             : 
      70             :   bool HasFPARMv8 = false;
      71             :   bool HasNEON = false;
      72             :   bool HasCrypto = false;
      73             :   bool HasDotProd = false;
      74             :   bool HasCRC = false;
      75             :   bool HasLSE = false;
      76             :   bool HasRAS = false;
      77             :   bool HasRDM = false;
      78             :   bool HasPerfMon = false;
      79             :   bool HasFullFP16 = false;
      80             :   bool HasSPE = false;
      81             :   bool HasLSLFast = false;
      82             :   bool HasSVE = false;
      83             :   bool HasRCPC = false;
      84             :   bool HasAggressiveFMA = false;
      85             : 
      86             :   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
      87             :   bool HasZeroCycleRegMove = false;
      88             : 
      89             :   // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
      90             :   bool HasZeroCycleZeroing = false;
      91             :   bool HasZeroCycleZeroingFPWorkaround = false;
      92             : 
      93             :   // StrictAlign - Disallow unaligned memory accesses.
      94             :   bool StrictAlign = false;
      95             : 
      96             :   // NegativeImmediates - transform instructions with negative immediates
      97             :   bool NegativeImmediates = true;
      98             : 
      99             :   // Enable 64-bit vectorization in SLP.
     100             :   unsigned MinVectorRegisterBitWidth = 64;
     101             : 
     102             :   bool UseAA = false;
     103             :   bool PredictableSelectIsExpensive = false;
     104             :   bool BalanceFPOps = false;
     105             :   bool CustomAsCheapAsMove = false;
     106             :   bool ExynosAsCheapAsMove = false;
     107             :   bool UsePostRAScheduler = false;
     108             :   bool Misaligned128StoreIsSlow = false;
     109             :   bool Paired128IsSlow = false;
     110             :   bool STRQroIsSlow = false;
     111             :   bool UseAlternateSExtLoadCVTF32Pattern = false;
     112             :   bool HasArithmeticBccFusion = false;
     113             :   bool HasArithmeticCbzFusion = false;
     114             :   bool HasFuseAddress = false;
     115             :   bool HasFuseAES = false;
     116             :   bool HasFuseCCSelect = false;
     117             :   bool HasFuseLiterals = false;
     118             :   bool DisableLatencySchedHeuristic = false;
     119             :   bool UseRSqrt = false;
     120             :   uint8_t MaxInterleaveFactor = 2;
     121             :   uint8_t VectorInsertExtractBaseCost = 3;
     122             :   uint16_t CacheLineSize = 0;
     123             :   uint16_t PrefetchDistance = 0;
     124             :   uint16_t MinPrefetchStride = 1;
     125             :   unsigned MaxPrefetchIterationsAhead = UINT_MAX;
     126             :   unsigned PrefFunctionAlignment = 0;
     127             :   unsigned PrefLoopAlignment = 0;
     128             :   unsigned MaxJumpTableSize = 0;
     129             :   unsigned WideningBaseCost = 0;
     130             : 
     131             :   // ReserveX18 - X18 is not available as a general purpose register.
     132             :   bool ReserveX18;
     133             : 
     134             :   // ReserveX20 - X20 is not available as a general purpose register.
     135             :   bool ReserveX20 = false;
     136             : 
     137             :   bool IsLittle;
     138             : 
     139             :   /// TargetTriple - What processor and OS we're targeting.
     140             :   Triple TargetTriple;
     141             : 
     142             :   AArch64FrameLowering FrameLowering;
     143             :   AArch64InstrInfo InstrInfo;
     144             :   AArch64SelectionDAGInfo TSInfo;
     145             :   AArch64TargetLowering TLInfo;
     146             : 
     147             :   /// GlobalISel related APIs.
     148             :   std::unique_ptr<CallLowering> CallLoweringInfo;
     149             :   std::unique_ptr<InstructionSelector> InstSelector;
     150             :   std::unique_ptr<LegalizerInfo> Legalizer;
     151             :   std::unique_ptr<RegisterBankInfo> RegBankInfo;
     152             : 
     153             : private:
     154             :   /// initializeSubtargetDependencies - Initializes using CPUString and the
     155             :   /// passed in feature string so that we can use initializer lists for
     156             :   /// subtarget initialization.
     157             :   AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
     158             :                                                     StringRef CPUString);
     159             : 
     160             :   /// Initialize properties based on the selected processor family.
     161             :   void initializeProperties();
     162             : 
     163             : public:
     164             :   /// This constructor initializes the data members to match that
     165             :   /// of the specified triple.
     166             :   AArch64Subtarget(const Triple &TT, const std::string &CPU,
     167             :                    const std::string &FS, const TargetMachine &TM,
     168             :                    bool LittleEndian);
     169             : 
     170       14541 :   const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
     171       14541 :     return &TSInfo;
     172             :   }
     173      564348 :   const AArch64FrameLowering *getFrameLowering() const override {
     174      564348 :     return &FrameLowering;
     175             :   }
     176      371146 :   const AArch64TargetLowering *getTargetLowering() const override {
     177      774677 :     return &TLInfo;
     178             :   }
     179     1399879 :   const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
     180     3058441 :   const AArch64RegisterInfo *getRegisterInfo() const override {
     181     3058441 :     return &getInstrInfo()->getRegisterInfo();
     182             :   }
     183             :   const CallLowering *getCallLowering() const override;
     184             :   const InstructionSelector *getInstructionSelector() const override;
     185             :   const LegalizerInfo *getLegalizerInfo() const override;
     186             :   const RegisterBankInfo *getRegBankInfo() const override;
     187        1438 :   const Triple &getTargetTriple() const { return TargetTriple; }
     188       41091 :   bool enableMachineScheduler() const override { return true; }
     189       10385 :   bool enablePostRAScheduler() const override {
     190       10385 :     return UsePostRAScheduler;
     191             :   }
     192             : 
     193             :   /// Returns ARM processor family.
     194             :   /// Avoid this function! CPU specifics should be kept local to this class
     195             :   /// and preferably modeled with SubtargetFeatures or properties in
     196             :   /// initializeProperties().
     197             :   ARMProcFamilyEnum getProcFamily() const {
     198             :     return ARMProcFamily;
     199             :   }
     200             : 
     201             :   bool hasV8_1aOps() const { return HasV8_1aOps; }
     202             :   bool hasV8_2aOps() const { return HasV8_2aOps; }
     203             :   bool hasV8_3aOps() const { return HasV8_3aOps; }
     204             : 
     205             :   bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
     206             : 
     207             :   bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
     208             : 
     209             :   bool hasZeroCycleZeroingFPWorkaround() const {
     210             :     return HasZeroCycleZeroingFPWorkaround;
     211             :   }
     212             : 
     213             :   bool requiresStrictAlign() const { return StrictAlign; }
     214             : 
     215           3 :   bool isXRaySupported() const override { return true; }
     216             : 
     217             :   unsigned getMinVectorRegisterBitWidth() const {
     218             :     return MinVectorRegisterBitWidth;
     219             :   }
     220             : 
     221             :   bool isX18Reserved() const { return ReserveX18; }
     222             :   bool isX20Reserved() const { return ReserveX20; }
     223             :   bool hasFPARMv8() const { return HasFPARMv8; }
     224             :   bool hasNEON() const { return HasNEON; }
     225             :   bool hasCrypto() const { return HasCrypto; }
     226             :   bool hasDotProd() const { return HasDotProd; }
     227             :   bool hasCRC() const { return HasCRC; }
     228             :   bool hasLSE() const { return HasLSE; }
     229             :   bool hasRAS() const { return HasRAS; }
     230             :   bool hasRDM() const { return HasRDM; }
     231             :   bool balanceFPOps() const { return BalanceFPOps; }
     232             :   bool predictableSelectIsExpensive() const {
     233             :     return PredictableSelectIsExpensive;
     234             :   }
     235             :   bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
     236             :   bool hasExynosCheapAsMoveHandling() const { return ExynosAsCheapAsMove; }
     237             :   bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
     238             :   bool isPaired128Slow() const { return Paired128IsSlow; }
     239             :   bool isSTRQroSlow() const { return STRQroIsSlow; }
     240             :   bool useAlternateSExtLoadCVTF32Pattern() const {
     241             :     return UseAlternateSExtLoadCVTF32Pattern;
     242             :   }
     243             :   bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
     244             :   bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
     245             :   bool hasFuseAddress() const { return HasFuseAddress; }
     246             :   bool hasFuseAES() const { return HasFuseAES; }
     247             :   bool hasFuseCCSelect() const { return HasFuseCCSelect; }
     248             :   bool hasFuseLiterals() const { return HasFuseLiterals; }
     249             : 
     250             :   /// Return true if the CPU supports any kind of instruction fusion.
     251             :   bool hasFusion() const {
     252       67721 :     return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
     253       45894 :            hasFuseAES() || hasFuseCCSelect() || hasFuseLiterals();
     254             :   }
     255             : 
     256             :   bool useRSqrt() const { return UseRSqrt; }
     257          34 :   unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
     258             :   unsigned getVectorInsertExtractBaseCost() const {
     259             :     return VectorInsertExtractBaseCost;
     260             :   }
     261           0 :   unsigned getCacheLineSize() const { return CacheLineSize; }
     262       13407 :   unsigned getPrefetchDistance() const { return PrefetchDistance; }
     263          12 :   unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
     264             :   unsigned getMaxPrefetchIterationsAhead() const {
     265             :     return MaxPrefetchIterationsAhead;
     266             :   }
     267             :   unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
     268             :   unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
     269             : 
     270             :   unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
     271             : 
     272             :   unsigned getWideningBaseCost() const { return WideningBaseCost; }
     273             : 
     274             :   /// CPU has TBI (top byte of addresses is ignored during HW address
     275             :   /// translation) and OS enables it.
     276             :   bool supportsAddressTopByteIgnored() const;
     277             : 
     278             :   bool hasPerfMon() const { return HasPerfMon; }
     279             :   bool hasFullFP16() const { return HasFullFP16; }
     280             :   bool hasSPE() const { return HasSPE; }
     281             :   bool hasLSLFast() const { return HasLSLFast; }
     282             :   bool hasSVE() const { return HasSVE; }
     283             :   bool hasRCPC() const { return HasRCPC; }
     284             :   bool hasAggressiveFMA() const { return HasAggressiveFMA; }
     285             : 
     286             :   bool isLittleEndian() const { return IsLittle; }
     287             : 
     288             :   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
     289             :   bool isTargetIOS() const { return TargetTriple.isiOS(); }
     290             :   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
     291             :   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
     292             :   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
     293             :   bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
     294             : 
     295             :   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
     296             :   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
     297             :   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
     298             : 
     299       41603 :   bool useAA() const override { return UseAA; }
     300             : 
     301             :   bool useSmallAddressing() const {
     302        6945 :     switch (TLInfo.getTargetMachine().getCodeModel()) {
     303             :       case CodeModel::Kernel:
     304             :         // Kernel is currently allowed only for Fuchsia targets,
     305             :         // where it is the same as Small for almost all purposes.
     306             :       case CodeModel::Small:
     307             :         return true;
     308             :       default:
     309             :         return false;
     310             :     }
     311             :   }
     312             : 
     313             :   /// ParseSubtargetFeatures - Parses features string setting specified
     314             :   /// subtarget options.  Definition of function is auto generated by tblgen.
     315             :   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
     316             : 
     317             :   /// ClassifyGlobalReference - Find the target operand flags that describe
     318             :   /// how a global value should be referenced for the current subtarget.
     319             :   unsigned char ClassifyGlobalReference(const GlobalValue *GV,
     320             :                                         const TargetMachine &TM) const;
     321             : 
     322             :   unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
     323             :                                                 const TargetMachine &TM) const;
     324             : 
     325             :   void overrideSchedPolicy(MachineSchedPolicy &Policy,
     326             :                            unsigned NumRegionInstrs) const override;
     327             : 
     328             :   bool enableEarlyIfConversion() const override;
     329             : 
     330             :   std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
     331             : 
     332             :   bool isCallingConvWin64(CallingConv::ID CC) const {
     333       31656 :     switch (CC) {
     334             :     case CallingConv::C:
     335             :       return isTargetWindows();
     336             :     case CallingConv::Win64:
     337             :       return true;
     338          86 :     default:
     339             :       return false;
     340             :     }
     341             :   }
     342             : 
     343             :   void mirFileLoaded(MachineFunction &MF) const override;
     344             : };
     345             : } // End llvm namespace
     346             : 
     347             : #endif

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