LCOV - code coverage report
Current view: top level - lib/Target/AArch64/InstPrinter - AArch64InstPrinter.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 883 1076 82.1 %
Date: 2018-09-23 13:06:45 Functions: 102 126 81.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This class prints an AArch64 MCInst to a .s file.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "AArch64InstPrinter.h"
      15             : #include "MCTargetDesc/AArch64AddressingModes.h"
      16             : #include "Utils/AArch64BaseInfo.h"
      17             : #include "llvm/ADT/STLExtras.h"
      18             : #include "llvm/ADT/StringExtras.h"
      19             : #include "llvm/ADT/StringRef.h"
      20             : #include "llvm/MC/MCAsmInfo.h"
      21             : #include "llvm/MC/MCExpr.h"
      22             : #include "llvm/MC/MCInst.h"
      23             : #include "llvm/MC/MCRegisterInfo.h"
      24             : #include "llvm/MC/MCSubtargetInfo.h"
      25             : #include "llvm/Support/Casting.h"
      26             : #include "llvm/Support/ErrorHandling.h"
      27             : #include "llvm/Support/Format.h"
      28             : #include "llvm/Support/MathExtras.h"
      29             : #include "llvm/Support/raw_ostream.h"
      30             : #include <cassert>
      31             : #include <cstdint>
      32             : #include <string>
      33             : 
      34             : using namespace llvm;
      35             : 
      36             : #define DEBUG_TYPE "asm-printer"
      37             : 
      38             : #define GET_INSTRUCTION_NAME
      39             : #define PRINT_ALIAS_INSTR
      40             : #include "AArch64GenAsmWriter.inc"
      41             : #define GET_INSTRUCTION_NAME
      42             : #define PRINT_ALIAS_INSTR
      43             : #include "AArch64GenAsmWriter1.inc"
      44             : 
      45        3186 : AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI,
      46             :                                        const MCInstrInfo &MII,
      47             :                                        const MCRegisterInfo &MRI)
      48        3186 :     : MCInstPrinter(MAI, MII, MRI) {}
      49             : 
      50         414 : AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI,
      51             :                                                  const MCInstrInfo &MII,
      52         414 :                                                  const MCRegisterInfo &MRI)
      53         414 :     : AArch64InstPrinter(MAI, MII, MRI) {}
      54             : 
      55        2473 : void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
      56             :   // This is for .cfi directives.
      57        2473 :   OS << getRegisterName(RegNo);
      58        2473 : }
      59             : 
      60      111570 : void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
      61             :                                    StringRef Annot,
      62             :                                    const MCSubtargetInfo &STI) {
      63             :   // Check for special encodings and print the canonical alias instead.
      64             : 
      65      111570 :   unsigned Opcode = MI->getOpcode();
      66             : 
      67      111570 :   if (Opcode == AArch64::SYSxt)
      68         375 :     if (printSysAlias(MI, STI, O)) {
      69         310 :       printAnnotation(O, Annot);
      70         310 :       return;
      71             :     }
      72             : 
      73             :   // SBFM/UBFM should print to a nicer aliased form if possible.
      74      222520 :   if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
      75      111260 :       Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
      76             :     const MCOperand &Op0 = MI->getOperand(0);
      77             :     const MCOperand &Op1 = MI->getOperand(1);
      78             :     const MCOperand &Op2 = MI->getOperand(2);
      79             :     const MCOperand &Op3 = MI->getOperand(3);
      80             : 
      81             :     bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
      82        1406 :     bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
      83        1406 :     if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
      84             :       const char *AsmMnemonic = nullptr;
      85             : 
      86         483 :       switch (Op3.getImm()) {
      87             :       default:
      88             :         break;
      89         177 :       case 7:
      90         177 :         if (IsSigned)
      91             :           AsmMnemonic = "sxtb";
      92          96 :         else if (!Is64Bit)
      93             :           AsmMnemonic = "uxtb";
      94             :         break;
      95         122 :       case 15:
      96         122 :         if (IsSigned)
      97             :           AsmMnemonic = "sxth";
      98          50 :         else if (!Is64Bit)
      99             :           AsmMnemonic = "uxth";
     100             :         break;
     101         108 :       case 31:
     102             :         // *xtw is only valid for signed 64-bit operations.
     103         108 :         if (Is64Bit && IsSigned)
     104             :           AsmMnemonic = "sxtw";
     105             :         break;
     106             :       }
     107             : 
     108             :       if (AsmMnemonic) {
     109         702 :         O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
     110         351 :           << ", " << getRegisterName(getWRegFromXReg(Op1.getReg()));
     111         351 :         printAnnotation(O, Annot);
     112         351 :         return;
     113             :       }
     114             :     }
     115             : 
     116             :     // All immediate shifts are aliases, implemented using the Bitfield
     117             :     // instruction. In all cases the immediate shift amount shift must be in
     118             :     // the range 0 to (reg.size -1).
     119        1055 :     if (Op2.isImm() && Op3.isImm()) {
     120             :       const char *AsmMnemonic = nullptr;
     121             :       int shift = 0;
     122        1055 :       int64_t immr = Op2.getImm();
     123        1055 :       int64_t imms = Op3.getImm();
     124        1055 :       if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
     125             :         AsmMnemonic = "lsl";
     126          88 :         shift = 31 - imms;
     127         967 :       } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
     128         405 :                  ((imms + 1 == immr))) {
     129             :         AsmMnemonic = "lsl";
     130         315 :         shift = 63 - imms;
     131         652 :       } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
     132             :         AsmMnemonic = "lsr";
     133          89 :         shift = immr;
     134         563 :       } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
     135             :         AsmMnemonic = "lsr";
     136         147 :         shift = immr;
     137         416 :       } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
     138             :         AsmMnemonic = "asr";
     139          63 :         shift = immr;
     140         353 :       } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
     141             :         AsmMnemonic = "asr";
     142          68 :         shift = immr;
     143             :       }
     144             :       if (AsmMnemonic) {
     145        1540 :         O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
     146         770 :           << ", " << getRegisterName(Op1.getReg()) << ", #" << shift;
     147         770 :         printAnnotation(O, Annot);
     148         770 :         return;
     149             :       }
     150             :     }
     151             : 
     152             :     // SBFIZ/UBFIZ aliases
     153         285 :     if (Op2.getImm() > Op3.getImm()) {
     154         126 :       O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t'
     155          92 :         << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
     156         126 :         << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
     157          92 :       printAnnotation(O, Annot);
     158          92 :       return;
     159             :     }
     160             : 
     161             :     // Otherwise SBFX/UBFX is the preferred form
     162         305 :     O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'
     163         193 :       << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
     164         193 :       << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
     165         193 :     printAnnotation(O, Annot);
     166         193 :     return;
     167             :   }
     168             : 
     169      109854 :   if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
     170             :     const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
     171             :     const MCOperand &Op2 = MI->getOperand(2);
     172         215 :     int ImmR = MI->getOperand(3).getImm();
     173         215 :     int ImmS = MI->getOperand(4).getImm();
     174             : 
     175         215 :     if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&
     176          19 :         (ImmR == 0 || ImmS < ImmR)) {
     177             :       // BFC takes precedence over its entire range, sligtly differently to BFI.
     178          14 :       int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
     179          14 :       int LSB = (BitWidth - ImmR) % BitWidth;
     180          14 :       int Width = ImmS + 1;
     181             : 
     182          14 :       O << "\tbfc\t" << getRegisterName(Op0.getReg())
     183          28 :         << ", #" << LSB << ", #" << Width;
     184          14 :       printAnnotation(O, Annot);
     185          14 :       return;
     186         201 :     } else if (ImmS < ImmR) {
     187             :       // BFI alias
     188          92 :       int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
     189          92 :       int LSB = (BitWidth - ImmR) % BitWidth;
     190          92 :       int Width = ImmS + 1;
     191             : 
     192          92 :       O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
     193         184 :         << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width;
     194          92 :       printAnnotation(O, Annot);
     195          92 :       return;
     196             :     }
     197             : 
     198             :     int LSB = ImmR;
     199         109 :     int Width = ImmS - ImmR + 1;
     200             :     // Otherwise BFXIL the preferred form
     201         109 :     O << "\tbfxil\t"
     202         109 :       << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())
     203         218 :       << ", #" << LSB << ", #" << Width;
     204         109 :     printAnnotation(O, Annot);
     205         109 :     return;
     206             :   }
     207             : 
     208             :   // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
     209             :   // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
     210             :   // printed.
     211      219278 :   if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
     212      109639 :        Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
     213         956 :       MI->getOperand(1).isExpr()) {
     214          94 :     if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
     215          68 :       O << "\tmovz\t";
     216             :     else
     217          26 :       O << "\tmovn\t";
     218             : 
     219          94 :     O << getRegisterName(MI->getOperand(0).getReg()) << ", #";
     220          94 :     MI->getOperand(1).getExpr()->print(O, &MAI);
     221          94 :     return;
     222             :   }
     223             : 
     224      109545 :   if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
     225         428 :       MI->getOperand(2).isExpr()) {
     226         119 :     O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #";
     227         119 :     MI->getOperand(2).getExpr()->print(O, &MAI);
     228         119 :     return;
     229             :   }
     230             : 
     231             :   // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
     232             :   // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
     233             :   // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
     234             :   // that can represent the move is the MOV alias, and the rest get printed
     235             :   // normally.
     236         745 :   if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
     237      109426 :       MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
     238         745 :     int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
     239         745 :     int Shift = MI->getOperand(2).getImm();
     240         745 :     uint64_t Value = (uint64_t)MI->getOperand(1).getImm() << Shift;
     241             : 
     242        1466 :     if (AArch64_AM::isMOVZMovAlias(Value, Shift,
     243             :                                    Opcode == AArch64::MOVZXi ? 64 : 32)) {
     244         721 :       O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
     245        1442 :         << formatImm(SignExtend64(Value, RegWidth));
     246         721 :       return;
     247             :     }
     248             :   }
     249             : 
     250      108822 :   if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
     251      108705 :       MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
     252         117 :     int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
     253         117 :     int Shift = MI->getOperand(2).getImm();
     254         117 :     uint64_t Value = ~((uint64_t)MI->getOperand(1).getImm() << Shift);
     255         117 :     if (RegWidth == 32)
     256          66 :       Value = Value & 0xffffffff;
     257             : 
     258         117 :     if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
     259         111 :       O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
     260         222 :         << formatImm(SignExtend64(Value, RegWidth));
     261         111 :       return;
     262             :     }
     263             :   }
     264             : 
     265      109799 :   if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
     266        1205 :       (MI->getOperand(1).getReg() == AArch64::XZR ||
     267      108594 :        MI->getOperand(1).getReg() == AArch64::WZR) &&
     268        1129 :       MI->getOperand(2).isImm()) {
     269        1129 :     int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
     270        2258 :     uint64_t Value = AArch64_AM::decodeLogicalImmediate(
     271        1129 :         MI->getOperand(2).getImm(), RegWidth);
     272        1129 :     if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
     273          68 :       O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
     274         136 :         << formatImm(SignExtend64(Value, RegWidth));
     275          68 :       return;
     276             :     }
     277             :   }
     278             : 
     279      108526 :   if (Opcode == AArch64::CompilerBarrier) {
     280           2 :     O << '\t' << MAI.getCommentString() << " COMPILER BARRIER";
     281           2 :     printAnnotation(O, Annot);
     282           2 :     return;
     283             :   }
     284             : 
     285             :   // Instruction TSB is specified as a one operand instruction, but 'csync' is
     286             :   // not encoded, so for printing it is treated as a special case here:
     287      108524 :   if (Opcode == AArch64::TSB) {
     288           2 :     O << "\ttsb\tcsync";
     289           2 :     return;
     290             :   }
     291             : 
     292      108522 :   if (!printAliasInstr(MI, STI, O))
     293       70663 :     printInstruction(MI, STI, O);
     294             : 
     295      108522 :   printAnnotation(O, Annot);
     296             : }
     297             : 
     298             : static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
     299             :                                 bool &IsTbx) {
     300       29179 :   switch (Opcode) {
     301           8 :   case AArch64::TBXv8i8One:
     302             :   case AArch64::TBXv8i8Two:
     303             :   case AArch64::TBXv8i8Three:
     304             :   case AArch64::TBXv8i8Four:
     305             :     IsTbx = true;
     306           8 :     Layout = ".8b";
     307             :     return true;
     308          17 :   case AArch64::TBLv8i8One:
     309             :   case AArch64::TBLv8i8Two:
     310             :   case AArch64::TBLv8i8Three:
     311             :   case AArch64::TBLv8i8Four:
     312             :     IsTbx = false;
     313          17 :     Layout = ".8b";
     314             :     return true;
     315           8 :   case AArch64::TBXv16i8One:
     316             :   case AArch64::TBXv16i8Two:
     317             :   case AArch64::TBXv16i8Three:
     318             :   case AArch64::TBXv16i8Four:
     319             :     IsTbx = true;
     320           8 :     Layout = ".16b";
     321             :     return true;
     322          17 :   case AArch64::TBLv16i8One:
     323             :   case AArch64::TBLv16i8Two:
     324             :   case AArch64::TBLv16i8Three:
     325             :   case AArch64::TBLv16i8Four:
     326             :     IsTbx = false;
     327          17 :     Layout = ".16b";
     328             :     return true;
     329             :   default:
     330             :     return false;
     331             :   }
     332             : }
     333             : 
     334             : struct LdStNInstrDesc {
     335             :   unsigned Opcode;
     336             :   const char *Mnemonic;
     337             :   const char *Layout;
     338             :   int ListOperand;
     339             :   bool HasLane;
     340             :   int NaturalOffset;
     341             : };
     342             : 
     343             : static const LdStNInstrDesc LdStNInstInfo[] = {
     344             :   { AArch64::LD1i8,             "ld1",  ".b",     1, true,  0  },
     345             :   { AArch64::LD1i16,            "ld1",  ".h",     1, true,  0  },
     346             :   { AArch64::LD1i32,            "ld1",  ".s",     1, true,  0  },
     347             :   { AArch64::LD1i64,            "ld1",  ".d",     1, true,  0  },
     348             :   { AArch64::LD1i8_POST,        "ld1",  ".b",     2, true,  1  },
     349             :   { AArch64::LD1i16_POST,       "ld1",  ".h",     2, true,  2  },
     350             :   { AArch64::LD1i32_POST,       "ld1",  ".s",     2, true,  4  },
     351             :   { AArch64::LD1i64_POST,       "ld1",  ".d",     2, true,  8  },
     352             :   { AArch64::LD1Rv16b,          "ld1r", ".16b",   0, false, 0  },
     353             :   { AArch64::LD1Rv8h,           "ld1r", ".8h",    0, false, 0  },
     354             :   { AArch64::LD1Rv4s,           "ld1r", ".4s",    0, false, 0  },
     355             :   { AArch64::LD1Rv2d,           "ld1r", ".2d",    0, false, 0  },
     356             :   { AArch64::LD1Rv8b,           "ld1r", ".8b",    0, false, 0  },
     357             :   { AArch64::LD1Rv4h,           "ld1r", ".4h",    0, false, 0  },
     358             :   { AArch64::LD1Rv2s,           "ld1r", ".2s",    0, false, 0  },
     359             :   { AArch64::LD1Rv1d,           "ld1r", ".1d",    0, false, 0  },
     360             :   { AArch64::LD1Rv16b_POST,     "ld1r", ".16b",   1, false, 1  },
     361             :   { AArch64::LD1Rv8h_POST,      "ld1r", ".8h",    1, false, 2  },
     362             :   { AArch64::LD1Rv4s_POST,      "ld1r", ".4s",    1, false, 4  },
     363             :   { AArch64::LD1Rv2d_POST,      "ld1r", ".2d",    1, false, 8  },
     364             :   { AArch64::LD1Rv8b_POST,      "ld1r", ".8b",    1, false, 1  },
     365             :   { AArch64::LD1Rv4h_POST,      "ld1r", ".4h",    1, false, 2  },
     366             :   { AArch64::LD1Rv2s_POST,      "ld1r", ".2s",    1, false, 4  },
     367             :   { AArch64::LD1Rv1d_POST,      "ld1r", ".1d",    1, false, 8  },
     368             :   { AArch64::LD1Onev16b,        "ld1",  ".16b",   0, false, 0  },
     369             :   { AArch64::LD1Onev8h,         "ld1",  ".8h",    0, false, 0  },
     370             :   { AArch64::LD1Onev4s,         "ld1",  ".4s",    0, false, 0  },
     371             :   { AArch64::LD1Onev2d,         "ld1",  ".2d",    0, false, 0  },
     372             :   { AArch64::LD1Onev8b,         "ld1",  ".8b",    0, false, 0  },
     373             :   { AArch64::LD1Onev4h,         "ld1",  ".4h",    0, false, 0  },
     374             :   { AArch64::LD1Onev2s,         "ld1",  ".2s",    0, false, 0  },
     375             :   { AArch64::LD1Onev1d,         "ld1",  ".1d",    0, false, 0  },
     376             :   { AArch64::LD1Onev16b_POST,   "ld1",  ".16b",   1, false, 16 },
     377             :   { AArch64::LD1Onev8h_POST,    "ld1",  ".8h",    1, false, 16 },
     378             :   { AArch64::LD1Onev4s_POST,    "ld1",  ".4s",    1, false, 16 },
     379             :   { AArch64::LD1Onev2d_POST,    "ld1",  ".2d",    1, false, 16 },
     380             :   { AArch64::LD1Onev8b_POST,    "ld1",  ".8b",    1, false, 8  },
     381             :   { AArch64::LD1Onev4h_POST,    "ld1",  ".4h",    1, false, 8  },
     382             :   { AArch64::LD1Onev2s_POST,    "ld1",  ".2s",    1, false, 8  },
     383             :   { AArch64::LD1Onev1d_POST,    "ld1",  ".1d",    1, false, 8  },
     384             :   { AArch64::LD1Twov16b,        "ld1",  ".16b",   0, false, 0  },
     385             :   { AArch64::LD1Twov8h,         "ld1",  ".8h",    0, false, 0  },
     386             :   { AArch64::LD1Twov4s,         "ld1",  ".4s",    0, false, 0  },
     387             :   { AArch64::LD1Twov2d,         "ld1",  ".2d",    0, false, 0  },
     388             :   { AArch64::LD1Twov8b,         "ld1",  ".8b",    0, false, 0  },
     389             :   { AArch64::LD1Twov4h,         "ld1",  ".4h",    0, false, 0  },
     390             :   { AArch64::LD1Twov2s,         "ld1",  ".2s",    0, false, 0  },
     391             :   { AArch64::LD1Twov1d,         "ld1",  ".1d",    0, false, 0  },
     392             :   { AArch64::LD1Twov16b_POST,   "ld1",  ".16b",   1, false, 32 },
     393             :   { AArch64::LD1Twov8h_POST,    "ld1",  ".8h",    1, false, 32 },
     394             :   { AArch64::LD1Twov4s_POST,    "ld1",  ".4s",    1, false, 32 },
     395             :   { AArch64::LD1Twov2d_POST,    "ld1",  ".2d",    1, false, 32 },
     396             :   { AArch64::LD1Twov8b_POST,    "ld1",  ".8b",    1, false, 16 },
     397             :   { AArch64::LD1Twov4h_POST,    "ld1",  ".4h",    1, false, 16 },
     398             :   { AArch64::LD1Twov2s_POST,    "ld1",  ".2s",    1, false, 16 },
     399             :   { AArch64::LD1Twov1d_POST,    "ld1",  ".1d",    1, false, 16 },
     400             :   { AArch64::LD1Threev16b,      "ld1",  ".16b",   0, false, 0  },
     401             :   { AArch64::LD1Threev8h,       "ld1",  ".8h",    0, false, 0  },
     402             :   { AArch64::LD1Threev4s,       "ld1",  ".4s",    0, false, 0  },
     403             :   { AArch64::LD1Threev2d,       "ld1",  ".2d",    0, false, 0  },
     404             :   { AArch64::LD1Threev8b,       "ld1",  ".8b",    0, false, 0  },
     405             :   { AArch64::LD1Threev4h,       "ld1",  ".4h",    0, false, 0  },
     406             :   { AArch64::LD1Threev2s,       "ld1",  ".2s",    0, false, 0  },
     407             :   { AArch64::LD1Threev1d,       "ld1",  ".1d",    0, false, 0  },
     408             :   { AArch64::LD1Threev16b_POST, "ld1",  ".16b",   1, false, 48 },
     409             :   { AArch64::LD1Threev8h_POST,  "ld1",  ".8h",    1, false, 48 },
     410             :   { AArch64::LD1Threev4s_POST,  "ld1",  ".4s",    1, false, 48 },
     411             :   { AArch64::LD1Threev2d_POST,  "ld1",  ".2d",    1, false, 48 },
     412             :   { AArch64::LD1Threev8b_POST,  "ld1",  ".8b",    1, false, 24 },
     413             :   { AArch64::LD1Threev4h_POST,  "ld1",  ".4h",    1, false, 24 },
     414             :   { AArch64::LD1Threev2s_POST,  "ld1",  ".2s",    1, false, 24 },
     415             :   { AArch64::LD1Threev1d_POST,  "ld1",  ".1d",    1, false, 24 },
     416             :   { AArch64::LD1Fourv16b,       "ld1",  ".16b",   0, false, 0  },
     417             :   { AArch64::LD1Fourv8h,        "ld1",  ".8h",    0, false, 0  },
     418             :   { AArch64::LD1Fourv4s,        "ld1",  ".4s",    0, false, 0  },
     419             :   { AArch64::LD1Fourv2d,        "ld1",  ".2d",    0, false, 0  },
     420             :   { AArch64::LD1Fourv8b,        "ld1",  ".8b",    0, false, 0  },
     421             :   { AArch64::LD1Fourv4h,        "ld1",  ".4h",    0, false, 0  },
     422             :   { AArch64::LD1Fourv2s,        "ld1",  ".2s",    0, false, 0  },
     423             :   { AArch64::LD1Fourv1d,        "ld1",  ".1d",    0, false, 0  },
     424             :   { AArch64::LD1Fourv16b_POST,  "ld1",  ".16b",   1, false, 64 },
     425             :   { AArch64::LD1Fourv8h_POST,   "ld1",  ".8h",    1, false, 64 },
     426             :   { AArch64::LD1Fourv4s_POST,   "ld1",  ".4s",    1, false, 64 },
     427             :   { AArch64::LD1Fourv2d_POST,   "ld1",  ".2d",    1, false, 64 },
     428             :   { AArch64::LD1Fourv8b_POST,   "ld1",  ".8b",    1, false, 32 },
     429             :   { AArch64::LD1Fourv4h_POST,   "ld1",  ".4h",    1, false, 32 },
     430             :   { AArch64::LD1Fourv2s_POST,   "ld1",  ".2s",    1, false, 32 },
     431             :   { AArch64::LD1Fourv1d_POST,   "ld1",  ".1d",    1, false, 32 },
     432             :   { AArch64::LD2i8,             "ld2",  ".b",     1, true,  0  },
     433             :   { AArch64::LD2i16,            "ld2",  ".h",     1, true,  0  },
     434             :   { AArch64::LD2i32,            "ld2",  ".s",     1, true,  0  },
     435             :   { AArch64::LD2i64,            "ld2",  ".d",     1, true,  0  },
     436             :   { AArch64::LD2i8_POST,        "ld2",  ".b",     2, true,  2  },
     437             :   { AArch64::LD2i16_POST,       "ld2",  ".h",     2, true,  4  },
     438             :   { AArch64::LD2i32_POST,       "ld2",  ".s",     2, true,  8  },
     439             :   { AArch64::LD2i64_POST,       "ld2",  ".d",     2, true,  16  },
     440             :   { AArch64::LD2Rv16b,          "ld2r", ".16b",   0, false, 0  },
     441             :   { AArch64::LD2Rv8h,           "ld2r", ".8h",    0, false, 0  },
     442             :   { AArch64::LD2Rv4s,           "ld2r", ".4s",    0, false, 0  },
     443             :   { AArch64::LD2Rv2d,           "ld2r", ".2d",    0, false, 0  },
     444             :   { AArch64::LD2Rv8b,           "ld2r", ".8b",    0, false, 0  },
     445             :   { AArch64::LD2Rv4h,           "ld2r", ".4h",    0, false, 0  },
     446             :   { AArch64::LD2Rv2s,           "ld2r", ".2s",    0, false, 0  },
     447             :   { AArch64::LD2Rv1d,           "ld2r", ".1d",    0, false, 0  },
     448             :   { AArch64::LD2Rv16b_POST,     "ld2r", ".16b",   1, false, 2  },
     449             :   { AArch64::LD2Rv8h_POST,      "ld2r", ".8h",    1, false, 4  },
     450             :   { AArch64::LD2Rv4s_POST,      "ld2r", ".4s",    1, false, 8  },
     451             :   { AArch64::LD2Rv2d_POST,      "ld2r", ".2d",    1, false, 16 },
     452             :   { AArch64::LD2Rv8b_POST,      "ld2r", ".8b",    1, false, 2  },
     453             :   { AArch64::LD2Rv4h_POST,      "ld2r", ".4h",    1, false, 4  },
     454             :   { AArch64::LD2Rv2s_POST,      "ld2r", ".2s",    1, false, 8  },
     455             :   { AArch64::LD2Rv1d_POST,      "ld2r", ".1d",    1, false, 16 },
     456             :   { AArch64::LD2Twov16b,        "ld2",  ".16b",   0, false, 0  },
     457             :   { AArch64::LD2Twov8h,         "ld2",  ".8h",    0, false, 0  },
     458             :   { AArch64::LD2Twov4s,         "ld2",  ".4s",    0, false, 0  },
     459             :   { AArch64::LD2Twov2d,         "ld2",  ".2d",    0, false, 0  },
     460             :   { AArch64::LD2Twov8b,         "ld2",  ".8b",    0, false, 0  },
     461             :   { AArch64::LD2Twov4h,         "ld2",  ".4h",    0, false, 0  },
     462             :   { AArch64::LD2Twov2s,         "ld2",  ".2s",    0, false, 0  },
     463             :   { AArch64::LD2Twov16b_POST,   "ld2",  ".16b",   1, false, 32 },
     464             :   { AArch64::LD2Twov8h_POST,    "ld2",  ".8h",    1, false, 32 },
     465             :   { AArch64::LD2Twov4s_POST,    "ld2",  ".4s",    1, false, 32 },
     466             :   { AArch64::LD2Twov2d_POST,    "ld2",  ".2d",    1, false, 32 },
     467             :   { AArch64::LD2Twov8b_POST,    "ld2",  ".8b",    1, false, 16 },
     468             :   { AArch64::LD2Twov4h_POST,    "ld2",  ".4h",    1, false, 16 },
     469             :   { AArch64::LD2Twov2s_POST,    "ld2",  ".2s",    1, false, 16 },
     470             :   { AArch64::LD3i8,             "ld3",  ".b",     1, true,  0  },
     471             :   { AArch64::LD3i16,            "ld3",  ".h",     1, true,  0  },
     472             :   { AArch64::LD3i32,            "ld3",  ".s",     1, true,  0  },
     473             :   { AArch64::LD3i64,            "ld3",  ".d",     1, true,  0  },
     474             :   { AArch64::LD3i8_POST,        "ld3",  ".b",     2, true,  3  },
     475             :   { AArch64::LD3i16_POST,       "ld3",  ".h",     2, true,  6  },
     476             :   { AArch64::LD3i32_POST,       "ld3",  ".s",     2, true,  12 },
     477             :   { AArch64::LD3i64_POST,       "ld3",  ".d",     2, true,  24 },
     478             :   { AArch64::LD3Rv16b,          "ld3r", ".16b",   0, false, 0  },
     479             :   { AArch64::LD3Rv8h,           "ld3r", ".8h",    0, false, 0  },
     480             :   { AArch64::LD3Rv4s,           "ld3r", ".4s",    0, false, 0  },
     481             :   { AArch64::LD3Rv2d,           "ld3r", ".2d",    0, false, 0  },
     482             :   { AArch64::LD3Rv8b,           "ld3r", ".8b",    0, false, 0  },
     483             :   { AArch64::LD3Rv4h,           "ld3r", ".4h",    0, false, 0  },
     484             :   { AArch64::LD3Rv2s,           "ld3r", ".2s",    0, false, 0  },
     485             :   { AArch64::LD3Rv1d,           "ld3r", ".1d",    0, false, 0  },
     486             :   { AArch64::LD3Rv16b_POST,     "ld3r", ".16b",   1, false, 3  },
     487             :   { AArch64::LD3Rv8h_POST,      "ld3r", ".8h",    1, false, 6  },
     488             :   { AArch64::LD3Rv4s_POST,      "ld3r", ".4s",    1, false, 12 },
     489             :   { AArch64::LD3Rv2d_POST,      "ld3r", ".2d",    1, false, 24 },
     490             :   { AArch64::LD3Rv8b_POST,      "ld3r", ".8b",    1, false, 3  },
     491             :   { AArch64::LD3Rv4h_POST,      "ld3r", ".4h",    1, false, 6  },
     492             :   { AArch64::LD3Rv2s_POST,      "ld3r", ".2s",    1, false, 12 },
     493             :   { AArch64::LD3Rv1d_POST,      "ld3r", ".1d",    1, false, 24 },
     494             :   { AArch64::LD3Threev16b,      "ld3",  ".16b",   0, false, 0  },
     495             :   { AArch64::LD3Threev8h,       "ld3",  ".8h",    0, false, 0  },
     496             :   { AArch64::LD3Threev4s,       "ld3",  ".4s",    0, false, 0  },
     497             :   { AArch64::LD3Threev2d,       "ld3",  ".2d",    0, false, 0  },
     498             :   { AArch64::LD3Threev8b,       "ld3",  ".8b",    0, false, 0  },
     499             :   { AArch64::LD3Threev4h,       "ld3",  ".4h",    0, false, 0  },
     500             :   { AArch64::LD3Threev2s,       "ld3",  ".2s",    0, false, 0  },
     501             :   { AArch64::LD3Threev16b_POST, "ld3",  ".16b",   1, false, 48 },
     502             :   { AArch64::LD3Threev8h_POST,  "ld3",  ".8h",    1, false, 48 },
     503             :   { AArch64::LD3Threev4s_POST,  "ld3",  ".4s",    1, false, 48 },
     504             :   { AArch64::LD3Threev2d_POST,  "ld3",  ".2d",    1, false, 48 },
     505             :   { AArch64::LD3Threev8b_POST,  "ld3",  ".8b",    1, false, 24 },
     506             :   { AArch64::LD3Threev4h_POST,  "ld3",  ".4h",    1, false, 24 },
     507             :   { AArch64::LD3Threev2s_POST,  "ld3",  ".2s",    1, false, 24 },
     508             :   { AArch64::LD4i8,             "ld4",  ".b",     1, true,  0  },
     509             :   { AArch64::LD4i16,            "ld4",  ".h",     1, true,  0  },
     510             :   { AArch64::LD4i32,            "ld4",  ".s",     1, true,  0  },
     511             :   { AArch64::LD4i64,            "ld4",  ".d",     1, true,  0  },
     512             :   { AArch64::LD4i8_POST,        "ld4",  ".b",     2, true,  4  },
     513             :   { AArch64::LD4i16_POST,       "ld4",  ".h",     2, true,  8  },
     514             :   { AArch64::LD4i32_POST,       "ld4",  ".s",     2, true,  16 },
     515             :   { AArch64::LD4i64_POST,       "ld4",  ".d",     2, true,  32 },
     516             :   { AArch64::LD4Rv16b,          "ld4r", ".16b",   0, false, 0  },
     517             :   { AArch64::LD4Rv8h,           "ld4r", ".8h",    0, false, 0  },
     518             :   { AArch64::LD4Rv4s,           "ld4r", ".4s",    0, false, 0  },
     519             :   { AArch64::LD4Rv2d,           "ld4r", ".2d",    0, false, 0  },
     520             :   { AArch64::LD4Rv8b,           "ld4r", ".8b",    0, false, 0  },
     521             :   { AArch64::LD4Rv4h,           "ld4r", ".4h",    0, false, 0  },
     522             :   { AArch64::LD4Rv2s,           "ld4r", ".2s",    0, false, 0  },
     523             :   { AArch64::LD4Rv1d,           "ld4r", ".1d",    0, false, 0  },
     524             :   { AArch64::LD4Rv16b_POST,     "ld4r", ".16b",   1, false, 4  },
     525             :   { AArch64::LD4Rv8h_POST,      "ld4r", ".8h",    1, false, 8  },
     526             :   { AArch64::LD4Rv4s_POST,      "ld4r", ".4s",    1, false, 16 },
     527             :   { AArch64::LD4Rv2d_POST,      "ld4r", ".2d",    1, false, 32 },
     528             :   { AArch64::LD4Rv8b_POST,      "ld4r", ".8b",    1, false, 4  },
     529             :   { AArch64::LD4Rv4h_POST,      "ld4r", ".4h",    1, false, 8  },
     530             :   { AArch64::LD4Rv2s_POST,      "ld4r", ".2s",    1, false, 16 },
     531             :   { AArch64::LD4Rv1d_POST,      "ld4r", ".1d",    1, false, 32 },
     532             :   { AArch64::LD4Fourv16b,       "ld4",  ".16b",   0, false, 0  },
     533             :   { AArch64::LD4Fourv8h,        "ld4",  ".8h",    0, false, 0  },
     534             :   { AArch64::LD4Fourv4s,        "ld4",  ".4s",    0, false, 0  },
     535             :   { AArch64::LD4Fourv2d,        "ld4",  ".2d",    0, false, 0  },
     536             :   { AArch64::LD4Fourv8b,        "ld4",  ".8b",    0, false, 0  },
     537             :   { AArch64::LD4Fourv4h,        "ld4",  ".4h",    0, false, 0  },
     538             :   { AArch64::LD4Fourv2s,        "ld4",  ".2s",    0, false, 0  },
     539             :   { AArch64::LD4Fourv16b_POST,  "ld4",  ".16b",   1, false, 64 },
     540             :   { AArch64::LD4Fourv8h_POST,   "ld4",  ".8h",    1, false, 64 },
     541             :   { AArch64::LD4Fourv4s_POST,   "ld4",  ".4s",    1, false, 64 },
     542             :   { AArch64::LD4Fourv2d_POST,   "ld4",  ".2d",    1, false, 64 },
     543             :   { AArch64::LD4Fourv8b_POST,   "ld4",  ".8b",    1, false, 32 },
     544             :   { AArch64::LD4Fourv4h_POST,   "ld4",  ".4h",    1, false, 32 },
     545             :   { AArch64::LD4Fourv2s_POST,   "ld4",  ".2s",    1, false, 32 },
     546             :   { AArch64::ST1i8,             "st1",  ".b",     0, true,  0  },
     547             :   { AArch64::ST1i16,            "st1",  ".h",     0, true,  0  },
     548             :   { AArch64::ST1i32,            "st1",  ".s",     0, true,  0  },
     549             :   { AArch64::ST1i64,            "st1",  ".d",     0, true,  0  },
     550             :   { AArch64::ST1i8_POST,        "st1",  ".b",     1, true,  1  },
     551             :   { AArch64::ST1i16_POST,       "st1",  ".h",     1, true,  2  },
     552             :   { AArch64::ST1i32_POST,       "st1",  ".s",     1, true,  4  },
     553             :   { AArch64::ST1i64_POST,       "st1",  ".d",     1, true,  8  },
     554             :   { AArch64::ST1Onev16b,        "st1",  ".16b",   0, false, 0  },
     555             :   { AArch64::ST1Onev8h,         "st1",  ".8h",    0, false, 0  },
     556             :   { AArch64::ST1Onev4s,         "st1",  ".4s",    0, false, 0  },
     557             :   { AArch64::ST1Onev2d,         "st1",  ".2d",    0, false, 0  },
     558             :   { AArch64::ST1Onev8b,         "st1",  ".8b",    0, false, 0  },
     559             :   { AArch64::ST1Onev4h,         "st1",  ".4h",    0, false, 0  },
     560             :   { AArch64::ST1Onev2s,         "st1",  ".2s",    0, false, 0  },
     561             :   { AArch64::ST1Onev1d,         "st1",  ".1d",    0, false, 0  },
     562             :   { AArch64::ST1Onev16b_POST,   "st1",  ".16b",   1, false, 16 },
     563             :   { AArch64::ST1Onev8h_POST,    "st1",  ".8h",    1, false, 16 },
     564             :   { AArch64::ST1Onev4s_POST,    "st1",  ".4s",    1, false, 16 },
     565             :   { AArch64::ST1Onev2d_POST,    "st1",  ".2d",    1, false, 16 },
     566             :   { AArch64::ST1Onev8b_POST,    "st1",  ".8b",    1, false, 8  },
     567             :   { AArch64::ST1Onev4h_POST,    "st1",  ".4h",    1, false, 8  },
     568             :   { AArch64::ST1Onev2s_POST,    "st1",  ".2s",    1, false, 8  },
     569             :   { AArch64::ST1Onev1d_POST,    "st1",  ".1d",    1, false, 8  },
     570             :   { AArch64::ST1Twov16b,        "st1",  ".16b",   0, false, 0  },
     571             :   { AArch64::ST1Twov8h,         "st1",  ".8h",    0, false, 0  },
     572             :   { AArch64::ST1Twov4s,         "st1",  ".4s",    0, false, 0  },
     573             :   { AArch64::ST1Twov2d,         "st1",  ".2d",    0, false, 0  },
     574             :   { AArch64::ST1Twov8b,         "st1",  ".8b",    0, false, 0  },
     575             :   { AArch64::ST1Twov4h,         "st1",  ".4h",    0, false, 0  },
     576             :   { AArch64::ST1Twov2s,         "st1",  ".2s",    0, false, 0  },
     577             :   { AArch64::ST1Twov1d,         "st1",  ".1d",    0, false, 0  },
     578             :   { AArch64::ST1Twov16b_POST,   "st1",  ".16b",   1, false, 32 },
     579             :   { AArch64::ST1Twov8h_POST,    "st1",  ".8h",    1, false, 32 },
     580             :   { AArch64::ST1Twov4s_POST,    "st1",  ".4s",    1, false, 32 },
     581             :   { AArch64::ST1Twov2d_POST,    "st1",  ".2d",    1, false, 32 },
     582             :   { AArch64::ST1Twov8b_POST,    "st1",  ".8b",    1, false, 16 },
     583             :   { AArch64::ST1Twov4h_POST,    "st1",  ".4h",    1, false, 16 },
     584             :   { AArch64::ST1Twov2s_POST,    "st1",  ".2s",    1, false, 16 },
     585             :   { AArch64::ST1Twov1d_POST,    "st1",  ".1d",    1, false, 16 },
     586             :   { AArch64::ST1Threev16b,      "st1",  ".16b",   0, false, 0  },
     587             :   { AArch64::ST1Threev8h,       "st1",  ".8h",    0, false, 0  },
     588             :   { AArch64::ST1Threev4s,       "st1",  ".4s",    0, false, 0  },
     589             :   { AArch64::ST1Threev2d,       "st1",  ".2d",    0, false, 0  },
     590             :   { AArch64::ST1Threev8b,       "st1",  ".8b",    0, false, 0  },
     591             :   { AArch64::ST1Threev4h,       "st1",  ".4h",    0, false, 0  },
     592             :   { AArch64::ST1Threev2s,       "st1",  ".2s",    0, false, 0  },
     593             :   { AArch64::ST1Threev1d,       "st1",  ".1d",    0, false, 0  },
     594             :   { AArch64::ST1Threev16b_POST, "st1",  ".16b",   1, false, 48 },
     595             :   { AArch64::ST1Threev8h_POST,  "st1",  ".8h",    1, false, 48 },
     596             :   { AArch64::ST1Threev4s_POST,  "st1",  ".4s",    1, false, 48 },
     597             :   { AArch64::ST1Threev2d_POST,  "st1",  ".2d",    1, false, 48 },
     598             :   { AArch64::ST1Threev8b_POST,  "st1",  ".8b",    1, false, 24 },
     599             :   { AArch64::ST1Threev4h_POST,  "st1",  ".4h",    1, false, 24 },
     600             :   { AArch64::ST1Threev2s_POST,  "st1",  ".2s",    1, false, 24 },
     601             :   { AArch64::ST1Threev1d_POST,  "st1",  ".1d",    1, false, 24 },
     602             :   { AArch64::ST1Fourv16b,       "st1",  ".16b",   0, false, 0  },
     603             :   { AArch64::ST1Fourv8h,        "st1",  ".8h",    0, false, 0  },
     604             :   { AArch64::ST1Fourv4s,        "st1",  ".4s",    0, false, 0  },
     605             :   { AArch64::ST1Fourv2d,        "st1",  ".2d",    0, false, 0  },
     606             :   { AArch64::ST1Fourv8b,        "st1",  ".8b",    0, false, 0  },
     607             :   { AArch64::ST1Fourv4h,        "st1",  ".4h",    0, false, 0  },
     608             :   { AArch64::ST1Fourv2s,        "st1",  ".2s",    0, false, 0  },
     609             :   { AArch64::ST1Fourv1d,        "st1",  ".1d",    0, false, 0  },
     610             :   { AArch64::ST1Fourv16b_POST,  "st1",  ".16b",   1, false, 64 },
     611             :   { AArch64::ST1Fourv8h_POST,   "st1",  ".8h",    1, false, 64 },
     612             :   { AArch64::ST1Fourv4s_POST,   "st1",  ".4s",    1, false, 64 },
     613             :   { AArch64::ST1Fourv2d_POST,   "st1",  ".2d",    1, false, 64 },
     614             :   { AArch64::ST1Fourv8b_POST,   "st1",  ".8b",    1, false, 32 },
     615             :   { AArch64::ST1Fourv4h_POST,   "st1",  ".4h",    1, false, 32 },
     616             :   { AArch64::ST1Fourv2s_POST,   "st1",  ".2s",    1, false, 32 },
     617             :   { AArch64::ST1Fourv1d_POST,   "st1",  ".1d",    1, false, 32 },
     618             :   { AArch64::ST2i8,             "st2",  ".b",     0, true,  0  },
     619             :   { AArch64::ST2i16,            "st2",  ".h",     0, true,  0  },
     620             :   { AArch64::ST2i32,            "st2",  ".s",     0, true,  0  },
     621             :   { AArch64::ST2i64,            "st2",  ".d",     0, true,  0  },
     622             :   { AArch64::ST2i8_POST,        "st2",  ".b",     1, true,  2  },
     623             :   { AArch64::ST2i16_POST,       "st2",  ".h",     1, true,  4  },
     624             :   { AArch64::ST2i32_POST,       "st2",  ".s",     1, true,  8  },
     625             :   { AArch64::ST2i64_POST,       "st2",  ".d",     1, true,  16 },
     626             :   { AArch64::ST2Twov16b,        "st2",  ".16b",   0, false, 0  },
     627             :   { AArch64::ST2Twov8h,         "st2",  ".8h",    0, false, 0  },
     628             :   { AArch64::ST2Twov4s,         "st2",  ".4s",    0, false, 0  },
     629             :   { AArch64::ST2Twov2d,         "st2",  ".2d",    0, false, 0  },
     630             :   { AArch64::ST2Twov8b,         "st2",  ".8b",    0, false, 0  },
     631             :   { AArch64::ST2Twov4h,         "st2",  ".4h",    0, false, 0  },
     632             :   { AArch64::ST2Twov2s,         "st2",  ".2s",    0, false, 0  },
     633             :   { AArch64::ST2Twov16b_POST,   "st2",  ".16b",   1, false, 32 },
     634             :   { AArch64::ST2Twov8h_POST,    "st2",  ".8h",    1, false, 32 },
     635             :   { AArch64::ST2Twov4s_POST,    "st2",  ".4s",    1, false, 32 },
     636             :   { AArch64::ST2Twov2d_POST,    "st2",  ".2d",    1, false, 32 },
     637             :   { AArch64::ST2Twov8b_POST,    "st2",  ".8b",    1, false, 16 },
     638             :   { AArch64::ST2Twov4h_POST,    "st2",  ".4h",    1, false, 16 },
     639             :   { AArch64::ST2Twov2s_POST,    "st2",  ".2s",    1, false, 16 },
     640             :   { AArch64::ST3i8,             "st3",  ".b",     0, true,  0  },
     641             :   { AArch64::ST3i16,            "st3",  ".h",     0, true,  0  },
     642             :   { AArch64::ST3i32,            "st3",  ".s",     0, true,  0  },
     643             :   { AArch64::ST3i64,            "st3",  ".d",     0, true,  0  },
     644             :   { AArch64::ST3i8_POST,        "st3",  ".b",     1, true,  3  },
     645             :   { AArch64::ST3i16_POST,       "st3",  ".h",     1, true,  6  },
     646             :   { AArch64::ST3i32_POST,       "st3",  ".s",     1, true,  12 },
     647             :   { AArch64::ST3i64_POST,       "st3",  ".d",     1, true,  24 },
     648             :   { AArch64::ST3Threev16b,      "st3",  ".16b",   0, false, 0  },
     649             :   { AArch64::ST3Threev8h,       "st3",  ".8h",    0, false, 0  },
     650             :   { AArch64::ST3Threev4s,       "st3",  ".4s",    0, false, 0  },
     651             :   { AArch64::ST3Threev2d,       "st3",  ".2d",    0, false, 0  },
     652             :   { AArch64::ST3Threev8b,       "st3",  ".8b",    0, false, 0  },
     653             :   { AArch64::ST3Threev4h,       "st3",  ".4h",    0, false, 0  },
     654             :   { AArch64::ST3Threev2s,       "st3",  ".2s",    0, false, 0  },
     655             :   { AArch64::ST3Threev16b_POST, "st3",  ".16b",   1, false, 48 },
     656             :   { AArch64::ST3Threev8h_POST,  "st3",  ".8h",    1, false, 48 },
     657             :   { AArch64::ST3Threev4s_POST,  "st3",  ".4s",    1, false, 48 },
     658             :   { AArch64::ST3Threev2d_POST,  "st3",  ".2d",    1, false, 48 },
     659             :   { AArch64::ST3Threev8b_POST,  "st3",  ".8b",    1, false, 24 },
     660             :   { AArch64::ST3Threev4h_POST,  "st3",  ".4h",    1, false, 24 },
     661             :   { AArch64::ST3Threev2s_POST,  "st3",  ".2s",    1, false, 24 },
     662             :   { AArch64::ST4i8,             "st4",  ".b",     0, true,  0  },
     663             :   { AArch64::ST4i16,            "st4",  ".h",     0, true,  0  },
     664             :   { AArch64::ST4i32,            "st4",  ".s",     0, true,  0  },
     665             :   { AArch64::ST4i64,            "st4",  ".d",     0, true,  0  },
     666             :   { AArch64::ST4i8_POST,        "st4",  ".b",     1, true,  4  },
     667             :   { AArch64::ST4i16_POST,       "st4",  ".h",     1, true,  8  },
     668             :   { AArch64::ST4i32_POST,       "st4",  ".s",     1, true,  16 },
     669             :   { AArch64::ST4i64_POST,       "st4",  ".d",     1, true,  32 },
     670             :   { AArch64::ST4Fourv16b,       "st4",  ".16b",   0, false, 0  },
     671             :   { AArch64::ST4Fourv8h,        "st4",  ".8h",    0, false, 0  },
     672             :   { AArch64::ST4Fourv4s,        "st4",  ".4s",    0, false, 0  },
     673             :   { AArch64::ST4Fourv2d,        "st4",  ".2d",    0, false, 0  },
     674             :   { AArch64::ST4Fourv8b,        "st4",  ".8b",    0, false, 0  },
     675             :   { AArch64::ST4Fourv4h,        "st4",  ".4h",    0, false, 0  },
     676             :   { AArch64::ST4Fourv2s,        "st4",  ".2s",    0, false, 0  },
     677             :   { AArch64::ST4Fourv16b_POST,  "st4",  ".16b",   1, false, 64 },
     678             :   { AArch64::ST4Fourv8h_POST,   "st4",  ".8h",    1, false, 64 },
     679             :   { AArch64::ST4Fourv4s_POST,   "st4",  ".4s",    1, false, 64 },
     680             :   { AArch64::ST4Fourv2d_POST,   "st4",  ".2d",    1, false, 64 },
     681             :   { AArch64::ST4Fourv8b_POST,   "st4",  ".8b",    1, false, 32 },
     682             :   { AArch64::ST4Fourv4h_POST,   "st4",  ".4h",    1, false, 32 },
     683             :   { AArch64::ST4Fourv2s_POST,   "st4",  ".2s",    1, false, 32 },
     684             : };
     685             : 
     686             : static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
     687             :   unsigned Idx;
     688     9551614 :   for (Idx = 0; Idx != array_lengthof(LdStNInstInfo); ++Idx)
     689     9524799 :     if (LdStNInstInfo[Idx].Opcode == Opcode)
     690        2314 :       return &LdStNInstInfo[Idx];
     691             : 
     692             :   return nullptr;
     693             : }
     694             : 
     695       29179 : void AArch64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
     696             :                                         StringRef Annot,
     697             :                                         const MCSubtargetInfo &STI) {
     698       29179 :   unsigned Opcode = MI->getOpcode();
     699       29179 :   StringRef Layout;
     700             : 
     701             :   bool IsTbx;
     702             :   if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
     703          84 :     O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t'
     704          50 :       << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", ";
     705             : 
     706          50 :     unsigned ListOpNum = IsTbx ? 2 : 1;
     707         100 :     printVectorList(MI, ListOpNum, STI, O, "");
     708             : 
     709          50 :     O << ", "
     710         100 :       << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
     711          50 :     printAnnotation(O, Annot);
     712        2364 :     return;
     713             :   }
     714             : 
     715       29129 :   if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
     716        2314 :     O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
     717             : 
     718             :     // Now onto the operands: first a vector list with possible lane
     719             :     // specifier. E.g. { v0 }[2]
     720        2314 :     int OpNum = LdStDesc->ListOperand;
     721        4628 :     printVectorList(MI, OpNum++, STI, O, "");
     722             : 
     723        2314 :     if (LdStDesc->HasLane)
     724        1172 :       O << '[' << MI->getOperand(OpNum++).getImm() << ']';
     725             : 
     726             :     // Next the address: [xN]
     727        2314 :     unsigned AddrReg = MI->getOperand(OpNum++).getReg();
     728        2314 :     O << ", [" << getRegisterName(AddrReg) << ']';
     729             : 
     730             :     // Finally, there might be a post-indexed offset.
     731        2314 :     if (LdStDesc->NaturalOffset != 0) {
     732        1521 :       unsigned Reg = MI->getOperand(OpNum++).getReg();
     733        1521 :       if (Reg != AArch64::XZR)
     734         735 :         O << ", " << getRegisterName(Reg);
     735             :       else {
     736             :         assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
     737         786 :         O << ", #" << LdStDesc->NaturalOffset;
     738             :       }
     739             :     }
     740             : 
     741        2314 :     printAnnotation(O, Annot);
     742        2314 :     return;
     743             :   }
     744             : 
     745       26815 :   AArch64InstPrinter::printInst(MI, O, Annot, STI);
     746             : }
     747             : 
     748         375 : bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
     749             :                                        const MCSubtargetInfo &STI,
     750             :                                        raw_ostream &O) {
     751             : #ifndef NDEBUG
     752             :   unsigned Opcode = MI->getOpcode();
     753             :   assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
     754             : #endif
     755             : 
     756             :   const MCOperand &Op1 = MI->getOperand(0);
     757             :   const MCOperand &Cn = MI->getOperand(1);
     758             :   const MCOperand &Cm = MI->getOperand(2);
     759             :   const MCOperand &Op2 = MI->getOperand(3);
     760             : 
     761         375 :   unsigned Op1Val = Op1.getImm();
     762         375 :   unsigned CnVal = Cn.getImm();
     763         375 :   unsigned CmVal = Cm.getImm();
     764         375 :   unsigned Op2Val = Op2.getImm();
     765             : 
     766         375 :   uint16_t Encoding = Op2Val;
     767         375 :   Encoding |= CmVal << 3;
     768         375 :   Encoding |= CnVal << 7;
     769         375 :   Encoding |= Op1Val << 11;
     770             : 
     771             :   bool NeedsReg;
     772             :   std::string Ins;
     773             :   std::string Name;
     774             : 
     775         375 :   if (CnVal == 7) {
     776             :     switch (CmVal) {
     777             :     default: return false;
     778             :     // IC aliases
     779          21 :     case 1: case 5: {
     780          21 :       const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding);
     781          42 :       if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
     782           0 :         return false;
     783             : 
     784          21 :       NeedsReg = IC->NeedsReg;
     785             :       Ins = "ic\t";
     786          21 :       Name = std::string(IC->Name);
     787             :     }
     788          21 :     break;
     789             :     // DC aliases
     790          60 :     case 4: case 6: case 10: case 11: case 12: case 14:
     791             :     {
     792          60 :       const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
     793         120 :       if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
     794           1 :         return false;
     795             : 
     796             :       NeedsReg = true;
     797             :       Ins = "dc\t";
     798          59 :       Name = std::string(DC->Name);
     799             :     }
     800          59 :     break;
     801             :     // AT aliases
     802          42 :     case 8: case 9: {
     803          42 :       const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
     804          84 :       if (!AT || !AT->haveFeatures(STI.getFeatureBits()))
     805           2 :         return false;
     806             : 
     807             :       NeedsReg = true;
     808             :       Ins = "at\t";
     809          40 :       Name = std::string(AT->Name);
     810             :     }
     811          40 :     break;
     812             :     }
     813         252 :   } else if (CnVal == 8) {
     814             :     // TLBI aliases
     815         236 :     const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
     816         472 :     if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
     817          46 :       return false;
     818             : 
     819         190 :     NeedsReg = TLBI->NeedsReg;
     820             :     Ins = "tlbi\t";
     821         380 :     Name = std::string(TLBI->Name);
     822             :   }
     823             :   else
     824             :     return false;
     825             : 
     826         310 :   std::string Str = Ins + Name;
     827             :   std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower);
     828             : 
     829             :   O << '\t' << Str;
     830         310 :   if (NeedsReg)
     831         256 :     O << ", " << getRegisterName(MI->getOperand(4).getReg());
     832             : 
     833             :   return true;
     834             : }
     835             : 
     836      132906 : void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
     837             :                                       const MCSubtargetInfo &STI,
     838             :                                       raw_ostream &O) {
     839             :   const MCOperand &Op = MI->getOperand(OpNo);
     840      132906 :   if (Op.isReg()) {
     841      125859 :     unsigned Reg = Op.getReg();
     842      125859 :     O << getRegisterName(Reg);
     843        7047 :   } else if (Op.isImm()) {
     844        6917 :     printImm(MI, OpNo, STI, O);
     845             :   } else {
     846             :     assert(Op.isExpr() && "unknown operand kind in printOperand");
     847         130 :     Op.getExpr()->print(O, &MAI);
     848             :   }
     849      132906 : }
     850             : 
     851        8027 : void AArch64InstPrinter::printImm(const MCInst *MI, unsigned OpNo,
     852             :                                      const MCSubtargetInfo &STI,
     853             :                                      raw_ostream &O) {
     854             :   const MCOperand &Op = MI->getOperand(OpNo);
     855        8027 :   O << "#" << formatImm(Op.getImm());
     856        8027 : }
     857             : 
     858         100 : void AArch64InstPrinter::printImmHex(const MCInst *MI, unsigned OpNo,
     859             :                                      const MCSubtargetInfo &STI,
     860             :                                      raw_ostream &O) {
     861             :   const MCOperand &Op = MI->getOperand(OpNo);
     862         200 :   O << format("#%#llx", Op.getImm());
     863         100 : }
     864             : 
     865         118 : void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
     866             :                                              unsigned Imm, raw_ostream &O) {
     867             :   const MCOperand &Op = MI->getOperand(OpNo);
     868         118 :   if (Op.isReg()) {
     869         118 :     unsigned Reg = Op.getReg();
     870         118 :     if (Reg == AArch64::XZR)
     871           0 :       O << "#" << Imm;
     872             :     else
     873         118 :       O << getRegisterName(Reg);
     874             :   } else
     875           0 :     llvm_unreachable("unknown operand kind in printPostIncOperand64");
     876         118 : }
     877             : 
     878       40388 : void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
     879             :                                           const MCSubtargetInfo &STI,
     880             :                                           raw_ostream &O) {
     881             :   const MCOperand &Op = MI->getOperand(OpNo);
     882             :   assert(Op.isReg() && "Non-register vreg operand!");
     883       40388 :   unsigned Reg = Op.getReg();
     884       40388 :   O << getRegisterName(Reg, AArch64::vreg);
     885       40388 : }
     886             : 
     887         156 : void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
     888             :                                            const MCSubtargetInfo &STI,
     889             :                                            raw_ostream &O) {
     890             :   const MCOperand &Op = MI->getOperand(OpNo);
     891             :   assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
     892         156 :   O << "c" << Op.getImm();
     893         156 : }
     894             : 
     895        5596 : void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
     896             :                                         const MCSubtargetInfo &STI,
     897             :                                         raw_ostream &O) {
     898             :   const MCOperand &MO = MI->getOperand(OpNum);
     899        5596 :   if (MO.isImm()) {
     900        3441 :     unsigned Val = (MO.getImm() & 0xfff);
     901             :     assert(Val == MO.getImm() && "Add/sub immediate out of range!");
     902             :     unsigned Shift =
     903        6882 :         AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
     904        3441 :     O << '#' << formatImm(Val);
     905        3441 :     if (Shift != 0)
     906         185 :       printShifter(MI, OpNum + 1, STI, O);
     907             : 
     908        3441 :     if (CommentStream)
     909        6444 :       *CommentStream << '=' << formatImm(Val << Shift) << '\n';
     910             :   } else {
     911             :     assert(MO.isExpr() && "Unexpected operand type!");
     912        2155 :     MO.getExpr()->print(O, &MAI);
     913        2155 :     printShifter(MI, OpNum + 1, STI, O);
     914             :   }
     915        5596 : }
     916             : 
     917             : template <typename T>
     918           0 : void AArch64InstPrinter::printLogicalImm(const MCInst *MI, unsigned OpNum,
     919             :                                          const MCSubtargetInfo &STI,
     920             :                                          raw_ostream &O) {
     921           0 :   uint64_t Val = MI->getOperand(OpNum).getImm();
     922           0 :   O << "#0x";
     923           0 :   O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 8 * sizeof(T)));
     924           0 : }
     925           0 : 
     926             : void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
     927             :                                       const MCSubtargetInfo &STI,
     928           0 :                                       raw_ostream &O) {
     929           0 :   unsigned Val = MI->getOperand(OpNum).getImm();
     930           0 :   // LSL #0 should not be printed.
     931           0 :   if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL &&
     932           0 :       AArch64_AM::getShiftValue(Val) == 0)
     933             :     return;
     934             :   O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val))
     935           0 :     << " #" << AArch64_AM::getShiftValue(Val);
     936           0 : }
     937           0 : 
     938           0 : void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
     939           0 :                                               const MCSubtargetInfo &STI,
     940             :                                               raw_ostream &O) {
     941             :   O << getRegisterName(MI->getOperand(OpNum).getReg());
     942           0 :   printShifter(MI, OpNum + 1, STI, O);
     943           0 : }
     944           0 : 
     945           0 : void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
     946           0 :                                                const MCSubtargetInfo &STI,
     947             :                                                raw_ostream &O) {
     948             :   O << getRegisterName(MI->getOperand(OpNum).getReg());
     949           0 :   printArithExtend(MI, OpNum + 1, STI, O);
     950           0 : }
     951           0 : 
     952           0 : void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
     953             :                                           const MCSubtargetInfo &STI,
     954        4480 :                                           raw_ostream &O) {
     955             :   unsigned Val = MI->getOperand(OpNum).getImm();
     956             :   AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val);
     957        4480 :   unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val);
     958             : 
     959        4480 :   // If the destination or first source register operand is [W]SP, print
     960             :   // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
     961             :   // all.
     962        4016 :   if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
     963        2008 :     unsigned Dest = MI->getOperand(0).getReg();
     964             :     unsigned Src1 = MI->getOperand(1).getReg();
     965             :     if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
     966         776 :           ExtType == AArch64_AM::UXTX) ||
     967             :          ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
     968             :           ExtType == AArch64_AM::UXTW) ) {
     969         776 :       if (ShiftVal != 0)
     970         776 :         O << ", lsl #" << ShiftVal;
     971         776 :       return;
     972             :     }
     973         291 :   }
     974             :   O << ", " << AArch64_AM::getShiftExtendName(ExtType);
     975             :   if (ShiftVal != 0)
     976         291 :     O << " #" << ShiftVal;
     977         291 : }
     978         291 : 
     979             : static void printMemExtendImpl(bool SignExtend, bool DoShift,
     980         437 :                                unsigned Width, char SrcRegKind,
     981             :                                raw_ostream &O) {
     982             :   // sxtw, sxtx, uxtw or lsl (== uxtx)
     983         437 :   bool IsLSL = !SignExtend && SrcRegKind == 'x';
     984             :   if (IsLSL)
     985             :     O << "lsl";
     986             :   else
     987             :     O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
     988             : 
     989             :   if (DoShift || IsLSL)
     990         437 :     O << " #" << Log2_32(Width / 8);
     991         101 : }
     992         101 : 
     993         101 : void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
     994          95 :                                         raw_ostream &O, char SrcRegKind,
     995          95 :                                         unsigned Width) {
     996             :   bool SignExtend = MI->getOperand(OpNum).getImm();
     997          10 :   bool DoShift = MI->getOperand(OpNum + 1).getImm();
     998          10 :   printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O);
     999          10 : }
    1000             : 
    1001             : template <bool SignExtend, int ExtWidth, char SrcRegKind, char Suffix>
    1002         427 : void AArch64InstPrinter::printRegWithShiftExtend(const MCInst *MI,
    1003         427 :                                                  unsigned OpNum,
    1004          88 :                                                  const MCSubtargetInfo &STI,
    1005             :                                                  raw_ostream &O) {
    1006             :   printOperand(MI, OpNum, STI, O);
    1007        1035 :   if (Suffix == 's' || Suffix == 'd')
    1008             :     O << '.' << Suffix;
    1009             :   else
    1010             :     assert(Suffix == 0 && "Unsupported suffix size");
    1011        1035 : 
    1012        1035 :   bool DoShift = ExtWidth != 8;
    1013         417 :   if (SignExtend || DoShift || SrcRegKind == 'w') {
    1014             :     O << ", ";
    1015        1236 :     printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O);
    1016             :   }
    1017        1035 : }
    1018         677 : 
    1019        1035 : void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
    1020             :                                        const MCSubtargetInfo &STI,
    1021         583 :                                        raw_ostream &O) {
    1022             :   AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
    1023             :   O << AArch64CC::getCondCodeName(CC);
    1024         583 : }
    1025         583 : 
    1026         583 : void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
    1027         583 :                                               const MCSubtargetInfo &STI,
    1028             :                                               raw_ostream &O) {
    1029             :   AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
    1030         498 :   O << AArch64CC::getCondCodeName(AArch64CC::getInvertedCondCode(CC));
    1031             : }
    1032             : 
    1033             : void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
    1034         570 :                                         const MCSubtargetInfo &STI,
    1035             :                                         raw_ostream &O) {
    1036             :   O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
    1037             : }
    1038             : 
    1039             : template<int Scale>
    1040             : void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
    1041             :                                        const MCSubtargetInfo &STI,
    1042         452 :                                        raw_ostream &O) {
    1043         452 :   O << '#' << formatImm(Scale * MI->getOperand(OpNum).getImm());
    1044             : }
    1045         498 : 
    1046          14 : void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
    1047             :                                            unsigned Scale, raw_ostream &O) {
    1048             :   const MCOperand MO = MI->getOperand(OpNum);
    1049             :   if (MO.isImm()) {
    1050          14 :     O << "#" << formatImm(MO.getImm() * Scale);
    1051             :   } else {
    1052             :     assert(MO.isExpr() && "Unexpected operand type!");
    1053             :     MO.getExpr()->print(O, &MAI);
    1054             :   }
    1055             : }
    1056             : 
    1057             : void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
    1058          14 :                                           unsigned Scale, raw_ostream &O) {
    1059          14 :   const MCOperand MO1 = MI->getOperand(OpNum + 1);
    1060             :   O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
    1061          14 :   if (MO1.isImm()) {
    1062          42 :       O << ", #" << formatImm(MO1.getImm() * Scale);
    1063             :   } else {
    1064             :     assert(MO1.isExpr() && "Unexpected operand type!");
    1065             :     O << ", ";
    1066          42 :     MO1.getExpr()->print(O, &MAI);
    1067             :   }
    1068             :   O << ']';
    1069             : }
    1070             : 
    1071             : template <bool IsSVEPrefetch>
    1072             : void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
    1073             :                                          const MCSubtargetInfo &STI,
    1074             :                                          raw_ostream &O) {
    1075             :   unsigned prfop = MI->getOperand(OpNum).getImm();
    1076             :   if (IsSVEPrefetch) {
    1077          42 :     if (auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) {
    1078          42 :       O << PRFM->Name;
    1079             :       return;
    1080             :     }
    1081             :   } else if (auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop)) {
    1082          42 :     O << PRFM->Name;
    1083             :     return;
    1084             :   }
    1085             : 
    1086             :   O << '#' << formatImm(prfop);
    1087             : }
    1088             : 
    1089             : void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
    1090          42 :                                         const MCSubtargetInfo &STI,
    1091          42 :                                         raw_ostream &O) {
    1092             :   unsigned psbhintop = MI->getOperand(OpNum).getImm();
    1093          42 :   auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
    1094          42 :   if (PSB)
    1095             :     O << PSB->Name;
    1096             :   else
    1097             :     O << '#' << formatImm(psbhintop);
    1098          42 : }
    1099             : 
    1100             : void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
    1101             :                                            const MCSubtargetInfo &STI,
    1102             :                                            raw_ostream &O) {
    1103             :   const MCOperand &MO = MI->getOperand(OpNum);
    1104             :   float FPImm =
    1105             :       MO.isFPImm() ? MO.getFPImm() : AArch64_AM::getFPImmFloat(MO.getImm());
    1106          42 : 
    1107          42 :   // 8 decimal places are enough to perfectly represent permitted floats.
    1108             :   O << format("#%.8f", FPImm);
    1109          42 : }
    1110          26 : 
    1111             : static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
    1112             :   while (Stride--) {
    1113             :     switch (Reg) {
    1114          26 :     default:
    1115             :       llvm_unreachable("Vector register expected!");
    1116             :     case AArch64::Q0:  Reg = AArch64::Q1;  break;
    1117             :     case AArch64::Q1:  Reg = AArch64::Q2;  break;
    1118             :     case AArch64::Q2:  Reg = AArch64::Q3;  break;
    1119             :     case AArch64::Q3:  Reg = AArch64::Q4;  break;
    1120             :     case AArch64::Q4:  Reg = AArch64::Q5;  break;
    1121             :     case AArch64::Q5:  Reg = AArch64::Q6;  break;
    1122          26 :     case AArch64::Q6:  Reg = AArch64::Q7;  break;
    1123          26 :     case AArch64::Q7:  Reg = AArch64::Q8;  break;
    1124             :     case AArch64::Q8:  Reg = AArch64::Q9;  break;
    1125          26 :     case AArch64::Q9:  Reg = AArch64::Q10; break;
    1126          30 :     case AArch64::Q10: Reg = AArch64::Q11; break;
    1127             :     case AArch64::Q11: Reg = AArch64::Q12; break;
    1128             :     case AArch64::Q12: Reg = AArch64::Q13; break;
    1129             :     case AArch64::Q13: Reg = AArch64::Q14; break;
    1130          30 :     case AArch64::Q14: Reg = AArch64::Q15; break;
    1131             :     case AArch64::Q15: Reg = AArch64::Q16; break;
    1132             :     case AArch64::Q16: Reg = AArch64::Q17; break;
    1133             :     case AArch64::Q17: Reg = AArch64::Q18; break;
    1134             :     case AArch64::Q18: Reg = AArch64::Q19; break;
    1135             :     case AArch64::Q19: Reg = AArch64::Q20; break;
    1136             :     case AArch64::Q20: Reg = AArch64::Q21; break;
    1137             :     case AArch64::Q21: Reg = AArch64::Q22; break;
    1138          30 :     case AArch64::Q22: Reg = AArch64::Q23; break;
    1139          30 :     case AArch64::Q23: Reg = AArch64::Q24; break;
    1140             :     case AArch64::Q24: Reg = AArch64::Q25; break;
    1141          30 :     case AArch64::Q25: Reg = AArch64::Q26; break;
    1142          10 :     case AArch64::Q26: Reg = AArch64::Q27; break;
    1143             :     case AArch64::Q27: Reg = AArch64::Q28; break;
    1144             :     case AArch64::Q28: Reg = AArch64::Q29; break;
    1145             :     case AArch64::Q29: Reg = AArch64::Q30; break;
    1146          10 :     case AArch64::Q30: Reg = AArch64::Q31; break;
    1147             :     // Vector lists can wrap around.
    1148             :     case AArch64::Q31:
    1149             :       Reg = AArch64::Q0;
    1150             :       break;
    1151             :     case AArch64::Z0:  Reg = AArch64::Z1;  break;
    1152             :     case AArch64::Z1:  Reg = AArch64::Z2;  break;
    1153             :     case AArch64::Z2:  Reg = AArch64::Z3;  break;
    1154          10 :     case AArch64::Z3:  Reg = AArch64::Z4;  break;
    1155          10 :     case AArch64::Z4:  Reg = AArch64::Z5;  break;
    1156             :     case AArch64::Z5:  Reg = AArch64::Z6;  break;
    1157          10 :     case AArch64::Z6:  Reg = AArch64::Z7;  break;
    1158          10 :     case AArch64::Z7:  Reg = AArch64::Z8;  break;
    1159             :     case AArch64::Z8:  Reg = AArch64::Z9;  break;
    1160             :     case AArch64::Z9:  Reg = AArch64::Z10; break;
    1161             :     case AArch64::Z10: Reg = AArch64::Z11; break;
    1162          10 :     case AArch64::Z11: Reg = AArch64::Z12; break;
    1163             :     case AArch64::Z12: Reg = AArch64::Z13; break;
    1164             :     case AArch64::Z13: Reg = AArch64::Z14; break;
    1165             :     case AArch64::Z14: Reg = AArch64::Z15; break;
    1166             :     case AArch64::Z15: Reg = AArch64::Z16; break;
    1167             :     case AArch64::Z16: Reg = AArch64::Z17; break;
    1168             :     case AArch64::Z17: Reg = AArch64::Z18; break;
    1169             :     case AArch64::Z18: Reg = AArch64::Z19; break;
    1170          10 :     case AArch64::Z19: Reg = AArch64::Z20; break;
    1171          10 :     case AArch64::Z20: Reg = AArch64::Z21; break;
    1172             :     case AArch64::Z21: Reg = AArch64::Z22; break;
    1173          10 :     case AArch64::Z22: Reg = AArch64::Z23; break;
    1174          10 :     case AArch64::Z23: Reg = AArch64::Z24; break;
    1175             :     case AArch64::Z24: Reg = AArch64::Z25; break;
    1176             :     case AArch64::Z25: Reg = AArch64::Z26; break;
    1177             :     case AArch64::Z26: Reg = AArch64::Z27; break;
    1178          10 :     case AArch64::Z27: Reg = AArch64::Z28; break;
    1179             :     case AArch64::Z28: Reg = AArch64::Z29; break;
    1180             :     case AArch64::Z29: Reg = AArch64::Z30; break;
    1181             :     case AArch64::Z30: Reg = AArch64::Z31; break;
    1182             :     // Vector lists can wrap around.
    1183             :     case AArch64::Z31:
    1184             :       Reg = AArch64::Z0;
    1185             :       break;
    1186          10 :     }
    1187          10 :   }
    1188             :   return Reg;
    1189          10 : }
    1190          38 : 
    1191             : template<unsigned size>
    1192             : void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI,
    1193             :                                                    unsigned OpNum,
    1194          38 :                                                    const MCSubtargetInfo &STI,
    1195             :                                                    raw_ostream &O) {
    1196             :   static_assert(size == 64 || size == 32,
    1197             :                 "Template parameter must be either 32 or 64");
    1198             :   unsigned Reg = MI->getOperand(OpNum).getReg();
    1199             : 
    1200             :   unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
    1201             :   unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
    1202          38 : 
    1203          38 :   unsigned Even = MRI.getSubReg(Reg,  Sube);
    1204             :   unsigned Odd = MRI.getSubReg(Reg,  Subo);
    1205          38 :   O << getRegisterName(Even) << ", " << getRegisterName(Odd);
    1206           2 : }
    1207             : 
    1208             : void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
    1209             :                                          const MCSubtargetInfo &STI,
    1210           2 :                                          raw_ostream &O,
    1211             :                                          StringRef LayoutSuffix) {
    1212             :   unsigned Reg = MI->getOperand(OpNum).getReg();
    1213             : 
    1214             :   O << "{ ";
    1215             : 
    1216             :   // Work out how many registers there are in the list (if there is an actual
    1217             :   // list).
    1218           2 :   unsigned NumRegs = 1;
    1219           2 :   if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
    1220             :       MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
    1221           2 :       MRI.getRegClass(AArch64::QQRegClassID).contains(Reg))
    1222           2 :     NumRegs = 2;
    1223             :   else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
    1224             :            MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
    1225             :            MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
    1226           2 :     NumRegs = 3;
    1227             :   else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
    1228             :            MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||
    1229             :            MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg))
    1230             :     NumRegs = 4;
    1231             : 
    1232             :   // Now forget about the list and find out what the first register is.
    1233             :   if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
    1234           2 :     Reg = FirstReg;
    1235           2 :   else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
    1236             :     Reg = FirstReg;
    1237           2 :   else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
    1238          14 :     Reg = FirstReg;
    1239             : 
    1240             :   // If it's a D-reg, we need to promote it to the equivalent Q-reg before
    1241             :   // printing (otherwise getRegisterName fails).
    1242          14 :   if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
    1243             :     const MCRegisterClass &FPR128RC =
    1244             :         MRI.getRegClass(AArch64::FPR128RegClassID);
    1245             :     Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
    1246             :   }
    1247             : 
    1248             :   for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
    1249             :     if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
    1250          14 :       O << getRegisterName(Reg) << LayoutSuffix;
    1251          14 :     else
    1252             :       O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix;
    1253          14 : 
    1254          14 :     if (i + 1 != NumRegs)
    1255             :       O << ", ";
    1256             :   }
    1257             : 
    1258          14 :   O << " }";
    1259             : }
    1260             : 
    1261             : void
    1262             : AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
    1263             :                                                    unsigned OpNum,
    1264             :                                                    const MCSubtargetInfo &STI,
    1265             :                                                    raw_ostream &O) {
    1266          14 :   printVectorList(MI, OpNum, STI, O, "");
    1267          14 : }
    1268             : 
    1269          14 : template <unsigned NumLanes, char LaneKind>
    1270           2 : void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
    1271             :                                               const MCSubtargetInfo &STI,
    1272             :                                               raw_ostream &O) {
    1273             :   std::string Suffix(".");
    1274           2 :   if (NumLanes)
    1275             :     Suffix += itostr(NumLanes) + LaneKind;
    1276             :   else
    1277             :     Suffix += LaneKind;
    1278             : 
    1279             :   printVectorList(MI, OpNum, STI, O, Suffix);
    1280             : }
    1281             : 
    1282           2 : void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
    1283           2 :                                           const MCSubtargetInfo &STI,
    1284             :                                           raw_ostream &O) {
    1285           2 :   O << "[" << MI->getOperand(OpNum).getImm() << "]";
    1286          60 : }
    1287             : 
    1288             : void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, unsigned OpNum,
    1289             :                                            const MCSubtargetInfo &STI,
    1290          60 :                                            raw_ostream &O) {
    1291             :   const MCOperand &Op = MI->getOperand(OpNum);
    1292             : 
    1293             :   // If the label has already been resolved to an immediate offset (say, when
    1294             :   // we're running the disassembler), just print the immediate.
    1295             :   if (Op.isImm()) {
    1296             :     O << "#" << formatImm(Op.getImm() * 4);
    1297             :     return;
    1298          60 :   }
    1299          60 : 
    1300             :   // If the branch target is simply an address then print it in hex.
    1301          60 :   const MCConstantExpr *BranchTarget =
    1302          12 :       dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
    1303             :   int64_t Address;
    1304             :   if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
    1305             :     O << "0x";
    1306          12 :     O.write_hex(Address);
    1307             :   } else {
    1308             :     // Otherwise, just print the expression.
    1309             :     MI->getOperand(OpNum).getExpr()->print(O, &MAI);
    1310             :   }
    1311             : }
    1312             : 
    1313             : void AArch64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum,
    1314          12 :                                         const MCSubtargetInfo &STI,
    1315          12 :                                         raw_ostream &O) {
    1316             :   const MCOperand &Op = MI->getOperand(OpNum);
    1317          12 : 
    1318          12 :   // If the label has already been resolved to an immediate offset (say, when
    1319             :   // we're running the disassembler), just print the immediate.
    1320             :   if (Op.isImm()) {
    1321             :     O << "#" << formatImm(Op.getImm() * (1 << 12));
    1322          12 :     return;
    1323             :   }
    1324             : 
    1325             :   // Otherwise, just print the expression.
    1326             :   MI->getOperand(OpNum).getExpr()->print(O, &MAI);
    1327             : }
    1328             : 
    1329             : void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
    1330          12 :                                             const MCSubtargetInfo &STI,
    1331          12 :                                             raw_ostream &O) {
    1332             :   unsigned Val = MI->getOperand(OpNo).getImm();
    1333          12 :   unsigned Opcode = MI->getOpcode();
    1334          50 : 
    1335             :   StringRef Name;
    1336             :   if (Opcode == AArch64::ISB) {
    1337             :     auto ISB = AArch64ISB::lookupISBByEncoding(Val);
    1338          50 :     Name = ISB ? ISB->Name : "";
    1339             :   } else if (Opcode == AArch64::TSB) {
    1340             :     auto TSB = AArch64TSB::lookupTSBByEncoding(Val);
    1341             :     Name = TSB ? TSB->Name : "";
    1342             :   } else {
    1343             :     auto DB = AArch64DB::lookupDBByEncoding(Val);
    1344             :     Name = DB ? DB->Name : "";
    1345             :   }
    1346          50 :   if (!Name.empty())
    1347          50 :     O << Name;
    1348             :   else
    1349          50 :     O << "#" << Val;
    1350          14 : }
    1351             : 
    1352             : void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
    1353             :                                                 const MCSubtargetInfo &STI,
    1354          14 :                                                 raw_ostream &O) {
    1355             :   unsigned Val = MI->getOperand(OpNo).getImm();
    1356             : 
    1357             :   // Horrible hack for the one register that has identical encodings but
    1358             :   // different names in MSR and MRS. Because of this, one of MRS and MSR is
    1359             :   // going to get the wrong entry
    1360             :   if (Val == AArch64SysReg::DBGDTRRX_EL0) {
    1361             :     O << "DBGDTRRX_EL0";
    1362          14 :     return;
    1363          14 :   }
    1364             : 
    1365          14 :   const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val);
    1366          14 :   if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits()))
    1367             :     O << Reg->Name;
    1368             :   else
    1369             :     O << AArch64SysReg::genericRegisterString(Val);
    1370          14 : }
    1371             : 
    1372             : void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
    1373             :                                                 const MCSubtargetInfo &STI,
    1374             :                                                 raw_ostream &O) {
    1375             :   unsigned Val = MI->getOperand(OpNo).getImm();
    1376             : 
    1377             :   // Horrible hack for the one register that has identical encodings but
    1378          14 :   // different names in MSR and MRS. Because of this, one of MRS and MSR is
    1379          14 :   // going to get the wrong entry
    1380             :   if (Val == AArch64SysReg::DBGDTRTX_EL0) {
    1381          14 :     O << "DBGDTRTX_EL0";
    1382          14 :     return;
    1383             :   }
    1384             : 
    1385             :   const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val);
    1386          14 :   if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits()))
    1387             :     O << Reg->Name;
    1388             :   else
    1389             :     O << AArch64SysReg::genericRegisterString(Val);
    1390             : }
    1391             : 
    1392             : void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
    1393             :                                                 const MCSubtargetInfo &STI,
    1394          14 :                                                 raw_ostream &O) {
    1395          14 :   unsigned Val = MI->getOperand(OpNo).getImm();
    1396             : 
    1397          14 :   auto PState = AArch64PState::lookupPStateByEncoding(Val);
    1398           8 :   if (PState && PState->haveFeatures(STI.getFeatureBits()))
    1399             :     O << PState->Name;
    1400             :   else
    1401             :     O << "#" << formatImm(Val);
    1402           8 : }
    1403             : 
    1404             : void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
    1405             :                                                 const MCSubtargetInfo &STI,
    1406             :                                                 raw_ostream &O) {
    1407             :   unsigned RawVal = MI->getOperand(OpNo).getImm();
    1408             :   uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal);
    1409             :   O << format("#%#016llx", Val);
    1410           8 : }
    1411           8 : 
    1412             : template<int64_t Angle, int64_t Remainder>
    1413           8 : void AArch64InstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
    1414           8 :                                                 const MCSubtargetInfo &STI,
    1415             :                                                 raw_ostream &O) {
    1416             :   unsigned Val = MI->getOperand(OpNo).getImm();
    1417             :   O << "#" << (Val * Angle) + Remainder;
    1418           8 : }
    1419             : 
    1420             : void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum,
    1421             :                                          const MCSubtargetInfo &STI,
    1422             :                                          raw_ostream &O) {
    1423             :   unsigned Val = MI->getOperand(OpNum).getImm();
    1424             :   if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val))
    1425             :     O << Pat->Name;
    1426           8 :   else
    1427           8 :     O << '#' << formatImm(Val);
    1428             : }
    1429           8 : 
    1430           4 : template <char suffix>
    1431             : void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
    1432             :                                        const MCSubtargetInfo &STI,
    1433             :                                        raw_ostream &O) {
    1434           4 :   switch (suffix) {
    1435             :   case 0:
    1436             :   case 'b':
    1437             :   case 'h':
    1438             :   case 's':
    1439             :   case 'd':
    1440             :   case 'q':
    1441             :     break;
    1442             :   default: llvm_unreachable("Invalid kind specifier.");
    1443             :   }
    1444             : 
    1445           4 :   unsigned Reg = MI->getOperand(OpNum).getReg();
    1446           2 :   O << getRegisterName(Reg);
    1447             :   if (suffix != 0)
    1448             :     O << '.' << suffix;
    1449             : }
    1450           2 : 
    1451             : template <typename T>
    1452             : void AArch64InstPrinter::printImmSVE(T Value, raw_ostream &O) {
    1453             :   typename std::make_unsigned<T>::type HexValue = Value;
    1454             : 
    1455             :   if (getPrintImmHex())
    1456             :     O << '#' << formatHex((uint64_t)HexValue);
    1457             :   else
    1458           2 :     O << '#' << formatDec(Value);
    1459           2 : 
    1460             :   if (CommentStream) {
    1461           2 :     // Do the opposite to that used for instruction operands.
    1462           2 :     if (getPrintImmHex())
    1463             :       *CommentStream << '=' << formatDec(HexValue) << '\n';
    1464             :     else
    1465             :       *CommentStream << '=' << formatHex((uint64_t)Value) << '\n';
    1466           2 :   }
    1467             : }
    1468             : 
    1469             : template <typename T>
    1470             : void AArch64InstPrinter::printImm8OptLsl(const MCInst *MI, unsigned OpNum,
    1471             :                                          const MCSubtargetInfo &STI,
    1472             :                                          raw_ostream &O) {
    1473             :   unsigned UnscaledVal = MI->getOperand(OpNum).getImm();
    1474           2 :   unsigned Shift = MI->getOperand(OpNum + 1).getImm();
    1475           2 :   assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL &&
    1476             :          "Unexepected shift type!");
    1477           2 : 
    1478             :   // #0 lsl #8 is never pretty printed
    1479        1658 :   if ((UnscaledVal == 0) && (AArch64_AM::getShiftValue(Shift) != 0)) {
    1480             :     O << '#' << formatImm(UnscaledVal);
    1481             :     printShifter(MI, OpNum + 1, STI, O);
    1482        1658 :     return;
    1483        1658 :   }
    1484        1658 : 
    1485             :   T Val;
    1486         766 :   if (std::is_signed<T>())
    1487             :     Val = (int8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
    1488             :   else
    1489         766 :     Val = (uint8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
    1490         766 : 
    1491         766 :   printImmSVE(Val, O);
    1492             : }
    1493           0 : 
    1494             : template <typename T>
    1495             : void AArch64InstPrinter::printSVELogicalImm(const MCInst *MI, unsigned OpNum,
    1496           0 :                                             const MCSubtargetInfo &STI,
    1497           0 :                                             raw_ostream &O) {
    1498             :   typedef typename std::make_signed<T>::type SignedT;
    1499             :   typedef typename std::make_unsigned<T>::type UnsignedT;
    1500           0 : 
    1501             :   uint64_t Val = MI->getOperand(OpNum).getImm();
    1502             :   UnsignedT PrintVal = AArch64_AM::decodeLogicalImmediate(Val, 64);
    1503           0 : 
    1504           0 :   // Prefer the default format for 16bit values, hex otherwise.
    1505           0 :   if ((int16_t)PrintVal == (SignedT)PrintVal)
    1506             :     printImmSVE((T)PrintVal, O);
    1507             :   else if ((uint16_t)PrintVal == PrintVal)
    1508           0 :     printImmSVE(PrintVal, O);
    1509           0 :   else
    1510           0 :     O << '#' << formatHex((uint64_t)PrintVal);
    1511             : }
    1512             : 
    1513           0 : template <int Width>
    1514           0 : void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum,
    1515           0 :                                        const MCSubtargetInfo &STI,
    1516             :                                        raw_ostream &O) {
    1517             :   unsigned Base;
    1518           0 :   switch (Width) {
    1519           0 :   case 8:   Base = AArch64::B0; break;
    1520           0 :   case 16:  Base = AArch64::H0; break;
    1521             :   case 32:  Base = AArch64::S0; break;
    1522             :   case 64:  Base = AArch64::D0; break;
    1523           0 :   case 128: Base = AArch64::Q0; break;
    1524           0 :   default:
    1525           0 :     llvm_unreachable("Unsupported width");
    1526             :   }
    1527             :   unsigned Reg = MI->getOperand(OpNum).getReg();
    1528           0 :   O << getRegisterName(Reg - AArch64::Z0 + Base);
    1529           0 : }
    1530             : 
    1531        6472 : template <unsigned ImmIs0, unsigned ImmIs1>
    1532             : void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
    1533        6472 :                                          const MCSubtargetInfo &STI,
    1534        6472 :                                          raw_ostream  &O) {
    1535        4439 :   auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0);
    1536             :   auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1);
    1537             :   unsigned Val = MI->getOperand(OpNum).getImm();
    1538        2033 :   O << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr);
    1539             : }
    1540        6472 : 
    1541             : void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
    1542           0 :                                         const MCSubtargetInfo &STI,
    1543             :                                         raw_ostream &O) {
    1544           0 :   unsigned Reg = MI->getOperand(OpNum).getReg();
    1545           0 :   O << getRegisterName(getWRegFromXReg(Reg));
    1546           0 : }

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