LCOV - code coverage report
Current view: top level - lib/Target/AArch64/InstPrinter - AArch64InstPrinter.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 3 94 3.2 %
Date: 2018-09-23 13:06:45 Functions: 0 29 0.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This class prints an AArch64 MCInst to a .s file.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #ifndef LLVM_LIB_TARGET_AARCH64_INSTPRINTER_AARCH64INSTPRINTER_H
      15             : #define LLVM_LIB_TARGET_AARCH64_INSTPRINTER_AARCH64INSTPRINTER_H
      16             : 
      17             : #include "MCTargetDesc/AArch64MCTargetDesc.h"
      18             : #include "llvm/ADT/StringRef.h"
      19             : #include "llvm/MC/MCInstPrinter.h"
      20             : #include "../Utils/AArch64BaseInfo.h"
      21             : 
      22             : namespace llvm {
      23             : 
      24             : class AArch64InstPrinter : public MCInstPrinter {
      25             : public:
      26             :   AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
      27             :                      const MCRegisterInfo &MRI);
      28             : 
      29             :   void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
      30             :                  const MCSubtargetInfo &STI) override;
      31             :   void printRegName(raw_ostream &OS, unsigned RegNo) const override;
      32             : 
      33             :   // Autogenerated by tblgen.
      34             :   virtual void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
      35             :                                 raw_ostream &O);
      36             :   virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
      37             :                                raw_ostream &O);
      38             :   virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
      39             :                                        unsigned PrintMethodIdx,
      40             :                                        const MCSubtargetInfo &STI,
      41             :                                        raw_ostream &O);
      42             : 
      43           0 :   virtual StringRef getRegName(unsigned RegNo) const {
      44           0 :     return getRegisterName(RegNo);
      45             :   }
      46             : 
      47             :   static const char *getRegisterName(unsigned RegNo,
      48             :                                      unsigned AltIdx = AArch64::NoRegAltName);
      49             : 
      50             : protected:
      51             :   bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
      52             :                      raw_ostream &O);
      53             :   // Operand printers
      54             :   void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
      55             :                     raw_ostream &O);
      56             :   void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
      57             :                 raw_ostream &O);
      58             :   void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
      59             :                    raw_ostream &O);
      60             :   template <typename T> void printImmSVE(T Value, raw_ostream &O);
      61             :   void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
      62             :                            raw_ostream &O);
      63             :   template <int Amount>
      64           0 :   void printPostIncOperand(const MCInst *MI, unsigned OpNo,
      65             :                            const MCSubtargetInfo &STI, raw_ostream &O) {
      66         118 :     printPostIncOperand(MI, OpNo, Amount, O);
      67           0 :   }
      68           0 : 
      69             :   void printVRegOperand(const MCInst *MI, unsigned OpNo,
      70           0 :                         const MCSubtargetInfo &STI, raw_ostream &O);
      71           0 :   void printSysCROperand(const MCInst *MI, unsigned OpNo,
      72           0 :                          const MCSubtargetInfo &STI, raw_ostream &O);
      73             :   void printAddSubImm(const MCInst *MI, unsigned OpNum,
      74           0 :                       const MCSubtargetInfo &STI, raw_ostream &O);
      75           0 :   template <typename T>
      76           0 :   void printLogicalImm(const MCInst *MI, unsigned OpNum,
      77             :                        const MCSubtargetInfo &STI, raw_ostream &O);
      78           0 :   void printShifter(const MCInst *MI, unsigned OpNum,
      79           0 :                     const MCSubtargetInfo &STI, raw_ostream &O);
      80           0 :   void printShiftedRegister(const MCInst *MI, unsigned OpNum,
      81             :                             const MCSubtargetInfo &STI, raw_ostream &O);
      82           0 :   void printExtendedRegister(const MCInst *MI, unsigned OpNum,
      83           0 :                              const MCSubtargetInfo &STI, raw_ostream &O);
      84           0 :   void printArithExtend(const MCInst *MI, unsigned OpNum,
      85             :                         const MCSubtargetInfo &STI, raw_ostream &O);
      86           0 : 
      87           0 :   void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O,
      88           0 :                       char SrcRegKind, unsigned Width);
      89             :   template <char SrcRegKind, unsigned Width>
      90           0 :   void printMemExtend(const MCInst *MI, unsigned OpNum,
      91           0 :                       const MCSubtargetInfo &STI, raw_ostream &O) {
      92           0 :     printMemExtend(MI, OpNum, O, SrcRegKind, Width);
      93             :   }
      94           0 :   template <bool SignedExtend, int ExtWidth, char SrcRegKind, char Suffix>
      95           0 :   void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum,
      96           0 :                                const MCSubtargetInfo &STI, raw_ostream &O);
      97             :   void printCondCode(const MCInst *MI, unsigned OpNum,
      98           0 :                      const MCSubtargetInfo &STI, raw_ostream &O);
      99           0 :   void printInverseCondCode(const MCInst *MI, unsigned OpNum,
     100           0 :                             const MCSubtargetInfo &STI, raw_ostream &O);
     101             :   void printAlignedLabel(const MCInst *MI, unsigned OpNum,
     102           0 :                          const MCSubtargetInfo &STI, raw_ostream &O);
     103           0 :   void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale,
     104           0 :                          raw_ostream &O);
     105             :   void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale,
     106           0 :                         raw_ostream &O);
     107           0 : 
     108           0 :   template <int Scale>
     109             :   void printUImm12Offset(const MCInst *MI, unsigned OpNum,
     110           0 :                          const MCSubtargetInfo &STI, raw_ostream &O) {
     111           0 :     printUImm12Offset(MI, OpNum, Scale, O);
     112           0 :   }
     113             : 
     114           0 :   template <int BitWidth>
     115           0 :   void printAMIndexedWB(const MCInst *MI, unsigned OpNum,
     116             :                         const MCSubtargetInfo &STI, raw_ostream &O) {
     117             :     printAMIndexedWB(MI, OpNum, BitWidth / 8, O);
     118             :   }
     119             : 
     120             :   void printAMNoIndex(const MCInst *MI, unsigned OpNum,
     121             :                       const MCSubtargetInfo &STI, raw_ostream &O);
     122             : 
     123             :   template <int Scale>
     124             :   void printImmScale(const MCInst *MI, unsigned OpNum,
     125             :                      const MCSubtargetInfo &STI, raw_ostream &O);
     126             : 
     127             :   template <bool IsSVEPrefetch = false>
     128             :   void printPrefetchOp(const MCInst *MI, unsigned OpNum,
     129             :                        const MCSubtargetInfo &STI, raw_ostream &O);
     130             : 
     131             :   void printPSBHintOp(const MCInst *MI, unsigned OpNum,
     132             :                       const MCSubtargetInfo &STI, raw_ostream &O);
     133             : 
     134             :   void printFPImmOperand(const MCInst *MI, unsigned OpNum,
     135             :                          const MCSubtargetInfo &STI, raw_ostream &O);
     136             : 
     137             :   void printVectorList(const MCInst *MI, unsigned OpNum,
     138           0 :                        const MCSubtargetInfo &STI, raw_ostream &O,
     139             :                        StringRef LayoutSuffix);
     140         583 : 
     141           0 :   /// Print a list of vector registers where the type suffix is implicit
     142           0 :   /// (i.e. attached to the instruction rather than the registers).
     143             :   void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum,
     144           0 :                                       const MCSubtargetInfo &STI,
     145           0 :                                       raw_ostream &O);
     146           0 : 
     147             :   template <unsigned NumLanes, char LaneKind>
     148           0 :   void printTypedVectorList(const MCInst *MI, unsigned OpNum,
     149           0 :                             const MCSubtargetInfo &STI, raw_ostream &O);
     150           0 : 
     151             :   void printVectorIndex(const MCInst *MI, unsigned OpNum,
     152           0 :                         const MCSubtargetInfo &STI, raw_ostream &O);
     153           0 :   void printAdrpLabel(const MCInst *MI, unsigned OpNum,
     154           0 :                       const MCSubtargetInfo &STI, raw_ostream &O);
     155             :   void printBarrierOption(const MCInst *MI, unsigned OpNum,
     156           0 :                           const MCSubtargetInfo &STI, raw_ostream &O);
     157           0 :   void printMSRSystemRegister(const MCInst *MI, unsigned OpNum,
     158           0 :                               const MCSubtargetInfo &STI, raw_ostream &O);
     159             :   void printMRSSystemRegister(const MCInst *MI, unsigned OpNum,
     160           0 :                               const MCSubtargetInfo &STI, raw_ostream &O);
     161           0 :   void printSystemPStateField(const MCInst *MI, unsigned OpNum,
     162           0 :                               const MCSubtargetInfo &STI, raw_ostream &O);
     163             :   void printSIMDType10Operand(const MCInst *MI, unsigned OpNum,
     164           0 :                               const MCSubtargetInfo &STI, raw_ostream &O);
     165           0 :   template<int64_t Angle, int64_t Remainder>
     166           0 :   void printComplexRotationOp(const MCInst *MI, unsigned OpNo,
     167             :                             const MCSubtargetInfo &STI, raw_ostream &O);
     168           0 :   template<unsigned size>
     169           0 :   void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum,
     170           0 :                                     const MCSubtargetInfo &STI,
     171             :                                     raw_ostream &O);
     172           0 :   template <typename T>
     173           0 :   void printImm8OptLsl(const MCInst *MI, unsigned OpNum,
     174           0 :                        const MCSubtargetInfo &STI, raw_ostream &O);
     175             :   template <typename T>
     176           0 :   void printSVELogicalImm(const MCInst *MI, unsigned OpNum,
     177           0 :                           const MCSubtargetInfo &STI, raw_ostream &O);
     178           0 :   void printSVEPattern(const MCInst *MI, unsigned OpNum,
     179             :                        const MCSubtargetInfo &STI, raw_ostream &O);
     180           0 :   template <char = 0>
     181           0 :   void printSVERegOp(const MCInst *MI, unsigned OpNum,
     182             :                     const MCSubtargetInfo &STI, raw_ostream &O);
     183             :   void printGPR64as32(const MCInst *MI, unsigned OpNum,
     184             :                       const MCSubtargetInfo &STI, raw_ostream &O);
     185             :   template <int Width>
     186             :   void printZPRasFPR(const MCInst *MI, unsigned OpNum,
     187             :                      const MCSubtargetInfo &STI, raw_ostream &O);
     188             :   template <unsigned ImmIs0, unsigned ImmIs1>
     189             :   void printExactFPImm(const MCInst *MI, unsigned OpNum,
     190             :                        const MCSubtargetInfo &STI, raw_ostream &O);
     191             : };
     192             : 
     193             : class AArch64AppleInstPrinter : public AArch64InstPrinter {
     194             : public:
     195             :   AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
     196             :                           const MCRegisterInfo &MRI);
     197           0 : 
     198             :   void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
     199        6472 :                  const MCSubtargetInfo &STI) override;
     200           0 : 
     201           0 :   void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
     202             :                         raw_ostream &O) override;
     203           0 :   bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
     204           0 :                        raw_ostream &O) override;
     205           0 :   void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
     206             :                                unsigned PrintMethodIdx,
     207           0 :                                const MCSubtargetInfo &STI,
     208           0 :                                raw_ostream &O) override;
     209           0 : 
     210             :   StringRef getRegName(unsigned RegNo) const override {
     211           0 :     return getRegisterName(RegNo);
     212           0 :   }
     213           0 : 
     214             :   static const char *getRegisterName(unsigned RegNo,
     215           0 :                                      unsigned AltIdx = AArch64::NoRegAltName);
     216           0 : };
     217           0 : 
     218             : } // end namespace llvm
     219           0 : 
     220           0 : #endif // LLVM_LIB_TARGET_AARCH64_INSTPRINTER_AARCH64INSTPRINTER_H

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