LCOV - code coverage report
Current view: top level - lib/Target/AArch64/MCTargetDesc - AArch64ELFObjectWriter.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 214 240 89.2 %
Date: 2018-06-17 00:07:59 Functions: 4 5 80.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file handles ELF-specific object emission, converting LLVM's internal
      11             : // fixups into the appropriate relocations.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "MCTargetDesc/AArch64FixupKinds.h"
      16             : #include "MCTargetDesc/AArch64MCExpr.h"
      17             : #include "MCTargetDesc/AArch64MCTargetDesc.h"
      18             : #include "llvm/BinaryFormat/ELF.h"
      19             : #include "llvm/MC/MCContext.h"
      20             : #include "llvm/MC/MCELFObjectWriter.h"
      21             : #include "llvm/MC/MCFixup.h"
      22             : #include "llvm/MC/MCObjectWriter.h"
      23             : #include "llvm/MC/MCValue.h"
      24             : #include "llvm/Support/ErrorHandling.h"
      25             : #include <cassert>
      26             : #include <cstdint>
      27             : 
      28             : using namespace llvm;
      29             : 
      30             : namespace {
      31             : 
      32             : class AArch64ELFObjectWriter : public MCELFObjectTargetWriter {
      33             : public:
      34             :   AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
      35             : 
      36        1702 :   ~AArch64ELFObjectWriter() override = default;
      37             : 
      38             : protected:
      39             :   unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
      40             :                         const MCFixup &Fixup, bool IsPCRel) const override;
      41             :   bool IsILP32;
      42             : };
      43             : 
      44             : } // end anonymous namespace
      45             : 
      46        1707 : AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
      47             :     : MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI, ELF::EM_AARCH64,
      48             :                               /*HasRelocationAddend*/ true),
      49        1707 :       IsILP32(IsILP32) {}
      50             : 
      51             : #define R_CLS(rtype)                                                           \
      52             :   IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype
      53             : #define BAD_ILP32_MOV(lp64rtype)                                               \
      54             :   "ILP32 absolute MOV relocation not "                                         \
      55             :   "supported (LP64 eqv: " #lp64rtype ")"
      56             : 
      57             : // assumes IsILP32 is true
      58          85 : static bool isNonILP32reloc(const MCFixup &Fixup,
      59             :                             AArch64MCExpr::VariantKind RefKind,
      60             :                             MCContext &Ctx) {
      61          85 :   if ((unsigned)Fixup.getKind() != AArch64::fixup_aarch64_movw)
      62             :     return false;
      63          12 :   switch (RefKind) {
      64             :   case AArch64MCExpr::VK_ABS_G3:
      65           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G3));
      66           1 :     return true;
      67             :   case AArch64MCExpr::VK_ABS_G2:
      68           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2));
      69           1 :     return true;
      70             :   case AArch64MCExpr::VK_ABS_G2_S:
      71           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G2));
      72           1 :     return true;
      73             :   case AArch64MCExpr::VK_ABS_G2_NC:
      74           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2_NC));
      75           1 :     return true;
      76             :   case AArch64MCExpr::VK_ABS_G1_S:
      77           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G1));
      78           1 :     return true;
      79             :   case AArch64MCExpr::VK_ABS_G1_NC:
      80           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G1_NC));
      81           1 :     return true;
      82             :   case AArch64MCExpr::VK_DTPREL_G2:
      83           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G2));
      84           1 :     return true;
      85             :   case AArch64MCExpr::VK_DTPREL_G1_NC:
      86           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G1_NC));
      87           1 :     return true;
      88             :   case AArch64MCExpr::VK_TPREL_G2:
      89           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G2));
      90           1 :     return true;
      91             :   case AArch64MCExpr::VK_TPREL_G1_NC:
      92           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G1_NC));
      93           1 :     return true;
      94             :   case AArch64MCExpr::VK_GOTTPREL_G1:
      95           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G1));
      96           1 :     return true;
      97             :   case AArch64MCExpr::VK_GOTTPREL_G0_NC:
      98           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G0_NC));
      99           1 :     return true;
     100             :   default:
     101             :     return false;
     102             :   }
     103             :   return false;
     104             : }
     105             : 
     106         963 : unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
     107             :                                               const MCValue &Target,
     108             :                                               const MCFixup &Fixup,
     109             :                                               bool IsPCRel) const {
     110             :   AArch64MCExpr::VariantKind RefKind =
     111         963 :       static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
     112             :   AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind);
     113             :   bool IsNC = AArch64MCExpr::isNotChecked(RefKind);
     114             : 
     115             :   assert((!Target.getSymA() ||
     116             :           Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None) &&
     117             :          "Should only be expression-level modifiers here");
     118             : 
     119             :   assert((!Target.getSymB() ||
     120             :           Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None) &&
     121             :          "Should only be expression-level modifiers here");
     122             : 
     123         963 :   if (IsPCRel) {
     124         296 :     switch ((unsigned)Fixup.getKind()) {
     125             :     case FK_Data_1:
     126           1 :       Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
     127           1 :       return ELF::R_AARCH64_NONE;
     128           6 :     case FK_Data_2:
     129           6 :       return R_CLS(PREL16);
     130          46 :     case FK_Data_4:
     131          46 :       return R_CLS(PREL32);
     132           8 :     case FK_Data_8:
     133           8 :       if (IsILP32) {
     134           1 :         Ctx.reportError(Fixup.getLoc(),
     135             :                         "ILP32 8 byte PC relative data "
     136             :                         "relocation not supported (LP64 eqv: PREL64)");
     137           1 :         return ELF::R_AARCH64_NONE;
     138             :       } else
     139             :         return ELF::R_AARCH64_PREL64;
     140           6 :     case AArch64::fixup_aarch64_pcrel_adr_imm21:
     141             :       assert(SymLoc == AArch64MCExpr::VK_NONE && "unexpected ADR relocation");
     142           6 :       return R_CLS(ADR_PREL_LO21);
     143         145 :     case AArch64::fixup_aarch64_pcrel_adrp_imm21:
     144         145 :       if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC)
     145          88 :         return R_CLS(ADR_PREL_PG_HI21);
     146          57 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) {
     147           0 :         if (IsILP32) {
     148           0 :           Ctx.reportError(Fixup.getLoc(),
     149             :                           "invalid fixup for 32-bit pcrel ADRP instruction "
     150             :                           "VK_ABS VK_NC");
     151           0 :           return ELF::R_AARCH64_NONE;
     152             :         } else {
     153             :           return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC;
     154             :         }
     155             :       }
     156          57 :       if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC)
     157          18 :         return R_CLS(ADR_GOT_PAGE);
     158          39 :       if (SymLoc == AArch64MCExpr::VK_GOTTPREL && !IsNC)
     159          15 :         return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21);
     160          24 :       if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC)
     161          24 :         return R_CLS(TLSDESC_ADR_PAGE21);
     162           0 :       Ctx.reportError(Fixup.getLoc(),
     163             :                       "invalid symbol kind for ADRP relocation");
     164           0 :       return ELF::R_AARCH64_NONE;
     165          12 :     case AArch64::fixup_aarch64_pcrel_branch26:
     166          12 :       return R_CLS(JUMP26);
     167          37 :     case AArch64::fixup_aarch64_pcrel_call26:
     168          37 :       return R_CLS(CALL26);
     169          14 :     case AArch64::fixup_aarch64_ldr_pcrel_imm19:
     170          14 :       if (SymLoc == AArch64MCExpr::VK_GOTTPREL)
     171           2 :         return R_CLS(TLSIE_LD_GOTTPREL_PREL19);
     172          12 :       return R_CLS(LD_PREL_LO19);
     173           8 :     case AArch64::fixup_aarch64_pcrel_branch14:
     174           8 :       return R_CLS(TSTBR14);
     175           8 :     case AArch64::fixup_aarch64_pcrel_branch19:
     176           8 :       return R_CLS(CONDBR19);
     177             :     default:
     178           5 :       Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
     179           5 :       return ELF::R_AARCH64_NONE;
     180             :     }
     181             :   } else {
     182         667 :     if (IsILP32 && isNonILP32reloc(Fixup, RefKind, Ctx))
     183             :       return ELF::R_AARCH64_NONE;
     184         655 :     switch ((unsigned)Fixup.getKind()) {
     185             :     case FK_Data_1:
     186           1 :       Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
     187           1 :       return ELF::R_AARCH64_NONE;
     188           6 :     case FK_Data_2:
     189           6 :       return R_CLS(ABS16);
     190          72 :     case FK_Data_4:
     191          72 :       return R_CLS(ABS32);
     192          63 :     case FK_Data_8:
     193          63 :       if (IsILP32) {
     194           1 :         Ctx.reportError(Fixup.getLoc(),
     195             :                         "ILP32 8 byte absolute data "
     196             :                         "relocation not supported (LP64 eqv: ABS64)");
     197           1 :         return ELF::R_AARCH64_NONE;
     198             :       } else
     199             :         return ELF::R_AARCH64_ABS64;
     200         106 :     case AArch64::fixup_aarch64_add_imm12:
     201         106 :       if (RefKind == AArch64MCExpr::VK_DTPREL_HI12)
     202           8 :         return R_CLS(TLSLD_ADD_DTPREL_HI12);
     203          98 :       if (RefKind == AArch64MCExpr::VK_TPREL_HI12)
     204          13 :         return R_CLS(TLSLE_ADD_TPREL_HI12);
     205          85 :       if (RefKind == AArch64MCExpr::VK_DTPREL_LO12_NC)
     206          11 :         return R_CLS(TLSLD_ADD_DTPREL_LO12_NC);
     207          74 :       if (RefKind == AArch64MCExpr::VK_DTPREL_LO12)
     208           8 :         return R_CLS(TLSLD_ADD_DTPREL_LO12);
     209          66 :       if (RefKind == AArch64MCExpr::VK_TPREL_LO12_NC)
     210          11 :         return R_CLS(TLSLE_ADD_TPREL_LO12_NC);
     211          55 :       if (RefKind == AArch64MCExpr::VK_TPREL_LO12)
     212           8 :         return R_CLS(TLSLE_ADD_TPREL_LO12);
     213          47 :       if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12)
     214          24 :         return R_CLS(TLSDESC_ADD_LO12);
     215          23 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     216          23 :         return R_CLS(ADD_ABS_LO12_NC);
     217             : 
     218           0 :       Ctx.reportError(Fixup.getLoc(),
     219             :                       "invalid fixup for add (uimm12) instruction");
     220           0 :       return ELF::R_AARCH64_NONE;
     221          44 :     case AArch64::fixup_aarch64_ldst_imm12_scale1:
     222          44 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     223          18 :         return R_CLS(LDST8_ABS_LO12_NC);
     224          26 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
     225           6 :         return R_CLS(TLSLD_LDST8_DTPREL_LO12);
     226          20 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
     227           6 :         return R_CLS(TLSLD_LDST8_DTPREL_LO12_NC);
     228          14 :       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
     229           6 :         return R_CLS(TLSLE_LDST8_TPREL_LO12);
     230           8 :       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
     231           7 :         return R_CLS(TLSLE_LDST8_TPREL_LO12_NC);
     232             : 
     233           1 :       Ctx.reportError(Fixup.getLoc(),
     234             :                       "invalid fixup for 8-bit load/store instruction");
     235           1 :       return ELF::R_AARCH64_NONE;
     236          46 :     case AArch64::fixup_aarch64_ldst_imm12_scale2:
     237          46 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     238          20 :         return R_CLS(LDST16_ABS_LO12_NC);
     239          26 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
     240           6 :         return R_CLS(TLSLD_LDST16_DTPREL_LO12);
     241          20 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
     242           6 :         return R_CLS(TLSLD_LDST16_DTPREL_LO12_NC);
     243          14 :       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
     244           6 :         return R_CLS(TLSLE_LDST16_TPREL_LO12);
     245           8 :       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
     246           7 :         return R_CLS(TLSLE_LDST16_TPREL_LO12_NC);
     247             : 
     248           1 :       Ctx.reportError(Fixup.getLoc(),
     249             :                       "invalid fixup for 16-bit load/store instruction");
     250           1 :       return ELF::R_AARCH64_NONE;
     251          46 :     case AArch64::fixup_aarch64_ldst_imm12_scale4:
     252          46 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     253          18 :         return R_CLS(LDST32_ABS_LO12_NC);
     254          28 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
     255           4 :         return R_CLS(TLSLD_LDST32_DTPREL_LO12);
     256          24 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
     257           6 :         return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC);
     258          18 :       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
     259           4 :         return R_CLS(TLSLE_LDST32_TPREL_LO12);
     260          14 :       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
     261           7 :         return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);
     262           7 :       if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
     263           2 :         if (IsILP32) {
     264             :           return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC;
     265             :         } else {
     266           0 :           Ctx.reportError(Fixup.getLoc(),
     267             :                           "LP64 4 byte unchecked GOT load/store relocation "
     268             :                           "not supported (ILP32 eqv: LD32_GOT_LO12_NC");
     269           0 :           return ELF::R_AARCH64_NONE;
     270             :         }
     271             :       }
     272           5 :       if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) {
     273           0 :         if (IsILP32) {
     274           0 :           Ctx.reportError(Fixup.getLoc(),
     275             :                           "ILP32 4 byte checked GOT load/store relocation "
     276             :                           "not supported (unchecked eqv: LD32_GOT_LO12_NC)");
     277             :         } else {
     278           0 :           Ctx.reportError(Fixup.getLoc(),
     279             :                           "LP64 4 byte checked GOT load/store relocation "
     280             :                           "not supported (unchecked/ILP32 eqv: "
     281             :                           "LD32_GOT_LO12_NC)");
     282             :         }
     283             :         return ELF::R_AARCH64_NONE;
     284             :       }
     285           5 :       if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
     286           3 :         if (IsILP32) {
     287             :           return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC;
     288             :         } else {
     289           1 :           Ctx.reportError(Fixup.getLoc(),
     290             :                           "LP64 32-bit load/store "
     291             :                           "relocation not supported (ILP32 eqv: "
     292             :                           "TLSIE_LD32_GOTTPREL_LO12_NC)");
     293           1 :           return ELF::R_AARCH64_NONE;
     294             :         }
     295             :       }
     296           2 :       if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) {
     297           2 :         if (IsILP32) {
     298             :           return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12;
     299             :         } else {
     300           0 :           Ctx.reportError(Fixup.getLoc(),
     301             :                           "LP64 4 byte TLSDESC load/store relocation "
     302             :                           "not supported (ILP32 eqv: TLSDESC_LD64_LO12)");
     303           0 :           return ELF::R_AARCH64_NONE;
     304             :         }
     305             :       }
     306             : 
     307           0 :       Ctx.reportError(Fixup.getLoc(),
     308             :                       "invalid fixup for 32-bit load/store instruction "
     309             :                       "fixup_aarch64_ldst_imm12_scale4");
     310           0 :       return ELF::R_AARCH64_NONE;
     311         137 :     case AArch64::fixup_aarch64_ldst_imm12_scale8:
     312         137 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     313          26 :         return R_CLS(LDST64_ABS_LO12_NC);
     314         111 :       if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
     315          57 :         if (!IsILP32) {
     316             :           return ELF::R_AARCH64_LD64_GOT_LO12_NC;
     317             :         } else {
     318           2 :           Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
     319             :                                           "relocation not supported (LP64 eqv: "
     320             :                                           "LD64_GOT_LO12_NC)");
     321           2 :           return ELF::R_AARCH64_NONE;
     322             :         }
     323             :       }
     324          54 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
     325           4 :         return R_CLS(TLSLD_LDST64_DTPREL_LO12);
     326          50 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
     327           4 :         return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC);
     328          46 :       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
     329           4 :         return R_CLS(TLSLE_LDST64_TPREL_LO12);
     330          42 :       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
     331           5 :         return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);
     332          37 :       if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
     333          16 :         if (!IsILP32) {
     334             :           return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
     335             :         } else {
     336           4 :           Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
     337             :                                           "relocation not supported (LP64 eqv: "
     338             :                                           "TLSIE_LD64_GOTTPREL_LO12_NC)");
     339           4 :           return ELF::R_AARCH64_NONE;
     340             :         }
     341             :       }
     342          21 :       if (SymLoc == AArch64MCExpr::VK_TLSDESC) {
     343          21 :         if (!IsILP32) {
     344             :           return ELF::R_AARCH64_TLSDESC_LD64_LO12;
     345             :         } else {
     346           0 :           Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
     347             :                                           "relocation not supported (LP64 eqv: "
     348             :                                           "TLSDESC_LD64_LO12)");
     349           0 :           return ELF::R_AARCH64_NONE;
     350             :         }
     351             :       }
     352           0 :       Ctx.reportError(Fixup.getLoc(),
     353             :                       "invalid fixup for 64-bit load/store instruction");
     354           0 :       return ELF::R_AARCH64_NONE;
     355          21 :     case AArch64::fixup_aarch64_ldst_imm12_scale16:
     356          21 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     357           8 :         return R_CLS(LDST128_ABS_LO12_NC);
     358          13 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
     359           3 :         return R_CLS(TLSLD_LDST128_DTPREL_LO12);
     360          10 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
     361           3 :         return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC);
     362           7 :       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
     363           3 :         return R_CLS(TLSLE_LDST128_TPREL_LO12);
     364           4 :       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
     365           4 :         return R_CLS(TLSLE_LDST128_TPREL_LO12_NC);
     366             : 
     367           0 :       Ctx.reportError(Fixup.getLoc(),
     368             :                       "invalid fixup for 128-bit load/store instruction");
     369           0 :       return ELF::R_AARCH64_NONE;
     370             :     // ILP32 case not reached here, tested with isNonILP32reloc
     371          94 :     case AArch64::fixup_aarch64_movw:
     372          94 :       if (RefKind == AArch64MCExpr::VK_ABS_G3)
     373             :         return ELF::R_AARCH64_MOVW_UABS_G3;
     374          87 :       if (RefKind == AArch64MCExpr::VK_ABS_G2)
     375             :         return ELF::R_AARCH64_MOVW_UABS_G2;
     376          85 :       if (RefKind == AArch64MCExpr::VK_ABS_G2_S)
     377             :         return ELF::R_AARCH64_MOVW_SABS_G2;
     378          83 :       if (RefKind == AArch64MCExpr::VK_ABS_G2_NC)
     379             :         return ELF::R_AARCH64_MOVW_UABS_G2_NC;
     380          78 :       if (RefKind == AArch64MCExpr::VK_ABS_G1)
     381           2 :         return R_CLS(MOVW_UABS_G1);
     382          76 :       if (RefKind == AArch64MCExpr::VK_ABS_G1_S)
     383             :         return ELF::R_AARCH64_MOVW_SABS_G1;
     384          74 :       if (RefKind == AArch64MCExpr::VK_ABS_G1_NC)
     385             :         return ELF::R_AARCH64_MOVW_UABS_G1_NC;
     386          69 :       if (RefKind == AArch64MCExpr::VK_ABS_G0)
     387           2 :         return R_CLS(MOVW_UABS_G0);
     388          67 :       if (RefKind == AArch64MCExpr::VK_ABS_G0_S)
     389           2 :         return R_CLS(MOVW_SABS_G0);
     390          65 :       if (RefKind == AArch64MCExpr::VK_ABS_G0_NC)
     391           5 :         return R_CLS(MOVW_UABS_G0_NC);
     392          60 :       if (RefKind == AArch64MCExpr::VK_DTPREL_G2)
     393             :         return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
     394          54 :       if (RefKind == AArch64MCExpr::VK_DTPREL_G1)
     395           7 :         return R_CLS(TLSLD_MOVW_DTPREL_G1);
     396          47 :       if (RefKind == AArch64MCExpr::VK_DTPREL_G1_NC)
     397             :         return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
     398          43 :       if (RefKind == AArch64MCExpr::VK_DTPREL_G0)
     399           7 :         return R_CLS(TLSLD_MOVW_DTPREL_G0);
     400          36 :       if (RefKind == AArch64MCExpr::VK_DTPREL_G0_NC)
     401           4 :         return R_CLS(TLSLD_MOVW_DTPREL_G0_NC);
     402          32 :       if (RefKind == AArch64MCExpr::VK_TPREL_G2)
     403             :         return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
     404          28 :       if (RefKind == AArch64MCExpr::VK_TPREL_G1)
     405           7 :         return R_CLS(TLSLE_MOVW_TPREL_G1);
     406          21 :       if (RefKind == AArch64MCExpr::VK_TPREL_G1_NC)
     407             :         return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
     408          17 :       if (RefKind == AArch64MCExpr::VK_TPREL_G0)
     409           7 :         return R_CLS(TLSLE_MOVW_TPREL_G0);
     410          10 :       if (RefKind == AArch64MCExpr::VK_TPREL_G0_NC)
     411           4 :         return R_CLS(TLSLE_MOVW_TPREL_G0_NC);
     412           6 :       if (RefKind == AArch64MCExpr::VK_GOTTPREL_G1)
     413             :         return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
     414           3 :       if (RefKind == AArch64MCExpr::VK_GOTTPREL_G0_NC)
     415             :         return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
     416           0 :       Ctx.reportError(Fixup.getLoc(),
     417             :                       "invalid fixup for movz/movk instruction");
     418           0 :       return ELF::R_AARCH64_NONE;
     419          19 :     case AArch64::fixup_aarch64_tlsdesc_call:
     420          19 :       return R_CLS(TLSDESC_CALL);
     421             :     default:
     422           0 :       Ctx.reportError(Fixup.getLoc(), "Unknown ELF relocation type");
     423           0 :       return ELF::R_AARCH64_NONE;
     424             :     }
     425             :   }
     426             : 
     427             :   llvm_unreachable("Unimplemented fixup -> relocation");
     428             : }
     429             : 
     430             : std::unique_ptr<MCObjectTargetWriter>
     431        1707 : llvm::createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32) {
     432        3414 :   return llvm::make_unique<AArch64ELFObjectWriter>(OSABI, IsILP32);
     433             : }

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