LCOV - code coverage report
Current view: top level - lib/Target/AArch64/MCTargetDesc - AArch64ELFObjectWriter.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 232 259 89.6 %
Date: 2017-09-14 15:23:50 Functions: 4 5 80.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file handles ELF-specific object emission, converting LLVM's internal
      11             : // fixups into the appropriate relocations.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "MCTargetDesc/AArch64FixupKinds.h"
      16             : #include "MCTargetDesc/AArch64MCExpr.h"
      17             : #include "MCTargetDesc/AArch64MCTargetDesc.h"
      18             : #include "llvm/BinaryFormat/ELF.h"
      19             : #include "llvm/MC/MCContext.h"
      20             : #include "llvm/MC/MCELFObjectWriter.h"
      21             : #include "llvm/MC/MCFixup.h"
      22             : #include "llvm/MC/MCValue.h"
      23             : #include "llvm/Support/ErrorHandling.h"
      24             : #include <cassert>
      25             : #include <cstdint>
      26             : 
      27             : using namespace llvm;
      28             : 
      29             : namespace {
      30             : 
      31             : class AArch64ELFObjectWriter : public MCELFObjectTargetWriter {
      32             : public:
      33             :   AArch64ELFObjectWriter(uint8_t OSABI, bool IsLittleEndian, bool IsILP32);
      34             : 
      35         156 :   ~AArch64ELFObjectWriter() override = default;
      36             : 
      37             : protected:
      38             :   unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
      39             :                         const MCFixup &Fixup, bool IsPCRel) const override;
      40             :   bool IsILP32;
      41             : };
      42             : 
      43             : } // end anonymous namespace
      44             : 
      45             : AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI,
      46             :                                                bool IsLittleEndian,
      47         156 :                                                bool IsILP32)
      48             :     : MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI, ELF::EM_AARCH64,
      49             :                               /*HasRelocationAddend*/ true),
      50         156 :       IsILP32(IsILP32) {}
      51             : 
      52             : #define R_CLS(rtype)                                                           \
      53             :   IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype
      54             : #define BAD_ILP32_MOV(lp64rtype)                                               \
      55             :   "ILP32 absolute MOV relocation not "                                         \
      56             :   "supported (LP64 eqv: " #lp64rtype ")"
      57             : 
      58             : // assumes IsILP32 is true
      59          85 : static bool isNonILP32reloc(const MCFixup &Fixup,
      60             :                             AArch64MCExpr::VariantKind RefKind,
      61             :                             MCContext &Ctx) {
      62          85 :   if ((unsigned)Fixup.getKind() != AArch64::fixup_aarch64_movw)
      63             :     return false;
      64          12 :   switch (RefKind) {
      65           1 :   case AArch64MCExpr::VK_ABS_G3:
      66           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G3));
      67           1 :     return true;
      68           1 :   case AArch64MCExpr::VK_ABS_G2:
      69           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2));
      70           1 :     return true;
      71           1 :   case AArch64MCExpr::VK_ABS_G2_S:
      72           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G2));
      73           1 :     return true;
      74           1 :   case AArch64MCExpr::VK_ABS_G2_NC:
      75           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2_NC));
      76           1 :     return true;
      77           1 :   case AArch64MCExpr::VK_ABS_G1_S:
      78           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G1));
      79           1 :     return true;
      80           1 :   case AArch64MCExpr::VK_ABS_G1_NC:
      81           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G1_NC));
      82           1 :     return true;
      83           1 :   case AArch64MCExpr::VK_DTPREL_G2:
      84           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G2));
      85           1 :     return true;
      86           1 :   case AArch64MCExpr::VK_DTPREL_G1_NC:
      87           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G1_NC));
      88           1 :     return true;
      89           1 :   case AArch64MCExpr::VK_TPREL_G2:
      90           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G2));
      91           1 :     return true;
      92           1 :   case AArch64MCExpr::VK_TPREL_G1_NC:
      93           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G1_NC));
      94           1 :     return true;
      95           1 :   case AArch64MCExpr::VK_GOTTPREL_G1:
      96           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G1));
      97           1 :     return true;
      98           1 :   case AArch64MCExpr::VK_GOTTPREL_G0_NC:
      99           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G0_NC));
     100           1 :     return true;
     101             :   default:
     102             :     return false;
     103             :   }
     104             :   return false;
     105             : }
     106             : 
     107         810 : unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
     108             :                                               const MCValue &Target,
     109             :                                               const MCFixup &Fixup,
     110             :                                               bool IsPCRel) const {
     111             :   AArch64MCExpr::VariantKind RefKind =
     112         810 :       static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
     113         810 :   AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind);
     114         810 :   bool IsNC = AArch64MCExpr::isNotChecked(RefKind);
     115             : 
     116             :   assert((!Target.getSymA() ||
     117             :           Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None) &&
     118             :          "Should only be expression-level modifiers here");
     119             : 
     120             :   assert((!Target.getSymB() ||
     121             :           Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None) &&
     122             :          "Should only be expression-level modifiers here");
     123             : 
     124         810 :   if (IsPCRel) {
     125         230 :     switch ((unsigned)Fixup.getKind()) {
     126           1 :     case FK_Data_1:
     127           1 :       Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
     128           1 :       return ELF::R_AARCH64_NONE;
     129           6 :     case FK_Data_2:
     130           6 :       return R_CLS(PREL16);
     131          46 :     case FK_Data_4:
     132          46 :       return R_CLS(PREL32);
     133           8 :     case FK_Data_8:
     134           8 :       if (IsILP32) {
     135           1 :         Ctx.reportError(Fixup.getLoc(),
     136             :                         "ILP32 8 byte PC relative data "
     137             :                         "relocation not supported (LP64 eqv: PREL64)");
     138           1 :         return ELF::R_AARCH64_NONE;
     139             :       } else
     140             :         return ELF::R_AARCH64_PREL64;
     141           6 :     case AArch64::fixup_aarch64_pcrel_adr_imm21:
     142             :       assert(SymLoc == AArch64MCExpr::VK_NONE && "unexpected ADR relocation");
     143           6 :       return R_CLS(ADR_PREL_LO21);
     144          92 :     case AArch64::fixup_aarch64_pcrel_adrp_imm21:
     145          92 :       if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC)
     146          35 :         return R_CLS(ADR_PREL_PG_HI21);
     147          57 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) {
     148           0 :         if (IsILP32) {
     149           0 :           Ctx.reportError(Fixup.getLoc(),
     150             :                           "invalid fixup for 32-bit pcrel ADRP instruction "
     151             :                           "VK_ABS VK_NC");
     152           0 :           return ELF::R_AARCH64_NONE;
     153             :         } else {
     154             :           return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC;
     155             :         }
     156             :       }
     157          57 :       if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC)
     158          18 :         return R_CLS(ADR_GOT_PAGE);
     159          39 :       if (SymLoc == AArch64MCExpr::VK_GOTTPREL && !IsNC)
     160          15 :         return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21);
     161          24 :       if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC)
     162          24 :         return R_CLS(TLSDESC_ADR_PAGE21);
     163           0 :       Ctx.reportError(Fixup.getLoc(),
     164             :                       "invalid symbol kind for ADRP relocation");
     165           0 :       return ELF::R_AARCH64_NONE;
     166          12 :     case AArch64::fixup_aarch64_pcrel_branch26:
     167          12 :       return R_CLS(JUMP26);
     168          28 :     case AArch64::fixup_aarch64_pcrel_call26:
     169          28 :       return R_CLS(CALL26);
     170          10 :     case AArch64::fixup_aarch64_ldr_pcrel_imm19:
     171          10 :       if (SymLoc == AArch64MCExpr::VK_GOTTPREL)
     172           2 :         return R_CLS(TLSIE_LD_GOTTPREL_PREL19);
     173           8 :       return R_CLS(LD_PREL_LO19);
     174           8 :     case AArch64::fixup_aarch64_pcrel_branch14:
     175           8 :       return R_CLS(TSTBR14);
     176           8 :     case AArch64::fixup_aarch64_pcrel_branch19:
     177           8 :       return R_CLS(CONDBR19);
     178           5 :     default:
     179           5 :       Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
     180           5 :       return ELF::R_AARCH64_NONE;
     181             :     }
     182             :   } else {
     183         580 :     if (IsILP32 && isNonILP32reloc(Fixup, RefKind, Ctx))
     184             :       return ELF::R_AARCH64_NONE;
     185         568 :     switch ((unsigned)Fixup.getKind()) {
     186           1 :     case FK_Data_1:
     187           1 :       Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
     188           1 :       return ELF::R_AARCH64_NONE;
     189           5 :     case FK_Data_2:
     190           5 :       return R_CLS(ABS16);
     191          71 :     case FK_Data_4:
     192          71 :       return R_CLS(ABS32);
     193          36 :     case FK_Data_8:
     194          36 :       if (IsILP32) {
     195           1 :         Ctx.reportError(Fixup.getLoc(),
     196             :                         "ILP32 8 byte absolute data "
     197             :                         "relocation not supported (LP64 eqv: ABS64)");
     198           1 :         return ELF::R_AARCH64_NONE;
     199             :       } else
     200             :         return ELF::R_AARCH64_ABS64;
     201         101 :     case AArch64::fixup_aarch64_add_imm12:
     202         101 :       if (RefKind == AArch64MCExpr::VK_DTPREL_HI12)
     203           8 :         return R_CLS(TLSLD_ADD_DTPREL_HI12);
     204          93 :       if (RefKind == AArch64MCExpr::VK_TPREL_HI12)
     205           8 :         return R_CLS(TLSLE_ADD_TPREL_HI12);
     206          85 :       if (RefKind == AArch64MCExpr::VK_DTPREL_LO12_NC)
     207          11 :         return R_CLS(TLSLD_ADD_DTPREL_LO12_NC);
     208          74 :       if (RefKind == AArch64MCExpr::VK_DTPREL_LO12)
     209           8 :         return R_CLS(TLSLD_ADD_DTPREL_LO12);
     210          66 :       if (RefKind == AArch64MCExpr::VK_TPREL_LO12_NC)
     211          11 :         return R_CLS(TLSLE_ADD_TPREL_LO12_NC);
     212          55 :       if (RefKind == AArch64MCExpr::VK_TPREL_LO12)
     213           8 :         return R_CLS(TLSLE_ADD_TPREL_LO12);
     214          47 :       if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12)
     215          24 :         return R_CLS(TLSDESC_ADD_LO12);
     216          23 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     217          23 :         return R_CLS(ADD_ABS_LO12_NC);
     218             : 
     219           0 :       Ctx.reportError(Fixup.getLoc(),
     220             :                       "invalid fixup for add (uimm12) instruction");
     221           0 :       return ELF::R_AARCH64_NONE;
     222          43 :     case AArch64::fixup_aarch64_ldst_imm12_scale1:
     223          43 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     224          18 :         return R_CLS(LDST8_ABS_LO12_NC);
     225          25 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
     226           6 :         return R_CLS(TLSLD_LDST8_DTPREL_LO12);
     227          19 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
     228           6 :         return R_CLS(TLSLD_LDST8_DTPREL_LO12_NC);
     229          13 :       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
     230           6 :         return R_CLS(TLSLE_LDST8_TPREL_LO12);
     231           7 :       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
     232           6 :         return R_CLS(TLSLE_LDST8_TPREL_LO12_NC);
     233             : 
     234           1 :       Ctx.reportError(Fixup.getLoc(),
     235             :                       "invalid fixup for 8-bit load/store instruction");
     236           1 :       return ELF::R_AARCH64_NONE;
     237          45 :     case AArch64::fixup_aarch64_ldst_imm12_scale2:
     238          45 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     239          20 :         return R_CLS(LDST16_ABS_LO12_NC);
     240          25 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
     241           6 :         return R_CLS(TLSLD_LDST16_DTPREL_LO12);
     242          19 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
     243           6 :         return R_CLS(TLSLD_LDST16_DTPREL_LO12_NC);
     244          13 :       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
     245           6 :         return R_CLS(TLSLE_LDST16_TPREL_LO12);
     246           7 :       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
     247           6 :         return R_CLS(TLSLE_LDST16_TPREL_LO12_NC);
     248             : 
     249           1 :       Ctx.reportError(Fixup.getLoc(),
     250             :                       "invalid fixup for 16-bit load/store instruction");
     251           1 :       return ELF::R_AARCH64_NONE;
     252          45 :     case AArch64::fixup_aarch64_ldst_imm12_scale4:
     253          45 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     254          18 :         return R_CLS(LDST32_ABS_LO12_NC);
     255          27 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
     256           4 :         return R_CLS(TLSLD_LDST32_DTPREL_LO12);
     257          23 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
     258           6 :         return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC);
     259          17 :       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
     260           4 :         return R_CLS(TLSLE_LDST32_TPREL_LO12);
     261          13 :       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
     262           6 :         return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);
     263           7 :       if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
     264           2 :         if (IsILP32) {
     265             :           return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC;
     266             :         } else {
     267           0 :           Ctx.reportError(Fixup.getLoc(),
     268             :                           "LP64 4 byte unchecked GOT load/store relocation "
     269             :                           "not supported (ILP32 eqv: LD32_GOT_LO12_NC");
     270           0 :           return ELF::R_AARCH64_NONE;
     271             :         }
     272             :       }
     273           5 :       if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) {
     274           0 :         if (IsILP32) {
     275           0 :           Ctx.reportError(Fixup.getLoc(),
     276             :                           "ILP32 4 byte checked GOT load/store relocation "
     277             :                           "not supported (unchecked eqv: LD32_GOT_LO12_NC)");
     278             :         } else {
     279           0 :           Ctx.reportError(Fixup.getLoc(),
     280             :                           "LP64 4 byte checked GOT load/store relocation "
     281             :                           "not supported (unchecked/ILP32 eqv: "
     282             :                           "LD32_GOT_LO12_NC)");
     283             :         }
     284             :         return ELF::R_AARCH64_NONE;
     285             :       }
     286           5 :       if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
     287           3 :         if (IsILP32) {
     288             :           return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC;
     289             :         } else {
     290           1 :           Ctx.reportError(Fixup.getLoc(),
     291             :                           "LP64 32-bit load/store "
     292             :                           "relocation not supported (ILP32 eqv: "
     293             :                           "TLSIE_LD32_GOTTPREL_LO12_NC)");
     294           1 :           return ELF::R_AARCH64_NONE;
     295             :         }
     296             :       }
     297           2 :       if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) {
     298           2 :         if (IsILP32) {
     299             :           return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12;
     300             :         } else {
     301           0 :           Ctx.reportError(Fixup.getLoc(),
     302             :                           "LP64 4 byte TLSDESC load/store relocation "
     303             :                           "not supported (ILP32 eqv: TLSDESC_LD64_LO12)");
     304           0 :           return ELF::R_AARCH64_NONE;
     305             :         }
     306             :       }
     307             : 
     308           0 :       Ctx.reportError(Fixup.getLoc(),
     309             :                       "invalid fixup for 32-bit load/store instruction "
     310             :                       "fixup_aarch64_ldst_imm12_scale4");
     311           0 :       return ELF::R_AARCH64_NONE;
     312          88 :     case AArch64::fixup_aarch64_ldst_imm12_scale8:
     313          88 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     314          17 :         return R_CLS(LDST64_ABS_LO12_NC);
     315          71 :       if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
     316          18 :         if (!IsILP32) {
     317             :           return ELF::R_AARCH64_LD64_GOT_LO12_NC;
     318             :         } else {
     319           2 :           Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
     320             :                                           "relocation not supported (LP64 eqv: "
     321             :                                           "LD64_GOT_LO12_NC)");
     322           2 :           return ELF::R_AARCH64_NONE;
     323             :         }
     324             :       }
     325          53 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
     326           4 :         return R_CLS(TLSLD_LDST64_DTPREL_LO12);
     327          49 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
     328           4 :         return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC);
     329          45 :       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
     330           4 :         return R_CLS(TLSLE_LDST64_TPREL_LO12);
     331          41 :       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
     332           4 :         return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);
     333          37 :       if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
     334          16 :         if (!IsILP32) {
     335             :           return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
     336             :         } else {
     337           4 :           Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
     338             :                                           "relocation not supported (LP64 eqv: "
     339             :                                           "TLSIE_LD64_GOTTPREL_LO12_NC)");
     340           4 :           return ELF::R_AARCH64_NONE;
     341             :         }
     342             :       }
     343          21 :       if (SymLoc == AArch64MCExpr::VK_TLSDESC) {
     344          21 :         if (!IsILP32) {
     345             :           return ELF::R_AARCH64_TLSDESC_LD64_LO12;
     346             :         } else {
     347           0 :           Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
     348             :                                           "relocation not supported (LP64 eqv: "
     349             :                                           "TLSDESC_LD64_LO12)");
     350           0 :           return ELF::R_AARCH64_NONE;
     351             :         }
     352             :       }
     353           0 :       Ctx.reportError(Fixup.getLoc(),
     354             :                       "invalid fixup for 64-bit load/store instruction");
     355           0 :       return ELF::R_AARCH64_NONE;
     356          20 :     case AArch64::fixup_aarch64_ldst_imm12_scale16:
     357          20 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     358           8 :         return R_CLS(LDST128_ABS_LO12_NC);
     359          12 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
     360           3 :         return R_CLS(TLSLD_LDST128_DTPREL_LO12);
     361           9 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
     362           3 :         return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC);
     363           6 :       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
     364           3 :         return R_CLS(TLSLE_LDST128_TPREL_LO12);
     365           3 :       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
     366           3 :         return R_CLS(TLSLE_LDST128_TPREL_LO12_NC);
     367             : 
     368           0 :       Ctx.reportError(Fixup.getLoc(),
     369             :                       "invalid fixup for 128-bit load/store instruction");
     370           0 :       return ELF::R_AARCH64_NONE;
     371             :     // ILP32 case not reached here, tested with isNonILP32reloc
     372          94 :     case AArch64::fixup_aarch64_movw:
     373          94 :       if (RefKind == AArch64MCExpr::VK_ABS_G3)
     374             :         return ELF::R_AARCH64_MOVW_UABS_G3;
     375          87 :       if (RefKind == AArch64MCExpr::VK_ABS_G2)
     376             :         return ELF::R_AARCH64_MOVW_UABS_G2;
     377          85 :       if (RefKind == AArch64MCExpr::VK_ABS_G2_S)
     378             :         return ELF::R_AARCH64_MOVW_SABS_G2;
     379          83 :       if (RefKind == AArch64MCExpr::VK_ABS_G2_NC)
     380             :         return ELF::R_AARCH64_MOVW_UABS_G2_NC;
     381          78 :       if (RefKind == AArch64MCExpr::VK_ABS_G1)
     382           2 :         return R_CLS(MOVW_UABS_G1);
     383          76 :       if (RefKind == AArch64MCExpr::VK_ABS_G1_S)
     384             :         return ELF::R_AARCH64_MOVW_SABS_G1;
     385          74 :       if (RefKind == AArch64MCExpr::VK_ABS_G1_NC)
     386             :         return ELF::R_AARCH64_MOVW_UABS_G1_NC;
     387          69 :       if (RefKind == AArch64MCExpr::VK_ABS_G0)
     388           2 :         return R_CLS(MOVW_UABS_G0);
     389          67 :       if (RefKind == AArch64MCExpr::VK_ABS_G0_S)
     390           2 :         return R_CLS(MOVW_SABS_G0);
     391          65 :       if (RefKind == AArch64MCExpr::VK_ABS_G0_NC)
     392           5 :         return R_CLS(MOVW_UABS_G0_NC);
     393          60 :       if (RefKind == AArch64MCExpr::VK_DTPREL_G2)
     394             :         return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
     395          54 :       if (RefKind == AArch64MCExpr::VK_DTPREL_G1)
     396           7 :         return R_CLS(TLSLD_MOVW_DTPREL_G1);
     397          47 :       if (RefKind == AArch64MCExpr::VK_DTPREL_G1_NC)
     398             :         return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
     399          43 :       if (RefKind == AArch64MCExpr::VK_DTPREL_G0)
     400           7 :         return R_CLS(TLSLD_MOVW_DTPREL_G0);
     401          36 :       if (RefKind == AArch64MCExpr::VK_DTPREL_G0_NC)
     402           4 :         return R_CLS(TLSLD_MOVW_DTPREL_G0_NC);
     403          32 :       if (RefKind == AArch64MCExpr::VK_TPREL_G2)
     404             :         return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
     405          28 :       if (RefKind == AArch64MCExpr::VK_TPREL_G1)
     406           7 :         return R_CLS(TLSLE_MOVW_TPREL_G1);
     407          21 :       if (RefKind == AArch64MCExpr::VK_TPREL_G1_NC)
     408             :         return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
     409          17 :       if (RefKind == AArch64MCExpr::VK_TPREL_G0)
     410           7 :         return R_CLS(TLSLE_MOVW_TPREL_G0);
     411          10 :       if (RefKind == AArch64MCExpr::VK_TPREL_G0_NC)
     412           4 :         return R_CLS(TLSLE_MOVW_TPREL_G0_NC);
     413           6 :       if (RefKind == AArch64MCExpr::VK_GOTTPREL_G1)
     414             :         return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
     415           3 :       if (RefKind == AArch64MCExpr::VK_GOTTPREL_G0_NC)
     416             :         return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
     417           0 :       Ctx.reportError(Fixup.getLoc(),
     418             :                       "invalid fixup for movz/movk instruction");
     419           0 :       return ELF::R_AARCH64_NONE;
     420          19 :     case AArch64::fixup_aarch64_tlsdesc_call:
     421          19 :       return R_CLS(TLSDESC_CALL);
     422           0 :     default:
     423           0 :       Ctx.reportError(Fixup.getLoc(), "Unknown ELF relocation type");
     424           0 :       return ELF::R_AARCH64_NONE;
     425             :     }
     426             :   }
     427             : 
     428             :   llvm_unreachable("Unimplemented fixup -> relocation");
     429             : }
     430             : 
     431         156 : MCObjectWriter *llvm::createAArch64ELFObjectWriter(raw_pwrite_stream &OS,
     432             :                                                    uint8_t OSABI,
     433             :                                                    bool IsLittleEndian,
     434             :                                                    bool IsILP32) {
     435             :   MCELFObjectTargetWriter *MOTW =
     436         312 :       new AArch64ELFObjectWriter(OSABI, IsLittleEndian, IsILP32);
     437         156 :   return createELFObjectWriter(MOTW, OS, IsLittleEndian);
     438             : }

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