LCOV - code coverage report
Current view: top level - lib/Target/AArch64/MCTargetDesc - AArch64ELFObjectWriter.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 215 241 89.2 %
Date: 2018-02-22 04:41:24 Functions: 4 5 80.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file handles ELF-specific object emission, converting LLVM's internal
      11             : // fixups into the appropriate relocations.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "MCTargetDesc/AArch64FixupKinds.h"
      16             : #include "MCTargetDesc/AArch64MCExpr.h"
      17             : #include "MCTargetDesc/AArch64MCTargetDesc.h"
      18             : #include "llvm/BinaryFormat/ELF.h"
      19             : #include "llvm/MC/MCContext.h"
      20             : #include "llvm/MC/MCELFObjectWriter.h"
      21             : #include "llvm/MC/MCFixup.h"
      22             : #include "llvm/MC/MCObjectWriter.h"
      23             : #include "llvm/MC/MCValue.h"
      24             : #include "llvm/Support/ErrorHandling.h"
      25             : #include <cassert>
      26             : #include <cstdint>
      27             : 
      28             : using namespace llvm;
      29             : 
      30             : namespace {
      31             : 
      32             : class AArch64ELFObjectWriter : public MCELFObjectTargetWriter {
      33             : public:
      34             :   AArch64ELFObjectWriter(uint8_t OSABI, bool IsLittleEndian, bool IsILP32);
      35             : 
      36         193 :   ~AArch64ELFObjectWriter() override = default;
      37             : 
      38             : protected:
      39             :   unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
      40             :                         const MCFixup &Fixup, bool IsPCRel) const override;
      41             :   bool IsILP32;
      42             : };
      43             : 
      44             : } // end anonymous namespace
      45             : 
      46             : AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI,
      47             :                                                bool IsLittleEndian,
      48         193 :                                                bool IsILP32)
      49             :     : MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI, ELF::EM_AARCH64,
      50             :                               /*HasRelocationAddend*/ true),
      51         193 :       IsILP32(IsILP32) {}
      52             : 
      53             : #define R_CLS(rtype)                                                           \
      54             :   IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype
      55             : #define BAD_ILP32_MOV(lp64rtype)                                               \
      56             :   "ILP32 absolute MOV relocation not "                                         \
      57             :   "supported (LP64 eqv: " #lp64rtype ")"
      58             : 
      59             : // assumes IsILP32 is true
      60          85 : static bool isNonILP32reloc(const MCFixup &Fixup,
      61             :                             AArch64MCExpr::VariantKind RefKind,
      62             :                             MCContext &Ctx) {
      63          85 :   if ((unsigned)Fixup.getKind() != AArch64::fixup_aarch64_movw)
      64             :     return false;
      65          12 :   switch (RefKind) {
      66             :   case AArch64MCExpr::VK_ABS_G3:
      67           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G3));
      68           1 :     return true;
      69             :   case AArch64MCExpr::VK_ABS_G2:
      70           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2));
      71           1 :     return true;
      72             :   case AArch64MCExpr::VK_ABS_G2_S:
      73           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G2));
      74           1 :     return true;
      75             :   case AArch64MCExpr::VK_ABS_G2_NC:
      76           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2_NC));
      77           1 :     return true;
      78             :   case AArch64MCExpr::VK_ABS_G1_S:
      79           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G1));
      80           1 :     return true;
      81             :   case AArch64MCExpr::VK_ABS_G1_NC:
      82           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G1_NC));
      83           1 :     return true;
      84             :   case AArch64MCExpr::VK_DTPREL_G2:
      85           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G2));
      86           1 :     return true;
      87             :   case AArch64MCExpr::VK_DTPREL_G1_NC:
      88           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G1_NC));
      89           1 :     return true;
      90             :   case AArch64MCExpr::VK_TPREL_G2:
      91           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G2));
      92           1 :     return true;
      93             :   case AArch64MCExpr::VK_TPREL_G1_NC:
      94           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G1_NC));
      95           1 :     return true;
      96             :   case AArch64MCExpr::VK_GOTTPREL_G1:
      97           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G1));
      98           1 :     return true;
      99             :   case AArch64MCExpr::VK_GOTTPREL_G0_NC:
     100           1 :     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G0_NC));
     101           1 :     return true;
     102             :   default:
     103             :     return false;
     104             :   }
     105             :   return false;
     106             : }
     107             : 
     108         953 : unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
     109             :                                               const MCValue &Target,
     110             :                                               const MCFixup &Fixup,
     111             :                                               bool IsPCRel) const {
     112             :   AArch64MCExpr::VariantKind RefKind =
     113         953 :       static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
     114             :   AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind);
     115             :   bool IsNC = AArch64MCExpr::isNotChecked(RefKind);
     116             : 
     117             :   assert((!Target.getSymA() ||
     118             :           Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None) &&
     119             :          "Should only be expression-level modifiers here");
     120             : 
     121             :   assert((!Target.getSymB() ||
     122             :           Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None) &&
     123             :          "Should only be expression-level modifiers here");
     124             : 
     125         953 :   if (IsPCRel) {
     126         296 :     switch ((unsigned)Fixup.getKind()) {
     127             :     case FK_Data_1:
     128           1 :       Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
     129           1 :       return ELF::R_AARCH64_NONE;
     130           6 :     case FK_Data_2:
     131           6 :       return R_CLS(PREL16);
     132          46 :     case FK_Data_4:
     133          46 :       return R_CLS(PREL32);
     134           8 :     case FK_Data_8:
     135           8 :       if (IsILP32) {
     136           1 :         Ctx.reportError(Fixup.getLoc(),
     137             :                         "ILP32 8 byte PC relative data "
     138             :                         "relocation not supported (LP64 eqv: PREL64)");
     139           1 :         return ELF::R_AARCH64_NONE;
     140             :       } else
     141             :         return ELF::R_AARCH64_PREL64;
     142           6 :     case AArch64::fixup_aarch64_pcrel_adr_imm21:
     143             :       assert(SymLoc == AArch64MCExpr::VK_NONE && "unexpected ADR relocation");
     144           6 :       return R_CLS(ADR_PREL_LO21);
     145         145 :     case AArch64::fixup_aarch64_pcrel_adrp_imm21:
     146         145 :       if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC)
     147          88 :         return R_CLS(ADR_PREL_PG_HI21);
     148          57 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) {
     149           0 :         if (IsILP32) {
     150           0 :           Ctx.reportError(Fixup.getLoc(),
     151             :                           "invalid fixup for 32-bit pcrel ADRP instruction "
     152             :                           "VK_ABS VK_NC");
     153           0 :           return ELF::R_AARCH64_NONE;
     154             :         } else {
     155             :           return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC;
     156             :         }
     157             :       }
     158          57 :       if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC)
     159          18 :         return R_CLS(ADR_GOT_PAGE);
     160          39 :       if (SymLoc == AArch64MCExpr::VK_GOTTPREL && !IsNC)
     161          15 :         return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21);
     162          24 :       if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC)
     163          24 :         return R_CLS(TLSDESC_ADR_PAGE21);
     164           0 :       Ctx.reportError(Fixup.getLoc(),
     165             :                       "invalid symbol kind for ADRP relocation");
     166           0 :       return ELF::R_AARCH64_NONE;
     167          12 :     case AArch64::fixup_aarch64_pcrel_branch26:
     168          12 :       return R_CLS(JUMP26);
     169          37 :     case AArch64::fixup_aarch64_pcrel_call26:
     170          37 :       return R_CLS(CALL26);
     171          14 :     case AArch64::fixup_aarch64_ldr_pcrel_imm19:
     172          14 :       if (SymLoc == AArch64MCExpr::VK_GOTTPREL)
     173           2 :         return R_CLS(TLSIE_LD_GOTTPREL_PREL19);
     174          12 :       return R_CLS(LD_PREL_LO19);
     175           8 :     case AArch64::fixup_aarch64_pcrel_branch14:
     176           8 :       return R_CLS(TSTBR14);
     177           8 :     case AArch64::fixup_aarch64_pcrel_branch19:
     178           8 :       return R_CLS(CONDBR19);
     179             :     default:
     180           5 :       Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
     181           5 :       return ELF::R_AARCH64_NONE;
     182             :     }
     183             :   } else {
     184         657 :     if (IsILP32 && isNonILP32reloc(Fixup, RefKind, Ctx))
     185             :       return ELF::R_AARCH64_NONE;
     186         645 :     switch ((unsigned)Fixup.getKind()) {
     187             :     case FK_Data_1:
     188           1 :       Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
     189           1 :       return ELF::R_AARCH64_NONE;
     190           6 :     case FK_Data_2:
     191           6 :       return R_CLS(ABS16);
     192          72 :     case FK_Data_4:
     193          72 :       return R_CLS(ABS32);
     194          63 :     case FK_Data_8:
     195          63 :       if (IsILP32) {
     196           1 :         Ctx.reportError(Fixup.getLoc(),
     197             :                         "ILP32 8 byte absolute data "
     198             :                         "relocation not supported (LP64 eqv: ABS64)");
     199           1 :         return ELF::R_AARCH64_NONE;
     200             :       } else
     201             :         return ELF::R_AARCH64_ABS64;
     202         101 :     case AArch64::fixup_aarch64_add_imm12:
     203         101 :       if (RefKind == AArch64MCExpr::VK_DTPREL_HI12)
     204           8 :         return R_CLS(TLSLD_ADD_DTPREL_HI12);
     205          93 :       if (RefKind == AArch64MCExpr::VK_TPREL_HI12)
     206           8 :         return R_CLS(TLSLE_ADD_TPREL_HI12);
     207          85 :       if (RefKind == AArch64MCExpr::VK_DTPREL_LO12_NC)
     208          11 :         return R_CLS(TLSLD_ADD_DTPREL_LO12_NC);
     209          74 :       if (RefKind == AArch64MCExpr::VK_DTPREL_LO12)
     210           8 :         return R_CLS(TLSLD_ADD_DTPREL_LO12);
     211          66 :       if (RefKind == AArch64MCExpr::VK_TPREL_LO12_NC)
     212          11 :         return R_CLS(TLSLE_ADD_TPREL_LO12_NC);
     213          55 :       if (RefKind == AArch64MCExpr::VK_TPREL_LO12)
     214           8 :         return R_CLS(TLSLE_ADD_TPREL_LO12);
     215          47 :       if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12)
     216          24 :         return R_CLS(TLSDESC_ADD_LO12);
     217          23 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     218          23 :         return R_CLS(ADD_ABS_LO12_NC);
     219             : 
     220           0 :       Ctx.reportError(Fixup.getLoc(),
     221             :                       "invalid fixup for add (uimm12) instruction");
     222           0 :       return ELF::R_AARCH64_NONE;
     223          43 :     case AArch64::fixup_aarch64_ldst_imm12_scale1:
     224          43 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     225          18 :         return R_CLS(LDST8_ABS_LO12_NC);
     226          25 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
     227           6 :         return R_CLS(TLSLD_LDST8_DTPREL_LO12);
     228          19 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
     229           6 :         return R_CLS(TLSLD_LDST8_DTPREL_LO12_NC);
     230          13 :       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
     231           6 :         return R_CLS(TLSLE_LDST8_TPREL_LO12);
     232           7 :       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
     233           6 :         return R_CLS(TLSLE_LDST8_TPREL_LO12_NC);
     234             : 
     235           1 :       Ctx.reportError(Fixup.getLoc(),
     236             :                       "invalid fixup for 8-bit load/store instruction");
     237           1 :       return ELF::R_AARCH64_NONE;
     238          45 :     case AArch64::fixup_aarch64_ldst_imm12_scale2:
     239          45 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     240          20 :         return R_CLS(LDST16_ABS_LO12_NC);
     241          25 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
     242           6 :         return R_CLS(TLSLD_LDST16_DTPREL_LO12);
     243          19 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
     244           6 :         return R_CLS(TLSLD_LDST16_DTPREL_LO12_NC);
     245          13 :       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
     246           6 :         return R_CLS(TLSLE_LDST16_TPREL_LO12);
     247           7 :       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
     248           6 :         return R_CLS(TLSLE_LDST16_TPREL_LO12_NC);
     249             : 
     250           1 :       Ctx.reportError(Fixup.getLoc(),
     251             :                       "invalid fixup for 16-bit load/store instruction");
     252           1 :       return ELF::R_AARCH64_NONE;
     253          45 :     case AArch64::fixup_aarch64_ldst_imm12_scale4:
     254          45 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     255          18 :         return R_CLS(LDST32_ABS_LO12_NC);
     256          27 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
     257           4 :         return R_CLS(TLSLD_LDST32_DTPREL_LO12);
     258          23 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
     259           6 :         return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC);
     260          17 :       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
     261           4 :         return R_CLS(TLSLE_LDST32_TPREL_LO12);
     262          13 :       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
     263           6 :         return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);
     264           7 :       if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
     265           2 :         if (IsILP32) {
     266             :           return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC;
     267             :         } else {
     268           0 :           Ctx.reportError(Fixup.getLoc(),
     269             :                           "LP64 4 byte unchecked GOT load/store relocation "
     270             :                           "not supported (ILP32 eqv: LD32_GOT_LO12_NC");
     271           0 :           return ELF::R_AARCH64_NONE;
     272             :         }
     273             :       }
     274           5 :       if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) {
     275           0 :         if (IsILP32) {
     276           0 :           Ctx.reportError(Fixup.getLoc(),
     277             :                           "ILP32 4 byte checked GOT load/store relocation "
     278             :                           "not supported (unchecked eqv: LD32_GOT_LO12_NC)");
     279             :         } else {
     280           0 :           Ctx.reportError(Fixup.getLoc(),
     281             :                           "LP64 4 byte checked GOT load/store relocation "
     282             :                           "not supported (unchecked/ILP32 eqv: "
     283             :                           "LD32_GOT_LO12_NC)");
     284             :         }
     285             :         return ELF::R_AARCH64_NONE;
     286             :       }
     287           5 :       if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
     288           3 :         if (IsILP32) {
     289             :           return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC;
     290             :         } else {
     291           1 :           Ctx.reportError(Fixup.getLoc(),
     292             :                           "LP64 32-bit load/store "
     293             :                           "relocation not supported (ILP32 eqv: "
     294             :                           "TLSIE_LD32_GOTTPREL_LO12_NC)");
     295           1 :           return ELF::R_AARCH64_NONE;
     296             :         }
     297             :       }
     298           2 :       if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) {
     299           2 :         if (IsILP32) {
     300             :           return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12;
     301             :         } else {
     302           0 :           Ctx.reportError(Fixup.getLoc(),
     303             :                           "LP64 4 byte TLSDESC load/store relocation "
     304             :                           "not supported (ILP32 eqv: TLSDESC_LD64_LO12)");
     305           0 :           return ELF::R_AARCH64_NONE;
     306             :         }
     307             :       }
     308             : 
     309           0 :       Ctx.reportError(Fixup.getLoc(),
     310             :                       "invalid fixup for 32-bit load/store instruction "
     311             :                       "fixup_aarch64_ldst_imm12_scale4");
     312           0 :       return ELF::R_AARCH64_NONE;
     313         136 :     case AArch64::fixup_aarch64_ldst_imm12_scale8:
     314         136 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     315          26 :         return R_CLS(LDST64_ABS_LO12_NC);
     316         110 :       if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
     317          57 :         if (!IsILP32) {
     318             :           return ELF::R_AARCH64_LD64_GOT_LO12_NC;
     319             :         } else {
     320           2 :           Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
     321             :                                           "relocation not supported (LP64 eqv: "
     322             :                                           "LD64_GOT_LO12_NC)");
     323           2 :           return ELF::R_AARCH64_NONE;
     324             :         }
     325             :       }
     326          53 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
     327           4 :         return R_CLS(TLSLD_LDST64_DTPREL_LO12);
     328          49 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
     329           4 :         return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC);
     330          45 :       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
     331           4 :         return R_CLS(TLSLE_LDST64_TPREL_LO12);
     332          41 :       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
     333           4 :         return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);
     334          37 :       if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
     335          16 :         if (!IsILP32) {
     336             :           return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
     337             :         } else {
     338           4 :           Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
     339             :                                           "relocation not supported (LP64 eqv: "
     340             :                                           "TLSIE_LD64_GOTTPREL_LO12_NC)");
     341           4 :           return ELF::R_AARCH64_NONE;
     342             :         }
     343             :       }
     344          21 :       if (SymLoc == AArch64MCExpr::VK_TLSDESC) {
     345          21 :         if (!IsILP32) {
     346             :           return ELF::R_AARCH64_TLSDESC_LD64_LO12;
     347             :         } else {
     348           0 :           Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
     349             :                                           "relocation not supported (LP64 eqv: "
     350             :                                           "TLSDESC_LD64_LO12)");
     351           0 :           return ELF::R_AARCH64_NONE;
     352             :         }
     353             :       }
     354           0 :       Ctx.reportError(Fixup.getLoc(),
     355             :                       "invalid fixup for 64-bit load/store instruction");
     356           0 :       return ELF::R_AARCH64_NONE;
     357          20 :     case AArch64::fixup_aarch64_ldst_imm12_scale16:
     358          20 :       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
     359           8 :         return R_CLS(LDST128_ABS_LO12_NC);
     360          12 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
     361           3 :         return R_CLS(TLSLD_LDST128_DTPREL_LO12);
     362           9 :       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
     363           3 :         return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC);
     364           6 :       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
     365           3 :         return R_CLS(TLSLE_LDST128_TPREL_LO12);
     366           3 :       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
     367           3 :         return R_CLS(TLSLE_LDST128_TPREL_LO12_NC);
     368             : 
     369           0 :       Ctx.reportError(Fixup.getLoc(),
     370             :                       "invalid fixup for 128-bit load/store instruction");
     371           0 :       return ELF::R_AARCH64_NONE;
     372             :     // ILP32 case not reached here, tested with isNonILP32reloc
     373          94 :     case AArch64::fixup_aarch64_movw:
     374          94 :       if (RefKind == AArch64MCExpr::VK_ABS_G3)
     375             :         return ELF::R_AARCH64_MOVW_UABS_G3;
     376          87 :       if (RefKind == AArch64MCExpr::VK_ABS_G2)
     377             :         return ELF::R_AARCH64_MOVW_UABS_G2;
     378          85 :       if (RefKind == AArch64MCExpr::VK_ABS_G2_S)
     379             :         return ELF::R_AARCH64_MOVW_SABS_G2;
     380          83 :       if (RefKind == AArch64MCExpr::VK_ABS_G2_NC)
     381             :         return ELF::R_AARCH64_MOVW_UABS_G2_NC;
     382          78 :       if (RefKind == AArch64MCExpr::VK_ABS_G1)
     383           2 :         return R_CLS(MOVW_UABS_G1);
     384          76 :       if (RefKind == AArch64MCExpr::VK_ABS_G1_S)
     385             :         return ELF::R_AARCH64_MOVW_SABS_G1;
     386          74 :       if (RefKind == AArch64MCExpr::VK_ABS_G1_NC)
     387             :         return ELF::R_AARCH64_MOVW_UABS_G1_NC;
     388          69 :       if (RefKind == AArch64MCExpr::VK_ABS_G0)
     389           2 :         return R_CLS(MOVW_UABS_G0);
     390          67 :       if (RefKind == AArch64MCExpr::VK_ABS_G0_S)
     391           2 :         return R_CLS(MOVW_SABS_G0);
     392          65 :       if (RefKind == AArch64MCExpr::VK_ABS_G0_NC)
     393           5 :         return R_CLS(MOVW_UABS_G0_NC);
     394          60 :       if (RefKind == AArch64MCExpr::VK_DTPREL_G2)
     395             :         return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
     396          54 :       if (RefKind == AArch64MCExpr::VK_DTPREL_G1)
     397           7 :         return R_CLS(TLSLD_MOVW_DTPREL_G1);
     398          47 :       if (RefKind == AArch64MCExpr::VK_DTPREL_G1_NC)
     399             :         return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
     400          43 :       if (RefKind == AArch64MCExpr::VK_DTPREL_G0)
     401           7 :         return R_CLS(TLSLD_MOVW_DTPREL_G0);
     402          36 :       if (RefKind == AArch64MCExpr::VK_DTPREL_G0_NC)
     403           4 :         return R_CLS(TLSLD_MOVW_DTPREL_G0_NC);
     404          32 :       if (RefKind == AArch64MCExpr::VK_TPREL_G2)
     405             :         return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
     406          28 :       if (RefKind == AArch64MCExpr::VK_TPREL_G1)
     407           7 :         return R_CLS(TLSLE_MOVW_TPREL_G1);
     408          21 :       if (RefKind == AArch64MCExpr::VK_TPREL_G1_NC)
     409             :         return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
     410          17 :       if (RefKind == AArch64MCExpr::VK_TPREL_G0)
     411           7 :         return R_CLS(TLSLE_MOVW_TPREL_G0);
     412          10 :       if (RefKind == AArch64MCExpr::VK_TPREL_G0_NC)
     413           4 :         return R_CLS(TLSLE_MOVW_TPREL_G0_NC);
     414           6 :       if (RefKind == AArch64MCExpr::VK_GOTTPREL_G1)
     415             :         return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
     416           3 :       if (RefKind == AArch64MCExpr::VK_GOTTPREL_G0_NC)
     417             :         return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
     418           0 :       Ctx.reportError(Fixup.getLoc(),
     419             :                       "invalid fixup for movz/movk instruction");
     420           0 :       return ELF::R_AARCH64_NONE;
     421          19 :     case AArch64::fixup_aarch64_tlsdesc_call:
     422          19 :       return R_CLS(TLSDESC_CALL);
     423             :     default:
     424           0 :       Ctx.reportError(Fixup.getLoc(), "Unknown ELF relocation type");
     425           0 :       return ELF::R_AARCH64_NONE;
     426             :     }
     427             :   }
     428             : 
     429             :   llvm_unreachable("Unimplemented fixup -> relocation");
     430             : }
     431             : 
     432             : std::unique_ptr<MCObjectWriter>
     433         193 : llvm::createAArch64ELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
     434             :                                    bool IsLittleEndian, bool IsILP32) {
     435             :   auto MOTW =
     436         193 :       llvm::make_unique<AArch64ELFObjectWriter>(OSABI, IsLittleEndian, IsILP32);
     437         772 :   return createELFObjectWriter(std::move(MOTW), OS, IsLittleEndian);
     438             : }

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