LCOV - code coverage report
Current view: top level - lib/Target/AArch64/Utils - AArch64BaseInfo.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 74 147 50.3 %
Date: 2018-07-13 00:08:38 Functions: 5 5 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains small standalone helper functions and enum definitions for
      11             : // the AArch64 target useful for the compiler back-end and the MC libraries.
      12             : // As such, it deliberately does not include references to LLVM core
      13             : // code gen types, passes, etc..
      14             : //
      15             : //===----------------------------------------------------------------------===//
      16             : 
      17             : #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
      18             : #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
      19             : 
      20             : // FIXME: Is it easiest to fix this layering violation by moving the .inc
      21             : // #includes from AArch64MCTargetDesc.h to here?
      22             : #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
      23             : #include "llvm/ADT/STLExtras.h"
      24             : #include "llvm/ADT/StringSwitch.h"
      25             : #include "llvm/MC/SubtargetFeature.h"
      26             : #include "llvm/Support/ErrorHandling.h"
      27             : 
      28             : namespace llvm {
      29             : 
      30         453 : inline static unsigned getWRegFromXReg(unsigned Reg) {
      31         453 :   switch (Reg) {
      32             :   case AArch64::X0: return AArch64::W0;
      33          26 :   case AArch64::X1: return AArch64::W1;
      34           7 :   case AArch64::X2: return AArch64::W2;
      35           6 :   case AArch64::X3: return AArch64::W3;
      36           0 :   case AArch64::X4: return AArch64::W4;
      37           2 :   case AArch64::X5: return AArch64::W5;
      38           0 :   case AArch64::X6: return AArch64::W6;
      39           0 :   case AArch64::X7: return AArch64::W7;
      40          14 :   case AArch64::X8: return AArch64::W8;
      41           4 :   case AArch64::X9: return AArch64::W9;
      42           0 :   case AArch64::X10: return AArch64::W10;
      43           0 :   case AArch64::X11: return AArch64::W11;
      44           0 :   case AArch64::X12: return AArch64::W12;
      45           0 :   case AArch64::X13: return AArch64::W13;
      46           0 :   case AArch64::X14: return AArch64::W14;
      47           0 :   case AArch64::X15: return AArch64::W15;
      48           0 :   case AArch64::X16: return AArch64::W16;
      49           0 :   case AArch64::X17: return AArch64::W17;
      50           0 :   case AArch64::X18: return AArch64::W18;
      51           0 :   case AArch64::X19: return AArch64::W19;
      52           0 :   case AArch64::X20: return AArch64::W20;
      53           0 :   case AArch64::X21: return AArch64::W21;
      54           1 :   case AArch64::X22: return AArch64::W22;
      55           0 :   case AArch64::X23: return AArch64::W23;
      56           0 :   case AArch64::X24: return AArch64::W24;
      57           0 :   case AArch64::X25: return AArch64::W25;
      58           0 :   case AArch64::X26: return AArch64::W26;
      59           0 :   case AArch64::X27: return AArch64::W27;
      60           0 :   case AArch64::X28: return AArch64::W28;
      61           0 :   case AArch64::FP: return AArch64::W29;
      62           5 :   case AArch64::LR: return AArch64::W30;
      63           1 :   case AArch64::SP: return AArch64::WSP;
      64          18 :   case AArch64::XZR: return AArch64::WZR;
      65             :   }
      66             :   // For anything else, return it unchanged.
      67         256 :   return Reg;
      68             : }
      69             : 
      70         254 : inline static unsigned getXRegFromWReg(unsigned Reg) {
      71         254 :   switch (Reg) {
      72             :   case AArch64::W0: return AArch64::X0;
      73          21 :   case AArch64::W1: return AArch64::X1;
      74           4 :   case AArch64::W2: return AArch64::X2;
      75           1 :   case AArch64::W3: return AArch64::X3;
      76           0 :   case AArch64::W4: return AArch64::X4;
      77           0 :   case AArch64::W5: return AArch64::X5;
      78           0 :   case AArch64::W6: return AArch64::X6;
      79           0 :   case AArch64::W7: return AArch64::X7;
      80           3 :   case AArch64::W8: return AArch64::X8;
      81           0 :   case AArch64::W9: return AArch64::X9;
      82           2 :   case AArch64::W10: return AArch64::X10;
      83           0 :   case AArch64::W11: return AArch64::X11;
      84           0 :   case AArch64::W12: return AArch64::X12;
      85           0 :   case AArch64::W13: return AArch64::X13;
      86           0 :   case AArch64::W14: return AArch64::X14;
      87           0 :   case AArch64::W15: return AArch64::X15;
      88           0 :   case AArch64::W16: return AArch64::X16;
      89           0 :   case AArch64::W17: return AArch64::X17;
      90           0 :   case AArch64::W18: return AArch64::X18;
      91           2 :   case AArch64::W19: return AArch64::X19;
      92           2 :   case AArch64::W20: return AArch64::X20;
      93           1 :   case AArch64::W21: return AArch64::X21;
      94           1 :   case AArch64::W22: return AArch64::X22;
      95           1 :   case AArch64::W23: return AArch64::X23;
      96           1 :   case AArch64::W24: return AArch64::X24;
      97           1 :   case AArch64::W25: return AArch64::X25;
      98           1 :   case AArch64::W26: return AArch64::X26;
      99           2 :   case AArch64::W27: return AArch64::X27;
     100           2 :   case AArch64::W28: return AArch64::X28;
     101           9 :   case AArch64::W29: return AArch64::FP;
     102           3 :   case AArch64::W30: return AArch64::LR;
     103           0 :   case AArch64::WSP: return AArch64::SP;
     104          28 :   case AArch64::WZR: return AArch64::XZR;
     105             :   }
     106             :   // For anything else, return it unchanged.
     107          21 :   return Reg;
     108             : }
     109             : 
     110             : static inline unsigned getBRegFromDReg(unsigned Reg) {
     111             :   switch (Reg) {
     112             :   case AArch64::D0:  return AArch64::B0;
     113             :   case AArch64::D1:  return AArch64::B1;
     114             :   case AArch64::D2:  return AArch64::B2;
     115             :   case AArch64::D3:  return AArch64::B3;
     116             :   case AArch64::D4:  return AArch64::B4;
     117             :   case AArch64::D5:  return AArch64::B5;
     118             :   case AArch64::D6:  return AArch64::B6;
     119             :   case AArch64::D7:  return AArch64::B7;
     120             :   case AArch64::D8:  return AArch64::B8;
     121             :   case AArch64::D9:  return AArch64::B9;
     122             :   case AArch64::D10: return AArch64::B10;
     123             :   case AArch64::D11: return AArch64::B11;
     124             :   case AArch64::D12: return AArch64::B12;
     125             :   case AArch64::D13: return AArch64::B13;
     126             :   case AArch64::D14: return AArch64::B14;
     127             :   case AArch64::D15: return AArch64::B15;
     128             :   case AArch64::D16: return AArch64::B16;
     129             :   case AArch64::D17: return AArch64::B17;
     130             :   case AArch64::D18: return AArch64::B18;
     131             :   case AArch64::D19: return AArch64::B19;
     132             :   case AArch64::D20: return AArch64::B20;
     133             :   case AArch64::D21: return AArch64::B21;
     134             :   case AArch64::D22: return AArch64::B22;
     135             :   case AArch64::D23: return AArch64::B23;
     136             :   case AArch64::D24: return AArch64::B24;
     137             :   case AArch64::D25: return AArch64::B25;
     138             :   case AArch64::D26: return AArch64::B26;
     139             :   case AArch64::D27: return AArch64::B27;
     140             :   case AArch64::D28: return AArch64::B28;
     141             :   case AArch64::D29: return AArch64::B29;
     142             :   case AArch64::D30: return AArch64::B30;
     143             :   case AArch64::D31: return AArch64::B31;
     144             :   }
     145             :   // For anything else, return it unchanged.
     146             :   return Reg;
     147             : }
     148             : 
     149             : 
     150           4 : static inline unsigned getDRegFromBReg(unsigned Reg) {
     151           4 :   switch (Reg) {
     152             :   case AArch64::B0:  return AArch64::D0;
     153           0 :   case AArch64::B1:  return AArch64::D1;
     154           0 :   case AArch64::B2:  return AArch64::D2;
     155           0 :   case AArch64::B3:  return AArch64::D3;
     156           0 :   case AArch64::B4:  return AArch64::D4;
     157           0 :   case AArch64::B5:  return AArch64::D5;
     158           0 :   case AArch64::B6:  return AArch64::D6;
     159           0 :   case AArch64::B7:  return AArch64::D7;
     160           0 :   case AArch64::B8:  return AArch64::D8;
     161           0 :   case AArch64::B9:  return AArch64::D9;
     162           0 :   case AArch64::B10: return AArch64::D10;
     163           0 :   case AArch64::B11: return AArch64::D11;
     164           0 :   case AArch64::B12: return AArch64::D12;
     165           0 :   case AArch64::B13: return AArch64::D13;
     166           0 :   case AArch64::B14: return AArch64::D14;
     167           0 :   case AArch64::B15: return AArch64::D15;
     168           0 :   case AArch64::B16: return AArch64::D16;
     169           0 :   case AArch64::B17: return AArch64::D17;
     170           0 :   case AArch64::B18: return AArch64::D18;
     171           0 :   case AArch64::B19: return AArch64::D19;
     172           0 :   case AArch64::B20: return AArch64::D20;
     173           0 :   case AArch64::B21: return AArch64::D21;
     174           0 :   case AArch64::B22: return AArch64::D22;
     175           0 :   case AArch64::B23: return AArch64::D23;
     176           0 :   case AArch64::B24: return AArch64::D24;
     177           0 :   case AArch64::B25: return AArch64::D25;
     178           0 :   case AArch64::B26: return AArch64::D26;
     179           0 :   case AArch64::B27: return AArch64::D27;
     180           0 :   case AArch64::B28: return AArch64::D28;
     181           0 :   case AArch64::B29: return AArch64::D29;
     182           0 :   case AArch64::B30: return AArch64::D30;
     183           0 :   case AArch64::B31: return AArch64::D31;
     184             :   }
     185             :   // For anything else, return it unchanged.
     186           4 :   return Reg;
     187             : }
     188             : 
     189             : namespace AArch64CC {
     190             : 
     191             : // The CondCodes constants map directly to the 4-bit encoding of the condition
     192             : // field for predicated instructions.
     193             : enum CondCode {  // Meaning (integer)          Meaning (floating-point)
     194             :   EQ = 0x0,      // Equal                      Equal
     195             :   NE = 0x1,      // Not equal                  Not equal, or unordered
     196             :   HS = 0x2,      // Unsigned higher or same    >, ==, or unordered
     197             :   LO = 0x3,      // Unsigned lower             Less than
     198             :   MI = 0x4,      // Minus, negative            Less than
     199             :   PL = 0x5,      // Plus, positive or zero     >, ==, or unordered
     200             :   VS = 0x6,      // Overflow                   Unordered
     201             :   VC = 0x7,      // No overflow                Not unordered
     202             :   HI = 0x8,      // Unsigned higher            Greater than, or unordered
     203             :   LS = 0x9,      // Unsigned lower or same     Less than or equal
     204             :   GE = 0xa,      // Greater than or equal      Greater than or equal
     205             :   LT = 0xb,      // Less than                  Less than, or unordered
     206             :   GT = 0xc,      // Greater than               Greater than
     207             :   LE = 0xd,      // Less than or equal         <, ==, or unordered
     208             :   AL = 0xe,      // Always (unconditional)     Always (unconditional)
     209             :   NV = 0xf,      // Always (unconditional)     Always (unconditional)
     210             :   // Note the NV exists purely to disassemble 0b1111. Execution is "always".
     211             :   Invalid
     212             : };
     213             : 
     214        2306 : inline static const char *getCondCodeName(CondCode Code) {
     215        2306 :   switch (Code) {
     216           0 :   default: llvm_unreachable("Unknown condition code");
     217             :   case EQ:  return "eq";
     218         443 :   case NE:  return "ne";
     219         120 :   case HS:  return "hs";
     220          84 :   case LO:  return "lo";
     221         126 :   case MI:  return "mi";
     222          54 :   case PL:  return "pl";
     223          81 :   case VS:  return "vs";
     224          77 :   case VC:  return "vc";
     225         103 :   case HI:  return "hi";
     226          79 :   case LS:  return "ls";
     227         125 :   case GE:  return "ge";
     228         211 :   case LT:  return "lt";
     229         199 :   case GT:  return "gt";
     230         176 :   case LE:  return "le";
     231          21 :   case AL:  return "al";
     232          20 :   case NV:  return "nv";
     233             :   }
     234             : }
     235             : 
     236             : inline static CondCode getInvertedCondCode(CondCode Code) {
     237             :   // To reverse a condition it's necessary to only invert the low bit:
     238             : 
     239        2759 :   return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
     240             : }
     241             : 
     242             : /// Given a condition code, return NZCV flags that would satisfy that condition.
     243             : /// The flag bits are in the format expected by the ccmp instructions.
     244             : /// Note that many different flag settings can satisfy a given condition code,
     245             : /// this function just returns one of them.
     246          49 : inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
     247             :   // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
     248             :   enum { N = 8, Z = 4, C = 2, V = 1 };
     249          49 :   switch (Code) {
     250           0 :   default: llvm_unreachable("Unknown condition code");
     251             :   case EQ: return Z; // Z == 1
     252           7 :   case NE: return 0; // Z == 0
     253           0 :   case HS: return C; // C == 1
     254           0 :   case LO: return 0; // C == 0
     255           7 :   case MI: return N; // N == 1
     256           2 :   case PL: return 0; // N == 0
     257           7 :   case VS: return V; // V == 1
     258           0 :   case VC: return 0; // V == 0
     259           1 :   case HI: return C; // C == 1 && Z == 0
     260           0 :   case LS: return 0; // C == 0 || Z == 1
     261           2 :   case GE: return 0; // N == V
     262           4 :   case LT: return N; // N != V
     263           7 :   case GT: return 0; // Z == 0 && N == V
     264             :   case LE: return Z; // Z == 1 || N != V
     265             :   }
     266             : }
     267             : } // end namespace AArch64CC
     268             : 
     269             : struct SysAlias {
     270             :   const char *Name;
     271             :   uint16_t Encoding;
     272             :   FeatureBitset FeaturesRequired;
     273             : 
     274     3491005 :   SysAlias (const char *N, uint16_t E) : Name(N), Encoding(E) {};
     275    11969160 :   SysAlias (const char *N, uint16_t E, FeatureBitset F) :
     276    11969160 :     Name(N), Encoding(E), FeaturesRequired(F) {};
     277             : 
     278             :   bool haveFeatures(FeatureBitset ActiveFeatures) const {
     279         750 :     return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
     280             :   }
     281             : 
     282          53 :   FeatureBitset getRequiredFeatures() const { return FeaturesRequired; }
     283             : };
     284             : 
     285             : struct SysAliasReg : SysAlias {
     286             :   bool NeedsReg;
     287      398972 :   SysAliasReg(const char *N, uint16_t E, bool R) : SysAlias(N, E), NeedsReg(R) {};
     288     7779954 :   SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F) : SysAlias(N, E, F),
     289     7779954 :     NeedsReg(R) {};
     290             : };
     291             : 
     292             : namespace AArch64AT{
     293             :   struct AT : SysAlias {
     294             :     using SysAlias::SysAlias;
     295             :   };
     296             :   #define GET_AT_DECL
     297             :   #include "AArch64GenSystemOperands.inc"
     298             : }
     299             : 
     300             : namespace AArch64DB {
     301             :   struct DB : SysAlias {
     302             :     using SysAlias::SysAlias;
     303             :   };
     304             :   #define GET_DB_DECL
     305             :   #include "AArch64GenSystemOperands.inc"
     306             : }
     307             : 
     308             : namespace  AArch64DC {
     309             :   struct DC : SysAlias {
     310             :     using SysAlias::SysAlias;
     311             :   };
     312             :   #define GET_DC_DECL
     313             :   #include "AArch64GenSystemOperands.inc"
     314             : }
     315             : 
     316             : namespace  AArch64IC {
     317             :   struct IC : SysAliasReg {
     318             :     using SysAliasReg::SysAliasReg;
     319             :   };
     320             :   #define GET_IC_DECL
     321             :   #include "AArch64GenSystemOperands.inc"
     322             : }
     323             : 
     324             : namespace  AArch64ISB {
     325             :   struct ISB : SysAlias {
     326             :     using SysAlias::SysAlias;
     327             :   };
     328             :   #define GET_ISB_DECL
     329             :   #include "AArch64GenSystemOperands.inc"
     330             : }
     331             : 
     332             : namespace  AArch64TSB {
     333             :   struct TSB : SysAlias {
     334             :     using SysAlias::SysAlias;
     335             :   };
     336             :   #define GET_TSB_DECL
     337             :   #include "AArch64GenSystemOperands.inc"
     338             : }
     339             : 
     340             : namespace AArch64PRFM {
     341             :   struct PRFM : SysAlias {
     342             :     using SysAlias::SysAlias;
     343             :   };
     344             :   #define GET_PRFM_DECL
     345             :   #include "AArch64GenSystemOperands.inc"
     346             : }
     347             : 
     348             : namespace AArch64SVEPRFM {
     349             :   struct SVEPRFM : SysAlias {
     350             :     using SysAlias::SysAlias;
     351             :   };
     352             : #define GET_SVEPRFM_DECL
     353             : #include "AArch64GenSystemOperands.inc"
     354             : }
     355             : 
     356             : namespace AArch64SVEPredPattern {
     357             :   struct SVEPREDPAT {
     358             :     const char *Name;
     359             :     uint16_t Encoding;
     360             :   };
     361             : #define GET_SVEPREDPAT_DECL
     362             : #include "AArch64GenSystemOperands.inc"
     363             : }
     364             : 
     365             : namespace AArch64ExactFPImm {
     366             :   struct ExactFPImm {
     367             :     const char *Name;
     368             :     int Enum;
     369             :     const char *Repr;
     370             :   };
     371             : #define GET_EXACTFPIMM_DECL
     372             : #include "AArch64GenSystemOperands.inc"
     373             : }
     374             : 
     375             : namespace AArch64PState {
     376             :   struct PState : SysAlias{
     377             :     using SysAlias::SysAlias;
     378             :   };
     379             :   #define GET_PSTATE_DECL
     380             :   #include "AArch64GenSystemOperands.inc"
     381             : }
     382             : 
     383             : namespace AArch64PSBHint {
     384             :   struct PSB : SysAlias {
     385             :     using SysAlias::SysAlias;
     386             :   };
     387             :   #define GET_PSB_DECL
     388             :   #include "AArch64GenSystemOperands.inc"
     389             : }
     390             : 
     391             : namespace AArch64SE {
     392             :     enum ShiftExtSpecifiers {
     393             :         Invalid = -1,
     394             :         LSL,
     395             :         MSL,
     396             :         LSR,
     397             :         ASR,
     398             :         ROR,
     399             : 
     400             :         UXTB,
     401             :         UXTH,
     402             :         UXTW,
     403             :         UXTX,
     404             : 
     405             :         SXTB,
     406             :         SXTH,
     407             :         SXTW,
     408             :         SXTX
     409             :     };
     410             : }
     411             : 
     412             : namespace AArch64Layout {
     413             :     enum VectorLayout {
     414             :         Invalid = -1,
     415             :         VL_8B,
     416             :         VL_4H,
     417             :         VL_2S,
     418             :         VL_1D,
     419             : 
     420             :         VL_16B,
     421             :         VL_8H,
     422             :         VL_4S,
     423             :         VL_2D,
     424             : 
     425             :         // Bare layout for the 128-bit vector
     426             :         // (only show ".b", ".h", ".s", ".d" without vector number)
     427             :         VL_B,
     428             :         VL_H,
     429             :         VL_S,
     430             :         VL_D
     431             :     };
     432             : }
     433             : 
     434             : inline static const char *
     435             : AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) {
     436             :   switch (Layout) {
     437             :   case AArch64Layout::VL_8B:  return ".8b";
     438             :   case AArch64Layout::VL_4H:  return ".4h";
     439             :   case AArch64Layout::VL_2S:  return ".2s";
     440             :   case AArch64Layout::VL_1D:  return ".1d";
     441             :   case AArch64Layout::VL_16B:  return ".16b";
     442             :   case AArch64Layout::VL_8H:  return ".8h";
     443             :   case AArch64Layout::VL_4S:  return ".4s";
     444             :   case AArch64Layout::VL_2D:  return ".2d";
     445             :   case AArch64Layout::VL_B:  return ".b";
     446             :   case AArch64Layout::VL_H:  return ".h";
     447             :   case AArch64Layout::VL_S:  return ".s";
     448             :   case AArch64Layout::VL_D:  return ".d";
     449             :   default: llvm_unreachable("Unknown Vector Layout");
     450             :   }
     451             : }
     452             : 
     453             : inline static AArch64Layout::VectorLayout
     454             : AArch64StringToVectorLayout(StringRef LayoutStr) {
     455             :   return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr)
     456             :              .Case(".8b", AArch64Layout::VL_8B)
     457             :              .Case(".4h", AArch64Layout::VL_4H)
     458             :              .Case(".2s", AArch64Layout::VL_2S)
     459             :              .Case(".1d", AArch64Layout::VL_1D)
     460             :              .Case(".16b", AArch64Layout::VL_16B)
     461             :              .Case(".8h", AArch64Layout::VL_8H)
     462             :              .Case(".4s", AArch64Layout::VL_4S)
     463             :              .Case(".2d", AArch64Layout::VL_2D)
     464             :              .Case(".b", AArch64Layout::VL_B)
     465             :              .Case(".h", AArch64Layout::VL_H)
     466             :              .Case(".s", AArch64Layout::VL_S)
     467             :              .Case(".d", AArch64Layout::VL_D)
     468             :              .Default(AArch64Layout::Invalid);
     469             : }
     470             : 
     471             : namespace AArch64SysReg {
     472             :   struct SysReg {
     473             :     const char *Name;
     474             :     unsigned Encoding;
     475             :     bool Readable;
     476             :     bool Writeable;
     477             :     FeatureBitset FeaturesRequired;
     478             : 
     479             :     bool haveFeatures(FeatureBitset ActiveFeatures) const {
     480        7780 :       return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
     481             :     }
     482             :   };
     483             : 
     484             :   #define GET_SYSREG_DECL
     485             :   #include "AArch64GenSystemOperands.inc"
     486             : 
     487             :   const SysReg *lookupSysRegByName(StringRef);
     488             :   const SysReg *lookupSysRegByEncoding(uint16_t);
     489             : 
     490             :   uint32_t parseGenericRegister(StringRef Name);
     491             :   std::string genericRegisterString(uint32_t Bits);
     492             : }
     493             : 
     494             : namespace AArch64TLBI {
     495             :   struct TLBI : SysAliasReg {
     496             :     using SysAliasReg::SysAliasReg;
     497             :   };
     498             :   #define GET_TLBI_DECL
     499             :   #include "AArch64GenSystemOperands.inc"
     500             : }
     501             : 
     502             : namespace AArch64II {
     503             :   /// Target Operand Flag enum.
     504             :   enum TOF {
     505             :     //===------------------------------------------------------------------===//
     506             :     // AArch64 Specific MachineOperand flags.
     507             : 
     508             :     MO_NO_FLAG,
     509             : 
     510             :     MO_FRAGMENT = 0xf,
     511             : 
     512             :     /// MO_PAGE - A symbol operand with this flag represents the pc-relative
     513             :     /// offset of the 4K page containing the symbol.  This is used with the
     514             :     /// ADRP instruction.
     515             :     MO_PAGE = 1,
     516             : 
     517             :     /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
     518             :     /// that symbol within a 4K page.  This offset is added to the page address
     519             :     /// to produce the complete address.
     520             :     MO_PAGEOFF = 2,
     521             : 
     522             :     /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
     523             :     /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
     524             :     MO_G3 = 3,
     525             : 
     526             :     /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
     527             :     /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
     528             :     MO_G2 = 4,
     529             : 
     530             :     /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
     531             :     /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
     532             :     MO_G1 = 5,
     533             : 
     534             :     /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
     535             :     /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
     536             :     MO_G0 = 6,
     537             : 
     538             :     /// MO_HI12 - This flag indicates that a symbol operand represents the bits
     539             :     /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
     540             :     /// by-12-bits instruction.
     541             :     MO_HI12 = 7,
     542             : 
     543             :     /// MO_GOT - This flag indicates that a symbol operand represents the
     544             :     /// address of the GOT entry for the symbol, rather than the address of
     545             :     /// the symbol itself.
     546             :     MO_GOT = 0x10,
     547             : 
     548             :     /// MO_NC - Indicates whether the linker is expected to check the symbol
     549             :     /// reference for overflow. For example in an ADRP/ADD pair of relocations
     550             :     /// the ADRP usually does check, but not the ADD.
     551             :     MO_NC = 0x20,
     552             : 
     553             :     /// MO_TLS - Indicates that the operand being accessed is some kind of
     554             :     /// thread-local symbol. On Darwin, only one type of thread-local access
     555             :     /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
     556             :     /// referee will affect interpretation.
     557             :     MO_TLS = 0x40,
     558             : 
     559             :     /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
     560             :     /// to the symbol is for an import stub.  This is used for DLL import
     561             :     /// storage class indication on Windows.
     562             :     MO_DLLIMPORT = 0x80,
     563             :   };
     564             : } // end namespace AArch64II
     565             : 
     566             : } // end namespace llvm
     567             : 
     568             : #endif

Generated by: LCOV version 1.13