LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - AMDGPUGenRegisterBankInfo.def (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 6 6 100.0 %
Date: 2017-09-14 15:23:50 Functions: 1 1 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- AMDGPUGenRegisterBankInfo.def -----------------------------*- C++ -*-==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : /// \file
      10             : /// This file defines all the static objects used by AMDGPURegisterBankInfo.
      11             : /// \todo This should be generated by TableGen.
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : namespace llvm {
      15             : namespace AMDGPU {
      16             : 
      17             : enum PartialMappingIdx {
      18             :   None = - 1,
      19             :   PM_SGPR32 = 0,
      20             :   PM_SGPR64 = 1,
      21             :   PM_VGPR32 = 2,
      22             :   PM_VGPR64 = 3
      23             : };
      24             : 
      25             : const RegisterBankInfo::PartialMapping PartMappings[] {
      26             :   // StartIdx, Length, RegBank
      27             :   {0, 32, SGPRRegBank},
      28             :   {0, 64, SGPRRegBank},
      29             :   {0, 32, VGPRRegBank},
      30             :   {0, 64, VGPRRegBank}
      31      361530 : };
      32             : 
      33             : const RegisterBankInfo::ValueMapping ValMappings[] {
      34             :   // SGPR 32-bit
      35             :   {&PartMappings[0], 1},
      36             :   // SGPR 64-bit
      37             :   {&PartMappings[1], 1},
      38             :   // VGPR 32-bit
      39             :   {&PartMappings[2], 1},
      40             :   // VGPR 64-bit
      41             :   {&PartMappings[3], 1}
      42      361530 : };
      43             : 
      44             : enum ValueMappingIdx {
      45             :   SGPRStartIdx = 0,
      46             :   VGPRStartIdx = 2
      47             : };
      48             : 
      49         246 : const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
      50             :                                                       unsigned Size) {
      51             :   assert(Size % 32 == 0);
      52         246 :   unsigned Idx = BankID == AMDGPU::SGPRRegBankID ? SGPRStartIdx : VGPRStartIdx;
      53         246 :   Idx += (Size / 32) - 1;
      54         246 :   return &ValMappings[Idx];
      55             : }
      56             : 
      57             : } // End AMDGPU namespace.
      58             : } // End llvm namespace.

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