LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - AMDGPUISelDAGToDAG.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 900 942 95.5 %
Date: 2017-09-14 15:23:50 Functions: 71 77 92.2 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- AMDGPUISelDAGToDAG.cpp - A dag to dag inst selector for AMDGPU ----===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //==-----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// \brief Defines an instruction selector for the AMDGPU target.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "AMDGPU.h"
      16             : #include "AMDGPUArgumentUsageInfo.h"
      17             : #include "AMDGPUISelLowering.h" // For AMDGPUISD
      18             : #include "AMDGPUInstrInfo.h"
      19             : #include "AMDGPURegisterInfo.h"
      20             : #include "AMDGPUSubtarget.h"
      21             : #include "SIDefines.h"
      22             : #include "SIISelLowering.h"
      23             : #include "SIInstrInfo.h"
      24             : #include "SIMachineFunctionInfo.h"
      25             : #include "SIRegisterInfo.h"
      26             : #include "llvm/ADT/APInt.h"
      27             : #include "llvm/ADT/SmallVector.h"
      28             : #include "llvm/ADT/StringRef.h"
      29             : #include "llvm/Analysis/ValueTracking.h"
      30             : #include "llvm/CodeGen/FunctionLoweringInfo.h"
      31             : #include "llvm/CodeGen/ISDOpcodes.h"
      32             : #include "llvm/CodeGen/MachineFunction.h"
      33             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      34             : #include "llvm/CodeGen/MachineValueType.h"
      35             : #include "llvm/CodeGen/SelectionDAG.h"
      36             : #include "llvm/CodeGen/SelectionDAGISel.h"
      37             : #include "llvm/CodeGen/SelectionDAGNodes.h"
      38             : #include "llvm/CodeGen/ValueTypes.h"
      39             : #include "llvm/IR/BasicBlock.h"
      40             : #include "llvm/IR/Instruction.h"
      41             : #include "llvm/MC/MCInstrDesc.h"
      42             : #include "llvm/Support/Casting.h"
      43             : #include "llvm/Support/CodeGen.h"
      44             : #include "llvm/Support/ErrorHandling.h"
      45             : #include "llvm/Support/MathExtras.h"
      46             : #include <cassert>
      47             : #include <cstdint>
      48             : #include <new>
      49             : #include <vector>
      50             : 
      51             : using namespace llvm;
      52             : 
      53             : namespace llvm {
      54             : 
      55             : class R600InstrInfo;
      56             : 
      57             : } // end namespace llvm
      58             : 
      59             : //===----------------------------------------------------------------------===//
      60             : // Instruction Selector Implementation
      61             : //===----------------------------------------------------------------------===//
      62             : 
      63             : namespace {
      64             : 
      65             : /// AMDGPU specific code to select AMDGPU machine instructions for
      66             : /// SelectionDAG operations.
      67             : class AMDGPUDAGToDAGISel : public SelectionDAGISel {
      68             :   // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
      69             :   // make the right decision when generating code for different targets.
      70             :   const AMDGPUSubtarget *Subtarget;
      71             :   AMDGPUAS AMDGPUASI;
      72             : 
      73             : public:
      74             :   explicit AMDGPUDAGToDAGISel(TargetMachine *TM = nullptr,
      75             :                               CodeGenOpt::Level OptLevel = CodeGenOpt::Default)
      76        1707 :     : SelectionDAGISel(*TM, OptLevel) {
      77        1707 :     AMDGPUASI = AMDGPU::getAMDGPUAS(*TM);
      78             :   }
      79        1698 :   ~AMDGPUDAGToDAGISel() override = default;
      80             : 
      81        1701 :   void getAnalysisUsage(AnalysisUsage &AU) const override {
      82        1701 :     AU.addRequired<AMDGPUArgumentUsageInfo>();
      83        1701 :     SelectionDAGISel::getAnalysisUsage(AU);
      84        1701 :   }
      85             : 
      86             :   bool runOnMachineFunction(MachineFunction &MF) override;
      87             :   void Select(SDNode *N) override;
      88             :   StringRef getPassName() const override;
      89             :   void PostprocessISelDAG() override;
      90             : 
      91             : protected:
      92             :   void SelectBuildVector(SDNode *N, unsigned RegClassID);
      93             : 
      94             : private:
      95             :   std::pair<SDValue, SDValue> foldFrameIndex(SDValue N) const;
      96             :   bool isNoNanSrc(SDValue N) const;
      97             :   bool isInlineImmediate(const SDNode *N) const;
      98             :   bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
      99             :                    const R600InstrInfo *TII);
     100             :   bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
     101             :   bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
     102             : 
     103             :   bool isConstantLoad(const MemSDNode *N, int cbID) const;
     104             :   bool isUniformBr(const SDNode *N) const;
     105             : 
     106             :   SDNode *glueCopyToM0(SDNode *N) const;
     107             : 
     108             :   const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
     109             :   bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
     110             :   bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
     111             :                                        SDValue& Offset);
     112             :   virtual bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
     113             :   virtual bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
     114             :   bool isDSOffsetLegal(const SDValue &Base, unsigned Offset,
     115             :                        unsigned OffsetBits) const;
     116             :   bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
     117             :   bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
     118             :                                  SDValue &Offset1) const;
     119             :   bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
     120             :                    SDValue &SOffset, SDValue &Offset, SDValue &Offen,
     121             :                    SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
     122             :                    SDValue &TFE) const;
     123             :   bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
     124             :                          SDValue &SOffset, SDValue &Offset, SDValue &GLC,
     125             :                          SDValue &SLC, SDValue &TFE) const;
     126             :   bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
     127             :                          SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
     128             :                          SDValue &SLC) const;
     129             :   bool SelectMUBUFScratchOffen(SDNode *Root,
     130             :                                SDValue Addr, SDValue &RSrc, SDValue &VAddr,
     131             :                                SDValue &SOffset, SDValue &ImmOffset) const;
     132             :   bool SelectMUBUFScratchOffset(SDNode *Root,
     133             :                                 SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
     134             :                                 SDValue &Offset) const;
     135             : 
     136             :   bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
     137             :                          SDValue &Offset, SDValue &GLC, SDValue &SLC,
     138             :                          SDValue &TFE) const;
     139             :   bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
     140             :                          SDValue &Offset, SDValue &SLC) const;
     141             :   bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
     142             :                          SDValue &Offset) const;
     143             :   bool SelectMUBUFConstant(SDValue Constant,
     144             :                            SDValue &SOffset,
     145             :                            SDValue &ImmOffset) const;
     146             :   bool SelectMUBUFIntrinsicOffset(SDValue Offset, SDValue &SOffset,
     147             :                                   SDValue &ImmOffset) const;
     148             :   bool SelectMUBUFIntrinsicVOffset(SDValue Offset, SDValue &SOffset,
     149             :                                    SDValue &ImmOffset, SDValue &VOffset) const;
     150             : 
     151             :   bool SelectFlatAtomic(SDValue Addr, SDValue &VAddr,
     152             :                         SDValue &Offset, SDValue &SLC) const;
     153             :   bool SelectFlatAtomicSigned(SDValue Addr, SDValue &VAddr,
     154             :                               SDValue &Offset, SDValue &SLC) const;
     155             : 
     156             :   template <bool IsSigned>
     157             :   bool SelectFlatOffset(SDValue Addr, SDValue &VAddr,
     158             :                         SDValue &Offset, SDValue &SLC) const;
     159             : 
     160             :   bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset,
     161             :                         bool &Imm) const;
     162             :   bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
     163             :                   bool &Imm) const;
     164             :   bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
     165             :   bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
     166             :   bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
     167             :   bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const;
     168             :   bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const;
     169             :   bool SelectSMRDBufferSgpr(SDValue Addr, SDValue &Offset) const;
     170             :   bool SelectMOVRELOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;
     171             : 
     172             :   bool SelectVOP3Mods_NNaN(SDValue In, SDValue &Src, SDValue &SrcMods) const;
     173             :   bool SelectVOP3ModsImpl(SDValue In, SDValue &Src, unsigned &SrcMods) const;
     174             :   bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
     175             :   bool SelectVOP3NoMods(SDValue In, SDValue &Src) const;
     176             :   bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
     177             :                        SDValue &Clamp, SDValue &Omod) const;
     178             :   bool SelectVOP3NoMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
     179             :                          SDValue &Clamp, SDValue &Omod) const;
     180             : 
     181             :   bool SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src, SDValue &SrcMods,
     182             :                                  SDValue &Clamp,
     183             :                                  SDValue &Omod) const;
     184             : 
     185             :   bool SelectVOP3OMods(SDValue In, SDValue &Src,
     186             :                        SDValue &Clamp, SDValue &Omod) const;
     187             : 
     188             :   bool SelectVOP3PMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
     189             :   bool SelectVOP3PMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
     190             :                         SDValue &Clamp) const;
     191             : 
     192             :   bool SelectVOP3OpSel(SDValue In, SDValue &Src, SDValue &SrcMods) const;
     193             :   bool SelectVOP3OpSel0(SDValue In, SDValue &Src, SDValue &SrcMods,
     194             :                         SDValue &Clamp) const;
     195             : 
     196             :   bool SelectVOP3OpSelMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
     197             :   bool SelectVOP3OpSelMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
     198             :                             SDValue &Clamp) const;
     199             :   bool SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src, unsigned &Mods) const;
     200             : 
     201             :   void SelectADD_SUB_I64(SDNode *N);
     202             :   void SelectUADDO_USUBO(SDNode *N);
     203             :   void SelectDIV_SCALE(SDNode *N);
     204             :   void SelectFMA_W_CHAIN(SDNode *N);
     205             :   void SelectFMUL_W_CHAIN(SDNode *N);
     206             : 
     207             :   SDNode *getS_BFE(unsigned Opcode, const SDLoc &DL, SDValue Val,
     208             :                    uint32_t Offset, uint32_t Width);
     209             :   void SelectS_BFEFromShifts(SDNode *N);
     210             :   void SelectS_BFE(SDNode *N);
     211             :   bool isCBranchSCC(const SDNode *N) const;
     212             :   void SelectBRCOND(SDNode *N);
     213             :   void SelectFMAD(SDNode *N);
     214             :   void SelectATOMIC_CMP_SWAP(SDNode *N);
     215             : 
     216             : protected:
     217             :   // Include the pieces autogenerated from the target description.
     218             : #include "AMDGPUGenDAGISel.inc"
     219             : };
     220             : 
     221         486 : class R600DAGToDAGISel : public AMDGPUDAGToDAGISel {
     222             : public:
     223             :   explicit R600DAGToDAGISel(TargetMachine *TM, CodeGenOpt::Level OptLevel) :
     224         488 :       AMDGPUDAGToDAGISel(TM, OptLevel) {}
     225             : 
     226             :   void Select(SDNode *N) override;
     227             : 
     228             :   bool SelectADDRIndirect(SDValue Addr, SDValue &Base,
     229             :                           SDValue &Offset) override;
     230             :   bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
     231             :                           SDValue &Offset) override;
     232             : };
     233             : 
     234             : }  // end anonymous namespace
     235             : 
     236       53042 : INITIALIZE_PASS_BEGIN(AMDGPUDAGToDAGISel, "isel",
     237             :                       "AMDGPU DAG->DAG Pattern Instruction Selection", false, false)
     238       53042 : INITIALIZE_PASS_DEPENDENCY(AMDGPUArgumentUsageInfo)
     239      312538 : INITIALIZE_PASS_END(AMDGPUDAGToDAGISel, "isel",
     240             :                     "AMDGPU DAG->DAG Pattern Instruction Selection", false, false)
     241             : 
     242             : /// \brief This pass converts a legalized DAG into a AMDGPU-specific
     243             : // DAG, ready for instruction scheduling.
     244        1463 : FunctionPass *llvm::createAMDGPUISelDag(TargetMachine *TM,
     245             :                                         CodeGenOpt::Level OptLevel) {
     246        2926 :   return new AMDGPUDAGToDAGISel(TM, OptLevel);
     247             : }
     248             : 
     249             : /// \brief This pass converts a legalized DAG into a R600-specific
     250             : // DAG, ready for instruction scheduling.
     251         244 : FunctionPass *llvm::createR600ISelDag(TargetMachine *TM,
     252             :                                       CodeGenOpt::Level OptLevel) {
     253         488 :   return new R600DAGToDAGISel(TM, OptLevel);
     254             : }
     255             : 
     256       16878 : bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
     257       16878 :   Subtarget = &MF.getSubtarget<AMDGPUSubtarget>();
     258       16878 :   return SelectionDAGISel::runOnMachineFunction(MF);
     259             : }
     260             : 
     261         492 : bool AMDGPUDAGToDAGISel::isNoNanSrc(SDValue N) const {
     262         492 :   if (TM.Options.NoNaNsFPMath)
     263             :     return true;
     264             : 
     265             :   // TODO: Move into isKnownNeverNaN
     266         228 :   if (N->getFlags().isDefined())
     267         204 :     return N->getFlags().hasNoNaNs();
     268             : 
     269          12 :   return CurDAG->isKnownNeverNaN(N);
     270             : }
     271             : 
     272        5063 : bool AMDGPUDAGToDAGISel::isInlineImmediate(const SDNode *N) const {
     273             :   const SIInstrInfo *TII
     274       10126 :     = static_cast<const SISubtarget *>(Subtarget)->getInstrInfo();
     275             : 
     276        4596 :   if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N))
     277        4596 :     return TII->isInlineConstant(C->getAPIntValue());
     278             : 
     279         441 :   if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N))
     280         882 :     return TII->isInlineConstant(C->getValueAPF().bitcastToAPInt());
     281             : 
     282             :   return false;
     283             : }
     284             : 
     285             : /// \brief Determine the register class for \p OpNo
     286             : /// \returns The register class of the virtual register that will be used for
     287             : /// the given operand number \OpNo or NULL if the register class cannot be
     288             : /// determined.
     289       20509 : const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
     290             :                                                           unsigned OpNo) const {
     291       20509 :   if (!N->isMachineOpcode()) {
     292        1246 :     if (N->getOpcode() == ISD::CopyToReg) {
     293        1869 :       unsigned Reg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
     294         623 :       if (TargetRegisterInfo::isVirtualRegister(Reg)) {
     295         309 :         MachineRegisterInfo &MRI = CurDAG->getMachineFunction().getRegInfo();
     296         309 :         return MRI.getRegClass(Reg);
     297             :       }
     298             : 
     299             :       const SIRegisterInfo *TRI
     300         628 :         = static_cast<const SISubtarget *>(Subtarget)->getRegisterInfo();
     301         314 :       return TRI->getPhysRegClass(Reg);
     302             :     }
     303             : 
     304             :     return nullptr;
     305             :   }
     306             : 
     307       39772 :   switch (N->getMachineOpcode()) {
     308       18361 :   default: {
     309             :     const MCInstrDesc &Desc =
     310       55083 :         Subtarget->getInstrInfo()->get(N->getMachineOpcode());
     311       18361 :     unsigned OpIdx = Desc.getNumDefs() + OpNo;
     312       18361 :     if (OpIdx >= Desc.getNumOperands())
     313             :       return nullptr;
     314       18361 :     int RegClass = Desc.OpInfo[OpIdx].RegClass;
     315       18361 :     if (RegClass == -1)
     316             :       return nullptr;
     317             : 
     318       36694 :     return Subtarget->getRegisterInfo()->getRegClass(RegClass);
     319             :   }
     320        1525 :   case AMDGPU::REG_SEQUENCE: {
     321        6100 :     unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
     322             :     const TargetRegisterClass *SuperRC =
     323        3050 :         Subtarget->getRegisterInfo()->getRegClass(RCID);
     324             : 
     325        3050 :     SDValue SubRegOp = N->getOperand(OpNo + 1);
     326        3050 :     unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
     327        1525 :     return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
     328        1525 :                                                               SubRegIdx);
     329             :   }
     330             :   }
     331             : }
     332             : 
     333       73240 : SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N) const {
     334      146480 :   if (cast<MemSDNode>(N)->getAddressSpace() != AMDGPUASI.LOCAL_ADDRESS)
     335             :     return N;
     336             : 
     337             :   const SITargetLowering& Lowering =
     338        7052 :       *static_cast<const SITargetLowering*>(getTargetLowering());
     339             : 
     340             :   // Write max value to m0 before each load operation
     341             : 
     342       14104 :   SDValue M0 = Lowering.copyToM0(*CurDAG, CurDAG->getEntryNode(), SDLoc(N),
     343       42312 :                                  CurDAG->getTargetConstant(-1, SDLoc(N), MVT::i32));
     344             : 
     345       14104 :   SDValue Glue = M0.getValue(1);
     346             : 
     347        7052 :   SmallVector <SDValue, 8> Ops;
     348       39107 :   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
     349       50006 :      Ops.push_back(N->getOperand(i));
     350             :   }
     351        7052 :   Ops.push_back(Glue);
     352       28208 :   CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), Ops);
     353             : 
     354        7052 :   return N;
     355             : }
     356             : 
     357             : static unsigned selectSGPRVectorRegClassID(unsigned NumVectorElts) {
     358       15484 :   switch (NumVectorElts) {
     359             :   case 1:
     360             :     return AMDGPU::SReg_32_XM0RegClassID;
     361        8642 :   case 2:
     362             :     return AMDGPU::SReg_64RegClassID;
     363        6464 :   case 4:
     364             :     return AMDGPU::SReg_128RegClassID;
     365         346 :   case 8:
     366             :     return AMDGPU::SReg_256RegClassID;
     367          32 :   case 16:
     368             :     return AMDGPU::SReg_512RegClassID;
     369             :   }
     370             : 
     371           0 :   llvm_unreachable("invalid vector size");
     372             : }
     373             : 
     374         387 : static bool getConstantValue(SDValue N, uint32_t &Out) {
     375         117 :   if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
     376         234 :     Out = C->getAPIntValue().getZExtValue();
     377             :     return true;
     378             :   }
     379             : 
     380         188 :   if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N)) {
     381         564 :     Out = C->getValueAPF().bitcastToAPInt().getZExtValue();
     382             :     return true;
     383             :   }
     384             : 
     385             :   return false;
     386             : }
     387             : 
     388       17870 : void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) {
     389       35740 :   EVT VT = N->getValueType(0);
     390       17870 :   unsigned NumVectorElts = VT.getVectorNumElements();
     391       17870 :   EVT EltVT = VT.getVectorElementType();
     392       17870 :   const AMDGPURegisterInfo *TRI = Subtarget->getRegisterInfo();
     393       35740 :   SDLoc DL(N);
     394       53610 :   SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
     395             : 
     396       17870 :   if (NumVectorElts == 1) {
     397           0 :     CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT, N->getOperand(0),
     398             :                          RegClass);
     399           0 :     return;
     400             :   }
     401             : 
     402             :   assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
     403             :                                   "supported yet");
     404             :   // 16 = Max Num Vector Elements
     405             :   // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
     406             :   // 1 = Vector Register Class
     407       53610 :   SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
     408             : 
     409       71480 :   RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
     410       17870 :   bool IsRegSeq = true;
     411       35740 :   unsigned NOps = N->getNumOperands();
     412       73088 :   for (unsigned i = 0; i < NOps; i++) {
     413             :     // XXX: Why is this here?
     414      165654 :     if (isa<RegisterSDNode>(N->getOperand(i))) {
     415             :       IsRegSeq = false;
     416             :       break;
     417             :     }
     418      165654 :     RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
     419      110436 :     RegSeqArgs[1 + (2 * i) + 1] =
     420      165654 :             CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL,
     421      110436 :                                       MVT::i32);
     422             :   }
     423       17870 :   if (NOps != NumVectorElts) {
     424             :     // Fill in the missing undef elements if this was a scalar_to_vector.
     425             :     assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
     426           4 :     MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
     427           4 :                                                    DL, EltVT);
     428           8 :     for (unsigned i = NOps; i < NumVectorElts; ++i) {
     429           8 :       RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
     430           8 :       RegSeqArgs[1 + (2 * i) + 1] =
     431          12 :         CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32);
     432             :     }
     433             :   }
     434             : 
     435       17870 :   if (!IsRegSeq)
     436             :     SelectCode(N);
     437       53610 :   CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(), RegSeqArgs);
     438             : }
     439             : 
     440      420720 : void AMDGPUDAGToDAGISel::Select(SDNode *N) {
     441      841440 :   unsigned int Opc = N->getOpcode();
     442      420720 :   if (N->isMachineOpcode()) {
     443         528 :     N->setNodeId(-1);
     444             :     return;   // Already selected.
     445             :   }
     446             : 
     447     1259130 :   if (isa<AtomicSDNode>(N) ||
     448      418746 :       (Opc == AMDGPUISD::ATOMIC_INC || Opc == AMDGPUISD::ATOMIC_DEC))
     449        1596 :     N = glueCopyToM0(N);
     450             : 
     451      420192 :   switch (Opc) {
     452             :   default: break;
     453             :   // We are selecting i64 ADD here instead of custom lower it during
     454             :   // DAG legalization, so we can fold some i64 ADDs used for address
     455             :   // calculation into the LOAD and STORE instructions.
     456       11058 :   case ISD::ADD:
     457             :   case ISD::ADDC:
     458             :   case ISD::ADDE:
     459             :   case ISD::SUB:
     460             :   case ISD::SUBC:
     461             :   case ISD::SUBE: {
     462       22116 :     if (N->getValueType(0) != MVT::i64)
     463             :       break;
     464             : 
     465        7007 :     SelectADD_SUB_I64(N);
     466        7007 :     return;
     467             :   }
     468          12 :   case ISD::UADDO:
     469             :   case ISD::USUBO: {
     470          12 :     SelectUADDO_USUBO(N);
     471          12 :     return;
     472             :   }
     473          45 :   case AMDGPUISD::FMUL_W_CHAIN: {
     474          45 :     SelectFMUL_W_CHAIN(N);
     475          45 :     return;
     476             :   }
     477         225 :   case AMDGPUISD::FMA_W_CHAIN: {
     478         225 :     SelectFMA_W_CHAIN(N);
     479         225 :     return;
     480             :   }
     481             : 
     482       15708 :   case ISD::SCALAR_TO_VECTOR:
     483             :   case ISD::BUILD_VECTOR: {
     484       31416 :     EVT VT = N->getValueType(0);
     485       15708 :     unsigned NumVectorElts = VT.getVectorNumElements();
     486             : 
     487       31313 :     if (VT == MVT::v2i16 || VT == MVT::v2f16) {
     488         224 :       if (Opc == ISD::BUILD_VECTOR) {
     489             :         uint32_t LHSVal, RHSVal;
     490         611 :         if (getConstantValue(N->getOperand(0), LHSVal) &&
     491         326 :             getConstantValue(N->getOperand(1), RHSVal)) {
     492         142 :           uint32_t K = LHSVal | (RHSVal << 16);
     493         426 :           CurDAG->SelectNodeTo(N, AMDGPU::S_MOV_B32, VT,
     494         568 :                                CurDAG->getTargetConstant(K, SDLoc(N), MVT::i32));
     495         142 :           return;
     496             :         }
     497             :       }
     498             : 
     499          82 :       break;
     500             :     }
     501             : 
     502             :     assert(VT.getVectorElementType().bitsEq(MVT::i32));
     503       15484 :     unsigned RegClassID = selectSGPRVectorRegClassID(NumVectorElts);
     504       15484 :     SelectBuildVector(N, RegClassID);
     505       15484 :     return;
     506             :   }
     507        1621 :   case ISD::BUILD_PAIR: {
     508        1621 :     SDValue RC, SubReg0, SubReg1;
     509        4863 :     SDLoc DL(N);
     510        4863 :     if (N->getValueType(0) == MVT::i128) {
     511           0 :       RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32);
     512           0 :       SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32);
     513           0 :       SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32);
     514        4863 :     } else if (N->getValueType(0) == MVT::i64) {
     515        4863 :       RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32);
     516        4863 :       SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
     517        4863 :       SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
     518             :     } else {
     519           0 :       llvm_unreachable("Unhandled value type for BUILD_PAIR");
     520             :     }
     521        3242 :     const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
     522        4863 :                             N->getOperand(1), SubReg1 };
     523        6484 :     ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
     524        1621 :                                           N->getValueType(0), Ops));
     525             :     return;
     526             :   }
     527             : 
     528       21572 :   case ISD::Constant:
     529             :   case ISD::ConstantFP: {
     530       63561 :     if (N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
     531             :       break;
     532             : 
     533             :     uint64_t Imm;
     534        1228 :     if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
     535         219 :       Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
     536             :     else {
     537        2164 :       ConstantSDNode *C = cast<ConstantSDNode>(N);
     538             :       Imm = C->getZExtValue();
     539             :     }
     540             : 
     541        3465 :     SDLoc DL(N);
     542        3465 :     SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
     543        1155 :                                 CurDAG->getConstant(Imm & 0xFFFFFFFF, DL,
     544        2310 :                                                     MVT::i32));
     545        3465 :     SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
     546        3465 :                                 CurDAG->getConstant(Imm >> 32, DL, MVT::i32));
     547             :     const SDValue Ops[] = {
     548        2310 :       CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
     549        2310 :       SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
     550        2310 :       SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
     551        5775 :     };
     552             : 
     553        4620 :     ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
     554        1155 :                                           N->getValueType(0), Ops));
     555             :     return;
     556             :   }
     557       71644 :   case ISD::LOAD:
     558             :   case ISD::STORE: {
     559       71644 :     N = glueCopyToM0(N);
     560       71644 :     break;
     561             :   }
     562             : 
     563         148 :   case AMDGPUISD::BFE_I32:
     564             :   case AMDGPUISD::BFE_U32: {
     565             :     // There is a scalar version available, but unlike the vector version which
     566             :     // has a separate operand for the offset and width, the scalar version packs
     567             :     // the width and offset into a single operand. Try to move to the scalar
     568             :     // version if the offsets are constant, so that we can try to keep extended
     569             :     // loads of kernel arguments in SGPRs.
     570             : 
     571             :     // TODO: Technically we could try to pattern match scalar bitshifts of
     572             :     // dynamic values, but it's probably not useful.
     573         432 :     ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
     574             :     if (!Offset)
     575             :       break;
     576             : 
     577         404 :     ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
     578             :     if (!Width)
     579             :       break;
     580             : 
     581         132 :     bool Signed = Opc == AMDGPUISD::BFE_I32;
     582             : 
     583         132 :     uint32_t OffsetVal = Offset->getZExtValue();
     584         132 :     uint32_t WidthVal = Width->getZExtValue();
     585             : 
     586         396 :     ReplaceNode(N, getS_BFE(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32,
     587         528 :                             SDLoc(N), N->getOperand(0), OffsetVal, WidthVal));
     588         132 :     return;
     589             :   }
     590         249 :   case AMDGPUISD::DIV_SCALE: {
     591         249 :     SelectDIV_SCALE(N);
     592         249 :     return;
     593             :   }
     594        9330 :   case ISD::CopyToReg: {
     595             :     const SITargetLowering& Lowering =
     596        9330 :       *static_cast<const SITargetLowering*>(getTargetLowering());
     597        9330 :     N = Lowering.legalizeTargetIndependentNode(N, *CurDAG);
     598        9330 :     break;
     599             :   }
     600       21308 :   case ISD::AND:
     601             :   case ISD::SRL:
     602             :   case ISD::SRA:
     603             :   case ISD::SIGN_EXTEND_INREG:
     604       42616 :     if (N->getValueType(0) != MVT::i32)
     605             :       break;
     606             : 
     607       16389 :     SelectS_BFE(N);
     608       16389 :     return;
     609         531 :   case ISD::BRCOND:
     610         531 :     SelectBRCOND(N);
     611         531 :     return;
     612        1263 :   case ISD::FMAD:
     613        1263 :     SelectFMAD(N);
     614        1263 :     return;
     615         195 :   case AMDGPUISD::ATOMIC_CMP_SWAP:
     616         195 :     SelectATOMIC_CMP_SWAP(N);
     617         195 :     return;
     618             :   }
     619             : 
     620      375742 :   SelectCode(N);
     621             : }
     622             : 
     623        6342 : bool AMDGPUDAGToDAGISel::isConstantLoad(const MemSDNode *N, int CbId) const {
     624       12684 :   if (!N->readMem())
     625             :     return false;
     626        6342 :   if (CbId == -1)
     627           0 :     return N->getAddressSpace() == AMDGPUASI.CONSTANT_ADDRESS;
     628             : 
     629        6342 :   return N->getAddressSpace() == AMDGPUASI.CONSTANT_BUFFER_0 + CbId;
     630             : }
     631             : 
     632         355 : bool AMDGPUDAGToDAGISel::isUniformBr(const SDNode *N) const {
     633         355 :   const BasicBlock *BB = FuncInfo->MBB->getBasicBlock();
     634         355 :   const Instruction *Term = BB->getTerminator();
     635         710 :   return Term->getMetadata("amdgpu.uniform") ||
     636         355 :          Term->getMetadata("structurizecfg.uniform");
     637             : }
     638             : 
     639           0 : StringRef AMDGPUDAGToDAGISel::getPassName() const {
     640           0 :   return "AMDGPU DAG->DAG Pattern Instruction Selection";
     641             : }
     642             : 
     643             : //===----------------------------------------------------------------------===//
     644             : // Complex Patterns
     645             : //===----------------------------------------------------------------------===//
     646             : 
     647        6079 : bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
     648             :                                                          SDValue& IntPtr) {
     649        6079 :   if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
     650       24316 :     IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, SDLoc(Addr),
     651        6079 :                                        true);
     652             :     return true;
     653             :   }
     654             :   return false;
     655             : }
     656             : 
     657           0 : bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
     658             :     SDValue& BaseReg, SDValue &Offset) {
     659           0 :   if (!isa<ConstantSDNode>(Addr)) {
     660           0 :     BaseReg = Addr;
     661           0 :     Offset = CurDAG->getIntPtrConstant(0, SDLoc(Addr), true);
     662             :     return true;
     663             :   }
     664             :   return false;
     665             : }
     666             : 
     667           0 : bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
     668             :                                             SDValue &Offset) {
     669           0 :   return false;
     670             : }
     671             : 
     672           0 : bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
     673             :                                             SDValue &Offset) {
     674             :   ConstantSDNode *C;
     675           0 :   SDLoc DL(Addr);
     676             : 
     677           0 :   if ((C = dyn_cast<ConstantSDNode>(Addr))) {
     678           0 :     Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
     679           0 :     Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
     680           0 :   } else if ((Addr.getOpcode() == AMDGPUISD::DWORDADDR) &&
     681           0 :              (C = dyn_cast<ConstantSDNode>(Addr.getOperand(0)))) {
     682           0 :     Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
     683           0 :     Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
     684           0 :   } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
     685           0 :             (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
     686           0 :     Base = Addr.getOperand(0);
     687           0 :     Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
     688             :   } else {
     689           0 :     Base = Addr;
     690           0 :     Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
     691             :   }
     692             : 
     693           0 :   return true;
     694             : }
     695             : 
     696        7007 : void AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
     697       14014 :   SDLoc DL(N);
     698       14014 :   SDValue LHS = N->getOperand(0);
     699       14014 :   SDValue RHS = N->getOperand(1);
     700             : 
     701       14014 :   unsigned Opcode = N->getOpcode();
     702        7007 :   bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE);
     703        7007 :   bool ProduceCarry =
     704        7007 :       ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC;
     705        7007 :   bool IsAdd =
     706        7007 :       (Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE);
     707             : 
     708       21021 :   SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
     709       21021 :   SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
     710             : 
     711       14014 :   SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
     712        7007 :                                        DL, MVT::i32, LHS, Sub0);
     713       14014 :   SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
     714        7007 :                                        DL, MVT::i32, LHS, Sub1);
     715             : 
     716       14014 :   SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
     717        7007 :                                        DL, MVT::i32, RHS, Sub0);
     718       14014 :   SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
     719        7007 :                                        DL, MVT::i32, RHS, Sub1);
     720             : 
     721       21021 :   SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
     722             : 
     723        7007 :   unsigned Opc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
     724        7007 :   unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
     725             : 
     726             :   SDNode *AddLo;
     727        7007 :   if (!ConsumeCarry) {
     728       21009 :     SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
     729       14006 :     AddLo = CurDAG->getMachineNode(Opc, DL, VTList, Args);
     730             :   } else {
     731          16 :     SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0), N->getOperand(2) };
     732           8 :     AddLo = CurDAG->getMachineNode(CarryOpc, DL, VTList, Args);
     733             :   }
     734             :   SDValue AddHiArgs[] = {
     735             :     SDValue(Hi0, 0),
     736             :     SDValue(Hi1, 0),
     737             :     SDValue(AddLo, 1)
     738       28028 :   };
     739       14014 :   SDNode *AddHi = CurDAG->getMachineNode(CarryOpc, DL, VTList, AddHiArgs);
     740             : 
     741             :   SDValue RegSequenceArgs[] = {
     742       14014 :     CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
     743             :     SDValue(AddLo,0),
     744             :     Sub0,
     745             :     SDValue(AddHi,0),
     746             :     Sub1,
     747       21021 :   };
     748       14014 :   SDNode *RegSequence = CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
     749       14014 :                                                MVT::i64, RegSequenceArgs);
     750             : 
     751        7007 :   if (ProduceCarry) {
     752             :     // Replace the carry-use
     753          24 :     CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(AddHi, 1));
     754             :   }
     755             : 
     756             :   // Replace the remaining uses.
     757        7007 :   CurDAG->ReplaceAllUsesWith(N, RegSequence);
     758        7007 :   CurDAG->RemoveDeadNode(N);
     759        7007 : }
     760             : 
     761          12 : void AMDGPUDAGToDAGISel::SelectUADDO_USUBO(SDNode *N) {
     762             :   // The name of the opcodes are misleading. v_add_i32/v_sub_i32 have unsigned
     763             :   // carry out despite the _i32 name. These were renamed in VI to _U32.
     764             :   // FIXME: We should probably rename the opcodes here.
     765          12 :   unsigned Opc = N->getOpcode() == ISD::UADDO ?
     766          12 :     AMDGPU::V_ADD_I32_e64 : AMDGPU::V_SUB_I32_e64;
     767             : 
     768          60 :   CurDAG->SelectNodeTo(N, Opc, N->getVTList(),
     769          48 :                        { N->getOperand(0), N->getOperand(1) });
     770          12 : }
     771             : 
     772         225 : void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) {
     773         450 :   SDLoc SL(N);
     774             :   //  src0_modifiers, src0,  src1_modifiers, src1, src2_modifiers, src2, clamp, omod
     775         225 :   SDValue Ops[10];
     776             : 
     777         450 :   SelectVOP3Mods0(N->getOperand(1), Ops[1], Ops[0], Ops[6], Ops[7]);
     778         450 :   SelectVOP3Mods(N->getOperand(2), Ops[3], Ops[2]);
     779         450 :   SelectVOP3Mods(N->getOperand(3), Ops[5], Ops[4]);
     780         450 :   Ops[8] = N->getOperand(0);
     781         450 :   Ops[9] = N->getOperand(4);
     782             : 
     783         675 :   CurDAG->SelectNodeTo(N, AMDGPU::V_FMA_F32, N->getVTList(), Ops);
     784         225 : }
     785             : 
     786          45 : void AMDGPUDAGToDAGISel::SelectFMUL_W_CHAIN(SDNode *N) {
     787          90 :   SDLoc SL(N);
     788             :   //    src0_modifiers, src0,  src1_modifiers, src1, clamp, omod
     789          45 :   SDValue Ops[8];
     790             : 
     791          90 :   SelectVOP3Mods0(N->getOperand(1), Ops[1], Ops[0], Ops[4], Ops[5]);
     792          90 :   SelectVOP3Mods(N->getOperand(2), Ops[3], Ops[2]);
     793          90 :   Ops[6] = N->getOperand(0);
     794          90 :   Ops[7] = N->getOperand(3);
     795             : 
     796         135 :   CurDAG->SelectNodeTo(N, AMDGPU::V_MUL_F32_e64, N->getVTList(), Ops);
     797          45 : }
     798             : 
     799             : // We need to handle this here because tablegen doesn't support matching
     800             : // instructions with multiple outputs.
     801         249 : void AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
     802         498 :   SDLoc SL(N);
     803         498 :   EVT VT = N->getValueType(0);
     804             : 
     805             :   assert(VT == MVT::f32 || VT == MVT::f64);
     806             : 
     807             :   unsigned Opc
     808         498 :     = (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
     809             : 
     810         996 :   SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) };
     811         747 :   CurDAG->SelectNodeTo(N, Opc, N->getVTList(), Ops);
     812         249 : }
     813             : 
     814        4925 : bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
     815             :                                          unsigned OffsetBits) const {
     816        4925 :   if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
     817         256 :       (OffsetBits == 8 && !isUInt<8>(Offset)))
     818             :     return false;
     819             : 
     820        6271 :   if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS ||
     821        1748 :       Subtarget->unsafeDSOffsetFoldingEnabled())
     822             :     return true;
     823             : 
     824             :   // On Southern Islands instruction with a negative base value and an offset
     825             :   // don't seem to work.
     826        1744 :   return CurDAG->SignBitIsZero(Base);
     827             : }
     828             : 
     829        6706 : bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
     830             :                                               SDValue &Offset) const {
     831       13412 :   SDLoc DL(Addr);
     832        6706 :   if (CurDAG->isBaseWithConstantOffset(Addr)) {
     833        9318 :     SDValue N0 = Addr.getOperand(0);
     834        9318 :     SDValue N1 = Addr.getOperand(1);
     835        4659 :     ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
     836        4659 :     if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) {
     837             :       // (add n0, c0)
     838        4217 :       Base = N0;
     839       16868 :       Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
     840        4217 :       return true;
     841             :     }
     842        4094 :   } else if (Addr.getOpcode() == ISD::SUB) {
     843             :     // sub C, x -> add (sub 0, x), C
     844          33 :     if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
     845          11 :       int64_t ByteOffset = C->getSExtValue();
     846          11 :       if (isUInt<16>(ByteOffset)) {
     847          30 :         SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
     848             : 
     849             :         // XXX - This is kind of hacky. Create a dummy sub node so we can check
     850             :         // the known bits in isDSOffsetLegal. We need to emit the selected node
     851             :         // here, so this is thrown away.
     852          10 :         SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
     853          30 :                                       Zero, Addr.getOperand(1));
     854             : 
     855          10 :         if (isDSOffsetLegal(Sub, ByteOffset, 16)) {
     856             :           MachineSDNode *MachineSub
     857          16 :             = CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32,
     858          24 :                                      Zero, Addr.getOperand(1));
     859             : 
     860           8 :           Base = SDValue(MachineSub, 0);
     861          24 :           Offset = CurDAG->getTargetConstant(ByteOffset, DL, MVT::i16);
     862           8 :           return true;
     863             :         }
     864             :       }
     865             :     }
     866         718 :   } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
     867             :     // If we have a constant address, prefer to put the constant into the
     868             :     // offset. This can save moves to load the constant address since multiple
     869             :     // operations can share the zero base address register, and enables merging
     870             :     // into read2 / write2 instructions.
     871             : 
     872         722 :     SDLoc DL(Addr);
     873             : 
     874         718 :     if (isUInt<16>(CAddr->getZExtValue())) {
     875        2142 :       SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
     876        1428 :       MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
     877         714 :                                  DL, MVT::i32, Zero);
     878         714 :       Base = SDValue(MovZero, 0);
     879        2856 :       Offset = CurDAG->getTargetConstant(CAddr->getZExtValue(), DL, MVT::i16);
     880             :       return true;
     881             :     }
     882             :   }
     883             : 
     884             :   // default case
     885        1767 :   Base = Addr;
     886        8835 :   Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i16);
     887        1767 :   return true;
     888             : }
     889             : 
     890             : // TODO: If offset is too big, put low 16-bit into offset.
     891         351 : bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
     892             :                                                    SDValue &Offset0,
     893             :                                                    SDValue &Offset1) const {
     894         702 :   SDLoc DL(Addr);
     895             : 
     896         351 :   if (CurDAG->isBaseWithConstantOffset(Addr)) {
     897         508 :     SDValue N0 = Addr.getOperand(0);
     898         508 :     SDValue N1 = Addr.getOperand(1);
     899         254 :     ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
     900         254 :     unsigned DWordOffset0 = C1->getZExtValue() / 4;
     901         254 :     unsigned DWordOffset1 = DWordOffset0 + 1;
     902             :     // (add n0, c0)
     903         254 :     if (isDSOffsetLegal(N0, DWordOffset1, 8)) {
     904         245 :       Base = N0;
     905         735 :       Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
     906         735 :       Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
     907         245 :       return true;
     908             :     }
     909         194 :   } else if (Addr.getOpcode() == ISD::SUB) {
     910             :     // sub C, x -> add (sub 0, x), C
     911           6 :     if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
     912           2 :       unsigned DWordOffset0 = C->getZExtValue() / 4;
     913           2 :       unsigned DWordOffset1 = DWordOffset0 + 1;
     914             : 
     915           2 :       if (isUInt<8>(DWordOffset0)) {
     916           3 :         SDLoc DL(Addr);
     917           6 :         SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
     918             : 
     919             :         // XXX - This is kind of hacky. Create a dummy sub node so we can check
     920             :         // the known bits in isDSOffsetLegal. We need to emit the selected node
     921             :         // here, so this is thrown away.
     922           2 :         SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
     923           6 :                                       Zero, Addr.getOperand(1));
     924             : 
     925           2 :         if (isDSOffsetLegal(Sub, DWordOffset1, 8)) {
     926             :           MachineSDNode *MachineSub
     927           2 :             = CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32,
     928           3 :                                      Zero, Addr.getOperand(1));
     929             : 
     930           1 :           Base = SDValue(MachineSub, 0);
     931           3 :           Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
     932           3 :           Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
     933           2 :           return true;
     934             :         }
     935             :       }
     936             :     }
     937          14 :   } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
     938          14 :     unsigned DWordOffset0 = CAddr->getZExtValue() / 4;
     939          14 :     unsigned DWordOffset1 = DWordOffset0 + 1;
     940             :     assert(4 * DWordOffset0 == CAddr->getZExtValue());
     941             : 
     942          14 :     if (isUInt<8>(DWordOffset0) && isUInt<8>(DWordOffset1)) {
     943          30 :       SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
     944             :       MachineSDNode *MovZero
     945          20 :         = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
     946          10 :                                  DL, MVT::i32, Zero);
     947          10 :       Base = SDValue(MovZero, 0);
     948          30 :       Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
     949          30 :       Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
     950             :       return true;
     951             :     }
     952             :   }
     953             : 
     954             :   // default case
     955             : 
     956             :   // FIXME: This is broken on SI where we still need to check if the base
     957             :   // pointer is positive here.
     958          95 :   Base = Addr;
     959         285 :   Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i8);
     960         285 :   Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8);
     961          95 :   return true;
     962             : }
     963             : 
     964             : static bool isLegalMUBUFImmOffset(unsigned Imm) {
     965       16366 :   return isUInt<12>(Imm);
     966             : }
     967             : 
     968             : static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) {
     969       44212 :   return isLegalMUBUFImmOffset(Imm->getZExtValue());
     970             : }
     971             : 
     972       42776 : bool AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
     973             :                                      SDValue &VAddr, SDValue &SOffset,
     974             :                                      SDValue &Offset, SDValue &Offen,
     975             :                                      SDValue &Idxen, SDValue &Addr64,
     976             :                                      SDValue &GLC, SDValue &SLC,
     977             :                                      SDValue &TFE) const {
     978             :   // Subtarget prefers to use flat instruction
     979       42776 :   if (Subtarget->useFlatForGlobal())
     980             :     return false;
     981             : 
     982       33439 :   SDLoc DL(Addr);
     983             : 
     984       33439 :   if (!GLC.getNode())
     985      100317 :     GLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
     986       33439 :   if (!SLC.getNode())
     987       99696 :     SLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
     988      100317 :   TFE = CurDAG->getTargetConstant(0, DL, MVT::i1);
     989             : 
     990      100317 :   Idxen = CurDAG->getTargetConstant(0, DL, MVT::i1);
     991      100317 :   Offen = CurDAG->getTargetConstant(0, DL, MVT::i1);
     992      100317 :   Addr64 = CurDAG->getTargetConstant(0, DL, MVT::i1);
     993      100317 :   SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
     994             : 
     995       33439 :   if (CurDAG->isBaseWithConstantOffset(Addr)) {
     996       22650 :     SDValue N0 = Addr.getOperand(0);
     997       22650 :     SDValue N1 = Addr.getOperand(1);
     998       11325 :     ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
     999             : 
    1000       22650 :     if (N0.getOpcode() == ISD::ADD) {
    1001             :       // (add (add N2, N3), C1) -> addr64
    1002        3158 :       SDValue N2 = N0.getOperand(0);
    1003        3158 :       SDValue N3 = N0.getOperand(1);
    1004        4737 :       Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
    1005        1579 :       Ptr = N2;
    1006        1579 :       VAddr = N3;
    1007             :     } else {
    1008             :       // (add N0, C1) -> offset
    1009       29238 :       VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
    1010        9746 :       Ptr = N0;
    1011             :     }
    1012             : 
    1013       11325 :     if (isLegalMUBUFImmOffset(C1)) {
    1014       44120 :       Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
    1015       11315 :       return true;
    1016             :     }
    1017             : 
    1018         295 :     if (isUInt<32>(C1->getZExtValue())) {
    1019             :       // Illegal offset, store it in soffset.
    1020         855 :       Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
    1021        1140 :       SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
    1022         855 :                    CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32)),
    1023             :                         0);
    1024             :       return true;
    1025             :     }
    1026             :   }
    1027             : 
    1028       44248 :   if (Addr.getOpcode() == ISD::ADD) {
    1029             :     // (add N0, N1) -> addr64
    1030        6586 :     SDValue N0 = Addr.getOperand(0);
    1031        6586 :     SDValue N1 = Addr.getOperand(1);
    1032        9879 :     Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
    1033        3293 :     Ptr = N0;
    1034        3293 :     VAddr = N1;
    1035        9879 :     Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
    1036             :     return true;
    1037             :   }
    1038             : 
    1039             :   // default case -> offset
    1040       56493 :   VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
    1041       18831 :   Ptr = Addr;
    1042       56493 :   Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
    1043             : 
    1044             :   return true;
    1045             : }
    1046             : 
    1047       28466 : bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
    1048             :                                            SDValue &VAddr, SDValue &SOffset,
    1049             :                                            SDValue &Offset, SDValue &GLC,
    1050             :                                            SDValue &SLC, SDValue &TFE) const {
    1051       28466 :   SDValue Ptr, Offen, Idxen, Addr64;
    1052             : 
    1053             :   // addr64 bit was removed for volcanic islands.
    1054       28466 :   if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
    1055             :     return false;
    1056             : 
    1057       16611 :   if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
    1058             :               GLC, SLC, TFE))
    1059             :     return false;
    1060             : 
    1061       14503 :   ConstantSDNode *C = cast<ConstantSDNode>(Addr64);
    1062       14503 :   if (C->getSExtValue()) {
    1063        7932 :     SDLoc DL(Addr);
    1064             : 
    1065             :     const SITargetLowering& Lowering =
    1066        3966 :       *static_cast<const SITargetLowering*>(getTargetLowering());
    1067             : 
    1068        3966 :     SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0);
    1069        3966 :     return true;
    1070             :   }
    1071             : 
    1072             :   return false;
    1073             : }
    1074             : 
    1075         557 : bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
    1076             :                                            SDValue &VAddr, SDValue &SOffset,
    1077             :                                            SDValue &Offset,
    1078             :                                            SDValue &SLC) const {
    1079        2785 :   SLC = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i1);
    1080         557 :   SDValue GLC, TFE;
    1081             : 
    1082         557 :   return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE);
    1083             : }
    1084             : 
    1085             : static bool isStackPtrRelative(const MachinePointerInfo &PtrInfo) {
    1086         244 :   auto PSV = PtrInfo.V.dyn_cast<const PseudoSourceValue *>();
    1087          89 :   return PSV && PSV->isStack();
    1088             : }
    1089             : 
    1090        5855 : std::pair<SDValue, SDValue> AMDGPUDAGToDAGISel::foldFrameIndex(SDValue N) const {
    1091        5855 :   const MachineFunction &MF = CurDAG->getMachineFunction();
    1092        5855 :   const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
    1093             : 
    1094        4802 :   if (auto FI = dyn_cast<FrameIndexSDNode>(N)) {
    1095        4802 :     SDValue TFI = CurDAG->getTargetFrameIndex(FI->getIndex(),
    1096       14406 :                                               FI->getValueType(0));
    1097             : 
    1098             :     // If we can resolve this to a frame index access, this is relative to the
    1099             :     // frame pointer SGPR.
    1100       14406 :     return std::make_pair(TFI, CurDAG->getRegister(Info->getFrameOffsetReg(),
    1101       14406 :                                                    MVT::i32));
    1102             :   }
    1103             : 
    1104             :   // If we don't know this private access is a local stack object, it needs to
    1105             :   // be relative to the entry point's scratch wave offset register.
    1106        3159 :   return std::make_pair(N, CurDAG->getRegister(Info->getScratchWaveOffsetReg(),
    1107        3159 :                                                MVT::i32));
    1108             : }
    1109             : 
    1110        5861 : bool AMDGPUDAGToDAGISel::SelectMUBUFScratchOffen(SDNode *Root,
    1111             :                                                  SDValue Addr, SDValue &Rsrc,
    1112             :                                                  SDValue &VAddr, SDValue &SOffset,
    1113             :                                                  SDValue &ImmOffset) const {
    1114             : 
    1115       11722 :   SDLoc DL(Addr);
    1116        5861 :   MachineFunction &MF = CurDAG->getMachineFunction();
    1117        5861 :   const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
    1118             : 
    1119       11722 :   Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);
    1120             : 
    1121           6 :   if (ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
    1122           6 :     unsigned Imm = CAddr->getZExtValue();
    1123             :     assert(!isLegalMUBUFImmOffset(Imm) &&
    1124             :            "should have been selected by other pattern");
    1125             : 
    1126          18 :     SDValue HighBits = CurDAG->getTargetConstant(Imm & ~4095, DL, MVT::i32);
    1127          12 :     MachineSDNode *MovHighBits = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
    1128           6 :                                                         DL, MVT::i32, HighBits);
    1129           6 :     VAddr = SDValue(MovHighBits, 0);
    1130             : 
    1131             :     // In a call sequence, stores to the argument stack area are relative to the
    1132             :     // stack pointer.
    1133          12 :     const MachinePointerInfo &PtrInfo = cast<MemSDNode>(Root)->getPointerInfo();
    1134           0 :     unsigned SOffsetReg = isStackPtrRelative(PtrInfo) ?
    1135           6 :       Info->getStackPtrOffsetReg() : Info->getScratchWaveOffsetReg();
    1136             : 
    1137          12 :     SOffset = CurDAG->getRegister(SOffsetReg, MVT::i32);
    1138          18 :     ImmOffset = CurDAG->getTargetConstant(Imm & 4095, DL, MVT::i16);
    1139             :     return true;
    1140             :   }
    1141             : 
    1142        5855 :   if (CurDAG->isBaseWithConstantOffset(Addr)) {
    1143             :     // (add n0, c1)
    1144             : 
    1145        9772 :     SDValue N0 = Addr.getOperand(0);
    1146        9772 :     SDValue N1 = Addr.getOperand(1);
    1147             : 
    1148             :     // Offsets in vaddr must be positive.
    1149        4886 :     ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
    1150        4886 :     if (isLegalMUBUFImmOffset(C1)) {
    1151       14622 :       std::tie(VAddr, SOffset) = foldFrameIndex(N0);
    1152       19496 :       ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
    1153        4874 :       return true;
    1154             :     }
    1155             :   }
    1156             : 
    1157             :   // (node)
    1158        2943 :   std::tie(VAddr, SOffset) = foldFrameIndex(Addr);
    1159        2943 :   ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
    1160         981 :   return true;
    1161             : }
    1162             : 
    1163        6010 : bool AMDGPUDAGToDAGISel::SelectMUBUFScratchOffset(SDNode *Root,
    1164             :                                                   SDValue Addr,
    1165             :                                                   SDValue &SRsrc,
    1166             :                                                   SDValue &SOffset,
    1167             :                                                   SDValue &Offset) const {
    1168         155 :   ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr);
    1169         155 :   if (!CAddr || !isLegalMUBUFImmOffset(CAddr))
    1170             :     return false;
    1171             : 
    1172         149 :   SDLoc DL(Addr);
    1173         149 :   MachineFunction &MF = CurDAG->getMachineFunction();
    1174         149 :   const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
    1175             : 
    1176         298 :   SRsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);
    1177             : 
    1178         298 :   const MachinePointerInfo &PtrInfo = cast<MemSDNode>(Root)->getPointerInfo();
    1179          89 :   unsigned SOffsetReg = isStackPtrRelative(PtrInfo) ?
    1180         149 :     Info->getStackPtrOffsetReg() : Info->getScratchWaveOffsetReg();
    1181             : 
    1182             :   // FIXME: Get from MachinePointerInfo? We should only be using the frame
    1183             :   // offset if we know this is in a call sequence.
    1184         298 :   SOffset = CurDAG->getRegister(SOffsetReg, MVT::i32);
    1185             : 
    1186         596 :   Offset = CurDAG->getTargetConstant(CAddr->getZExtValue(), DL, MVT::i16);
    1187         149 :   return true;
    1188             : }
    1189             : 
    1190       26165 : bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
    1191             :                                            SDValue &SOffset, SDValue &Offset,
    1192             :                                            SDValue &GLC, SDValue &SLC,
    1193             :                                            SDValue &TFE) const {
    1194       26165 :   SDValue Ptr, VAddr, Offen, Idxen, Addr64;
    1195             :   const SIInstrInfo *TII =
    1196       26165 :     static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
    1197             : 
    1198       26165 :   if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
    1199             :               GLC, SLC, TFE))
    1200             :     return false;
    1201             : 
    1202       37872 :   if (!cast<ConstantSDNode>(Offen)->getSExtValue() &&
    1203       56808 :       !cast<ConstantSDNode>(Idxen)->getSExtValue() &&
    1204       18936 :       !cast<ConstantSDNode>(Addr64)->getSExtValue()) {
    1205       18030 :     uint64_t Rsrc = TII->getDefaultRsrcDataFormat() |
    1206       54090 :                     APInt::getAllOnesValue(32).getZExtValue(); // Size
    1207       36060 :     SDLoc DL(Addr);
    1208             : 
    1209             :     const SITargetLowering& Lowering =
    1210       18030 :       *static_cast<const SITargetLowering*>(getTargetLowering());
    1211             : 
    1212       18030 :     SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0);
    1213       18030 :     return true;
    1214             :   }
    1215             :   return false;
    1216             : }
    1217             : 
    1218           8 : bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
    1219             :                                            SDValue &Soffset, SDValue &Offset
    1220             :                                            ) const {
    1221           8 :   SDValue GLC, SLC, TFE;
    1222             : 
    1223           8 :   return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
    1224             : }
    1225             : bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
    1226             :                                            SDValue &Soffset, SDValue &Offset,
    1227             :                                            SDValue &SLC) const {
    1228         493 :   SDValue GLC, TFE;
    1229             : 
    1230         493 :   return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
    1231             : }
    1232             : 
    1233         312 : bool AMDGPUDAGToDAGISel::SelectMUBUFConstant(SDValue Constant,
    1234             :                                              SDValue &SOffset,
    1235             :                                              SDValue &ImmOffset) const {
    1236         624 :   SDLoc DL(Constant);
    1237         624 :   uint32_t Imm = cast<ConstantSDNode>(Constant)->getZExtValue();
    1238         312 :   uint32_t Overflow = 0;
    1239             : 
    1240         312 :   if (Imm >= 4096) {
    1241          16 :     if (Imm <= 4095 + 64) {
    1242             :       // Use an SOffset inline constant for 1..64
    1243           2 :       Overflow = Imm - 4095;
    1244           2 :       Imm = 4095;
    1245             :     } else {
    1246             :       // Try to keep the same value in SOffset for adjacent loads, so that
    1247             :       // the corresponding register contents can be re-used.
    1248             :       //
    1249             :       // Load values with all low-bits set into SOffset, so that a larger
    1250             :       // range of values can be covered using s_movk_i32
    1251          14 :       uint32_t High = (Imm + 1) & ~4095;
    1252          14 :       uint32_t Low = (Imm + 1) & 4095;
    1253          14 :       Imm = Low;
    1254          14 :       Overflow = High - 1;
    1255             :     }
    1256             :   }
    1257             : 
    1258             :   // There is a hardware bug in SI and CI which prevents address clamping in
    1259             :   // MUBUF instructions from working correctly with SOffsets. The immediate
    1260             :   // offset is unaffected.
    1261          32 :   if (Overflow > 0 &&
    1262          16 :       Subtarget->getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS)
    1263             :     return false;
    1264             : 
    1265         912 :   ImmOffset = CurDAG->getTargetConstant(Imm, DL, MVT::i16);
    1266             : 
    1267         304 :   if (Overflow <= 64)
    1268         891 :     SOffset = CurDAG->getTargetConstant(Overflow, DL, MVT::i32);
    1269             :   else
    1270          28 :     SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
    1271          21 :                       CurDAG->getTargetConstant(Overflow, DL, MVT::i32)),
    1272             :                       0);
    1273             : 
    1274             :   return true;
    1275             : }
    1276             : 
    1277         201 : bool AMDGPUDAGToDAGISel::SelectMUBUFIntrinsicOffset(SDValue Offset,
    1278             :                                                     SDValue &SOffset,
    1279             :                                                     SDValue &ImmOffset) const {
    1280         402 :   SDLoc DL(Offset);
    1281             : 
    1282             :   if (!isa<ConstantSDNode>(Offset))
    1283             :     return false;
    1284             : 
    1285         201 :   return SelectMUBUFConstant(Offset, SOffset, ImmOffset);
    1286             : }
    1287             : 
    1288         257 : bool AMDGPUDAGToDAGISel::SelectMUBUFIntrinsicVOffset(SDValue Offset,
    1289             :                                                      SDValue &SOffset,
    1290             :                                                      SDValue &ImmOffset,
    1291             :                                                      SDValue &VOffset) const {
    1292         514 :   SDLoc DL(Offset);
    1293             : 
    1294             :   // Don't generate an unnecessary voffset for constant offsets.
    1295             :   if (isa<ConstantSDNode>(Offset)) {
    1296         209 :     SDValue Tmp1, Tmp2;
    1297             : 
    1298             :     // When necessary, use a voffset in <= CI anyway to work around a hardware
    1299             :     // bug.
    1300         312 :     if (Subtarget->getGeneration() > AMDGPUSubtarget::SEA_ISLANDS ||
    1301         103 :         SelectMUBUFConstant(Offset, Tmp1, Tmp2))
    1302         201 :       return false;
    1303             :   }
    1304             : 
    1305          56 :   if (CurDAG->isBaseWithConstantOffset(Offset)) {
    1306          20 :     SDValue N0 = Offset.getOperand(0);
    1307          20 :     SDValue N1 = Offset.getOperand(1);
    1308          28 :     if (cast<ConstantSDNode>(N1)->getSExtValue() >= 0 &&
    1309           8 :         SelectMUBUFConstant(N1, SOffset, ImmOffset)) {
    1310           8 :       VOffset = N0;
    1311           8 :       return true;
    1312             :     }
    1313             :   }
    1314             : 
    1315         144 :   SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
    1316         144 :   ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
    1317          48 :   VOffset = Offset;
    1318             : 
    1319          48 :   return true;
    1320             : }
    1321             : 
    1322             : template <bool IsSigned>
    1323        9462 : bool AMDGPUDAGToDAGISel::SelectFlatOffset(SDValue Addr,
    1324             :                                           SDValue &VAddr,
    1325             :                                           SDValue &Offset,
    1326             :                                           SDValue &SLC) const {
    1327        9462 :   int64_t OffsetVal = 0;
    1328             : 
    1329       11266 :   if (Subtarget->hasFlatInstOffsets() &&
    1330        1804 :       CurDAG->isBaseWithConstantOffset(Addr)) {
    1331         542 :     SDValue N0 = Addr.getOperand(0);
    1332         542 :     SDValue N1 = Addr.getOperand(1);
    1333         542 :     int64_t COffsetVal = cast<ConstantSDNode>(N1)->getSExtValue();
    1334             : 
    1335         271 :     if ((IsSigned && isInt<13>(COffsetVal)) ||
    1336          85 :         (!IsSigned && isUInt<12>(COffsetVal))) {
    1337         232 :       Addr = N0;
    1338         232 :       OffsetVal = COffsetVal;
    1339             :     }
    1340             :   }
    1341             : 
    1342        9462 :   VAddr = Addr;
    1343       47310 :   Offset = CurDAG->getTargetConstant(OffsetVal, SDLoc(), MVT::i16);
    1344       47310 :   SLC = CurDAG->getTargetConstant(0, SDLoc(), MVT::i1);
    1345             : 
    1346        9462 :   return true;
    1347             : }
    1348             : 
    1349             : bool AMDGPUDAGToDAGISel::SelectFlatAtomic(SDValue Addr,
    1350             :                                           SDValue &VAddr,
    1351             :                                           SDValue &Offset,
    1352             :                                           SDValue &SLC) const {
    1353         899 :   return SelectFlatOffset<false>(Addr, VAddr, Offset, SLC);
    1354             : }
    1355             : 
    1356             : bool AMDGPUDAGToDAGISel::SelectFlatAtomicSigned(SDValue Addr,
    1357             :                                           SDValue &VAddr,
    1358             :                                           SDValue &Offset,
    1359             :                                           SDValue &SLC) const {
    1360         188 :   return SelectFlatOffset<true>(Addr, VAddr, Offset, SLC);
    1361             : }
    1362             : 
    1363       27289 : bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
    1364             :                                           SDValue &Offset, bool &Imm) const {
    1365             : 
    1366             :   // FIXME: Handle non-constant offsets.
    1367       27289 :   ConstantSDNode *C = dyn_cast<ConstantSDNode>(ByteOffsetNode);
    1368             :   if (!C)
    1369             :     return false;
    1370             : 
    1371       27289 :   SDLoc SL(ByteOffsetNode);
    1372       27289 :   AMDGPUSubtarget::Generation Gen = Subtarget->getGeneration();
    1373       27289 :   int64_t ByteOffset = C->getSExtValue();
    1374       27289 :   int64_t EncodedOffset = AMDGPU::getSMRDEncodedOffset(*Subtarget, ByteOffset);
    1375             : 
    1376       27289 :   if (AMDGPU::isLegalSMRDImmOffset(*Subtarget, ByteOffset)) {
    1377       81618 :     Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
    1378       27206 :     Imm = true;
    1379             :     return true;
    1380             :   }
    1381             : 
    1382          83 :   if (!isUInt<32>(EncodedOffset) || !isUInt<32>(ByteOffset))
    1383             :     return false;
    1384             : 
    1385         108 :   if (Gen == AMDGPUSubtarget::SEA_ISLANDS && isUInt<32>(EncodedOffset)) {
    1386             :     // 32-bit Immediates are supported on Sea Islands.
    1387         108 :     Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
    1388             :   } else {
    1389         108 :     SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32);
    1390          72 :     Offset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32,
    1391          36 :                                             C32Bit), 0);
    1392             :   }
    1393          72 :   Imm = false;
    1394             :   return true;
    1395             : }
    1396             : 
    1397       28947 : bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase,
    1398             :                                      SDValue &Offset, bool &Imm) const {
    1399       57894 :   SDLoc SL(Addr);
    1400       28947 :   if (CurDAG->isBaseWithConstantOffset(Addr)) {
    1401       53580 :     SDValue N0 = Addr.getOperand(0);
    1402       53580 :     SDValue N1 = Addr.getOperand(1);
    1403             : 
    1404       26790 :     if (SelectSMRDOffset(N1, Offset, Imm)) {
    1405       26779 :       SBase = N0;
    1406       26779 :       return true;
    1407             :     }
    1408             :   }
    1409        2168 :   SBase = Addr;
    1410        6504 :   Offset = CurDAG->getTargetConstant(0, SL, MVT::i32);
    1411        2168 :   Imm = true;
    1412        2168 :   return true;
    1413             : }
    1414             : 
    1415             : bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase,
    1416             :                                        SDValue &Offset) const {
    1417             :   bool Imm;
    1418       28915 :   return SelectSMRD(Addr, SBase, Offset, Imm) && Imm;
    1419             : }
    1420             : 
    1421           9 : bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase,
    1422             :                                          SDValue &Offset) const {
    1423             : 
    1424           9 :   if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
    1425             :     return false;
    1426             : 
    1427             :   bool Imm;
    1428           9 :   if (!SelectSMRD(Addr, SBase, Offset, Imm))
    1429             :     return false;
    1430             : 
    1431           9 :   return !Imm && isa<ConstantSDNode>(Offset);
    1432             : }
    1433             : 
    1434          23 : bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase,
    1435             :                                         SDValue &Offset) const {
    1436             :   bool Imm;
    1437          23 :   return SelectSMRD(Addr, SBase, Offset, Imm) && !Imm &&
    1438          23 :          !isa<ConstantSDNode>(Offset);
    1439             : }
    1440             : 
    1441             : bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr,
    1442             :                                              SDValue &Offset) const {
    1443             :   bool Imm;
    1444         489 :   return SelectSMRDOffset(Addr, Offset, Imm) && Imm;
    1445             : }
    1446             : 
    1447           3 : bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm32(SDValue Addr,
    1448             :                                                SDValue &Offset) const {
    1449           3 :   if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
    1450             :     return false;
    1451             : 
    1452             :   bool Imm;
    1453           3 :   if (!SelectSMRDOffset(Addr, Offset, Imm))
    1454             :     return false;
    1455             : 
    1456           3 :   return !Imm && isa<ConstantSDNode>(Offset);
    1457             : }
    1458             : 
    1459           7 : bool AMDGPUDAGToDAGISel::SelectSMRDBufferSgpr(SDValue Addr,
    1460             :                                               SDValue &Offset) const {
    1461             :   bool Imm;
    1462           7 :   return SelectSMRDOffset(Addr, Offset, Imm) && !Imm &&
    1463           7 :          !isa<ConstantSDNode>(Offset);
    1464             : }
    1465             : 
    1466       32573 : bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index,
    1467             :                                             SDValue &Base,
    1468             :                                             SDValue &Offset) const {
    1469       65146 :   SDLoc DL(Index);
    1470             : 
    1471       32573 :   if (CurDAG->isBaseWithConstantOffset(Index)) {
    1472         160 :     SDValue N0 = Index.getOperand(0);
    1473         160 :     SDValue N1 = Index.getOperand(1);
    1474          80 :     ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
    1475             : 
    1476             :     // (add n0, c0)
    1477          80 :     Base = N0;
    1478         320 :     Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32);
    1479             :     return true;
    1480             :   }
    1481             : 
    1482          92 :   if (isa<ConstantSDNode>(Index))
    1483             :     return false;
    1484             : 
    1485          92 :   Base = Index;
    1486         276 :   Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
    1487             :   return true;
    1488             : }
    1489             : 
    1490        4869 : SDNode *AMDGPUDAGToDAGISel::getS_BFE(unsigned Opcode, const SDLoc &DL,
    1491             :                                      SDValue Val, uint32_t Offset,
    1492             :                                      uint32_t Width) {
    1493             :   // Transformation function, pack the offset and width of a BFE into
    1494             :   // the format expected by the S_BFE_I32 / S_BFE_U32. In the second
    1495             :   // source, bits [5:0] contain the offset and bits [22:16] the width.
    1496        4869 :   uint32_t PackedVal = Offset | (Width << 16);
    1497       14607 :   SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, DL, MVT::i32);
    1498             : 
    1499        9738 :   return CurDAG->getMachineNode(Opcode, DL, MVT::i32, Val, PackedConst);
    1500             : }
    1501             : 
    1502         166 : void AMDGPUDAGToDAGISel::SelectS_BFEFromShifts(SDNode *N) {
    1503             :   // "(a << b) srl c)" ---> "BFE_U32 a, (c-b), (32-c)
    1504             :   // "(a << b) sra c)" ---> "BFE_I32 a, (c-b), (32-c)
    1505             :   // Predicate: 0 < b <= c < 32
    1506             : 
    1507         332 :   const SDValue &Shl = N->getOperand(0);
    1508         498 :   ConstantSDNode *B = dyn_cast<ConstantSDNode>(Shl->getOperand(1));
    1509         498 :   ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
    1510             : 
    1511         166 :   if (B && C) {
    1512         150 :     uint32_t BVal = B->getZExtValue();
    1513         150 :     uint32_t CVal = C->getZExtValue();
    1514             : 
    1515         150 :     if (0 < BVal && BVal <= CVal && CVal < 32) {
    1516         292 :       bool Signed = N->getOpcode() == ISD::SRA;
    1517         146 :       unsigned Opcode = Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32;
    1518             : 
    1519         730 :       ReplaceNode(N, getS_BFE(Opcode, SDLoc(N), Shl.getOperand(0), CVal - BVal,
    1520             :                               32 - CVal));
    1521         146 :       return;
    1522             :     }
    1523             :   }
    1524             :   SelectCode(N);
    1525             : }
    1526             : 
    1527       16389 : void AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) {
    1528       32778 :   switch (N->getOpcode()) {
    1529        6518 :   case ISD::AND:
    1530       19554 :     if (N->getOperand(0).getOpcode() == ISD::SRL) {
    1531             :       // "(a srl b) & mask" ---> "BFE_U32 a, b, popcount(mask)"
    1532             :       // Predicate: isMask(mask)
    1533        5356 :       const SDValue &Srl = N->getOperand(0);
    1534        8034 :       ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1));
    1535        8034 :       ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
    1536             : 
    1537        2678 :       if (Shift && Mask) {
    1538        2665 :         uint32_t ShiftVal = Shift->getZExtValue();
    1539        2665 :         uint32_t MaskVal = Mask->getZExtValue();
    1540             : 
    1541        2490 :         if (isMask_32(MaskVal)) {
    1542        2490 :           uint32_t WidthVal = countPopulation(MaskVal);
    1543             : 
    1544        9960 :           ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N),
    1545        4980 :                                   Srl.getOperand(0), ShiftVal, WidthVal));
    1546        2490 :           return;
    1547             :         }
    1548             :       }
    1549             :     }
    1550             :     break;
    1551        4610 :   case ISD::SRL:
    1552       13830 :     if (N->getOperand(0).getOpcode() == ISD::AND) {
    1553             :       // "(a & mask) srl b)" ---> "BFE_U32 a, b, popcount(mask >> b)"
    1554             :       // Predicate: isMask(mask >> b)
    1555        1602 :       const SDValue &And = N->getOperand(0);
    1556        2403 :       ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N->getOperand(1));
    1557        2403 :       ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(And->getOperand(1));
    1558             : 
    1559         801 :       if (Shift && Mask) {
    1560         801 :         uint32_t ShiftVal = Shift->getZExtValue();
    1561         801 :         uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal;
    1562             : 
    1563         799 :         if (isMask_32(MaskVal)) {
    1564         799 :           uint32_t WidthVal = countPopulation(MaskVal);
    1565             : 
    1566        3196 :           ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N),
    1567        1598 :                                   And.getOperand(0), ShiftVal, WidthVal));
    1568         799 :           return;
    1569             :         }
    1570             :       }
    1571       11427 :     } else if (N->getOperand(0).getOpcode() == ISD::SHL) {
    1572          12 :       SelectS_BFEFromShifts(N);
    1573          12 :       return;
    1574             :     }
    1575             :     break;
    1576        1699 :   case ISD::SRA:
    1577        5097 :     if (N->getOperand(0).getOpcode() == ISD::SHL) {
    1578         154 :       SelectS_BFEFromShifts(N);
    1579         154 :       return;
    1580             :     }
    1581             :     break;
    1582             : 
    1583        3562 :   case ISD::SIGN_EXTEND_INREG: {
    1584             :     // sext_inreg (srl x, 16), i8 -> bfe_i32 x, 16, 8
    1585        7124 :     SDValue Src = N->getOperand(0);
    1586        7124 :     if (Src.getOpcode() != ISD::SRL)
    1587             :       break;
    1588             : 
    1589        3906 :     const ConstantSDNode *Amt = dyn_cast<ConstantSDNode>(Src.getOperand(1));
    1590             :     if (!Amt)
    1591             :       break;
    1592             : 
    1593        3906 :     unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
    1594        7812 :     ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_I32, SDLoc(N), Src.getOperand(0),
    1595             :                             Amt->getZExtValue(), Width));
    1596        1302 :     return;
    1597             :   }
    1598             :   }
    1599             : 
    1600             :   SelectCode(N);
    1601             : }
    1602             : 
    1603         810 : bool AMDGPUDAGToDAGISel::isCBranchSCC(const SDNode *N) const {
    1604             :   assert(N->getOpcode() == ISD::BRCOND);
    1605         810 :   if (!N->hasOneUse())
    1606             :     return false;
    1607             : 
    1608        1620 :   SDValue Cond = N->getOperand(1);
    1609        1620 :   if (Cond.getOpcode() == ISD::CopyToReg)
    1610           0 :     Cond = Cond.getOperand(2);
    1611             : 
    1612        2408 :   if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse())
    1613             :     return false;
    1614             : 
    1615        2352 :   MVT VT = Cond.getOperand(0).getSimpleValueType();
    1616         784 :   if (VT == MVT::i32)
    1617             :     return true;
    1618             : 
    1619          96 :   if (VT == MVT::i64) {
    1620          39 :     auto ST = static_cast<const SISubtarget *>(Subtarget);
    1621             : 
    1622         117 :     ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
    1623          76 :     return (CC == ISD::SETEQ || CC == ISD::SETNE) && ST->hasScalarCompareEq64();
    1624             :   }
    1625             : 
    1626             :   return false;
    1627             : }
    1628             : 
    1629         531 : void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
    1630        1062 :   SDValue Cond = N->getOperand(1);
    1631             : 
    1632        1062 :   if (Cond.isUndef()) {
    1633         152 :     CurDAG->SelectNodeTo(N, AMDGPU::SI_BR_UNDEF, MVT::Other,
    1634         304 :                          N->getOperand(2), N->getOperand(0));
    1635         507 :     return;
    1636             :   }
    1637             : 
    1638         455 :   if (isCBranchSCC(N)) {
    1639             :     // This brcond will use S_CBRANCH_SCC*, so let tablegen handle it.
    1640             :     SelectCode(N);
    1641             :     return;
    1642             :   }
    1643             : 
    1644         200 :   SDLoc SL(N);
    1645             : 
    1646         200 :   SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, AMDGPU::VCC, Cond);
    1647         300 :   CurDAG->SelectNodeTo(N, AMDGPU::S_CBRANCH_VCCNZ, MVT::Other,
    1648         200 :                        N->getOperand(2), // Basic Block
    1649         100 :                        VCC.getValue(0));
    1650             : }
    1651             : 
    1652        1263 : void AMDGPUDAGToDAGISel::SelectFMAD(SDNode *N) {
    1653        1263 :   MVT VT = N->getSimpleValueType(0);
    1654        2402 :   if (VT != MVT::f32 || !Subtarget->hasMadMixInsts()) {
    1655        1232 :     SelectCode(N);
    1656        1232 :     return;
    1657             :   }
    1658             : 
    1659          62 :   SDValue Src0 = N->getOperand(0);
    1660          62 :   SDValue Src1 = N->getOperand(1);
    1661          62 :   SDValue Src2 = N->getOperand(2);
    1662             :   unsigned Src0Mods, Src1Mods, Src2Mods;
    1663             : 
    1664             :   // Avoid using v_mad_mix_f32 unless there is actually an operand using the
    1665             :   // conversion from f16.
    1666          31 :   bool Sel0 = SelectVOP3PMadMixModsImpl(Src0, Src0, Src0Mods);
    1667          31 :   bool Sel1 = SelectVOP3PMadMixModsImpl(Src1, Src1, Src1Mods);
    1668          31 :   bool Sel2 = SelectVOP3PMadMixModsImpl(Src2, Src2, Src2Mods);
    1669             : 
    1670             :   assert(!Subtarget->hasFP32Denormals() &&
    1671             :          "fmad selected with denormals enabled");
    1672             :   // TODO: We can select this with f32 denormals enabled if all the sources are
    1673             :   // converted from f16 (in which case fmad isn't legal).
    1674             : 
    1675          31 :   if (Sel0 || Sel1 || Sel2) {
    1676             :     // For dummy operands.
    1677         135 :     SDValue Zero = CurDAG->getTargetConstant(0, SDLoc(), MVT::i32);
    1678             :     SDValue Ops[] = {
    1679         108 :       CurDAG->getTargetConstant(Src0Mods, SDLoc(), MVT::i32), Src0,
    1680         108 :       CurDAG->getTargetConstant(Src1Mods, SDLoc(), MVT::i32), Src1,
    1681         108 :       CurDAG->getTargetConstant(Src2Mods, SDLoc(), MVT::i32), Src2,
    1682         108 :       CurDAG->getTargetConstant(0, SDLoc(), MVT::i1),
    1683             :       Zero, Zero
    1684         216 :     };
    1685             : 
    1686          81 :     CurDAG->SelectNodeTo(N, AMDGPU::V_MAD_MIX_F32, MVT::f32, Ops);
    1687             :   } else {
    1688             :     SelectCode(N);
    1689             :   }
    1690             : }
    1691             : 
    1692             : // This is here because there isn't a way to use the generated sub0_sub1 as the
    1693             : // subreg index to EXTRACT_SUBREG in tablegen.
    1694         195 : void AMDGPUDAGToDAGISel::SelectATOMIC_CMP_SWAP(SDNode *N) {
    1695         195 :   MemSDNode *Mem = cast<MemSDNode>(N);
    1696         195 :   unsigned AS = Mem->getAddressSpace();
    1697         195 :   if (AS == AMDGPUASI.FLAT_ADDRESS) {
    1698             :     SelectCode(N);
    1699         169 :     return;
    1700             :   }
    1701             : 
    1702          51 :   MVT VT = N->getSimpleValueType(0);
    1703          51 :   bool Is32 = (VT == MVT::i32);
    1704          77 :   SDLoc SL(N);
    1705             : 
    1706          51 :   MachineSDNode *CmpSwap = nullptr;
    1707         102 :   if (Subtarget->hasAddr64()) {
    1708          17 :     SDValue SRsrc, VAddr, SOffset, Offset, GLC, SLC;
    1709             : 
    1710          17 :     if (SelectMUBUFAddr64(Mem->getBasePtr(), SRsrc, VAddr, SOffset, Offset, SLC)) {
    1711           8 :       unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN :
    1712             :         AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN;
    1713          16 :       SDValue CmpVal = Mem->getOperand(2);
    1714             : 
    1715             :       // XXX - Do we care about glue operands?
    1716             : 
    1717             :       SDValue Ops[] = {
    1718           8 :         CmpVal, VAddr, SRsrc, SOffset, Offset, SLC, Mem->getChain()
    1719          16 :       };
    1720             : 
    1721          24 :       CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops);
    1722             :     }
    1723             :   }
    1724             : 
    1725           8 :   if (!CmpSwap) {
    1726          43 :     SDValue SRsrc, SOffset, Offset, SLC;
    1727          86 :     if (SelectMUBUFOffset(Mem->getBasePtr(), SRsrc, SOffset, Offset, SLC)) {
    1728          18 :       unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN :
    1729             :         AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN;
    1730             : 
    1731          36 :       SDValue CmpVal = Mem->getOperand(2);
    1732             :       SDValue Ops[] = {
    1733          18 :         CmpVal, SRsrc, SOffset, Offset, SLC, Mem->getChain()
    1734          36 :       };
    1735             : 
    1736          54 :       CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops);
    1737             :     }
    1738             :   }
    1739             : 
    1740          51 :   if (!CmpSwap) {
    1741          25 :     SelectCode(N);
    1742             :     return;
    1743             :   }
    1744             : 
    1745          26 :   MachineSDNode::mmo_iterator MMOs = MF->allocateMemRefsArray(1);
    1746          26 :   *MMOs = Mem->getMemOperand();
    1747          52 :   CmpSwap->setMemRefs(MMOs, MMOs + 1);
    1748             : 
    1749          26 :   unsigned SubReg = Is32 ? AMDGPU::sub0 : AMDGPU::sub0_sub1;
    1750             :   SDValue Extract
    1751          78 :     = CurDAG->getTargetExtractSubreg(SubReg, SL, VT, SDValue(CmpSwap, 0));
    1752             : 
    1753          26 :   ReplaceUses(SDValue(N, 0), Extract);
    1754          26 :   ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 1));
    1755          26 :   CurDAG->RemoveDeadNode(N);
    1756             : }
    1757             : 
    1758          93 : bool AMDGPUDAGToDAGISel::SelectVOP3ModsImpl(SDValue In, SDValue &Src,
    1759             :                                             unsigned &Mods) const {
    1760       17942 :   Mods = 0;
    1761       17942 :   Src = In;
    1762             : 
    1763       35884 :   if (Src.getOpcode() == ISD::FNEG) {
    1764        1307 :     Mods |= SISrcMods::NEG;
    1765        2614 :     Src = Src.getOperand(0);
    1766             :   }
    1767             : 
    1768       35884 :   if (Src.getOpcode() == ISD::FABS) {
    1769         585 :     Mods |= SISrcMods::ABS;
    1770        1170 :     Src = Src.getOperand(0);
    1771             :   }
    1772             : 
    1773          93 :   return true;
    1774             : }
    1775             : 
    1776       17849 : bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
    1777             :                                         SDValue &SrcMods) const {
    1778             :   unsigned Mods;
    1779       35698 :   if (SelectVOP3ModsImpl(In, Src, Mods)) {
    1780       89245 :     SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
    1781             :     return true;
    1782             :   }
    1783             : 
    1784             :   return false;
    1785             : }
    1786             : 
    1787         492 : bool AMDGPUDAGToDAGISel::SelectVOP3Mods_NNaN(SDValue In, SDValue &Src,
    1788             :                                              SDValue &SrcMods) const {
    1789         492 :   SelectVOP3Mods(In, Src, SrcMods);
    1790         492 :   return isNoNanSrc(Src);
    1791             : }
    1792             : 
    1793             : bool AMDGPUDAGToDAGISel::SelectVOP3NoMods(SDValue In, SDValue &Src) const {
    1794        9801 :   if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG)
    1795             :     return false;
    1796             : 
    1797        2956 :   Src = In;
    1798             :   return true;
    1799             : }
    1800             : 
    1801        8340 : bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
    1802             :                                          SDValue &SrcMods, SDValue &Clamp,
    1803             :                                          SDValue &Omod) const {
    1804       16680 :   SDLoc DL(In);
    1805       25020 :   Clamp = CurDAG->getTargetConstant(0, DL, MVT::i1);
    1806       25020 :   Omod = CurDAG->getTargetConstant(0, DL, MVT::i1);
    1807             : 
    1808       16680 :   return SelectVOP3Mods(In, Src, SrcMods);
    1809             : }
    1810             : 
    1811          42 : bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src,
    1812             :                                                    SDValue &SrcMods,
    1813             :                                                    SDValue &Clamp,
    1814             :                                                    SDValue &Omod) const {
    1815         210 :   Clamp = Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
    1816          42 :   return SelectVOP3Mods(In, Src, SrcMods);
    1817             : }
    1818             : 
    1819         299 : bool AMDGPUDAGToDAGISel::SelectVOP3OMods(SDValue In, SDValue &Src,
    1820             :                                          SDValue &Clamp, SDValue &Omod) const {
    1821         299 :   Src = In;
    1822             : 
    1823         598 :   SDLoc DL(In);
    1824         897 :   Clamp = CurDAG->getTargetConstant(0, DL, MVT::i1);
    1825         897 :   Omod = CurDAG->getTargetConstant(0, DL, MVT::i1);
    1826             : 
    1827         598 :   return true;
    1828             : }
    1829             : 
    1830             : static SDValue stripBitcast(SDValue Val) {
    1831        1655 :   return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
    1832             : }
    1833             : 
    1834             : // Figure out if this is really an extract of the high 16-bits of a dword.
    1835         342 : static bool isExtractHiElt(SDValue In, SDValue &Out) {
    1836         342 :   In = stripBitcast(In);
    1837         684 :   if (In.getOpcode() != ISD::TRUNCATE)
    1838             :     return false;
    1839             : 
    1840         150 :   SDValue Srl = In.getOperand(0);
    1841         150 :   if (Srl.getOpcode() == ISD::SRL) {
    1842         138 :     if (ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(Srl.getOperand(1))) {
    1843          46 :       if (ShiftAmt->getZExtValue() == 16) {
    1844         138 :         Out = stripBitcast(Srl.getOperand(0));
    1845          46 :         return true;
    1846             :       }
    1847             :     }
    1848             :   }
    1849             : 
    1850             :   return false;
    1851             : }
    1852             : 
    1853             : // Look through operations that obscure just looking at the low 16-bits of the
    1854             : // same register.
    1855         276 : static SDValue stripExtractLoElt(SDValue In) {
    1856         552 :   if (In.getOpcode() == ISD::TRUNCATE) {
    1857          36 :     SDValue Src = In.getOperand(0);
    1858          36 :     if (Src.getValueType().getSizeInBits() == 32)
    1859          15 :       return stripBitcast(Src);
    1860             :   }
    1861             : 
    1862         261 :   return In;
    1863             : }
    1864             : 
    1865         578 : bool AMDGPUDAGToDAGISel::SelectVOP3PMods(SDValue In, SDValue &Src,
    1866             :                                          SDValue &SrcMods) const {
    1867         578 :   unsigned Mods = 0;
    1868         578 :   Src = In;
    1869             : 
    1870        1156 :   if (Src.getOpcode() == ISD::FNEG) {
    1871          13 :     Mods ^= (SISrcMods::NEG | SISrcMods::NEG_HI);
    1872          26 :     Src = Src.getOperand(0);
    1873             :   }
    1874             : 
    1875        1156 :   if (Src.getOpcode() == ISD::BUILD_VECTOR) {
    1876         138 :     unsigned VecMods = Mods;
    1877             : 
    1878         414 :     SDValue Lo = stripBitcast(Src.getOperand(0));
    1879         414 :     SDValue Hi = stripBitcast(Src.getOperand(1));
    1880             : 
    1881         276 :     if (Lo.getOpcode() == ISD::FNEG) {
    1882          33 :       Lo = stripBitcast(Lo.getOperand(0));
    1883          11 :       Mods ^= SISrcMods::NEG;
    1884             :     }
    1885             : 
    1886         276 :     if (Hi.getOpcode() == ISD::FNEG) {
    1887          33 :       Hi = stripBitcast(Hi.getOperand(0));
    1888          11 :       Mods ^= SISrcMods::NEG_HI;
    1889             :     }
    1890             : 
    1891         138 :     if (isExtractHiElt(Lo, Lo))
    1892          13 :       Mods |= SISrcMods::OP_SEL_0;
    1893             : 
    1894         138 :     if (isExtractHiElt(Hi, Hi))
    1895          11 :       Mods |= SISrcMods::OP_SEL_1;
    1896             : 
    1897         138 :     Lo = stripExtractLoElt(Lo);
    1898         138 :     Hi = stripExtractLoElt(Hi);
    1899             : 
    1900         112 :     if (Lo == Hi && !isInlineImmediate(Lo.getNode())) {
    1901             :       // Really a scalar input. Just select from the low half of the register to
    1902             :       // avoid packing.
    1903             : 
    1904          27 :       Src = Lo;
    1905         135 :       SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
    1906          27 :       return true;
    1907             :     }
    1908             : 
    1909         111 :     Mods = VecMods;
    1910             :   }
    1911             : 
    1912             :   // Packed instructions do not have abs modifiers.
    1913         551 :   Mods |= SISrcMods::OP_SEL_1;
    1914             : 
    1915        2755 :   SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
    1916         551 :   return true;
    1917             : }
    1918             : 
    1919         261 : bool AMDGPUDAGToDAGISel::SelectVOP3PMods0(SDValue In, SDValue &Src,
    1920             :                                           SDValue &SrcMods,
    1921             :                                           SDValue &Clamp) const {
    1922         522 :   SDLoc SL(In);
    1923             : 
    1924             :   // FIXME: Handle clamp and op_sel
    1925         783 :   Clamp = CurDAG->getTargetConstant(0, SL, MVT::i32);
    1926             : 
    1927         522 :   return SelectVOP3PMods(In, Src, SrcMods);
    1928             : }
    1929             : 
    1930          18 : bool AMDGPUDAGToDAGISel::SelectVOP3OpSel(SDValue In, SDValue &Src,
    1931             :                                          SDValue &SrcMods) const {
    1932          18 :   Src = In;
    1933             :   // FIXME: Handle op_sel
    1934          90 :   SrcMods = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
    1935          18 :   return true;
    1936             : }
    1937             : 
    1938           6 : bool AMDGPUDAGToDAGISel::SelectVOP3OpSel0(SDValue In, SDValue &Src,
    1939             :                                           SDValue &SrcMods,
    1940             :                                           SDValue &Clamp) const {
    1941          12 :   SDLoc SL(In);
    1942             : 
    1943             :   // FIXME: Handle clamp
    1944          18 :   Clamp = CurDAG->getTargetConstant(0, SL, MVT::i32);
    1945             : 
    1946          12 :   return SelectVOP3OpSel(In, Src, SrcMods);
    1947             : }
    1948             : 
    1949             : bool AMDGPUDAGToDAGISel::SelectVOP3OpSelMods(SDValue In, SDValue &Src,
    1950             :                                              SDValue &SrcMods) const {
    1951             :   // FIXME: Handle op_sel
    1952          24 :   return SelectVOP3Mods(In, Src, SrcMods);
    1953             : }
    1954             : 
    1955           8 : bool AMDGPUDAGToDAGISel::SelectVOP3OpSelMods0(SDValue In, SDValue &Src,
    1956             :                                               SDValue &SrcMods,
    1957             :                                               SDValue &Clamp) const {
    1958          16 :   SDLoc SL(In);
    1959             : 
    1960             :   // FIXME: Handle clamp
    1961          24 :   Clamp = CurDAG->getTargetConstant(0, SL, MVT::i32);
    1962             : 
    1963          24 :   return SelectVOP3OpSelMods(In, Src, SrcMods);
    1964             : }
    1965             : 
    1966             : // The return value is not whether the match is possible (which it always is),
    1967             : // but whether or not it a conversion is really used.
    1968          93 : bool AMDGPUDAGToDAGISel::SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src,
    1969             :                                                    unsigned &Mods) const {
    1970          93 :   Mods = 0;
    1971          93 :   SelectVOP3ModsImpl(In, Src, Mods);
    1972             : 
    1973         186 :   if (Src.getOpcode() == ISD::FP_EXTEND) {
    1974         132 :     Src = Src.getOperand(0);
    1975             :     assert(Src.getValueType() == MVT::f16);
    1976          66 :     Src = stripBitcast(Src);
    1977             : 
    1978             :     // op_sel/op_sel_hi decide the source type and source.
    1979             :     // If the source's op_sel_hi is set, it indicates to do a conversion from fp16.
    1980             :     // If the sources's op_sel is set, it picks the high half of the source
    1981             :     // register.
    1982             : 
    1983          66 :     Mods |= SISrcMods::OP_SEL_1;
    1984          66 :     if (isExtractHiElt(Src, Src))
    1985          22 :       Mods |= SISrcMods::OP_SEL_0;
    1986             : 
    1987             :     return true;
    1988             :   }
    1989             : 
    1990             :   return false;
    1991             : }
    1992             : 
    1993       19029 : void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
    1994             :   const AMDGPUTargetLowering& Lowering =
    1995       19029 :     *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
    1996       19029 :   bool IsModified = false;
    1997       21073 :   do {
    1998       21073 :     IsModified = false;
    1999             :     // Go over all selected nodes and try to fold them a bit more
    2000      928192 :     for (SDNode &Node : CurDAG->allnodes()) {
    2001      513068 :       MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(&Node);
    2002      372978 :       if (!MachineNode)
    2003      372978 :         continue;
    2004             : 
    2005      513068 :       SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
    2006      513068 :       if (ResNode != &Node) {
    2007       67120 :         ReplaceUses(&Node, ResNode);
    2008       33560 :         IsModified = true;
    2009             :       }
    2010             :     }
    2011       21073 :     CurDAG->RemoveDeadNodes();
    2012             :   } while (IsModified);
    2013       19029 : }
    2014             : 
    2015       80099 : void R600DAGToDAGISel::Select(SDNode *N) {
    2016      160198 :   unsigned int Opc = N->getOpcode();
    2017       80099 :   if (N->isMachineOpcode()) {
    2018           0 :     N->setNodeId(-1);
    2019             :     return;   // Already selected.
    2020             :   }
    2021             : 
    2022       80099 :   switch (Opc) {
    2023             :   default: break;
    2024        2386 :   case AMDGPUISD::BUILD_VERTICAL_VECTOR:
    2025             :   case ISD::SCALAR_TO_VECTOR:
    2026             :   case ISD::BUILD_VECTOR: {
    2027        4772 :     EVT VT = N->getValueType(0);
    2028        2386 :     unsigned NumVectorElts = VT.getVectorNumElements();
    2029             :     unsigned RegClassID;
    2030             :     // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
    2031             :     // that adds a 128 bits reg copy when going through TwoAddressInstructions
    2032             :     // pass. We want to avoid 128 bits copies as much as possible because they
    2033             :     // can't be bundled by our scheduler.
    2034        2386 :     switch(NumVectorElts) {
    2035             :     case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
    2036        2015 :     case 4:
    2037        2015 :       if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
    2038             :         RegClassID = AMDGPU::R600_Reg128VerticalRegClassID;
    2039             :       else
    2040        2007 :         RegClassID = AMDGPU::R600_Reg128RegClassID;
    2041             :       break;
    2042           0 :     default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
    2043             :     }
    2044        2386 :     SelectBuildVector(N, RegClassID);
    2045             :     return;
    2046             :   }
    2047             :   }
    2048             : 
    2049       77713 :   SelectCode(N);
    2050             : }
    2051             : 
    2052        1852 : bool R600DAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
    2053             :                                           SDValue &Offset) {
    2054             :   ConstantSDNode *C;
    2055        3704 :   SDLoc DL(Addr);
    2056             : 
    2057           0 :   if ((C = dyn_cast<ConstantSDNode>(Addr))) {
    2058           0 :     Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
    2059           0 :     Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
    2060        5339 :   } else if ((Addr.getOpcode() == AMDGPUISD::DWORDADDR) &&
    2061        3704 :              (C = dyn_cast<ConstantSDNode>(Addr.getOperand(0)))) {
    2062        3270 :     Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
    2063        6540 :     Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
    2064         868 :   } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
    2065           0 :             (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
    2066           0 :     Base = Addr.getOperand(0);
    2067           0 :     Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
    2068             :   } else {
    2069         217 :     Base = Addr;
    2070         651 :     Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
    2071             :   }
    2072             : 
    2073        3704 :   return true;
    2074             : }
    2075             : 
    2076        1487 : bool R600DAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
    2077             :                                           SDValue &Offset) {
    2078             :   ConstantSDNode *IMMOffset;
    2079             : 
    2080        1487 :   if (Addr.getOpcode() == ISD::ADD
    2081        1354 :       && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
    2082        2207 :       && isInt<16>(IMMOffset->getZExtValue())) {
    2083             : 
    2084         718 :       Base = Addr.getOperand(0);
    2085        1436 :       Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
    2086        1077 :                                          MVT::i32);
    2087         359 :       return true;
    2088             :   // If the pointer address is constant, we can move it to the offset field.
    2089             :   } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
    2090         711 :              && isInt<16>(IMMOffset->getZExtValue())) {
    2091         711 :     Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
    2092         948 :                                   SDLoc(CurDAG->getEntryNode()),
    2093         711 :                                   AMDGPU::ZERO, MVT::i32);
    2094         948 :     Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
    2095         474 :                                        MVT::i32);
    2096         237 :     return true;
    2097             :   }
    2098             : 
    2099             :   // Default case, no offset
    2100         891 :   Base = Addr;
    2101        4455 :   Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
    2102         891 :   return true;
    2103             : }

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