LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - AMDGPUISelLowering.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 12 12 100.0 %
Date: 2018-02-23 15:42:53 Functions: 5 5 100.0 %
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          Line data    Source code
       1             : //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// \brief Interface definition of the TargetLowering class that is common
      12             : /// to all AMD GPUs.
      13             : //
      14             : //===----------------------------------------------------------------------===//
      15             : 
      16             : #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
      17             : #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
      18             : 
      19             : #include "AMDGPU.h"
      20             : #include "llvm/CodeGen/CallingConvLower.h"
      21             : #include "llvm/CodeGen/TargetLowering.h"
      22             : 
      23             : namespace llvm {
      24             : 
      25             : class AMDGPUMachineFunction;
      26             : class AMDGPUSubtarget;
      27             : struct ArgDescriptor;
      28             : 
      29             : class AMDGPUTargetLowering : public TargetLowering {
      30             : private:
      31             :   /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
      32             :   /// legalized from a smaller type VT. Need to match pre-legalized type because
      33             :   /// the generic legalization inserts the add/sub between the select and
      34             :   /// compare.
      35             :   SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
      36             : 
      37             : public:
      38             :   static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
      39             :   static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
      40             : 
      41             : protected:
      42             :   const AMDGPUSubtarget *Subtarget;
      43             :   AMDGPUAS AMDGPUASI;
      44             : 
      45             :   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
      46             :   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
      47             :   /// \brief Split a vector store into multiple scalar stores.
      48             :   /// \returns The resulting chain.
      49             : 
      50             :   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
      51             :   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
      52             :   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
      53             :   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
      54             :   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
      55             : 
      56             :   SDValue LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const;
      57             :   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
      58             :   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
      59             :   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
      60             :   SDValue LowerFLOG(SDValue Op, SelectionDAG &Dag,
      61             :                     double Log2BaseInverted) const;
      62             : 
      63             :   SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
      64             : 
      65             :   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
      66             :   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
      67             :   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
      68             :   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
      69             : 
      70             :   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
      71             :   SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
      72             :   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
      73             :   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
      74             : 
      75             :   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
      76             : 
      77             : protected:
      78             :   bool shouldCombineMemoryType(EVT VT) const;
      79             :   SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
      80             :   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
      81             :   SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
      82             :   SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
      83             : 
      84             :   SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
      85             :                                        unsigned Opc, SDValue LHS,
      86             :                                        uint32_t ValLo, uint32_t ValHi) const;
      87             :   SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
      88             :   SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
      89             :   SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
      90             :   SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
      91             :   SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
      92             :   SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
      93             :   SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const;
      94             :   SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
      95             :                              SDValue RHS, DAGCombinerInfo &DCI) const;
      96             :   SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
      97             :   SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
      98             :   SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
      99             : 
     100             :   static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
     101             : 
     102             :   virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
     103             :                                      SelectionDAG &DAG) const;
     104             : 
     105             :   /// Return 64-bit value Op as two 32-bit integers.
     106             :   std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
     107             :                                               SelectionDAG &DAG) const;
     108             :   SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
     109             :   SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
     110             : 
     111             :   /// \brief Split a vector load into 2 loads of half the vector.
     112             :   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
     113             : 
     114             :   /// \brief Split a vector store into 2 stores of half the vector.
     115             :   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
     116             : 
     117             :   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
     118             :   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
     119             :   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
     120             :   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
     121             :   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
     122             :                                     SmallVectorImpl<SDValue> &Results) const;
     123             :   void analyzeFormalArgumentsCompute(CCState &State,
     124             :                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
     125             : public:
     126             :   AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
     127             : 
     128             :   bool mayIgnoreSignedZero(SDValue Op) const {
     129         147 :     if (getTargetMachine().Options.NoSignedZerosFPMath)
     130             :       return true;
     131             : 
     132             :     const auto Flags = Op.getNode()->getFlags();
     133         121 :     if (Flags.isDefined())
     134             :       return Flags.hasNoSignedZeros();
     135             : 
     136             :     return false;
     137             :   }
     138             : 
     139             :   static bool allUsesHaveSourceMods(const SDNode *N,
     140             :                                     unsigned CostThreshold = 4);
     141             :   bool isFAbsFree(EVT VT) const override;
     142             :   bool isFNegFree(EVT VT) const override;
     143             :   bool isTruncateFree(EVT Src, EVT Dest) const override;
     144             :   bool isTruncateFree(Type *Src, Type *Dest) const override;
     145             : 
     146             :   bool isZExtFree(Type *Src, Type *Dest) const override;
     147             :   bool isZExtFree(EVT Src, EVT Dest) const override;
     148             :   bool isZExtFree(SDValue Val, EVT VT2) const override;
     149             :   bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override;
     150             : 
     151             :   bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
     152             : 
     153             :   MVT getVectorIdxTy(const DataLayout &) const override;
     154             :   bool isSelectSupported(SelectSupportKind) const override;
     155             : 
     156             :   bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
     157             :   bool ShouldShrinkFPConstant(EVT VT) const override;
     158             :   bool shouldReduceLoadWidth(SDNode *Load,
     159             :                              ISD::LoadExtType ExtType,
     160             :                              EVT ExtVT) const override;
     161             : 
     162             :   bool isLoadBitCastBeneficial(EVT, EVT) const final;
     163             : 
     164             :   bool storeOfVectorConstantIsCheap(EVT MemVT,
     165             :                                     unsigned NumElem,
     166             :                                     unsigned AS) const override;
     167             :   bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
     168             :   bool isCheapToSpeculateCttz() const override;
     169             :   bool isCheapToSpeculateCtlz() const override;
     170             : 
     171             :   static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
     172             :   static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
     173             : 
     174             :   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
     175             :                       const SmallVectorImpl<ISD::OutputArg> &Outs,
     176             :                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
     177             :                       SelectionDAG &DAG) const override;
     178             : 
     179             :   SDValue addTokenForArgument(SDValue Chain,
     180             :                               SelectionDAG &DAG,
     181             :                               MachineFrameInfo &MFI,
     182             :                               int ClobberedFI) const;
     183             : 
     184             :   SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
     185             :                              SmallVectorImpl<SDValue> &InVals,
     186             :                              StringRef Reason) const;
     187             :   SDValue LowerCall(CallLoweringInfo &CLI,
     188             :                     SmallVectorImpl<SDValue> &InVals) const override;
     189             : 
     190             :   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
     191             :                                   SelectionDAG &DAG) const;
     192             : 
     193             :   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
     194             :   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
     195             :   void ReplaceNodeResults(SDNode * N,
     196             :                           SmallVectorImpl<SDValue> &Results,
     197             :                           SelectionDAG &DAG) const override;
     198             : 
     199             :   SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
     200             :                                SDValue RHS, SDValue True, SDValue False,
     201             :                                SDValue CC, DAGCombinerInfo &DCI) const;
     202             : 
     203             :   const char* getTargetNodeName(unsigned Opcode) const override;
     204             : 
     205             :   // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection
     206             :   // for AMDGPU.
     207             :   // A commit ( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319036
     208             :   // 91177308-0d34-0410-b5e6-96231b3b80d8 ) turned on
     209             :   // MergeConsecutiveStores() before Instruction Selection for all targets.
     210             :   // Enough AMDGPU compiles go into an infinite loop ( MergeConsecutiveStores()
     211             :   // merges two stores; LegalizeStoreOps() un-merges; MergeConsecutiveStores()
     212             :   // re-merges, etc. ) to warrant turning it off for now.
     213      253338 :   bool mergeStoresAfterLegalization() const override { return false; }
     214             : 
     215          33 :   bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
     216          33 :     return true;
     217             :   }
     218             :   SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
     219             :                            int &RefinementSteps, bool &UseOneConstNR,
     220             :                            bool Reciprocal) const override;
     221             :   SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
     222             :                            int &RefinementSteps) const override;
     223             : 
     224             :   virtual SDNode *PostISelFolding(MachineSDNode *N,
     225             :                                   SelectionDAG &DAG) const = 0;
     226             : 
     227             :   /// \brief Determine which of the bits specified in \p Mask are known to be
     228             :   /// either zero or one and return them in the \p KnownZero and \p KnownOne
     229             :   /// bitsets.
     230             :   void computeKnownBitsForTargetNode(const SDValue Op,
     231             :                                      KnownBits &Known,
     232             :                                      const APInt &DemandedElts,
     233             :                                      const SelectionDAG &DAG,
     234             :                                      unsigned Depth = 0) const override;
     235             : 
     236             :   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
     237             :                                            const SelectionDAG &DAG,
     238             :                                            unsigned Depth = 0) const override;
     239             : 
     240             :   /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
     241             :   /// MachineFunction.
     242             :   ///
     243             :   /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
     244             :   /// a copy from the register.
     245             :   SDValue CreateLiveInRegister(SelectionDAG &DAG,
     246             :                                const TargetRegisterClass *RC,
     247             :                                unsigned Reg, EVT VT,
     248             :                                const SDLoc &SL,
     249             :                                bool RawReg = false) const;
     250        1386 :   SDValue CreateLiveInRegister(SelectionDAG &DAG,
     251             :                                const TargetRegisterClass *RC,
     252             :                                unsigned Reg, EVT VT) const {
     253        2772 :     return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
     254             :   }
     255             : 
     256             :   // Returns the raw live in register rather than a copy from it.
     257         236 :   SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
     258             :                                   const TargetRegisterClass *RC,
     259             :                                   unsigned Reg, EVT VT) const {
     260         472 :     return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
     261             :   }
     262             : 
     263             :   /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
     264             :   /// slot rather than passed in a register.
     265             :   SDValue loadStackInputValue(SelectionDAG &DAG,
     266             :                               EVT VT,
     267             :                               const SDLoc &SL,
     268             :                               int64_t Offset) const;
     269             : 
     270             :   SDValue storeStackInputValue(SelectionDAG &DAG,
     271             :                                const SDLoc &SL,
     272             :                                SDValue Chain,
     273             :                                SDValue StackPtr,
     274             :                                SDValue ArgVal,
     275             :                                int64_t Offset) const;
     276             : 
     277             :   SDValue loadInputValue(SelectionDAG &DAG,
     278             :                          const TargetRegisterClass *RC,
     279             :                          EVT VT, const SDLoc &SL,
     280             :                          const ArgDescriptor &Arg) const;
     281             : 
     282             :   enum ImplicitParameter {
     283             :     FIRST_IMPLICIT,
     284             :     GRID_DIM = FIRST_IMPLICIT,
     285             :     GRID_OFFSET,
     286             :   };
     287             : 
     288             :   /// \brief Helper function that returns the byte offset of the given
     289             :   /// type of implicit parameter.
     290             :   uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
     291             :                                       const ImplicitParameter Param) const;
     292             : 
     293             :   AMDGPUAS getAMDGPUAS() const {
     294        2044 :     return AMDGPUASI;
     295             :   }
     296             : 
     297         150 :   MVT getFenceOperandTy(const DataLayout &DL) const override {
     298         150 :     return MVT::i32;
     299             :   }
     300             : };
     301             : 
     302             : namespace AMDGPUISD {
     303             : 
     304             : enum NodeType : unsigned {
     305             :   // AMDIL ISD Opcodes
     306             :   FIRST_NUMBER = ISD::BUILTIN_OP_END,
     307             :   UMUL,        // 32bit unsigned multiplication
     308             :   BRANCH_COND,
     309             :   // End AMDIL ISD Opcodes
     310             : 
     311             :   // Function call.
     312             :   CALL,
     313             :   TC_RETURN,
     314             :   TRAP,
     315             : 
     316             :   // Masked control flow nodes.
     317             :   IF,
     318             :   ELSE,
     319             :   LOOP,
     320             : 
     321             :   // A uniform kernel return that terminates the wavefront.
     322             :   ENDPGM,
     323             : 
     324             :   // Return to a shader part's epilog code.
     325             :   RETURN_TO_EPILOG,
     326             : 
     327             :   // Return with values from a non-entry function.
     328             :   RET_FLAG,
     329             : 
     330             :   DWORDADDR,
     331             :   FRACT,
     332             : 
     333             :   /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
     334             :   /// modifier behavior with dx10_enable.
     335             :   CLAMP,
     336             : 
     337             :   // This is SETCC with the full mask result which is used for a compare with a
     338             :   // result bit per item in the wavefront.
     339             :   SETCC,
     340             :   SETREG,
     341             :   // FP ops with input and output chain.
     342             :   FMA_W_CHAIN,
     343             :   FMUL_W_CHAIN,
     344             : 
     345             :   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
     346             :   // Denormals handled on some parts.
     347             :   COS_HW,
     348             :   SIN_HW,
     349             :   FMAX_LEGACY,
     350             :   FMIN_LEGACY,
     351             :   FMAX3,
     352             :   SMAX3,
     353             :   UMAX3,
     354             :   FMIN3,
     355             :   SMIN3,
     356             :   UMIN3,
     357             :   FMED3,
     358             :   SMED3,
     359             :   UMED3,
     360             :   URECIP,
     361             :   DIV_SCALE,
     362             :   DIV_FMAS,
     363             :   DIV_FIXUP,
     364             :   // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
     365             :   // treated as an illegal operation.
     366             :   FMAD_FTZ,
     367             :   TRIG_PREOP, // 1 ULP max error for f64
     368             : 
     369             :   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
     370             :   //            For f64, max error 2^29 ULP, handles denormals.
     371             :   RCP,
     372             :   RSQ,
     373             :   RCP_LEGACY,
     374             :   RSQ_LEGACY,
     375             :   FMUL_LEGACY,
     376             :   RSQ_CLAMP,
     377             :   LDEXP,
     378             :   FP_CLASS,
     379             :   DOT4,
     380             :   CARRY,
     381             :   BORROW,
     382             :   BFE_U32, // Extract range of bits with zero extension to 32-bits.
     383             :   BFE_I32, // Extract range of bits with sign extension to 32-bits.
     384             :   BFI, // (src0 & src1) | (~src0 & src2)
     385             :   BFM, // Insert a range of bits into a 32-bit word.
     386             :   FFBH_U32, // ctlz with -1 if input is zero.
     387             :   FFBH_I32,
     388             :   FFBL_B32, // cttz with -1 if input is zero.
     389             :   MUL_U24,
     390             :   MUL_I24,
     391             :   MULHI_U24,
     392             :   MULHI_I24,
     393             :   MAD_U24,
     394             :   MAD_I24,
     395             :   MAD_U64_U32,
     396             :   MAD_I64_I32,
     397             :   MUL_LOHI_I24,
     398             :   MUL_LOHI_U24,
     399             :   TEXTURE_FETCH,
     400             :   EXPORT, // exp on SI+
     401             :   EXPORT_DONE, // exp on SI+ with done bit set
     402             :   R600_EXPORT,
     403             :   CONST_ADDRESS,
     404             :   REGISTER_LOAD,
     405             :   REGISTER_STORE,
     406             :   SAMPLE,
     407             :   SAMPLEB,
     408             :   SAMPLED,
     409             :   SAMPLEL,
     410             : 
     411             :   // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
     412             :   CVT_F32_UBYTE0,
     413             :   CVT_F32_UBYTE1,
     414             :   CVT_F32_UBYTE2,
     415             :   CVT_F32_UBYTE3,
     416             : 
     417             :   // Convert two float 32 numbers into a single register holding two packed f16
     418             :   // with round to zero.
     419             :   CVT_PKRTZ_F16_F32,
     420             :   CVT_PKNORM_I16_F32,
     421             :   CVT_PKNORM_U16_F32,
     422             :   CVT_PK_I16_I32,
     423             :   CVT_PK_U16_U32,
     424             : 
     425             :   // Same as the standard node, except the high bits of the resulting integer
     426             :   // are known 0.
     427             :   FP_TO_FP16,
     428             : 
     429             :   // Wrapper around fp16 results that are known to zero the high bits.
     430             :   FP16_ZEXT,
     431             : 
     432             :   /// This node is for VLIW targets and it is used to represent a vector
     433             :   /// that is stored in consecutive registers with the same channel.
     434             :   /// For example:
     435             :   ///   |X  |Y|Z|W|
     436             :   /// T0|v.x| | | |
     437             :   /// T1|v.y| | | |
     438             :   /// T2|v.z| | | |
     439             :   /// T3|v.w| | | |
     440             :   BUILD_VERTICAL_VECTOR,
     441             :   /// Pointer to the start of the shader's constant data.
     442             :   CONST_DATA_PTR,
     443             :   INIT_EXEC,
     444             :   INIT_EXEC_FROM_INPUT,
     445             :   SENDMSG,
     446             :   SENDMSGHALT,
     447             :   INTERP_MOV,
     448             :   INTERP_P1,
     449             :   INTERP_P2,
     450             :   PC_ADD_REL_OFFSET,
     451             :   KILL,
     452             :   DUMMY_CHAIN,
     453             :   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
     454             :   STORE_MSKOR,
     455             :   LOAD_CONSTANT,
     456             :   TBUFFER_STORE_FORMAT,
     457             :   TBUFFER_STORE_FORMAT_X3,
     458             :   TBUFFER_STORE_FORMAT_D16,
     459             :   TBUFFER_LOAD_FORMAT,
     460             :   TBUFFER_LOAD_FORMAT_D16,
     461             :   ATOMIC_CMP_SWAP,
     462             :   ATOMIC_INC,
     463             :   ATOMIC_DEC,
     464             :   ATOMIC_LOAD_FADD,
     465             :   ATOMIC_LOAD_FMIN,
     466             :   ATOMIC_LOAD_FMAX,
     467             :   BUFFER_LOAD,
     468             :   BUFFER_LOAD_FORMAT,
     469             :   BUFFER_LOAD_FORMAT_D16,
     470             :   BUFFER_STORE,
     471             :   BUFFER_STORE_FORMAT,
     472             :   BUFFER_STORE_FORMAT_D16,
     473             :   BUFFER_ATOMIC_SWAP,
     474             :   BUFFER_ATOMIC_ADD,
     475             :   BUFFER_ATOMIC_SUB,
     476             :   BUFFER_ATOMIC_SMIN,
     477             :   BUFFER_ATOMIC_UMIN,
     478             :   BUFFER_ATOMIC_SMAX,
     479             :   BUFFER_ATOMIC_UMAX,
     480             :   BUFFER_ATOMIC_AND,
     481             :   BUFFER_ATOMIC_OR,
     482             :   BUFFER_ATOMIC_XOR,
     483             :   BUFFER_ATOMIC_CMPSWAP,
     484             :   IMAGE_LOAD,
     485             :   IMAGE_LOAD_MIP,
     486             :   IMAGE_STORE,
     487             :   IMAGE_STORE_MIP,
     488             : 
     489             :   // Basic sample.
     490             :   IMAGE_SAMPLE,
     491             :   IMAGE_SAMPLE_CL,
     492             :   IMAGE_SAMPLE_D,
     493             :   IMAGE_SAMPLE_D_CL,
     494             :   IMAGE_SAMPLE_L,
     495             :   IMAGE_SAMPLE_B,
     496             :   IMAGE_SAMPLE_B_CL,
     497             :   IMAGE_SAMPLE_LZ,
     498             :   IMAGE_SAMPLE_CD,
     499             :   IMAGE_SAMPLE_CD_CL,
     500             : 
     501             :   // Sample with comparison.
     502             :   IMAGE_SAMPLE_C,
     503             :   IMAGE_SAMPLE_C_CL,
     504             :   IMAGE_SAMPLE_C_D,
     505             :   IMAGE_SAMPLE_C_D_CL,
     506             :   IMAGE_SAMPLE_C_L,
     507             :   IMAGE_SAMPLE_C_B,
     508             :   IMAGE_SAMPLE_C_B_CL,
     509             :   IMAGE_SAMPLE_C_LZ,
     510             :   IMAGE_SAMPLE_C_CD,
     511             :   IMAGE_SAMPLE_C_CD_CL,
     512             : 
     513             :   // Sample with offsets.
     514             :   IMAGE_SAMPLE_O,
     515             :   IMAGE_SAMPLE_CL_O,
     516             :   IMAGE_SAMPLE_D_O,
     517             :   IMAGE_SAMPLE_D_CL_O,
     518             :   IMAGE_SAMPLE_L_O,
     519             :   IMAGE_SAMPLE_B_O,
     520             :   IMAGE_SAMPLE_B_CL_O,
     521             :   IMAGE_SAMPLE_LZ_O,
     522             :   IMAGE_SAMPLE_CD_O,
     523             :   IMAGE_SAMPLE_CD_CL_O,
     524             : 
     525             :   // Sample with comparison and offsets.
     526             :   IMAGE_SAMPLE_C_O,
     527             :   IMAGE_SAMPLE_C_CL_O,
     528             :   IMAGE_SAMPLE_C_D_O,
     529             :   IMAGE_SAMPLE_C_D_CL_O,
     530             :   IMAGE_SAMPLE_C_L_O,
     531             :   IMAGE_SAMPLE_C_B_O,
     532             :   IMAGE_SAMPLE_C_B_CL_O,
     533             :   IMAGE_SAMPLE_C_LZ_O,
     534             :   IMAGE_SAMPLE_C_CD_O,
     535             :   IMAGE_SAMPLE_C_CD_CL_O,
     536             : 
     537             :   // Basic gather4.
     538             :   IMAGE_GATHER4,
     539             :   IMAGE_GATHER4_CL,
     540             :   IMAGE_GATHER4_L,
     541             :   IMAGE_GATHER4_B,
     542             :   IMAGE_GATHER4_B_CL,
     543             :   IMAGE_GATHER4_LZ,
     544             : 
     545             :   // Gather4 with comparison.
     546             :   IMAGE_GATHER4_C,
     547             :   IMAGE_GATHER4_C_CL,
     548             :   IMAGE_GATHER4_C_L,
     549             :   IMAGE_GATHER4_C_B,
     550             :   IMAGE_GATHER4_C_B_CL,
     551             :   IMAGE_GATHER4_C_LZ,
     552             : 
     553             :   // Gather4 with offsets.
     554             :   IMAGE_GATHER4_O,
     555             :   IMAGE_GATHER4_CL_O,
     556             :   IMAGE_GATHER4_L_O,
     557             :   IMAGE_GATHER4_B_O,
     558             :   IMAGE_GATHER4_B_CL_O,
     559             :   IMAGE_GATHER4_LZ_O,
     560             : 
     561             :   // Gather4 with comparison and offsets.
     562             :   IMAGE_GATHER4_C_O,
     563             :   IMAGE_GATHER4_C_CL_O,
     564             :   IMAGE_GATHER4_C_L_O,
     565             :   IMAGE_GATHER4_C_B_O,
     566             :   IMAGE_GATHER4_C_B_CL_O,
     567             :   IMAGE_GATHER4_C_LZ_O,
     568             : 
     569             :   LAST_AMDGPU_ISD_NUMBER
     570             : };
     571             : 
     572             : 
     573             : } // End namespace AMDGPUISD
     574             : 
     575             : } // End namespace llvm
     576             : 
     577             : #endif

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