LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - AMDGPUInstrInfo.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 1 1 100.0 %
Date: 2017-09-14 15:23:50 Functions: 0 2 0.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// \brief Contains the definition of a TargetInstrInfo class that is common
      12             : /// to all AMD GPUs.
      13             : //
      14             : //===----------------------------------------------------------------------===//
      15             : 
      16             : #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
      17             : #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
      18             : 
      19             : #include "AMDGPU.h"
      20             : #include "Utils/AMDGPUBaseInfo.h"
      21             : #include "llvm/Target/TargetInstrInfo.h"
      22             : 
      23             : #define GET_INSTRINFO_HEADER
      24             : #include "AMDGPUGenInstrInfo.inc"
      25             : 
      26             : namespace llvm {
      27             : 
      28             : class AMDGPUSubtarget;
      29             : class MachineFunction;
      30             : class MachineInstr;
      31             : class MachineInstrBuilder;
      32             : 
      33        4080 : class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
      34             : private:
      35             :   const AMDGPUSubtarget &ST;
      36             : 
      37             :   virtual void anchor();
      38             : protected:
      39             :   AMDGPUAS AMDGPUASI;
      40             : 
      41             : public:
      42             :   explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st);
      43             : 
      44             :   bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
      45             :                                int64_t Offset1, int64_t Offset2,
      46             :                                unsigned NumLoads) const override;
      47             : 
      48             :   /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
      49             :   /// Return -1 if the target-specific opcode for the pseudo instruction does
      50             :   /// not exist. If Opcode is not a pseudo instruction, this is identity.
      51             :   int pseudoToMCOpcode(int Opcode) const;
      52             : 
      53             :   /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the
      54             :   /// equivalent opcode that writes \p Channels Channels.
      55             :   int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const;
      56             : };
      57             : } // End llvm namespace
      58             : 
      59             : #endif

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