LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - AMDGPUInstructionSelector.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 3 3 100.0 %
Date: 2018-06-17 00:07:59 Functions: 4 5 80.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : /// \file
      10             : /// This file declares the targeting of the InstructionSelector class for
      11             : /// AMDGPU.
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
      15             : #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
      16             : 
      17             : #include "AMDGPU.h"
      18             : #include "llvm/ADT/ArrayRef.h"
      19             : #include "llvm/ADT/SmallVector.h"
      20             : #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
      21             : 
      22             : namespace {
      23             : #define GET_GLOBALISEL_PREDICATE_BITSET
      24             : #include "AMDGPUGenGlobalISel.inc"
      25             : #undef GET_GLOBALISEL_PREDICATE_BITSET
      26             : }
      27             : 
      28             : namespace llvm {
      29             : 
      30             : class AMDGPUInstrInfo;
      31             : class AMDGPURegisterBankInfo;
      32             : class AMDGPUSubtarget;
      33             : class MachineInstr;
      34             : class MachineOperand;
      35             : class MachineRegisterInfo;
      36             : class SIInstrInfo;
      37             : class SIRegisterInfo;
      38             : class SISubtarget;
      39             : 
      40        6699 : class AMDGPUInstructionSelector : public InstructionSelector {
      41             : public:
      42             :   AMDGPUInstructionSelector(const SISubtarget &STI,
      43             :                             const AMDGPURegisterBankInfo &RBI,
      44             :                             const AMDGPUTargetMachine &TM);
      45             : 
      46             :   bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
      47             :   static const char *getName();
      48             : 
      49             : private:
      50         378 :   struct GEPInfo {
      51             :     const MachineInstr &GEP;
      52             :     SmallVector<unsigned, 2> SgprParts;
      53             :     SmallVector<unsigned, 2> VgprParts;
      54             :     int64_t Imm;
      55         126 :     GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
      56             :   };
      57             : 
      58             :   /// tblgen-erated 'select' implementation.
      59             :   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
      60             : 
      61             :   MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const;
      62             :   bool selectCOPY(MachineInstr &I) const;
      63             :   bool selectG_CONSTANT(MachineInstr &I) const;
      64             :   bool selectG_ADD(MachineInstr &I) const;
      65             :   bool selectG_GEP(MachineInstr &I) const;
      66             :   bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
      67             :   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
      68             :   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
      69             :                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
      70             :   bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
      71             :   bool selectG_LOAD(MachineInstr &I) const;
      72             :   bool selectG_STORE(MachineInstr &I) const;
      73             : 
      74             :   InstructionSelector::ComplexRendererFns
      75             :   selectVSRC0(MachineOperand &Root) const;
      76             : 
      77             :   InstructionSelector::ComplexRendererFns
      78             :   selectVOP3Mods0(MachineOperand &Root) const;
      79             :   InstructionSelector::ComplexRendererFns
      80             :   selectVOP3Mods(MachineOperand &Root) const;
      81             : 
      82             :   const SIInstrInfo &TII;
      83             :   const SIRegisterInfo &TRI;
      84             :   const AMDGPURegisterBankInfo &RBI;
      85             :   const AMDGPUTargetMachine &TM;
      86             :   const SISubtarget &STI;
      87             :   bool EnableLateStructurizeCFG;
      88             : #define GET_GLOBALISEL_PREDICATES_DECL
      89             : #include "AMDGPUGenGlobalISel.inc"
      90             : #undef GET_GLOBALISEL_PREDICATES_DECL
      91             : 
      92             : #define GET_GLOBALISEL_TEMPORARIES_DECL
      93             : #include "AMDGPUGenGlobalISel.inc"
      94             : #undef GET_GLOBALISEL_TEMPORARIES_DECL
      95             : 
      96             : protected:
      97             :   AMDGPUAS AMDGPUASI;
      98             : };
      99             : 
     100             : } // End llvm namespace.
     101             : #endif

Generated by: LCOV version 1.13