LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - AMDGPUInstructionSelector.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 3 3 100.0 %
Date: 2017-09-14 15:23:50 Functions: 3 5 60.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : /// \file
      10             : /// This file declares the targeting of the InstructionSelector class for
      11             : /// AMDGPU.
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
      15             : #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
      16             : 
      17             : #include "AMDGPU.h"
      18             : #include "llvm/ADT/ArrayRef.h"
      19             : #include "llvm/ADT/SmallVector.h"
      20             : #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
      21             : 
      22             : namespace llvm {
      23             : 
      24             : class AMDGPUInstrInfo;
      25             : class AMDGPURegisterBankInfo;
      26             : class MachineInstr;
      27             : class MachineOperand;
      28             : class MachineRegisterInfo;
      29             : class SIInstrInfo;
      30             : class SIRegisterInfo;
      31             : class SISubtarget;
      32             : 
      33        1788 : class AMDGPUInstructionSelector : public InstructionSelector {
      34             : public:
      35             :   AMDGPUInstructionSelector(const SISubtarget &STI,
      36             :                             const AMDGPURegisterBankInfo &RBI);
      37             : 
      38             :   bool select(MachineInstr &I) const override;
      39             : private:
      40         567 :   struct GEPInfo {
      41             :     const MachineInstr &GEP;
      42             :     SmallVector<unsigned, 2> SgprParts;
      43             :     SmallVector<unsigned, 2> VgprParts;
      44             :     int64_t Imm;
      45         189 :     GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
      46             :   };
      47             : 
      48             :   MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const;
      49             :   bool selectG_CONSTANT(MachineInstr &I) const;
      50             :   bool selectG_ADD(MachineInstr &I) const;
      51             :   bool selectG_GEP(MachineInstr &I) const;
      52             :   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
      53             :   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
      54             :                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
      55             :   bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
      56             :   bool selectG_LOAD(MachineInstr &I) const;
      57             :   bool selectG_STORE(MachineInstr &I) const;
      58             : 
      59             :   const SIInstrInfo &TII;
      60             :   const SIRegisterInfo &TRI;
      61             :   const AMDGPURegisterBankInfo &RBI;
      62             : protected:
      63             :   AMDGPUAS AMDGPUASI;
      64             : };
      65             : 
      66             : } // End llvm namespace.
      67             : #endif

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