LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - AMDGPULegalizerInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 39 39 100.0 %
Date: 2017-09-14 15:23:50 Functions: 1 1 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- AMDGPULegalizerInfo.cpp -----------------------------------*- C++ -*-==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : /// \file
      10             : /// This file implements the targeting of the Machinelegalizer class for
      11             : /// AMDGPU.
      12             : /// \todo This should be generated by TableGen.
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "AMDGPULegalizerInfo.h"
      16             : #include "llvm/CodeGen/ValueTypes.h"
      17             : #include "llvm/IR/DerivedTypes.h"
      18             : #include "llvm/IR/Type.h"
      19             : #include "llvm/Support/Debug.h"
      20             : #include "llvm/Target/TargetOpcodes.h"
      21             : 
      22             : using namespace llvm;
      23             : 
      24        1796 : AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
      25             :   using namespace TargetOpcode;
      26             : 
      27        1796 :   const LLT S1= LLT::scalar(1);
      28        1796 :   const LLT V2S16 = LLT::vector(2, 16);
      29        1796 :   const LLT S32 = LLT::scalar(32);
      30        1796 :   const LLT S64 = LLT::scalar(64);
      31        1796 :   const LLT P1 = LLT::pointer(1, 64);
      32        1796 :   const LLT P2 = LLT::pointer(2, 64);
      33             : 
      34        3592 :   setAction({G_ADD, S32}, Legal);
      35        3592 :   setAction({G_AND, S32}, Legal);
      36             : 
      37        3592 :   setAction({G_BITCAST, V2S16}, Legal);
      38        3592 :   setAction({G_BITCAST, 1, S32}, Legal);
      39             : 
      40        3592 :   setAction({G_BITCAST, S32}, Legal);
      41        3592 :   setAction({G_BITCAST, 1, V2S16}, Legal);
      42             : 
      43             :   // FIXME: i1 operands to intrinsics should always be legal, but other i1
      44             :   // values may not be legal.  We need to figure out how to distinguish
      45             :   // between these two scenarios.
      46        3592 :   setAction({G_CONSTANT, S1}, Legal);
      47        3592 :   setAction({G_CONSTANT, S32}, Legal);
      48        3592 :   setAction({G_CONSTANT, S64}, Legal);
      49             : 
      50        3592 :   setAction({G_FCONSTANT, S32}, Legal);
      51             : 
      52        3592 :   setAction({G_FMUL, S32}, Legal);
      53             : 
      54        3592 :   setAction({G_GEP, P1}, Legal);
      55        3592 :   setAction({G_GEP, P2}, Legal);
      56        3592 :   setAction({G_GEP, 1, S64}, Legal);
      57             : 
      58        3592 :   setAction({G_ICMP, S1}, Legal);
      59        3592 :   setAction({G_ICMP, 1, S32}, Legal);
      60             : 
      61        3592 :   setAction({G_LOAD, P1}, Legal);
      62        3592 :   setAction({G_LOAD, P2}, Legal);
      63        3592 :   setAction({G_LOAD, S32}, Legal);
      64        3592 :   setAction({G_LOAD, 1, P1}, Legal);
      65        3592 :   setAction({G_LOAD, 1, P2}, Legal);
      66             : 
      67        3592 :   setAction({G_OR, S32}, Legal);
      68             : 
      69        3592 :   setAction({G_SELECT, S32}, Legal);
      70        3592 :   setAction({G_SELECT, 1, S1}, Legal);
      71             : 
      72        3592 :   setAction({G_SHL, S32}, Legal);
      73             : 
      74        3592 :   setAction({G_STORE, S32}, Legal);
      75        3592 :   setAction({G_STORE, 1, P1}, Legal);
      76             : 
      77             :   // FIXME: When RegBankSelect inserts copies, it will only create new
      78             :   // registers with scalar types.  This means we can end up with
      79             :   // G_LOAD/G_STORE/G_GEP instruction with scalar types for their pointer
      80             :   // operands.  In assert builds, the instruction selector will assert
      81             :   // if it sees a generic instruction which isn't legal, so we need to
      82             :   // tell it that scalar types are legal for pointer operands
      83        3592 :   setAction({G_GEP, S64}, Legal);
      84        3592 :   setAction({G_LOAD, 1, S64}, Legal);
      85        3592 :   setAction({G_STORE, 1, S64}, Legal);
      86             : 
      87        1796 :   computeTables();
      88        1796 : }

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