LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - AMDGPUMCInstLower.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 109 118 92.4 %
Date: 2018-02-23 15:42:53 Functions: 7 7 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : //
      15             : 
      16             : #include "AMDGPUMCInstLower.h"
      17             : #include "AMDGPUAsmPrinter.h"
      18             : #include "AMDGPUSubtarget.h"
      19             : #include "AMDGPUTargetMachine.h"
      20             : #include "InstPrinter/AMDGPUInstPrinter.h"
      21             : #include "SIInstrInfo.h"
      22             : #include "llvm/CodeGen/MachineBasicBlock.h"
      23             : #include "llvm/CodeGen/MachineInstr.h"
      24             : #include "llvm/IR/Constants.h"
      25             : #include "llvm/IR/Function.h"
      26             : #include "llvm/IR/GlobalVariable.h"
      27             : #include "llvm/MC/MCCodeEmitter.h"
      28             : #include "llvm/MC/MCContext.h"
      29             : #include "llvm/MC/MCExpr.h"
      30             : #include "llvm/MC/MCInst.h"
      31             : #include "llvm/MC/MCObjectStreamer.h"
      32             : #include "llvm/MC/MCStreamer.h"
      33             : #include "llvm/Support/ErrorHandling.h"
      34             : #include "llvm/Support/Format.h"
      35             : #include <algorithm>
      36             : 
      37             : using namespace llvm;
      38             : 
      39             : #include "AMDGPUGenMCPseudoLowering.inc"
      40             : 
      41      399084 : AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st,
      42      399084 :                                      const AsmPrinter &ap):
      43      399084 :   Ctx(ctx), ST(st), AP(ap) { }
      44             : 
      45             : static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) {
      46             :   switch (MOFlags) {
      47             :   default:
      48             :     return MCSymbolRefExpr::VK_None;
      49             :   case SIInstrInfo::MO_GOTPCREL:
      50             :     return MCSymbolRefExpr::VK_GOTPCREL;
      51             :   case SIInstrInfo::MO_GOTPCREL32_LO:
      52             :     return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_LO;
      53             :   case SIInstrInfo::MO_GOTPCREL32_HI:
      54             :     return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_HI;
      55             :   case SIInstrInfo::MO_REL32_LO:
      56             :     return MCSymbolRefExpr::VK_AMDGPU_REL32_LO;
      57             :   case SIInstrInfo::MO_REL32_HI:
      58             :     return MCSymbolRefExpr::VK_AMDGPU_REL32_HI;
      59             :   }
      60             : }
      61             : 
      62          29 : const MCExpr *AMDGPUMCInstLower::getLongBranchBlockExpr(
      63             :   const MachineBasicBlock &SrcBB,
      64             :   const MachineOperand &MO) const {
      65             :   const MCExpr *DestBBSym
      66          29 :     = MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx);
      67          29 :   const MCExpr *SrcBBSym = MCSymbolRefExpr::create(SrcBB.getSymbol(), Ctx);
      68             : 
      69             :   assert(SrcBB.front().getOpcode() == AMDGPU::S_GETPC_B64 &&
      70             :          ST.getInstrInfo()->get(AMDGPU::S_GETPC_B64).Size == 4);
      71             : 
      72             :   // s_getpc_b64 returns the address of next instruction.
      73          29 :   const MCConstantExpr *One = MCConstantExpr::create(4, Ctx);
      74          29 :   SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx);
      75             : 
      76          29 :   if (MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_FORWARD)
      77          42 :     return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx);
      78             : 
      79             :   assert(MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_BACKWARD);
      80          16 :   return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx);
      81             : }
      82             : 
      83     1979375 : bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
      84             :                                      MCOperand &MCOp) const {
      85     1979375 :   switch (MO.getType()) {
      86           0 :   default:
      87           0 :     llvm_unreachable("unknown operand type");
      88     1230644 :   case MachineOperand::MO_Immediate:
      89     2461288 :     MCOp = MCOperand::createImm(MO.getImm());
      90     1230644 :     return true;
      91      745875 :   case MachineOperand::MO_Register:
      92     1491750 :     MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
      93      745875 :     return true;
      94             :   case MachineOperand::MO_MachineBasicBlock: {
      95         873 :     if (MO.getTargetFlags() != 0) {
      96          29 :       MCOp = MCOperand::createExpr(
      97          29 :         getLongBranchBlockExpr(*MO.getParent()->getParent(), MO));
      98             :     } else {
      99         844 :       MCOp = MCOperand::createExpr(
     100         844 :         MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx));
     101             :     }
     102             : 
     103             :     return true;
     104             :   }
     105        1047 :   case MachineOperand::MO_GlobalAddress: {
     106        1047 :     const GlobalValue *GV = MO.getGlobal();
     107             :     SmallString<128> SymbolName;
     108        1047 :     AP.getNameWithPrefix(SymbolName, GV);
     109        2094 :     MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
     110             :     const MCExpr *SymExpr =
     111        2094 :       MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx);
     112        1047 :     const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr,
     113        2094 :       MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
     114        1047 :     MCOp = MCOperand::createExpr(Expr);
     115             :     return true;
     116             :   }
     117         936 :   case MachineOperand::MO_ExternalSymbol: {
     118        1872 :     MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
     119             :     Sym->setExternal(true);
     120         936 :     const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
     121         936 :     MCOp = MCOperand::createExpr(Expr);
     122         936 :     return true;
     123             :   }
     124             :   case MachineOperand::MO_RegisterMask:
     125             :     // Regmasks are like implicit defs.
     126             :     return false;
     127             :   }
     128             : }
     129             : 
     130      397708 : void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
     131      397708 :   unsigned Opcode = MI->getOpcode();
     132      397708 :   const auto *TII = ST.getInstrInfo();
     133             : 
     134             :   // FIXME: Should be able to handle this with emitPseudoExpansionLowering. We
     135             :   // need to select it to the subtarget specific version, and there's no way to
     136             :   // do that with a single pseudo source operation.
     137      397708 :   if (Opcode == AMDGPU::S_SETPC_B64_return)
     138             :     Opcode = AMDGPU::S_SETPC_B64;
     139      396578 :   else if (Opcode == AMDGPU::SI_CALL) {
     140             :     // SI_CALL is just S_SWAPPC_B64 with an additional operand to track the
     141             :     // called function (which we need to remove here).
     142         439 :     OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
     143             :     MCOperand Dest, Src;
     144         439 :     lowerOperand(MI->getOperand(0), Dest);
     145         878 :     lowerOperand(MI->getOperand(1), Src);
     146             :     OutMI.addOperand(Dest);
     147             :     OutMI.addOperand(Src);
     148             :     return;
     149      396139 :   } else if (Opcode == AMDGPU::SI_TCRETURN) {
     150             :     // TODO: How to use branch immediate and avoid register+add?
     151             :     Opcode = AMDGPU::S_SETPC_B64;
     152             :   }
     153             : 
     154      397269 :   int MCOpcode = TII->pseudoToMCOpcode(Opcode);
     155      397269 :   if (MCOpcode == -1) {
     156           0 :     LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
     157           0 :     C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
     158           0 :                 "a target-specific version: " + Twine(MI->getOpcode()));
     159             :   }
     160             : 
     161      397269 :   OutMI.setOpcode(MCOpcode);
     162             : 
     163     4354167 :   for (const MachineOperand &MO : MI->explicit_operands()) {
     164             :     MCOperand MCOp;
     165     1978449 :     lowerOperand(MO, MCOp);
     166             :     OutMI.addOperand(MCOp);
     167             :   }
     168             : }
     169             : 
     170          48 : bool AMDGPUAsmPrinter::lowerOperand(const MachineOperand &MO,
     171             :                                     MCOperand &MCOp) const {
     172          48 :   const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
     173          48 :   AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
     174          48 :   return MCInstLowering.lowerOperand(MO, MCOp);
     175             : }
     176             : 
     177          56 : const MCExpr *AMDGPUAsmPrinter::lowerConstant(const Constant *CV) {
     178             :   // TargetMachine does not support llvm-style cast. Use C++-style cast.
     179             :   // This is safe since TM is always of type AMDGPUTargetMachine or its
     180             :   // derived class.
     181          56 :   auto *AT = static_cast<AMDGPUTargetMachine*>(&TM);
     182             :   auto *CE = dyn_cast<ConstantExpr>(CV);
     183             : 
     184             :   // Lower null pointers in private and local address space.
     185             :   // Clang generates addrspacecast for null pointers in private and local
     186             :   // address space, which needs to be lowered.
     187          56 :   if (CE && CE->getOpcode() == Instruction::AddrSpaceCast) {
     188             :     auto Op = CE->getOperand(0);
     189          56 :     auto SrcAddr = Op->getType()->getPointerAddressSpace();
     190          56 :     if (Op->isNullValue() && AT->getNullPointerValue(SrcAddr) == 0) {
     191          56 :       auto DstAddr = CE->getType()->getPointerAddressSpace();
     192         112 :       return MCConstantExpr::create(AT->getNullPointerValue(DstAddr),
     193          56 :         OutContext);
     194             :     }
     195             :   }
     196           0 :   return AsmPrinter::lowerConstant(CV);
     197             : }
     198             : 
     199      399060 : void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     200      399060 :   if (emitPseudoExpansionLowering(*OutStreamer, MI))
     201         851 :     return;
     202             : 
     203      399036 :   const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
     204      399036 :   AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
     205             : 
     206      399036 :   StringRef Err;
     207      399036 :   if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
     208           0 :     LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
     209           0 :     C.emitError("Illegal instruction detected: " + Err);
     210           0 :     MI->print(errs());
     211             :   }
     212             : 
     213      399036 :   if (MI->isBundle()) {
     214         501 :     const MachineBasicBlock *MBB = MI->getParent();
     215         501 :     MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
     216        4008 :     while (I != MBB->instr_end() && I->isInsideBundle()) {
     217        1503 :       EmitInstruction(&*I);
     218             :       ++I;
     219             :     }
     220             :   } else {
     221             :     // We don't want SI_MASK_BRANCH/SI_RETURN_TO_EPILOG encoded. They are
     222             :     // placeholder terminator instructions and should only be printed as
     223             :     // comments.
     224      398535 :     if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
     225         391 :       if (isVerbose()) {
     226             :         SmallVector<char, 16> BBStr;
     227             :         raw_svector_ostream Str(BBStr);
     228             : 
     229         388 :         const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
     230             :         const MCSymbolRefExpr *Expr
     231         388 :           = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
     232         388 :         Expr->print(Str, MAI);
     233         776 :         OutStreamer->emitRawComment(Twine(" mask branch ") + BBStr);
     234             :       }
     235             : 
     236         827 :       return;
     237             :     }
     238             : 
     239      398144 :     if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
     240         409 :       if (isVerbose())
     241         818 :         OutStreamer->emitRawComment(" return to shader part epilog");
     242             :       return;
     243             :     }
     244             : 
     245      397735 :     if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
     246          13 :       if (isVerbose())
     247          26 :         OutStreamer->emitRawComment(" wave barrier");
     248             :       return;
     249             :     }
     250             : 
     251      397722 :     if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
     252          14 :       if (isVerbose())
     253          26 :         OutStreamer->emitRawComment(" divergent unreachable");
     254             :       return;
     255             :     }
     256             : 
     257             :     MCInst TmpInst;
     258      397708 :     MCInstLowering.lower(MI, TmpInst);
     259      397708 :     EmitToStreamer(*OutStreamer, TmpInst);
     260             : 
     261      397708 :     if (STI.dumpCode()) {
     262             :       // Disassemble instruction/operands to text.
     263          28 :       DisasmLines.resize(DisasmLines.size() + 1);
     264             :       std::string &DisasmLine = DisasmLines.back();
     265          14 :       raw_string_ostream DisasmStream(DisasmLine);
     266             : 
     267          14 :       AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(),
     268          14 :                                     *STI.getInstrInfo(),
     269          28 :                                     *STI.getRegisterInfo());
     270          14 :       InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI);
     271             : 
     272             :       // Disassemble instruction/operands to hex representation.
     273             :       SmallVector<MCFixup, 4> Fixups;
     274             :       SmallVector<char, 16> CodeBytes;
     275             :       raw_svector_ostream CodeStream(CodeBytes);
     276             : 
     277             :       auto &ObjStreamer = static_cast<MCObjectStreamer&>(*OutStreamer);
     278          14 :       MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
     279          14 :       InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups,
     280          14 :                                     MF->getSubtarget<MCSubtargetInfo>());
     281          28 :       HexLines.resize(HexLines.size() + 1);
     282             :       std::string &HexLine = HexLines.back();
     283          14 :       raw_string_ostream HexStream(HexLine);
     284             : 
     285          50 :       for (size_t i = 0; i < CodeBytes.size(); i += 4) {
     286          18 :         unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
     287          36 :         HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
     288             :       }
     289             : 
     290             :       DisasmStream.flush();
     291          28 :       DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
     292             :     }
     293             :   }
     294             : }

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