LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - AMDGPURegisterBankInfo.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 2 2 100.0 %
Date: 2017-09-14 15:23:50 Functions: 1 4 25.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : /// \file
      10             : /// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
      11             : /// \todo This should be generated by TableGen.
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
      15             : #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
      16             : 
      17             : #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
      18             : 
      19             : namespace llvm {
      20             : 
      21             : class SIRegisterInfo;
      22             : class TargetRegisterInfo;
      23             : 
      24             : namespace AMDGPU {
      25             : enum {
      26             :   SGPRRegBankID = 0,
      27             :   VGPRRegBankID = 1,
      28             :   NumRegisterBanks
      29             : };
      30             : } // End AMDGPU namespace.
      31             : 
      32             : /// This class provides the information for the target register banks.
      33        1788 : class AMDGPUGenRegisterBankInfo : public RegisterBankInfo {
      34             : 
      35             : protected:
      36             : 
      37             : #define GET_TARGET_REGBANK_CLASS
      38             : #include "AMDGPUGenRegisterBank.inc"
      39             : };
      40        3576 : class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
      41             :   const SIRegisterInfo *TRI;
      42             : 
      43             :   /// See RegisterBankInfo::applyMapping.
      44             :   void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
      45             : 
      46             :   const RegisterBankInfo::InstructionMapping &
      47             :   getInstrMappingForLoad(const MachineInstr &MI) const;
      48             : 
      49             : public:
      50             :   AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI);
      51             : 
      52             :   unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
      53             :                     unsigned Size) const override;
      54             : 
      55             :   const RegisterBank &
      56             :   getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
      57             : 
      58             :   InstructionMappings
      59             :   getInstrAlternativeMappings(const MachineInstr &MI) const override;
      60             : 
      61             :   const InstructionMapping &
      62             :   getInstrMapping(const MachineInstr &MI) const override;
      63             : };
      64             : } // End llvm namespace.
      65             : #endif

Generated by: LCOV version 1.13