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1 : //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : /// \file
10 : /// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
11 : /// \todo This should be generated by TableGen.
12 : //===----------------------------------------------------------------------===//
13 :
14 : #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
15 : #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
16 :
17 : #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
18 :
19 : #define GET_REGBANK_DECLARATIONS
20 : #include "AMDGPUGenRegisterBank.inc"
21 : #undef GET_REGBANK_DECLARATIONS
22 :
23 : namespace llvm {
24 :
25 : class SIRegisterInfo;
26 : class TargetRegisterInfo;
27 :
28 : /// This class provides the information for the target register banks.
29 2262 : class AMDGPUGenRegisterBankInfo : public RegisterBankInfo {
30 :
31 : protected:
32 :
33 : #define GET_TARGET_REGBANK_CLASS
34 : #include "AMDGPUGenRegisterBank.inc"
35 : };
36 4524 : class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
37 : const SIRegisterInfo *TRI;
38 :
39 : /// See RegisterBankInfo::applyMapping.
40 : void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
41 :
42 : const RegisterBankInfo::InstructionMapping &
43 : getInstrMappingForLoad(const MachineInstr &MI) const;
44 :
45 : unsigned getRegBankID(unsigned Reg, const MachineRegisterInfo &MRI,
46 : const TargetRegisterInfo &TRI,
47 : unsigned Default = AMDGPU::VGPRRegBankID) const;
48 :
49 : bool isSALUMapping(const MachineInstr &MI) const;
50 : const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const;
51 : const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const;
52 : public:
53 : AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI);
54 :
55 : unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
56 : unsigned Size) const override;
57 :
58 : const RegisterBank &
59 : getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
60 :
61 : InstructionMappings
62 : getInstrAlternativeMappings(const MachineInstr &MI) const override;
63 :
64 : const InstructionMapping &
65 : getInstrMapping(const MachineInstr &MI) const override;
66 : };
67 : } // End llvm namespace.
68 : #endif
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