LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - AMDGPURegisterInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 18 18 100.0 %
Date: 2018-06-17 00:07:59 Functions: 7 7 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// Parent TargetRegisterInfo class common to all hw codegen targets.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "AMDGPURegisterInfo.h"
      16             : #include "AMDGPUTargetMachine.h"
      17             : #include "SIMachineFunctionInfo.h"
      18             : #include "SIRegisterInfo.h"
      19             : #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
      20             : 
      21             : using namespace llvm;
      22             : 
      23        2527 : AMDGPURegisterInfo::AMDGPURegisterInfo() : AMDGPUGenRegisterInfo(0) {}
      24             : 
      25             : //===----------------------------------------------------------------------===//
      26             : // Function handling callbacks - Functions are a seldom used feature of GPUS, so
      27             : // they are not supported at this time.
      28             : //===----------------------------------------------------------------------===//
      29             : 
      30       69012 : unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) {
      31             :   static const unsigned SubRegs[] = {
      32             :     AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
      33             :     AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
      34             :     AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
      35             :     AMDGPU::sub15
      36             :   };
      37             : 
      38             :   assert(Channel < array_lengthof(SubRegs));
      39       69012 :   return SubRegs[Channel];
      40             : }
      41             : 
      42     1609084 : void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
      43     1609084 :   MCRegAliasIterator R(Reg, this, true);
      44             : 
      45    16645552 :   for (; R.isValid(); ++R)
      46             :     Reserved.set(*R);
      47     1609084 : }
      48             : 
      49             : #define GET_REGINFO_TARGET_DESC
      50             : #include "AMDGPUGenRegisterInfo.inc"
      51             : 
      52             : // Forced to be here by one .inc
      53      446680 : const MCPhysReg *SIRegisterInfo::getCalleeSavedRegs(
      54             :   const MachineFunction *MF) const {
      55      446680 :   CallingConv::ID CC = MF->getFunction().getCallingConv();
      56             :   switch (CC) {
      57             :   case CallingConv::C:
      58             :   case CallingConv::Fast:
      59             :   case CallingConv::Cold:
      60             :     return CSR_AMDGPU_HighRegs_SaveList;
      61      411394 :   default: {
      62             :     // Dummy to not crash RegisterClassInfo.
      63             :     static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
      64      411394 :     return &NoCalleeSavedReg;
      65             :   }
      66             :   }
      67             : }
      68             : 
      69             : const MCPhysReg *
      70        2760 : SIRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
      71        2760 :   return nullptr;
      72             : }
      73             : 
      74         530 : const uint32_t *SIRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
      75             :                                                      CallingConv::ID CC) const {
      76             :   switch (CC) {
      77             :   case CallingConv::C:
      78             :   case CallingConv::Fast:
      79             :   case CallingConv::Cold:
      80             :     return CSR_AMDGPU_HighRegs_RegMask;
      81           3 :   default:
      82           3 :     return nullptr;
      83             :   }
      84             : }
      85             : 
      86          79 : unsigned SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
      87             :   const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
      88          79 :   return FuncInfo->getFrameOffsetReg();
      89             : }

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