LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - AMDGPURegisterInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 18 18 100.0 %
Date: 2018-02-19 03:08:00 Functions: 7 7 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// \brief Parent TargetRegisterInfo class common to all hw codegen targets.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "AMDGPURegisterInfo.h"
      16             : #include "AMDGPUTargetMachine.h"
      17             : #include "SIRegisterInfo.h"
      18             : 
      19             : using namespace llvm;
      20             : 
      21        2328 : AMDGPURegisterInfo::AMDGPURegisterInfo() : AMDGPUGenRegisterInfo(0) {}
      22             : 
      23             : //===----------------------------------------------------------------------===//
      24             : // Function handling callbacks - Functions are a seldom used feature of GPUS, so
      25             : // they are not supported at this time.
      26             : //===----------------------------------------------------------------------===//
      27             : 
      28       63379 : unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const {
      29             :   static const unsigned SubRegs[] = {
      30             :     AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
      31             :     AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
      32             :     AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
      33             :     AMDGPU::sub15
      34             :   };
      35             : 
      36             :   assert(Channel < array_lengthof(SubRegs));
      37       63379 :   return SubRegs[Channel];
      38             : }
      39             : 
      40     1518740 : void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
      41     1518740 :   MCRegAliasIterator R(Reg, this, true);
      42             : 
      43    15455390 :   for (; R.isValid(); ++R)
      44             :     Reserved.set(*R);
      45     1518740 : }
      46             : 
      47             : #define GET_REGINFO_TARGET_DESC
      48             : #include "AMDGPUGenRegisterInfo.inc"
      49             : 
      50             : // Forced to be here by one .inc
      51      387681 : const MCPhysReg *SIRegisterInfo::getCalleeSavedRegs(
      52             :   const MachineFunction *MF) const {
      53      387681 :   CallingConv::ID CC = MF->getFunction().getCallingConv();
      54             :   switch (CC) {
      55             :   case CallingConv::C:
      56             :   case CallingConv::Fast:
      57             :   case CallingConv::Cold:
      58             :     return CSR_AMDGPU_HighRegs_SaveList;
      59      360496 :   default: {
      60             :     // Dummy to not crash RegisterClassInfo.
      61             :     static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
      62      360496 :     return &NoCalleeSavedReg;
      63             :   }
      64             :   }
      65             : }
      66             : 
      67             : const MCPhysReg *
      68        2296 : SIRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
      69        2296 :   return nullptr;
      70             : }
      71             : 
      72       16864 : const uint32_t *SIRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
      73             :                                                      CallingConv::ID CC) const {
      74             :   switch (CC) {
      75             :   case CallingConv::C:
      76             :   case CallingConv::Fast:
      77             :   case CallingConv::Cold:
      78             :     return CSR_AMDGPU_HighRegs_RegMask;
      79       15368 :   default:
      80       15368 :     return nullptr;
      81             :   }
      82             : }
      83             : 
      84         101 : unsigned SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
      85         101 :   return AMDGPU::NoRegister;
      86             : }

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