LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - AMDGPURegisterInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 20 20 100.0 %
Date: 2017-09-14 15:23:50 Functions: 8 8 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// \brief Parent TargetRegisterInfo class common to all hw codegen targets.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "AMDGPURegisterInfo.h"
      16             : #include "AMDGPUTargetMachine.h"
      17             : #include "SIRegisterInfo.h"
      18             : 
      19             : using namespace llvm;
      20             : 
      21        2049 : AMDGPURegisterInfo::AMDGPURegisterInfo() : AMDGPUGenRegisterInfo(0) {}
      22             : 
      23             : //===----------------------------------------------------------------------===//
      24             : // Function handling callbacks - Functions are a seldom used feature of GPUS, so
      25             : // they are not supported at this time.
      26             : //===----------------------------------------------------------------------===//
      27             : 
      28       63182 : unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const {
      29             :   static const unsigned SubRegs[] = {
      30             :     AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
      31             :     AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
      32             :     AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
      33             :     AMDGPU::sub15
      34             :   };
      35             : 
      36             :   assert(Channel < array_lengthof(SubRegs));
      37       63182 :   return SubRegs[Channel];
      38             : }
      39             : 
      40             : #define GET_REGINFO_TARGET_DESC
      41             : #include "AMDGPUGenRegisterInfo.inc"
      42             : 
      43             : // Forced to be here by one .inc
      44      331489 : const MCPhysReg *SIRegisterInfo::getCalleeSavedRegs(
      45             :   const MachineFunction *MF) const {
      46      662978 :   CallingConv::ID CC = MF->getFunction()->getCallingConv();
      47      331489 :   switch (CC) {
      48             :   case CallingConv::C:
      49             :   case CallingConv::Fast:
      50             :     return CSR_AMDGPU_HighRegs_SaveList;
      51      316578 :   default: {
      52             :     // Dummy to not crash RegisterClassInfo.
      53             :     static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
      54      316578 :     return &NoCalleeSavedReg;
      55             :   }
      56             :   }
      57             : }
      58             : 
      59             : const MCPhysReg *
      60        1282 : SIRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
      61             :   // FIXME
      62             :   static MCPhysReg Regs[2];
      63             : 
      64        1282 :   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
      65             :   assert(!MFI->isEntryFunction());
      66             : 
      67        1282 :   Regs[0] = MFI->getFrameOffsetReg();
      68        1282 :   Regs[1] = AMDGPU::NoRegister;
      69             : 
      70        1282 :   return Regs;
      71             : }
      72             : 
      73         496 : const uint32_t *SIRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
      74             :                                                      CallingConv::ID CC) const {
      75         496 :   switch (CC) {
      76             :   case CallingConv::C:
      77             :   case CallingConv::Fast:
      78             :     return CSR_AMDGPU_HighRegs_RegMask;
      79           5 :   default:
      80           5 :     return nullptr;
      81             :   }
      82             : }
      83             : 
      84          97 : unsigned SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
      85          97 :   return AMDGPU::NoRegister;
      86      216918 : }

Generated by: LCOV version 1.13