LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - AMDGPURegisterInfo.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 1 1 100.0 %
Date: 2018-10-05 09:05:31 Functions: 1 1 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// TargetRegisterInfo interface that is implemented by all hw codegen
      12             : /// targets.
      13             : //
      14             : //===----------------------------------------------------------------------===//
      15             : 
      16             : #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H
      17             : #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H
      18             : 
      19             : #define GET_REGINFO_HEADER
      20             : #include "AMDGPUGenRegisterInfo.inc"
      21             : 
      22             : namespace llvm {
      23             : 
      24             : class GCNSubtarget;
      25             : class TargetInstrInfo;
      26             : 
      27             : struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
      28             :   AMDGPURegisterInfo();
      29             : 
      30      229414 :   bool enableMultipleCopyHints() const override { return true; }
      31             : 
      32             :   /// \returns the sub reg enum value for the given \p Channel
      33             :   /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
      34             :   static unsigned getSubRegFromChannel(unsigned Channel);
      35             : 
      36             :   void reserveRegisterTuples(BitVector &, unsigned Reg) const;
      37             : };
      38             : 
      39             : } // End namespace llvm
      40             : 
      41             : #endif

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