LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU/Disassembler - AMDGPUDisassembler.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 5 5 100.0 %
Date: 2017-09-14 15:23:50 Functions: 2 4 50.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : ///
      12             : /// This file contains declaration for AMDGPU ISA disassembler
      13             : //
      14             : //===----------------------------------------------------------------------===//
      15             : 
      16             : #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
      17             : #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
      18             : 
      19             : #include "llvm/ADT/ArrayRef.h"
      20             : #include "llvm/MC/MCDisassembler/MCDisassembler.h"
      21             : #include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
      22             : #include "llvm/MC/MCDisassembler/MCSymbolizer.h"
      23             : #include <algorithm>
      24             : #include <cstdint>
      25             : #include <memory>
      26             : 
      27             : namespace llvm {
      28             : 
      29             : class MCContext;
      30             : class MCInst;
      31             : class MCOperand;
      32             : class MCSubtargetInfo;
      33             : class Twine;
      34             : 
      35             : //===----------------------------------------------------------------------===//
      36             : // AMDGPUDisassembler
      37             : //===----------------------------------------------------------------------===//
      38             : 
      39             : class AMDGPUDisassembler : public MCDisassembler {
      40             : private:
      41             :   mutable ArrayRef<uint8_t> Bytes;
      42             :   mutable uint32_t Literal;
      43             :   mutable bool HasLiteral;
      44             : 
      45             : public:
      46          39 :   AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
      47         117 :     MCDisassembler(STI, Ctx) {}
      48             : 
      49          38 :   ~AMDGPUDisassembler() override = default;
      50             : 
      51             :   DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
      52             :                               ArrayRef<uint8_t> Bytes, uint64_t Address,
      53             :                               raw_ostream &WS, raw_ostream &CS) const override;
      54             : 
      55             :   const char* getRegClassName(unsigned RegClassID) const;
      56             : 
      57             :   MCOperand createRegOperand(unsigned int RegId) const;
      58             :   MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
      59             :   MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
      60             : 
      61             :   MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
      62             : 
      63             :   DecodeStatus tryDecodeInst(const uint8_t* Table, MCInst &MI, uint64_t Inst,
      64             :                              uint64_t Address) const;
      65             : 
      66             :   DecodeStatus convertSDWAInst(MCInst &MI) const;
      67             : 
      68             :   MCOperand decodeOperand_VGPR_32(unsigned Val) const;
      69             :   MCOperand decodeOperand_VS_32(unsigned Val) const;
      70             :   MCOperand decodeOperand_VS_64(unsigned Val) const;
      71             :   MCOperand decodeOperand_VS_128(unsigned Val) const;
      72             :   MCOperand decodeOperand_VSrc16(unsigned Val) const;
      73             :   MCOperand decodeOperand_VSrcV216(unsigned Val) const;
      74             : 
      75             :   MCOperand decodeOperand_VReg_64(unsigned Val) const;
      76             :   MCOperand decodeOperand_VReg_96(unsigned Val) const;
      77             :   MCOperand decodeOperand_VReg_128(unsigned Val) const;
      78             : 
      79             :   MCOperand decodeOperand_SReg_32(unsigned Val) const;
      80             :   MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const;
      81             :   MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const;
      82             :   MCOperand decodeOperand_SReg_64(unsigned Val) const;
      83             :   MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const;
      84             :   MCOperand decodeOperand_SReg_128(unsigned Val) const;
      85             :   MCOperand decodeOperand_SReg_256(unsigned Val) const;
      86             :   MCOperand decodeOperand_SReg_512(unsigned Val) const;
      87             : 
      88             :   enum OpWidthTy {
      89             :     OPW32,
      90             :     OPW64,
      91             :     OPW128,
      92             :     OPW16,
      93             :     OPWV216,
      94             :     OPW_LAST_,
      95             :     OPW_FIRST_ = OPW32
      96             :   };
      97             : 
      98             :   unsigned getVgprClassId(const OpWidthTy Width) const;
      99             :   unsigned getSgprClassId(const OpWidthTy Width) const;
     100             :   unsigned getTtmpClassId(const OpWidthTy Width) const;
     101             : 
     102             :   static MCOperand decodeIntImmed(unsigned Imm);
     103             :   static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm);
     104             :   MCOperand decodeLiteralConstant() const;
     105             : 
     106             :   MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
     107             :   MCOperand decodeSpecialReg32(unsigned Val) const;
     108             :   MCOperand decodeSpecialReg64(unsigned Val) const;
     109             : 
     110             :   MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const;
     111             :   MCOperand decodeSDWASrc16(unsigned Val) const;
     112             :   MCOperand decodeSDWASrc32(unsigned Val) const;
     113             :   MCOperand decodeSDWAVopcDst(unsigned Val) const;
     114             : };
     115             : 
     116             : //===----------------------------------------------------------------------===//
     117             : // AMDGPUSymbolizer
     118             : //===----------------------------------------------------------------------===//
     119             : 
     120           7 : class AMDGPUSymbolizer : public MCSymbolizer {
     121             : private:
     122             :   void *DisInfo;
     123             : 
     124             : public:
     125             :   AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
     126             :                    void *disInfo)
     127          28 :                    : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
     128             : 
     129             :   bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
     130             :                                 int64_t Value, uint64_t Address,
     131             :                                 bool IsBranch, uint64_t Offset,
     132             :                                 uint64_t InstSize) override;
     133             : 
     134             :   void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
     135             :                                        int64_t Value,
     136             :                                        uint64_t Address) override;
     137             : };
     138             : 
     139             : } // end namespace llvm
     140             : 
     141             : #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H

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