LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - GCNHazardRecognizer.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 2 2 100.0 %
Date: 2017-09-14 15:23:50 Functions: 3 3 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file defines hazard recognizers for scheduling on GCN processors.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
      15             : #define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
      16             : 
      17             : #include "llvm/ADT/STLExtras.h"
      18             : #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
      19             : #include <list>
      20             : 
      21             : namespace llvm {
      22             : 
      23             : class MachineFunction;
      24             : class MachineInstr;
      25             : class ScheduleDAG;
      26             : class SIInstrInfo;
      27             : class SISubtarget;
      28             : 
      29       78414 : class GCNHazardRecognizer final : public ScheduleHazardRecognizer {
      30             :   // This variable stores the instruction that has been emitted this cycle. It
      31             :   // will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is
      32             :   // called.
      33             :   MachineInstr *CurrCycleInstr;
      34             :   std::list<MachineInstr*> EmittedInstrs;
      35             :   const MachineFunction &MF;
      36             :   const SISubtarget &ST;
      37             :   const SIInstrInfo &TII;
      38             : 
      39             :   int getWaitStatesSince(function_ref<bool(MachineInstr *)> IsHazard);
      40             :   int getWaitStatesSinceDef(unsigned Reg,
      41             :                             function_ref<bool(MachineInstr *)> IsHazardDef =
      42             :                                 [](MachineInstr *) { return true; });
      43             :   int getWaitStatesSinceSetReg(function_ref<bool(MachineInstr *)> IsHazard);
      44             : 
      45             :   int checkSMEMSoftClauseHazards(MachineInstr *SMEM);
      46             :   int checkSMRDHazards(MachineInstr *SMRD);
      47             :   int checkVMEMHazards(MachineInstr* VMEM);
      48             :   int checkDPPHazards(MachineInstr *DPP);
      49             :   int checkDivFMasHazards(MachineInstr *DivFMas);
      50             :   int checkGetRegHazards(MachineInstr *GetRegInstr);
      51             :   int checkSetRegHazards(MachineInstr *SetRegInstr);
      52             :   int createsVALUHazard(const MachineInstr &MI);
      53             :   int checkVALUHazards(MachineInstr *VALU);
      54             :   int checkRWLaneHazards(MachineInstr *RWLane);
      55             :   int checkRFEHazards(MachineInstr *RFE);
      56             :   int checkAnyInstHazards(MachineInstr *MI);
      57             :   int checkReadM0Hazards(MachineInstr *SMovRel);
      58             : public:
      59             :   GCNHazardRecognizer(const MachineFunction &MF);
      60             :   // We can only issue one instruction per cycle.
      61      441989 :   bool atIssueLimit() const override { return true; }
      62             :   void EmitInstruction(SUnit *SU) override;
      63             :   void EmitInstruction(MachineInstr *MI) override;
      64             :   HazardType getHazardType(SUnit *SU, int Stalls) override;
      65             :   void EmitNoop() override;
      66             :   unsigned PreEmitNoops(SUnit *SU) override;
      67             :   unsigned PreEmitNoops(MachineInstr *) override;
      68             :   void AdvanceCycle() override;
      69             :   void RecedeCycle() override;
      70             : };
      71             : 
      72             : } // end namespace llvm
      73             : 
      74             : #endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H

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