LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU/MCTargetDesc - AMDGPUMCTargetDesc.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 35 35 100.0 %
Date: 2017-09-14 15:23:50 Functions: 10 10 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// \brief This file provides AMDGPU specific target descriptions.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "AMDGPUMCTargetDesc.h"
      16             : #include "AMDGPUELFStreamer.h"
      17             : #include "AMDGPUMCAsmInfo.h"
      18             : #include "AMDGPUTargetStreamer.h"
      19             : #include "InstPrinter/AMDGPUInstPrinter.h"
      20             : #include "SIDefines.h"
      21             : #include "llvm/MC/MCContext.h"
      22             : #include "llvm/MC/MCInstrInfo.h"
      23             : #include "llvm/MC/MCRegisterInfo.h"
      24             : #include "llvm/MC/MCStreamer.h"
      25             : #include "llvm/MC/MCSubtargetInfo.h"
      26             : #include "llvm/MC/MachineLocation.h"
      27             : #include "llvm/Support/ErrorHandling.h"
      28             : #include "llvm/Support/TargetRegistry.h"
      29             : 
      30             : using namespace llvm;
      31             : 
      32             : #define GET_INSTRINFO_MC_DESC
      33             : #include "AMDGPUGenInstrInfo.inc"
      34             : 
      35             : #define GET_SUBTARGETINFO_MC_DESC
      36             : #include "AMDGPUGenSubtargetInfo.inc"
      37             : 
      38             : #define GET_REGINFO_MC_DESC
      39             : #include "AMDGPUGenRegisterInfo.inc"
      40             : 
      41        2385 : static MCInstrInfo *createAMDGPUMCInstrInfo() {
      42        2385 :   MCInstrInfo *X = new MCInstrInfo();
      43        2385 :   InitAMDGPUMCInstrInfo(X);
      44        2385 :   return X;
      45             : }
      46             : 
      47        2408 : static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
      48        4816 :   MCRegisterInfo *X = new MCRegisterInfo();
      49        2408 :   InitAMDGPUMCRegisterInfo(X, 0);
      50        2408 :   return X;
      51             : }
      52             : 
      53             : static MCSubtargetInfo *
      54        2372 : createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
      55        2372 :   return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
      56             : }
      57             : 
      58        1954 : static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
      59             :                                                 unsigned SyntaxVariant,
      60             :                                                 const MCAsmInfo &MAI,
      61             :                                                 const MCInstrInfo &MII,
      62             :                                                 const MCRegisterInfo &MRI) {
      63        2195 :   return T.getArch() == Triple::r600 ? new R600InstPrinter(MAI, MII, MRI) : 
      64        3426 :                                        new AMDGPUInstPrinter(MAI, MII, MRI);
      65             : }
      66             : 
      67        1706 : static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
      68             :                                                       formatted_raw_ostream &OS,
      69             :                                                       MCInstPrinter *InstPrint,
      70             :                                                       bool isVerboseAsm) {
      71        1706 :   return new AMDGPUTargetAsmStreamer(S, OS);
      72             : }
      73             : 
      74          58 : static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
      75             :                                                    MCStreamer &S,
      76             :                                                    const MCSubtargetInfo &STI) {
      77          58 :   return new AMDGPUTargetELFStreamer(S);
      78             : }
      79             : 
      80          61 : static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
      81             :                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
      82             :                                     MCCodeEmitter *Emitter, bool RelaxAll) {
      83          61 :   if (T.getOS() == Triple::AMDHSA)
      84          44 :     return createAMDGPUELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
      85             : 
      86          17 :   return createELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
      87             : }
      88             : 
      89       56330 : extern "C" void LLVMInitializeAMDGPUTargetMC() {
      90      225320 :   for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
      91      112660 :     RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
      92             : 
      93      225320 :     TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
      94      225320 :     TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
      95      225320 :     TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
      96      225320 :     TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
      97      225320 :     TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
      98      225320 :     TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
      99             :   }
     100             : 
     101             :   // R600 specific registration
     102      112660 :   TargetRegistry::RegisterMCCodeEmitter(getTheAMDGPUTarget(),
     103             :                                         createR600MCCodeEmitter);
     104             : 
     105             :   // GCN specific registration
     106      112660 :   TargetRegistry::RegisterMCCodeEmitter(getTheGCNTarget(),
     107             :                                         createSIMCCodeEmitter);
     108             : 
     109      112660 :   TargetRegistry::RegisterAsmTargetStreamer(getTheGCNTarget(),
     110             :                                             createAMDGPUAsmTargetStreamer);
     111      112660 :   TargetRegistry::RegisterObjectTargetStreamer(
     112             :       getTheGCNTarget(), createAMDGPUObjectTargetStreamer);
     113      273248 : }

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