LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - R600ISelLowering.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 1 1 100.0 %
Date: 2017-09-14 15:23:50 Functions: 0 2 0.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// \brief R600 DAG Lowering interface definition
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #ifndef LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
      16             : #define LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
      17             : 
      18             : #include "AMDGPUISelLowering.h"
      19             : 
      20             : namespace llvm {
      21             : 
      22             : class R600InstrInfo;
      23             : class R600Subtarget;
      24             : 
      25         504 : class R600TargetLowering final : public AMDGPUTargetLowering {
      26             : public:
      27             :   R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI);
      28             : 
      29             :   const R600Subtarget *getSubtarget() const;
      30             : 
      31             :   MachineBasicBlock *
      32             :   EmitInstrWithCustomInserter(MachineInstr &MI,
      33             :                               MachineBasicBlock *BB) const override;
      34             :   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
      35             :   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
      36             :   void ReplaceNodeResults(SDNode * N,
      37             :                           SmallVectorImpl<SDValue> &Results,
      38             :                           SelectionDAG &DAG) const override;
      39             :   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
      40             :                                bool isVarArg,
      41             :                                const SmallVectorImpl<ISD::InputArg> &Ins,
      42             :                                const SDLoc &DL, SelectionDAG &DAG,
      43             :                                SmallVectorImpl<SDValue> &InVals) const override;
      44             :   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
      45             :                          EVT VT) const override;
      46             : 
      47             :   bool canMergeStoresTo(unsigned AS, EVT MemVT,
      48             :                         const SelectionDAG &DAG) const override;
      49             : 
      50             :   bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
      51             :                                       unsigned Align,
      52             :                                       bool *IsFast) const override;
      53             : 
      54             : private:
      55             :   unsigned Gen;
      56             :   /// Each OpenCL kernel has nine implicit parameters that are stored in the
      57             :   /// first nine dwords of a Vertex Buffer.  These implicit parameters are
      58             :   /// lowered to load instructions which retrieve the values from the Vertex
      59             :   /// Buffer.
      60             :   SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
      61             :                                  unsigned DwordOffset) const;
      62             : 
      63             :   void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
      64             :       MachineRegisterInfo & MRI, unsigned dword_offset) const;
      65             :   SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG,
      66             :                           const SDLoc &DL) const;
      67             :   SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
      68             : 
      69             :   SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
      70             :   SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
      71             :   SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
      72             :   SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
      73             :                              SelectionDAG &DAG) const override;
      74             :   SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
      75             : 
      76             :   SDValue lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const;
      77             :   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
      78             :   SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
      79             :   SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
      80             : 
      81             :   SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
      82             :   SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
      83             :   SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
      84             :   SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
      85             :   SDValue LowerSHLParts(SDValue Op, SelectionDAG &DAG) const;
      86             :   SDValue LowerSRXParts(SDValue Op, SelectionDAG &DAG) const;
      87             :   SDValue LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
      88             :                         unsigned mainop, unsigned ovf) const;
      89             : 
      90             :   SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
      91             :                                           SelectionDAG &DAG) const;
      92             :   void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
      93             :                        unsigned &Channel, unsigned &PtrIncr) const;
      94             :   bool isZero(SDValue Op) const;
      95             :   bool isHWTrueValue(SDValue Op) const;
      96             :   bool isHWFalseValue(SDValue Op) const;
      97             : 
      98             :  bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
      99             :                   SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,
     100             :                   SelectionDAG &DAG) const;
     101             : 
     102             :   SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
     103             : };
     104             : 
     105             : } // End namespace llvm;
     106             : 
     107             : #endif

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