LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - R600MachineScheduler.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 213 216 98.6 %
Date: 2018-07-13 00:08:38 Functions: 17 17 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- R600MachineScheduler.cpp - R600 Scheduler Interface -*- C++ -*-----===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// R600 Machine Scheduler interface
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "R600MachineScheduler.h"
      16             : #include "AMDGPUSubtarget.h"
      17             : #include "R600InstrInfo.h"
      18             : #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
      19             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      20             : #include "llvm/IR/LegacyPassManager.h"
      21             : #include "llvm/Pass.h"
      22             : #include "llvm/Support/raw_ostream.h"
      23             : 
      24             : using namespace llvm;
      25             : 
      26             : #define DEBUG_TYPE "machine-scheduler"
      27             : 
      28        2284 : void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {
      29             :   assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness");
      30        2284 :   DAG = static_cast<ScheduleDAGMILive*>(dag);
      31        2284 :   const R600Subtarget &ST = DAG->MF.getSubtarget<R600Subtarget>();
      32        2284 :   TII = static_cast<const R600InstrInfo*>(DAG->TII);
      33        2284 :   TRI = static_cast<const R600RegisterInfo*>(DAG->TRI);
      34        2284 :   VLIW5 = !ST.hasCaymanISA();
      35        2284 :   MRI = &DAG->MRI;
      36        2284 :   CurInstKind = IDOther;
      37        2284 :   CurEmitted = 0;
      38        2284 :   OccupedSlotsMask = 31;
      39        2284 :   InstKindLimit[IDAlu] = TII->getMaxAlusPerClause();
      40        2284 :   InstKindLimit[IDOther] = 32;
      41        2284 :   InstKindLimit[IDFetch] = ST.getTexVTXClauseSize();
      42        2284 :   AluInstCount = 0;
      43        2284 :   FetchInstCount = 0;
      44        2284 : }
      45             : 
      46       62170 : void R600SchedStrategy::MoveUnits(std::vector<SUnit *> &QSrc,
      47             :                                   std::vector<SUnit *> &QDst)
      48             : {
      49       62170 :   QDst.insert(QDst.end(), QSrc.begin(), QSrc.end());
      50             :   QSrc.clear();
      51       62170 : }
      52             : 
      53             : static unsigned getWFCountLimitedByGPR(unsigned GPRCount) {
      54             :   assert (GPRCount && "GPRCount cannot be 0");
      55        4230 :   return 248 / GPRCount;
      56             : }
      57             : 
      58       55700 : SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) {
      59             :   SUnit *SU = nullptr;
      60       55700 :   NextInstKind = IDOther;
      61             : 
      62       55700 :   IsTopNode = false;
      63             : 
      64             :   // check if we might want to switch current clause type
      65      111166 :   bool AllowSwitchToAlu = (CurEmitted >= InstKindLimit[CurInstKind]) ||
      66       55466 :       (Available[CurInstKind].empty());
      67       55934 :   bool AllowSwitchFromAlu = (CurEmitted >= InstKindLimit[CurInstKind]) &&
      68         200 :       (!Available[IDFetch].empty() || !Available[IDOther].empty());
      69             : 
      70      101939 :   if (CurInstKind == IDAlu && !Available[IDFetch].empty()) {
      71             :     // We use the heuristic provided by AMD Accelerated Parallel Processing
      72             :     // OpenCL Programming Guide :
      73             :     // The approx. number of WF that allows TEX inst to hide ALU inst is :
      74             :     // 500 (cycles for TEX) / (AluFetchRatio * 8 (cycles for ALU))
      75             :     float ALUFetchRationEstimate =
      76       12693 :         (AluInstCount + AvailablesAluCount() + Pending[IDAlu].size()) /
      77       12693 :         (FetchInstCount + Available[IDFetch].size());
      78        4231 :     if (ALUFetchRationEstimate == 0) {
      79             :       AllowSwitchFromAlu = true;
      80             :     } else {
      81        4230 :       unsigned NeededWF = 62.5f / ALUFetchRationEstimate;
      82             :       LLVM_DEBUG(dbgs() << NeededWF << " approx. Wavefronts Required\n");
      83             :       // We assume the local GPR requirements to be "dominated" by the requirement
      84             :       // of the TEX clause (which consumes 128 bits regs) ; ALU inst before and
      85             :       // after TEX are indeed likely to consume or generate values from/for the
      86             :       // TEX clause.
      87             :       // Available[IDFetch].size() * 2 : GPRs required in the Fetch clause
      88             :       // We assume that fetch instructions are either TnXYZW = TEX TnXYZW (need
      89             :       // one GPR) or TmXYZW = TnXYZW (need 2 GPR).
      90             :       // (TODO : use RegisterPressure)
      91             :       // If we are going too use too many GPR, we flush Fetch instruction to lower
      92             :       // register pressure on 128 bits regs.
      93        4230 :       unsigned NearRegisterRequirement = 2 * Available[IDFetch].size();
      94        4230 :       if (NeededWF > getWFCountLimitedByGPR(NearRegisterRequirement))
      95             :         AllowSwitchFromAlu = true;
      96             :     }
      97             :   }
      98             : 
      99       55700 :   if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
     100       51178 :       (!AllowSwitchFromAlu && CurInstKind == IDAlu))) {
     101             :     // try to pick ALU
     102       50663 :     SU = pickAlu();
     103       56724 :     if (!SU && !PhysicalRegCopy.empty()) {
     104        1637 :       SU = PhysicalRegCopy.front();
     105        1637 :       PhysicalRegCopy.erase(PhysicalRegCopy.begin());
     106             :     }
     107       50663 :     if (SU) {
     108       46239 :       if (CurEmitted >= InstKindLimit[IDAlu])
     109         192 :         CurEmitted = 0;
     110       46239 :       NextInstKind = IDAlu;
     111             :     }
     112             :   }
     113             : 
     114       50663 :   if (!SU) {
     115             :     // try to pick FETCH
     116        9461 :     SU = pickOther(IDFetch);
     117        9461 :     if (SU)
     118        1837 :       NextInstKind = IDFetch;
     119             :   }
     120             : 
     121             :   // try to pick other
     122       55700 :   if (!SU) {
     123        7624 :     SU = pickOther(IDOther);
     124        7624 :     if (SU)
     125        5340 :       NextInstKind = IDOther;
     126             :   }
     127             : 
     128             :   LLVM_DEBUG(if (SU) {
     129             :     dbgs() << " ** Pick node **\n";
     130             :     SU->dump(DAG);
     131             :   } else {
     132             :     dbgs() << "NO NODE \n";
     133             :     for (unsigned i = 0; i < DAG->SUnits.size(); i++) {
     134             :       const SUnit &S = DAG->SUnits[i];
     135             :       if (!S.isScheduled)
     136             :         S.dump(DAG);
     137             :     }
     138             :   });
     139             : 
     140       55700 :   return SU;
     141             : }
     142             : 
     143       53416 : void R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) {
     144       53416 :   if (NextInstKind != CurInstKind) {
     145             :     LLVM_DEBUG(dbgs() << "Instruction Type Switch\n");
     146        6127 :     if (NextInstKind != IDAlu)
     147        2075 :       OccupedSlotsMask |= 31;
     148        6127 :     CurEmitted = 0;
     149        6127 :     CurInstKind = NextInstKind;
     150             :   }
     151             : 
     152       53416 :   if (CurInstKind == IDAlu) {
     153       46239 :     AluInstCount ++;
     154       46239 :     switch (getAluKind(SU)) {
     155         132 :     case AluT_XYZW:
     156         132 :       CurEmitted += 4;
     157         132 :       break;
     158             :     case AluDiscarded:
     159             :       break;
     160       46107 :     default: {
     161       46107 :       ++CurEmitted;
     162      884509 :       for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(),
     163      930616 :           E = SU->getInstr()->operands_end(); It != E; ++It) {
     164             :         MachineOperand &MO = *It;
     165      838402 :         if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X)
     166       20795 :           ++CurEmitted;
     167       46107 :       }
     168             :     }
     169             :     }
     170             :   } else {
     171        7177 :     ++CurEmitted;
     172             :   }
     173             : 
     174             :   LLVM_DEBUG(dbgs() << CurEmitted << " Instructions Emitted in this clause\n");
     175             : 
     176       53416 :   if (CurInstKind != IDFetch) {
     177       51579 :     MoveUnits(Pending[IDFetch], Available[IDFetch]);
     178             :   } else
     179        1837 :     FetchInstCount++;
     180       53416 : }
     181             : 
     182             : static bool
     183             : isPhysicalRegCopy(MachineInstr *MI) {
     184      106832 :   if (MI->getOpcode() != R600::COPY)
     185             :     return false;
     186             : 
     187        4616 :   return !TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg());
     188             : }
     189             : 
     190       10404 : void R600SchedStrategy::releaseTopNode(SUnit *SU) {
     191             :   LLVM_DEBUG(dbgs() << "Top Releasing "; SU->dump(DAG););
     192       10404 : }
     193             : 
     194       53416 : void R600SchedStrategy::releaseBottomNode(SUnit *SU) {
     195             :   LLVM_DEBUG(dbgs() << "Bottom Releasing "; SU->dump(DAG););
     196       55724 :   if (isPhysicalRegCopy(SU->getInstr())) {
     197        1637 :     PhysicalRegCopy.push_back(SU);
     198        1637 :     return;
     199             :   }
     200             : 
     201       51779 :   int IK = getInstKind(SU);
     202             : 
     203             :   // There is no export clause, we can schedule one as soon as its ready
     204       51779 :   if (IK == IDOther)
     205        5340 :     Available[IDOther].push_back(SU);
     206             :   else
     207       46439 :     Pending[IK].push_back(SU);
     208             : 
     209             : }
     210             : 
     211      303777 : bool R600SchedStrategy::regBelongsToClass(unsigned Reg,
     212             :                                           const TargetRegisterClass *RC) const {
     213      303777 :   if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
     214           0 :     return RC->contains(Reg);
     215             :   } else {
     216      607554 :     return MRI->getRegClass(Reg) == RC;
     217             :   }
     218             : }
     219             : 
     220       90841 : R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const {
     221       90841 :   MachineInstr *MI = SU->getInstr();
     222             : 
     223       90841 :   if (TII->isTransOnly(*MI))
     224             :     return AluTrans;
     225             : 
     226      178002 :   switch (MI->getOpcode()) {
     227             :   case R600::PRED_X:
     228             :     return AluPredX;
     229          62 :   case R600::INTERP_PAIR_XY:
     230             :   case R600::INTERP_PAIR_ZW:
     231             :   case R600::INTERP_VEC_LOAD:
     232             :   case R600::DOT_4:
     233          62 :     return AluT_XYZW;
     234        2979 :   case R600::COPY:
     235        5958 :     if (MI->getOperand(1).isUndef()) {
     236             :       // MI will become a KILL, don't considers it in scheduling
     237             :       return AluDiscarded;
     238             :     }
     239             :   default:
     240             :     break;
     241             :   }
     242             : 
     243             :   // Does the instruction take a whole IG ?
     244             :   // XXX: Is it possible to add a helper function in R600InstrInfo that can
     245             :   // be used here and in R600PacketizerList::isSoloInstruction() ?
     246      177450 :   if(TII->isVector(*MI) ||
     247      266031 :      TII->isCubeOp(MI->getOpcode()) ||
     248      354804 :      TII->isReductionOp(MI->getOpcode()) ||
     249       88677 :      MI->getOpcode() == R600::GROUP_BARRIER) {
     250             :     return AluT_XYZW;
     251             :   }
     252             : 
     253       88669 :   if (TII->isLDSInstr(MI->getOpcode())) {
     254             :     return AluT_X;
     255             :   }
     256             : 
     257             :   // Is the result already assigned to a channel ?
     258       81851 :   unsigned DestSubReg = MI->getOperand(0).getSubReg();
     259       81851 :   switch (DestSubReg) {
     260             :   case R600::sub0:
     261             :     return AluT_X;
     262        3996 :   case R600::sub1:
     263        3996 :     return AluT_Y;
     264        3634 :   case R600::sub2:
     265        3634 :     return AluT_Z;
     266        3550 :   case R600::sub3:
     267        3550 :     return AluT_W;
     268             :   default:
     269             :     break;
     270             :   }
     271             : 
     272             :   // Is the result already member of a X/Y/Z/W class ?
     273       65956 :   unsigned DestReg = MI->getOperand(0).getReg();
     274      120557 :   if (regBelongsToClass(DestReg, &R600::R600_TReg32_XRegClass) ||
     275       54601 :       regBelongsToClass(DestReg, &R600::R600_AddrRegClass))
     276             :     return AluT_X;
     277       54601 :   if (regBelongsToClass(DestReg, &R600::R600_TReg32_YRegClass))
     278             :     return AluT_Y;
     279       52106 :   if (regBelongsToClass(DestReg, &R600::R600_TReg32_ZRegClass))
     280             :     return AluT_Z;
     281       48251 :   if (regBelongsToClass(DestReg, &R600::R600_TReg32_WRegClass))
     282             :     return AluT_W;
     283       28262 :   if (regBelongsToClass(DestReg, &R600::R600_Reg128RegClass))
     284             :     return AluT_XYZW;
     285             : 
     286             :   // LDS src registers cannot be used in the Trans slot.
     287       28213 :   if (TII->readsLDSSrcReg(*MI))
     288             :     return AluT_XYZW;
     289             : 
     290       28213 :   return AluAny;
     291             : }
     292             : 
     293       51779 : int R600SchedStrategy::getInstKind(SUnit* SU) {
     294       51779 :   int Opcode = SU->getInstr()->getOpcode();
     295             : 
     296       51779 :   if (TII->usesTextureCache(Opcode) || TII->usesVertexCache(Opcode))
     297             :     return IDFetch;
     298             : 
     299       49942 :   if (TII->isALUInstr(Opcode)) {
     300             :     return IDAlu;
     301             :   }
     302             : 
     303        6125 :   switch (Opcode) {
     304             :   case R600::PRED_X:
     305             :   case R600::COPY:
     306             :   case R600::CONST_COPY:
     307             :   case R600::INTERP_PAIR_XY:
     308             :   case R600::INTERP_PAIR_ZW:
     309             :   case R600::INTERP_VEC_LOAD:
     310             :   case R600::DOT_4:
     311             :     return IDAlu;
     312        5340 :   default:
     313        5340 :     return IDOther;
     314             :   }
     315             : }
     316             : 
     317      232505 : SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) {
     318      232505 :   if (Q.empty())
     319             :     return nullptr;
     320             :   for (std::vector<SUnit *>::reverse_iterator It = Q.rbegin(), E = Q.rend();
     321       46907 :       It != E; ++It) {
     322       46049 :     SUnit *SU = *It;
     323       92098 :     InstructionsGroupCandidate.push_back(SU->getInstr());
     324       46049 :     if (TII->fitsConstReadLimitations(InstructionsGroupCandidate) &&
     325       13207 :         (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) {
     326             :       InstructionsGroupCandidate.pop_back();
     327             :       Q.erase((It + 1).base());
     328             :       return SU;
     329             :     } else {
     330             :       InstructionsGroupCandidate.pop_back();
     331             :     }
     332             :   }
     333             :   return nullptr;
     334             : }
     335             : 
     336       21346 : void R600SchedStrategy::LoadAlu() {
     337             :   std::vector<SUnit *> &QSrc = Pending[IDAlu];
     338       87294 :   for (unsigned i = 0, e = QSrc.size(); i < e; ++i) {
     339       89204 :     AluKind AK = getAluKind(QSrc[i]);
     340       89204 :     AvailableAlus[AK].push_back(QSrc[i]);
     341             :   }
     342             :   QSrc.clear();
     343       21346 : }
     344             : 
     345       21346 : void R600SchedStrategy::PrepareNextSlot() {
     346             :   LLVM_DEBUG(dbgs() << "New Slot\n");
     347             :   assert (OccupedSlotsMask && "Slot wasn't filled");
     348       21346 :   OccupedSlotsMask = 0;
     349             : //  if (HwGen == R600Subtarget::NORTHERN_ISLANDS)
     350             : //    OccupedSlotsMask |= 16;
     351             :   InstructionsGroupCandidate.clear();
     352       21346 :   LoadAlu();
     353       21346 : }
     354             : 
     355       27925 : void R600SchedStrategy::AssignSlot(MachineInstr* MI, unsigned Slot) {
     356       55850 :   int DstIndex = TII->getOperandIdx(MI->getOpcode(), R600::OpName::dst);
     357       27925 :   if (DstIndex == -1) {
     358             :     return;
     359             :   }
     360       55748 :   unsigned DestReg = MI->getOperand(DstIndex).getReg();
     361             :   // PressureRegister crashes if an operand is def and used in the same inst
     362             :   // and we try to constraint its regclass
     363      567089 :   for (MachineInstr::mop_iterator It = MI->operands_begin(),
     364      622837 :       E = MI->operands_end(); It != E; ++It) {
     365             :     MachineOperand &MO = *It;
     366      653920 :     if (MO.isReg() && !MO.isDef() &&
     367       86824 :         MO.getReg() == DestReg)
     368             :       return;
     369             :   }
     370             :   // Constrains the regclass of DestReg to assign it to Slot
     371       27867 :   switch (Slot) {
     372        1714 :   case 0:
     373        1714 :     MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass);
     374        1714 :     break;
     375        2455 :   case 1:
     376        2455 :     MRI->constrainRegClass(DestReg, &R600::R600_TReg32_YRegClass);
     377        2455 :     break;
     378        3813 :   case 2:
     379        3813 :     MRI->constrainRegClass(DestReg, &R600::R600_TReg32_ZRegClass);
     380        3813 :     break;
     381       19885 :   case 3:
     382       19885 :     MRI->constrainRegClass(DestReg, &R600::R600_TReg32_WRegClass);
     383       19885 :     break;
     384             :   }
     385             : }
     386             : 
     387      123505 : SUnit *R600SchedStrategy::AttemptFillSlot(unsigned Slot, bool AnyAlu) {
     388             :   static const AluKind IndexToID[] = {AluT_X, AluT_Y, AluT_Z, AluT_W};
     389      123505 :   SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu);
     390      123505 :   if (SlotedSU)
     391             :     return SlotedSU;
     392      107914 :   SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu);
     393      107914 :   if (UnslotedSU)
     394       27925 :     AssignSlot(UnslotedSU->getInstr(), Slot);
     395             :   return UnslotedSU;
     396             : }
     397             : 
     398       76240 : unsigned R600SchedStrategy::AvailablesAluCount() const {
     399      304960 :   return AvailableAlus[AluAny].size() + AvailableAlus[AluT_XYZW].size() +
     400      304960 :       AvailableAlus[AluT_X].size() + AvailableAlus[AluT_Y].size() +
     401      304960 :       AvailableAlus[AluT_Z].size() + AvailableAlus[AluT_W].size() +
     402      304960 :       AvailableAlus[AluTrans].size() + AvailableAlus[AluDiscarded].size() +
     403      152480 :       AvailableAlus[AluPredX].size();
     404             : }
     405             : 
     406       50663 : SUnit* R600SchedStrategy::pickAlu() {
     407      112705 :   while (AvailablesAluCount() || !Pending[IDAlu].empty()) {
     408       65948 :     if (!OccupedSlotsMask) {
     409             :       // Bottom up scheduling : predX must comes first
     410       21346 :       if (!AvailableAlus[AluPredX].empty()) {
     411          83 :         OccupedSlotsMask |= 31;
     412          83 :         return PopInst(AvailableAlus[AluPredX], false);
     413             :       }
     414             :       // Flush physical reg copies (RA will discard them)
     415       21263 :       if (!AvailableAlus[AluDiscarded].empty()) {
     416           0 :         OccupedSlotsMask |= 31;
     417           0 :         return PopInst(AvailableAlus[AluDiscarded], false);
     418             :       }
     419             :       // If there is a T_XYZW alu available, use it
     420       21263 :       if (!AvailableAlus[AluT_XYZW].empty()) {
     421          83 :         OccupedSlotsMask |= 15;
     422          83 :         return PopInst(AvailableAlus[AluT_XYZW], false);
     423             :       }
     424             :     }
     425       65782 :     bool TransSlotOccuped = OccupedSlotsMask & 16;
     426       65782 :     if (!TransSlotOccuped && VLIW5) {
     427       23651 :       if (!AvailableAlus[AluTrans].empty()) {
     428         920 :         OccupedSlotsMask |= 16;
     429         920 :         return PopInst(AvailableAlus[AluTrans], false);
     430             :       }
     431       22731 :       SUnit *SU = AttemptFillSlot(3, true);
     432       22731 :       if (SU) {
     433       12305 :         OccupedSlotsMask |= 16;
     434       12305 :         return SU;
     435             :       }
     436             :     }
     437      324571 :     for (int Chan = 3; Chan > -1; --Chan) {
     438      167218 :       bool isOccupied = OccupedSlotsMask & (1 << Chan);
     439      167218 :       if (!isOccupied) {
     440      100774 :         SUnit *SU = AttemptFillSlot(Chan, false);
     441      100774 :         if (SU) {
     442       31211 :           OccupedSlotsMask |= (1 << Chan);
     443       62422 :           InstructionsGroupCandidate.push_back(SU->getInstr());
     444       31211 :           return SU;
     445             :         }
     446             :       }
     447             :     }
     448       21346 :     PrepareNextSlot();
     449             :   }
     450             :   return nullptr;
     451             : }
     452             : 
     453       17085 : SUnit* R600SchedStrategy::pickOther(int QID) {
     454             :   SUnit *SU = nullptr;
     455       17085 :   std::vector<SUnit *> &AQ = Available[QID];
     456             : 
     457       17085 :   if (AQ.empty()) {
     458       10591 :     MoveUnits(Pending[QID], AQ);
     459             :   }
     460       17085 :   if (!AQ.empty()) {
     461        7177 :     SU = AQ.back();
     462             :     AQ.pop_back();
     463             :   }
     464       17085 :   return SU;
     465             : }

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