LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - R600RegisterInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 45 47 95.7 %
Date: 2018-07-13 00:08:38 Functions: 10 11 90.9 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// R600 implementation of the TargetRegisterInfo class.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "R600RegisterInfo.h"
      16             : #include "AMDGPUTargetMachine.h"
      17             : #include "R600Defines.h"
      18             : #include "R600InstrInfo.h"
      19             : #include "R600MachineFunctionInfo.h"
      20             : #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
      21             : 
      22             : using namespace llvm;
      23             : 
      24         286 : R600RegisterInfo::R600RegisterInfo() : R600GenRegisterInfo(0) {
      25         286 :   RCW.RegWeight = 0;
      26         286 :   RCW.WeightLimit = 0;
      27         286 : }
      28             : 
      29             : #define GET_REGINFO_TARGET_DESC
      30             : #include "R600GenRegisterInfo.inc"
      31             : 
      32        4476 : BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
      33        4476 :   BitVector Reserved(getNumRegs());
      34             : 
      35        4476 :   const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
      36             :   const R600InstrInfo *TII = ST.getInstrInfo();
      37             : 
      38        4476 :   reserveRegisterTuples(Reserved, R600::ZERO);
      39        4476 :   reserveRegisterTuples(Reserved, R600::HALF);
      40        4476 :   reserveRegisterTuples(Reserved, R600::ONE);
      41        4476 :   reserveRegisterTuples(Reserved, R600::ONE_INT);
      42        4476 :   reserveRegisterTuples(Reserved, R600::NEG_HALF);
      43        4476 :   reserveRegisterTuples(Reserved, R600::NEG_ONE);
      44        4476 :   reserveRegisterTuples(Reserved, R600::PV_X);
      45        4476 :   reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X);
      46        4476 :   reserveRegisterTuples(Reserved, R600::ALU_CONST);
      47        4476 :   reserveRegisterTuples(Reserved, R600::PREDICATE_BIT);
      48        4476 :   reserveRegisterTuples(Reserved, R600::PRED_SEL_OFF);
      49        4476 :   reserveRegisterTuples(Reserved, R600::PRED_SEL_ZERO);
      50        4476 :   reserveRegisterTuples(Reserved, R600::PRED_SEL_ONE);
      51        4476 :   reserveRegisterTuples(Reserved, R600::INDIRECT_BASE_ADDR);
      52             : 
      53      572928 :   for (TargetRegisterClass::iterator I = R600::R600_AddrRegClass.begin(),
      54      577404 :                         E = R600::R600_AddrRegClass.end(); I != E; ++I) {
      55      572928 :     reserveRegisterTuples(Reserved, *I);
      56             :   }
      57             : 
      58        4476 :   TII->reserveIndirectRegisters(Reserved, MF, *this);
      59             : 
      60        4476 :   return Reserved;
      61             : }
      62             : 
      63             : // Dummy to not crash RegisterClassInfo.
      64             : static const MCPhysReg CalleeSavedReg = R600::NoRegister;
      65             : 
      66       22226 : const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs(
      67             :   const MachineFunction *) const {
      68       22226 :   return &CalleeSavedReg;
      69             : }
      70             : 
      71        2416 : unsigned R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
      72        2416 :   return R600::NoRegister;
      73             : }
      74             : 
      75      401948 : unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
      76      803896 :   return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
      77             : }
      78             : 
      79      203301 : unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
      80      406602 :   return GET_REG_INDEX(getEncodingValue(Reg));
      81             : }
      82             : 
      83           1 : const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
      84             :                                                                    MVT VT) const {
      85             :   switch(VT.SimpleTy) {
      86             :   default:
      87           1 :   case MVT::i32: return &R600::R600_TReg32RegClass;
      88             :   }
      89             : }
      90             : 
      91      455725 : const RegClassWeight &R600RegisterInfo::getRegClassWeight(
      92             :   const TargetRegisterClass *RC) const {
      93      455725 :   return RCW;
      94             : }
      95             : 
      96       45702 : bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
      97             :   assert(!TargetRegisterInfo::isVirtualRegister(Reg));
      98             : 
      99             :   switch (Reg) {
     100             :   case R600::OQAP:
     101             :   case R600::OQBP:
     102             :   case R600::AR_X:
     103             :     return false;
     104       45416 :   default:
     105       45416 :     return true;
     106             :   }
     107             : }
     108             : 
     109           0 : void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
     110             :                                            int SPAdj,
     111             :                                            unsigned FIOperandNum,
     112             :                                            RegScavenger *RS) const {
     113           0 :   llvm_unreachable("Subroutines not supported yet");
     114             : }
     115             : 
     116      643444 : void R600RegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
     117      643444 :   MCRegAliasIterator R(Reg, this, true);
     118             : 
     119     1974604 :   for (; R.isValid(); ++R)
     120             :     Reserved.set(*R);
     121      643444 : }

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