LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - R600RegisterInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 41 43 95.3 %
Date: 2018-06-17 00:07:59 Functions: 9 10 90.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// R600 implementation of the TargetRegisterInfo class.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "R600RegisterInfo.h"
      16             : #include "AMDGPUTargetMachine.h"
      17             : #include "R600Defines.h"
      18             : #include "R600InstrInfo.h"
      19             : #include "R600MachineFunctionInfo.h"
      20             : #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
      21             : 
      22             : using namespace llvm;
      23             : 
      24         286 : R600RegisterInfo::R600RegisterInfo() : AMDGPURegisterInfo() {
      25         286 :   RCW.RegWeight = 0;
      26         286 :   RCW.WeightLimit = 0;
      27         286 : }
      28             : 
      29        4462 : BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
      30        4462 :   BitVector Reserved(getNumRegs());
      31             : 
      32        4462 :   const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
      33             :   const R600InstrInfo *TII = ST.getInstrInfo();
      34             : 
      35        4462 :   reserveRegisterTuples(Reserved, AMDGPU::ZERO);
      36        4462 :   reserveRegisterTuples(Reserved, AMDGPU::HALF);
      37        4462 :   reserveRegisterTuples(Reserved, AMDGPU::ONE);
      38        4462 :   reserveRegisterTuples(Reserved, AMDGPU::ONE_INT);
      39        4462 :   reserveRegisterTuples(Reserved, AMDGPU::NEG_HALF);
      40        4462 :   reserveRegisterTuples(Reserved, AMDGPU::NEG_ONE);
      41        4462 :   reserveRegisterTuples(Reserved, AMDGPU::PV_X);
      42        4462 :   reserveRegisterTuples(Reserved, AMDGPU::ALU_LITERAL_X);
      43        4462 :   reserveRegisterTuples(Reserved, AMDGPU::ALU_CONST);
      44        4462 :   reserveRegisterTuples(Reserved, AMDGPU::PREDICATE_BIT);
      45        4462 :   reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_OFF);
      46        4462 :   reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_ZERO);
      47        4462 :   reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_ONE);
      48        4462 :   reserveRegisterTuples(Reserved, AMDGPU::INDIRECT_BASE_ADDR);
      49             : 
      50      575598 :   for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
      51      575598 :                         E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
      52      571136 :     reserveRegisterTuples(Reserved, *I);
      53             :   }
      54             : 
      55        4462 :   TII->reserveIndirectRegisters(Reserved, MF, *this);
      56             : 
      57        4462 :   return Reserved;
      58             : }
      59             : 
      60             : // Dummy to not crash RegisterClassInfo.
      61             : static const MCPhysReg CalleeSavedReg = AMDGPU::NoRegister;
      62             : 
      63       22141 : const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs(
      64             :   const MachineFunction *) const {
      65       22141 :   return &CalleeSavedReg;
      66             : }
      67             : 
      68        2416 : unsigned R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
      69        2416 :   return AMDGPU::NoRegister;
      70             : }
      71             : 
      72      401754 : unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
      73      803508 :   return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
      74             : }
      75             : 
      76      203170 : unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
      77      406340 :   return GET_REG_INDEX(getEncodingValue(Reg));
      78             : }
      79             : 
      80           1 : const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
      81             :                                                                    MVT VT) const {
      82             :   switch(VT.SimpleTy) {
      83             :   default:
      84           1 :   case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
      85             :   }
      86             : }
      87             : 
      88      481686 : const RegClassWeight &R600RegisterInfo::getRegClassWeight(
      89             :   const TargetRegisterClass *RC) const {
      90      481686 :   return RCW;
      91             : }
      92             : 
      93       45672 : bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
      94             :   assert(!TargetRegisterInfo::isVirtualRegister(Reg));
      95             : 
      96             :   switch (Reg) {
      97             :   case AMDGPU::OQAP:
      98             :   case AMDGPU::OQBP:
      99             :   case AMDGPU::AR_X:
     100             :     return false;
     101       45386 :   default:
     102       45386 :     return true;
     103             :   }
     104             : }
     105             : 
     106           0 : void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
     107             :                                            int SPAdj,
     108             :                                            unsigned FIOperandNum,
     109             :                                            RegScavenger *RS) const {
     110           0 :   llvm_unreachable("Subroutines not supported yet");
     111             : }

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