LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - R600RegisterInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 42 44 95.5 %
Date: 2017-09-14 15:23:50 Functions: 9 10 90.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// \brief R600 implementation of the TargetRegisterInfo class.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "R600RegisterInfo.h"
      16             : #include "AMDGPUTargetMachine.h"
      17             : #include "R600Defines.h"
      18             : #include "R600InstrInfo.h"
      19             : #include "R600MachineFunctionInfo.h"
      20             : 
      21             : using namespace llvm;
      22             : 
      23         253 : R600RegisterInfo::R600RegisterInfo() : AMDGPURegisterInfo() {
      24         253 :   RCW.RegWeight = 0;
      25         253 :   RCW.WeightLimit = 0;
      26         253 : }
      27             : 
      28        4114 : BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
      29        4114 :   BitVector Reserved(getNumRegs());
      30             : 
      31        4114 :   const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
      32        4114 :   const R600InstrInfo *TII = ST.getInstrInfo();
      33             : 
      34        4114 :   Reserved.set(AMDGPU::ZERO);
      35        4114 :   Reserved.set(AMDGPU::HALF);
      36        4114 :   Reserved.set(AMDGPU::ONE);
      37        4114 :   Reserved.set(AMDGPU::ONE_INT);
      38        4114 :   Reserved.set(AMDGPU::NEG_HALF);
      39        4114 :   Reserved.set(AMDGPU::NEG_ONE);
      40        4114 :   Reserved.set(AMDGPU::PV_X);
      41        4114 :   Reserved.set(AMDGPU::ALU_LITERAL_X);
      42        4114 :   Reserved.set(AMDGPU::ALU_CONST);
      43        4114 :   Reserved.set(AMDGPU::PREDICATE_BIT);
      44        4114 :   Reserved.set(AMDGPU::PRED_SEL_OFF);
      45        4114 :   Reserved.set(AMDGPU::PRED_SEL_ZERO);
      46        4114 :   Reserved.set(AMDGPU::PRED_SEL_ONE);
      47        4114 :   Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
      48             : 
      49      534820 :   for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
      50        8228 :                         E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
      51     1053184 :     Reserved.set(*I);
      52             :   }
      53             : 
      54        4114 :   TII->reserveIndirectRegisters(Reserved, MF);
      55             : 
      56        4114 :   return Reserved;
      57             : }
      58             : 
      59             : // Dummy to not crash RegisterClassInfo.
      60             : static const MCPhysReg CalleeSavedReg = AMDGPU::NoRegister;
      61             : 
      62       20305 : const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs(
      63             :   const MachineFunction *) const {
      64       20305 :   return &CalleeSavedReg;
      65             : }
      66             : 
      67        2342 : unsigned R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
      68        2342 :   return AMDGPU::NoRegister;
      69             : }
      70             : 
      71      393674 : unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
      72      787348 :   return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
      73             : }
      74             : 
      75      197320 : unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
      76      394640 :   return GET_REG_INDEX(getEncodingValue(Reg));
      77             : }
      78             : 
      79           1 : const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
      80             :                                                                    MVT VT) const {
      81             :   switch(VT.SimpleTy) {
      82             :   default:
      83           1 :   case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
      84             :   }
      85             : }
      86             : 
      87      410077 : const RegClassWeight &R600RegisterInfo::getRegClassWeight(
      88             :   const TargetRegisterClass *RC) const {
      89      410077 :   return RCW;
      90             : }
      91             : 
      92       44301 : bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
      93             :   assert(!TargetRegisterInfo::isVirtualRegister(Reg));
      94             : 
      95             :   switch (Reg) {
      96             :   case AMDGPU::OQAP:
      97             :   case AMDGPU::OQBP:
      98             :   case AMDGPU::AR_X:
      99             :     return false;
     100       44069 :   default:
     101       44069 :     return true;
     102             :   }
     103             : }
     104             : 
     105           0 : void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
     106             :                                            int SPAdj,
     107             :                                            unsigned FIOperandNum,
     108             :                                            RegScavenger *RS) const {
     109           0 :   llvm_unreachable("Subroutines not supported yet");
     110             : }

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