LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - R600RegisterInfo.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 1 1 100.0 %
Date: 2017-09-14 15:23:50 Functions: 0 2 0.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// \brief Interface definition for R600RegisterInfo
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #ifndef LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
      16             : #define LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
      17             : 
      18             : #include "AMDGPURegisterInfo.h"
      19             : 
      20             : namespace llvm {
      21             : 
      22             : class AMDGPUSubtarget;
      23             : 
      24         504 : struct R600RegisterInfo final : public AMDGPURegisterInfo {
      25             :   RegClassWeight RCW;
      26             : 
      27             :   R600RegisterInfo();
      28             : 
      29             :   BitVector getReservedRegs(const MachineFunction &MF) const override;
      30             :   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
      31             :   unsigned getFrameRegister(const MachineFunction &MF) const override;
      32             : 
      33             :   /// \brief get the HW encoding for a register's channel.
      34             :   unsigned getHWRegChan(unsigned reg) const;
      35             : 
      36             :   unsigned getHWRegIndex(unsigned Reg) const;
      37             : 
      38             :   /// \brief get the register class of the specified type to use in the
      39             :   /// CFGStructurizer
      40             :   const TargetRegisterClass *getCFGStructurizerRegClass(MVT VT) const;
      41             : 
      42             :   const RegClassWeight &
      43             :     getRegClassWeight(const TargetRegisterClass *RC) const override;
      44             : 
      45             :   // \returns true if \p Reg can be defined in one ALU clause and used in
      46             :   // another.
      47             :   bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
      48             : 
      49             :   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
      50             :                            unsigned FIOperandNum,
      51             :                            RegScavenger *RS = nullptr) const override;
      52             : };
      53             : 
      54             : } // End namespace llvm
      55             : 
      56             : #endif

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