LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - SIFixVGPRCopies.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 20 20 100.0 %
Date: 2017-09-14 15:23:50 Functions: 6 7 85.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- SIFixVGPRCopies.cpp - Fix VGPR Copies after regalloc --------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// \brief Add implicit use of exec to vector register copies.
      12             : ///
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "AMDGPU.h"
      16             : #include "AMDGPUSubtarget.h"
      17             : #include "SIInstrInfo.h"
      18             : #include "llvm/CodeGen/MachineFunctionPass.h"
      19             : 
      20             : using namespace llvm;
      21             : 
      22             : #define DEBUG_TYPE "si-fix-vgpr-copies"
      23             : 
      24             : namespace {
      25             : 
      26        1460 : class SIFixVGPRCopies : public MachineFunctionPass {
      27             : public:
      28             :   static char ID;
      29             : 
      30             : public:
      31        1468 :   SIFixVGPRCopies() : MachineFunctionPass(ID) {
      32        1468 :     initializeSIFixVGPRCopiesPass(*PassRegistry::getPassRegistry());
      33        1468 :   }
      34             : 
      35             :   bool runOnMachineFunction(MachineFunction &MF) override;
      36             : 
      37        1463 :   StringRef getPassName() const override { return "SI Fix VGPR copies"; }
      38             : };
      39             : 
      40             : } // End anonymous namespace.
      41             : 
      42      316942 : INITIALIZE_PASS(SIFixVGPRCopies, DEBUG_TYPE, "SI Fix VGPR copies", false, false)
      43             : 
      44             : char SIFixVGPRCopies::ID = 0;
      45             : 
      46             : char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopies::ID;
      47             : 
      48       14834 : bool SIFixVGPRCopies::runOnMachineFunction(MachineFunction &MF) {
      49       14834 :   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
      50       14834 :   const SIRegisterInfo *TRI = ST.getRegisterInfo();
      51       14834 :   const SIInstrInfo *TII = ST.getInstrInfo();
      52       14834 :   bool Changed = false;
      53             : 
      54       61428 :   for (MachineBasicBlock &MBB : MF) {
      55      573790 :     for (MachineInstr &MI : MBB) {
      56      253043 :       switch (MI.getOpcode()) {
      57       39931 :       case AMDGPU::COPY:
      58       68648 :         if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) {
      59       28716 :           MI.addOperand(MF,
      60       57432 :                         MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
      61             :           DEBUG(dbgs() << "Add exec use to " << MI);
      62       28716 :           Changed = true;
      63             :         }
      64             :         break;
      65             :       default:
      66             :         break;
      67             :       }
      68             :     }
      69             :   }
      70             : 
      71       14834 :   return Changed;
      72             : }

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