LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - SILowerI1Copies.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 81 82 98.8 %
Date: 2017-09-14 15:23:50 Functions: 7 9 77.8 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- SILowerI1Copies.cpp - Lower I1 Copies -----------------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : /// i1 values are usually inserted by the CFG Structurize pass and they are
       9             : /// unique in that they can be copied from VALU to SALU registers.
      10             : /// This is not possible for any other value type.  Since there are no
      11             : /// MOV instructions for i1, we to use V_CMP_* and V_CNDMASK to move the i1.
      12             : ///
      13             : //===----------------------------------------------------------------------===//
      14             : //
      15             : 
      16             : #define DEBUG_TYPE "si-i1-copies"
      17             : #include "AMDGPU.h"
      18             : #include "AMDGPUSubtarget.h"
      19             : #include "SIInstrInfo.h"
      20             : #include "llvm/CodeGen/LiveIntervalAnalysis.h"
      21             : #include "llvm/CodeGen/MachineFunctionPass.h"
      22             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      23             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      24             : #include "llvm/IR/Function.h"
      25             : #include "llvm/IR/LLVMContext.h"
      26             : #include "llvm/Support/Debug.h"
      27             : #include "llvm/Target/TargetMachine.h"
      28             : 
      29             : using namespace llvm;
      30             : 
      31             : namespace {
      32             : 
      33        1455 : class SILowerI1Copies : public MachineFunctionPass {
      34             : public:
      35             :   static char ID;
      36             : 
      37             : public:
      38        1463 :   SILowerI1Copies() : MachineFunctionPass(ID) {
      39        1463 :     initializeSILowerI1CopiesPass(*PassRegistry::getPassRegistry());
      40        1463 :   }
      41             : 
      42             :   bool runOnMachineFunction(MachineFunction &MF) override;
      43             : 
      44           0 :   StringRef getPassName() const override { return "SI Lower i1 Copies"; }
      45             : 
      46        1457 :   void getAnalysisUsage(AnalysisUsage &AU) const override {
      47        1457 :     AU.setPreservesCFG();
      48        1457 :     MachineFunctionPass::getAnalysisUsage(AU);
      49        1457 :   }
      50             : };
      51             : 
      52             : } // End anonymous namespace.
      53             : 
      54      316927 : INITIALIZE_PASS(SILowerI1Copies, DEBUG_TYPE,
      55             :                 "SI Lower i1 Copies", false, false)
      56             : 
      57             : char SILowerI1Copies::ID = 0;
      58             : 
      59             : char &llvm::SILowerI1CopiesID = SILowerI1Copies::ID;
      60             : 
      61        1463 : FunctionPass *llvm::createSILowerI1CopiesPass() {
      62        1463 :   return new SILowerI1Copies();
      63             : }
      64             : 
      65       14813 : bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
      66       14813 :   MachineRegisterInfo &MRI = MF.getRegInfo();
      67       14813 :   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
      68       14813 :   const SIInstrInfo *TII = ST.getInstrInfo();
      69       14813 :   const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
      70             : 
      71       29626 :   std::vector<unsigned> I1Defs;
      72             : 
      73       29626 :   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
      74       31610 :                                                   BI != BE; ++BI) {
      75             : 
      76       16797 :     MachineBasicBlock &MBB = *BI;
      77       33594 :     MachineBasicBlock::iterator I, Next;
      78      963453 :     for (I = MBB.begin(); I != MBB.end(); I = Next) {
      79      456531 :       Next = std::next(I);
      80      456531 :       MachineInstr &MI = *I;
      81             : 
      82      456531 :       if (MI.getOpcode() == AMDGPU::IMPLICIT_DEF) {
      83        5642 :         unsigned Reg = MI.getOperand(0).getReg();
      84        5642 :         const TargetRegisterClass *RC = MRI.getRegClass(Reg);
      85        5642 :         if (RC == &AMDGPU::VReg_1RegClass)
      86           6 :           MRI.setRegClass(Reg, &AMDGPU::SReg_64RegClass);
      87      315441 :         continue;
      88             :       }
      89             : 
      90      450889 :       if (MI.getOpcode() != AMDGPU::COPY)
      91      277390 :         continue;
      92             : 
      93      173499 :       const MachineOperand &Dst = MI.getOperand(0);
      94      346998 :       const MachineOperand &Src = MI.getOperand(1);
      95             : 
      96      498695 :       if (!TargetRegisterInfo::isVirtualRegister(Src.getReg()) ||
      97      303394 :           !TargetRegisterInfo::isVirtualRegister(Dst.getReg()))
      98       26681 :         continue;
      99             : 
     100      293636 :       const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg());
     101      293636 :       const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg());
     102             : 
     103      440368 :       DebugLoc DL = MI.getDebugLoc();
     104      146818 :       MachineInstr *DefInst = MRI.getUniqueVRegDef(Src.getReg());
     105      146970 :       if (DstRC == &AMDGPU::VReg_1RegClass &&
     106         152 :           TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) {
     107         304 :         I1Defs.push_back(Dst.getReg());
     108             : 
     109         304 :         if (DefInst->getOpcode() == AMDGPU::S_MOV_B64) {
     110         172 :           if (DefInst->getOperand(1).isImm()) {
     111         172 :             I1Defs.push_back(Dst.getReg());
     112             : 
     113          86 :             int64_t Val = DefInst->getOperand(1).getImm();
     114             :             assert(Val == 0 || Val == -1);
     115             : 
     116         258 :             BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_MOV_B32_e32))
     117          86 :                 .add(Dst)
     118          86 :                 .addImm(Val);
     119          86 :             MI.eraseFromParent();
     120          86 :             continue;
     121             :           }
     122             :         }
     123             : 
     124         198 :         BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64))
     125          66 :             .add(Dst)
     126          66 :             .addImm(0)
     127          66 :             .addImm(-1)
     128          66 :             .add(Src);
     129          66 :         MI.eraseFromParent();
     130      148123 :       } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
     131             :                  SrcRC == &AMDGPU::VReg_1RegClass) {
     132          69 :         if (DefInst->getOpcode() == AMDGPU::V_CNDMASK_B32_e64 &&
     133          70 :             DefInst->getOperand(1).isImm() && DefInst->getOperand(2).isImm() &&
     134          28 :             DefInst->getOperand(1).getImm() == 0 &&
     135          28 :             DefInst->getOperand(2).getImm() != 0 &&
     136          42 :             DefInst->getOperand(3).isReg() &&
     137          28 :             TargetRegisterInfo::isVirtualRegister(
     138          83 :               DefInst->getOperand(3).getReg()) &&
     139          28 :             TRI->getCommonSubClass(
     140          14 :               MRI.getRegClass(DefInst->getOperand(3).getReg()),
     141             :               &AMDGPU::SGPR_64RegClass)) {
     142          56 :           BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_B64))
     143          14 :               .add(Dst)
     144          14 :               .addReg(AMDGPU::EXEC)
     145          42 :               .add(DefInst->getOperand(3));
     146             :         } else {
     147         123 :           BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64))
     148          41 :               .add(Dst)
     149          41 :               .add(Src)
     150          41 :               .addImm(0);
     151             :         }
     152          55 :         MI.eraseFromParent();
     153             :       }
     154             :     }
     155             :   }
     156             : 
     157       59490 :   for (unsigned Reg : I1Defs)
     158         238 :     MRI.setRegClass(Reg, &AMDGPU::VGPR_32RegClass);
     159             : 
     160       29626 :   return false;
     161             : }

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