LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU - SIRegisterInfo.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 16 16 100.0 %
Date: 2017-09-14 15:23:50 Functions: 3 4 75.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// \brief Interface definition for SIRegisterInfo
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
      16             : #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
      17             : 
      18             : #include "AMDGPURegisterInfo.h"
      19             : #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
      20             : #include "SIDefines.h"
      21             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      22             : 
      23             : namespace llvm {
      24             : 
      25             : class MachineRegisterInfo;
      26             : class SISubtarget;
      27             : class SIMachineFunctionInfo;
      28             : 
      29        7152 : class SIRegisterInfo final : public AMDGPURegisterInfo {
      30             : private:
      31             :   unsigned SGPRSetID;
      32             :   unsigned VGPRSetID;
      33             :   BitVector SGPRPressureSets;
      34             :   BitVector VGPRPressureSets;
      35             :   bool SpillSGPRToVGPR;
      36             :   bool SpillSGPRToSMEM;
      37             : 
      38             :   void reserveRegisterTuples(BitVector &, unsigned Reg) const;
      39             :   void classifyPressureSet(unsigned PSetID, unsigned Reg,
      40             :                            BitVector &PressureSets) const;
      41             : public:
      42             :   SIRegisterInfo(const SISubtarget &ST);
      43             : 
      44             :   bool spillSGPRToVGPR() const {
      45             :     return SpillSGPRToVGPR;
      46             :   }
      47             : 
      48             :   bool spillSGPRToSMEM() const {
      49             :     return SpillSGPRToSMEM;
      50             :   }
      51             : 
      52             :   /// Return the end register initially reserved for the scratch buffer in case
      53             :   /// spilling is needed.
      54             :   unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
      55             : 
      56             :   /// Return the end register initially reserved for the scratch wave offset in
      57             :   /// case spilling is needed.
      58             :   unsigned reservedPrivateSegmentWaveByteOffsetReg(
      59             :     const MachineFunction &MF) const;
      60             : 
      61             :   unsigned reservedStackPtrOffsetReg(const MachineFunction &MF) const;
      62             : 
      63             :   BitVector getReservedRegs(const MachineFunction &MF) const override;
      64             : 
      65             :   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
      66             :   const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
      67             :   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
      68             :                                        CallingConv::ID) const override;
      69             : 
      70             :   // Stack access is very expensive. CSRs are also the high registers, and we
      71             :   // want to minimize the number of used registers.
      72       14663 :   unsigned getCSRFirstUseCost() const override {
      73       14663 :     return 100;
      74             :   }
      75             : 
      76             :   unsigned getFrameRegister(const MachineFunction &MF) const override;
      77             : 
      78             :   bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
      79             : 
      80             :   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
      81             :   bool requiresFrameIndexReplacementScavenging(
      82             :     const MachineFunction &MF) const override;
      83             :   bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
      84             :   bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
      85             : 
      86             :   int64_t getMUBUFInstrOffset(const MachineInstr *MI) const;
      87             : 
      88             :   int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
      89             :                                    int Idx) const override;
      90             : 
      91             :   bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
      92             : 
      93             :   void materializeFrameBaseRegister(MachineBasicBlock *MBB,
      94             :                                     unsigned BaseReg, int FrameIdx,
      95             :                                     int64_t Offset) const override;
      96             : 
      97             :   void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
      98             :                          int64_t Offset) const override;
      99             : 
     100             :   bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
     101             :                           int64_t Offset) const override;
     102             : 
     103             :   const TargetRegisterClass *getPointerRegClass(
     104             :     const MachineFunction &MF, unsigned Kind = 0) const override;
     105             : 
     106             :   /// If \p OnlyToVGPR is true, this will only succeed if this
     107             :   bool spillSGPR(MachineBasicBlock::iterator MI,
     108             :                  int FI, RegScavenger *RS,
     109             :                  bool OnlyToVGPR = false) const;
     110             : 
     111             :   bool restoreSGPR(MachineBasicBlock::iterator MI,
     112             :                    int FI, RegScavenger *RS,
     113             :                    bool OnlyToVGPR = false) const;
     114             : 
     115             :   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
     116             :                            unsigned FIOperandNum,
     117             :                            RegScavenger *RS) const override;
     118             : 
     119             :   bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI,
     120             :                                           int FI, RegScavenger *RS) const;
     121             : 
     122             :   StringRef getRegAsmName(unsigned Reg) const override;
     123             : 
     124             :   unsigned getHWRegIndex(unsigned Reg) const {
     125      102088 :     return getEncodingValue(Reg) & 0xff;
     126             :   }
     127             : 
     128             :   /// \brief Return the 'base' register class for this register.
     129             :   /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
     130             :   const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
     131             : 
     132             :   /// \returns true if this class contains only SGPR registers
     133             :   bool isSGPRClass(const TargetRegisterClass *RC) const {
     134     5318186 :     return !hasVGPRs(RC);
     135             :   }
     136             : 
     137             :   /// \returns true if this class ID contains only SGPR registers
     138             :   bool isSGPRClassID(unsigned RCID) const {
     139             :     return isSGPRClass(getRegClass(RCID));
     140             :   }
     141             : 
     142     1222473 :   bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const {
     143             :     const TargetRegisterClass *RC;
     144     1222473 :     if (TargetRegisterInfo::isVirtualRegister(Reg))
     145      495476 :       RC = MRI.getRegClass(Reg);
     146             :     else
     147      726997 :       RC = getPhysRegClass(Reg);
     148     1222473 :     return isSGPRClass(RC);
     149             :   }
     150             : 
     151             :   /// \returns true if this class contains VGPR registers.
     152             :   bool hasVGPRs(const TargetRegisterClass *RC) const;
     153             : 
     154             :   /// \returns A VGPR reg class with the same width as \p SRC
     155             :   const TargetRegisterClass *getEquivalentVGPRClass(
     156             :                                           const TargetRegisterClass *SRC) const;
     157             : 
     158             :   /// \returns A SGPR reg class with the same width as \p SRC
     159             :   const TargetRegisterClass *getEquivalentSGPRClass(
     160             :                                            const TargetRegisterClass *VRC) const;
     161             : 
     162             :   /// \returns The register class that is used for a sub-register of \p RC for
     163             :   /// the given \p SubIdx.  If \p SubIdx equals NoSubRegister, \p RC will
     164             :   /// be returned.
     165             :   const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
     166             :                                             unsigned SubIdx) const;
     167             : 
     168             :   bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
     169             :                             unsigned DefSubReg,
     170             :                             const TargetRegisterClass *SrcRC,
     171             :                             unsigned SrcSubReg) const override;
     172             : 
     173             :   /// \returns True if operands defined with this operand type can accept
     174             :   /// a literal constant (i.e. any 32-bit immediate).
     175             :   bool opCanUseLiteralConstant(unsigned OpType) const {
     176             :     // TODO: 64-bit operands have extending behavior from 32-bit literal.
     177       23359 :     return OpType >= AMDGPU::OPERAND_REG_IMM_FIRST &&
     178       23359 :            OpType <= AMDGPU::OPERAND_REG_IMM_LAST;
     179             :   }
     180             : 
     181             :   /// \returns True if operands defined with this operand type can accept
     182             :   /// an inline constant. i.e. An integer value in the range (-16, 64) or
     183             :   /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
     184             :   bool opCanUseInlineConstant(unsigned OpType) const {
     185       45545 :     return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
     186       45545 :            OpType <= AMDGPU::OPERAND_SRC_LAST;
     187             :   }
     188             : 
     189             :   unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
     190             :                               const TargetRegisterClass *RC,
     191             :                               const MachineFunction &MF) const;
     192             : 
     193             :   unsigned getSGPRPressureSet() const { return SGPRSetID; };
     194             :   unsigned getVGPRPressureSet() const { return VGPRSetID; };
     195             : 
     196             :   const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
     197             :                                                unsigned Reg) const;
     198             :   bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
     199             : 
     200             :   bool isSGPRPressureSet(unsigned SetID) const {
     201      107760 :     return SGPRPressureSets.test(SetID) && !VGPRPressureSets.test(SetID);
     202             :   }
     203             :   bool isVGPRPressureSet(unsigned SetID) const {
     204       98780 :     return VGPRPressureSets.test(SetID) && !SGPRPressureSets.test(SetID);
     205             :   }
     206             : 
     207             :   ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC,
     208             :                                      unsigned EltSize) const;
     209             : 
     210             :   bool shouldCoalesce(MachineInstr *MI,
     211             :                       const TargetRegisterClass *SrcRC,
     212             :                       unsigned SubReg,
     213             :                       const TargetRegisterClass *DstRC,
     214             :                       unsigned DstSubReg,
     215             :                       const TargetRegisterClass *NewRC) const override;
     216             : 
     217             :   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
     218             :                                MachineFunction &MF) const override;
     219             : 
     220             :   unsigned getRegPressureSetLimit(const MachineFunction &MF,
     221             :                                   unsigned Idx) const override;
     222             : 
     223             :   const int *getRegUnitPressureSets(unsigned RegUnit) const override;
     224             : 
     225             :   unsigned getReturnAddressReg(const MachineFunction &MF) const {
     226             :     // Not a callee saved register.
     227             :     return AMDGPU::SGPR30_SGPR31;
     228             :   }
     229             : 
     230             : private:
     231             :   void buildSpillLoadStore(MachineBasicBlock::iterator MI,
     232             :                            unsigned LoadStoreOp,
     233             :                            int Index,
     234             :                            unsigned ValueReg,
     235             :                            bool ValueIsKill,
     236             :                            unsigned ScratchRsrcReg,
     237             :                            unsigned ScratchOffsetReg,
     238             :                            int64_t InstrOffset,
     239             :                            MachineMemOperand *MMO,
     240             :                            RegScavenger *RS) const;
     241             : };
     242             : 
     243             : } // End namespace llvm
     244             : 
     245             : #endif

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