LCOV - code coverage report
Current view: top level - lib/Target/AMDGPU/Utils - AMDGPUBaseInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 359 384 93.5 %
Date: 2018-02-21 06:32:55 Functions: 79 83 95.2 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : 
      10             : #include "AMDGPUBaseInfo.h"
      11             : #include "AMDGPU.h"
      12             : #include "SIDefines.h"
      13             : #include "llvm/ADT/StringRef.h"
      14             : #include "llvm/ADT/Triple.h"
      15             : #include "llvm/BinaryFormat/ELF.h"
      16             : #include "llvm/CodeGen/MachineMemOperand.h"
      17             : #include "llvm/IR/Attributes.h"
      18             : #include "llvm/IR/Constants.h"
      19             : #include "llvm/IR/Function.h"
      20             : #include "llvm/IR/GlobalValue.h"
      21             : #include "llvm/IR/Instruction.h"
      22             : #include "llvm/IR/LLVMContext.h"
      23             : #include "llvm/IR/Module.h"
      24             : #include "llvm/MC/MCContext.h"
      25             : #include "llvm/MC/MCInstrDesc.h"
      26             : #include "llvm/MC/MCInstrInfo.h"
      27             : #include "llvm/MC/MCRegisterInfo.h"
      28             : #include "llvm/MC/MCSectionELF.h"
      29             : #include "llvm/MC/MCSubtargetInfo.h"
      30             : #include "llvm/MC/SubtargetFeature.h"
      31             : #include "llvm/Support/Casting.h"
      32             : #include "llvm/Support/ErrorHandling.h"
      33             : #include "llvm/Support/MathExtras.h"
      34             : #include <algorithm>
      35             : #include <cassert>
      36             : #include <cstdint>
      37             : #include <cstring>
      38             : #include <utility>
      39             : 
      40             : #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
      41             : 
      42             : #define GET_INSTRINFO_NAMED_OPS
      43             : #define GET_INSTRMAP_INFO
      44             : #include "AMDGPUGenInstrInfo.inc"
      45             : #undef GET_INSTRMAP_INFO
      46             : #undef GET_INSTRINFO_NAMED_OPS
      47             : 
      48             : namespace {
      49             : 
      50             : /// \returns Bit mask for given bit \p Shift and bit \p Width.
      51             : unsigned getBitMask(unsigned Shift, unsigned Width) {
      52             :   return ((1 << Width) - 1) << Shift;
      53             : }
      54             : 
      55             : /// \brief Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
      56             : ///
      57             : /// \returns Packed \p Dst.
      58             : unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
      59      168526 :   Dst &= ~(1 << Shift) & ~getBitMask(Shift, Width);
      60      168526 :   Dst |= (Src << Shift) & getBitMask(Shift, Width);
      61             :   return Dst;
      62             : }
      63             : 
      64             : /// \brief Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
      65             : ///
      66             : /// \returns Unpacked bits.
      67             : unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
      68      128202 :   return (Src & getBitMask(Shift, Width)) >> Shift;
      69             : }
      70             : 
      71             : /// \returns Vmcnt bit shift (lower bits).
      72             : unsigned getVmcntBitShiftLo() { return 0; }
      73             : 
      74             : /// \returns Vmcnt bit width (lower bits).
      75             : unsigned getVmcntBitWidthLo() { return 4; }
      76             : 
      77             : /// \returns Expcnt bit shift.
      78             : unsigned getExpcntBitShift() { return 4; }
      79             : 
      80             : /// \returns Expcnt bit width.
      81             : unsigned getExpcntBitWidth() { return 3; }
      82             : 
      83             : /// \returns Lgkmcnt bit shift.
      84             : unsigned getLgkmcntBitShift() { return 8; }
      85             : 
      86             : /// \returns Lgkmcnt bit width.
      87             : unsigned getLgkmcntBitWidth() { return 4; }
      88             : 
      89             : /// \returns Vmcnt bit shift (higher bits).
      90             : unsigned getVmcntBitShiftHi() { return 14; }
      91             : 
      92             : /// \returns Vmcnt bit width (higher bits).
      93             : unsigned getVmcntBitWidthHi() { return 2; }
      94             : 
      95             : } // end namespace anonymous
      96             : 
      97             : namespace llvm {
      98             : 
      99       97171 : static cl::opt<bool> EnablePackedInlinableLiterals(
     100             :     "enable-packed-inlinable-literals",
     101       97171 :     cl::desc("Enable packed inlinable literals (v2f16, v2i16)"),
     102      291513 :     cl::init(false));
     103             : 
     104             : namespace AMDGPU {
     105             : 
     106             : LLVM_READNONE
     107             : static inline Channels indexToChannel(unsigned Channel) {
     108         113 :   switch (Channel) {
     109             :   case 1:
     110             :     return AMDGPU::Channels_1;
     111          29 :   case 2:
     112             :     return AMDGPU::Channels_2;
     113          31 :   case 3:
     114             :     return AMDGPU::Channels_3;
     115           7 :   case 4:
     116             :     return AMDGPU::Channels_4;
     117           0 :   default:
     118           0 :     llvm_unreachable("invalid MIMG channel");
     119             :   }
     120             : }
     121             : 
     122             : 
     123             : // FIXME: Need to handle d16 images correctly.
     124             : static unsigned rcToChannels(unsigned RCID) {
     125         121 :   switch (RCID) {
     126             :   case AMDGPU::VGPR_32RegClassID:
     127             :     return 1;
     128           8 :   case AMDGPU::VReg_64RegClassID:
     129             :     return 2;
     130           0 :   case AMDGPU::VReg_96RegClassID:
     131             :     return 3;
     132          73 :   case AMDGPU::VReg_128RegClassID:
     133             :     return 4;
     134           0 :   default:
     135           0 :     llvm_unreachable("invalid MIMG register class");
     136             :   }
     137             : }
     138             : 
     139         113 : int getMaskedMIMGOp(const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels) {
     140             :   AMDGPU::Channels Channel = AMDGPU::indexToChannel(NewChannels);
     141         226 :   unsigned OrigChannels = rcToChannels(MII.get(Opc).OpInfo[0].RegClass);
     142         113 :   if (NewChannels == OrigChannels)
     143           3 :     return Opc;
     144             : 
     145         110 :   switch (OrigChannels) {
     146          33 :   case 1:
     147          33 :     return AMDGPU::getMaskedMIMGOp1(Opc, Channel);
     148           4 :   case 2:
     149           4 :     return AMDGPU::getMaskedMIMGOp2(Opc, Channel);
     150           0 :   case 3:
     151           0 :     return AMDGPU::getMaskedMIMGOp3(Opc, Channel);
     152          73 :   case 4:
     153          73 :     return AMDGPU::getMaskedMIMGOp4(Opc, Channel);
     154           0 :   default:
     155           0 :     llvm_unreachable("invalid MIMG channel");
     156             :   }
     157             : }
     158             : 
     159           8 : int getMaskedMIMGAtomicOp(const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels) {
     160             :   assert(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst) != -1);
     161             :   assert(NewChannels == 1 || NewChannels == 2 || NewChannels == 4);
     162             : 
     163          16 :   unsigned OrigChannels = rcToChannels(MII.get(Opc).OpInfo[0].RegClass);
     164             :   assert(OrigChannels == 1 || OrigChannels == 2 || OrigChannels == 4);
     165             : 
     166           8 :   if (NewChannels == OrigChannels) return Opc;
     167             : 
     168           6 :   if (OrigChannels <= 2 && NewChannels <= 2) {
     169             :     // This is an ordinary atomic (not an atomic_cmpswap)
     170           4 :     return (OrigChannels == 1)?
     171           2 :       AMDGPU::getMIMGAtomicOp1(Opc) : AMDGPU::getMIMGAtomicOp2(Opc);
     172           4 :   } else if (OrigChannels >= 2 && NewChannels >= 2) {
     173             :     // This is an atomic_cmpswap
     174           4 :     return (OrigChannels == 2)?
     175           2 :       AMDGPU::getMIMGAtomicOp1(Opc) : AMDGPU::getMIMGAtomicOp2(Opc);
     176             :   } else { // invalid OrigChannels/NewChannels value
     177             :     return -1;
     178             :   }
     179             : }
     180             : 
     181             : // Wrapper for Tablegen'd function.  enum Subtarget is not defined in any
     182             : // header files, so we need to wrap it in a function that takes unsigned
     183             : // instead.
     184     1221192 : int getMCOpcode(uint16_t Opcode, unsigned Gen) {
     185     1221192 :   return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
     186             : }
     187             : 
     188             : namespace IsaInfo {
     189             : 
     190     1178931 : IsaVersion getIsaVersion(const FeatureBitset &Features) {
     191             :   // GCN GFX6 (Southern Islands (SI)).
     192     1178931 :   if (Features.test(FeatureISAVersion6_0_0))
     193      104499 :     return {6, 0, 0};
     194     1074432 :   if (Features.test(FeatureISAVersion6_0_1))
     195       70137 :     return {6, 0, 1};
     196             : 
     197             :   // GCN GFX7 (Sea Islands (CI)).
     198     1004295 :   if (Features.test(FeatureISAVersion7_0_0))
     199       49587 :     return {7, 0, 0};
     200      954708 :   if (Features.test(FeatureISAVersion7_0_1))
     201       25775 :     return {7, 0, 1};
     202      928933 :   if (Features.test(FeatureISAVersion7_0_2))
     203          63 :     return {7, 0, 2};
     204      928870 :   if (Features.test(FeatureISAVersion7_0_3))
     205         635 :     return {7, 0, 3};
     206      928235 :   if (Features.test(FeatureISAVersion7_0_4))
     207       74912 :     return {7, 0, 4};
     208             : 
     209             :   // GCN GFX8 (Volcanic Islands (VI)).
     210      853323 :   if (Features.test(FeatureISAVersion8_0_1))
     211        3805 :     return {8, 0, 1};
     212      849518 :   if (Features.test(FeatureISAVersion8_0_2))
     213      248333 :     return {8, 0, 2};
     214      601185 :   if (Features.test(FeatureISAVersion8_0_3))
     215      132176 :     return {8, 0, 3};
     216      469009 :   if (Features.test(FeatureISAVersion8_1_0))
     217        3607 :     return {8, 1, 0};
     218             : 
     219             :   // GCN GFX9.
     220      465402 :   if (Features.test(FeatureISAVersion9_0_0))
     221      189628 :     return {9, 0, 0};
     222      275774 :   if (Features.test(FeatureISAVersion9_0_2))
     223          63 :     return {9, 0, 2};
     224             : 
     225      550682 :   if (!Features.test(FeatureGCN) || Features.test(FeatureSouthernIslands))
     226         962 :     return {0, 0, 0};
     227      274749 :   return {7, 0, 0};
     228             : }
     229             : 
     230        1692 : void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream) {
     231        1692 :   auto TargetTriple = STI->getTargetTriple();
     232        1692 :   auto ISAVersion = IsaInfo::getIsaVersion(STI->getFeatureBits());
     233             : 
     234        1692 :   Stream << TargetTriple.getArchName() << '-'
     235        1692 :          << TargetTriple.getVendorName() << '-'
     236        1692 :          << TargetTriple.getOSName() << '-'
     237        1692 :          << TargetTriple.getEnvironmentName() << '-'
     238        1692 :          << "gfx"
     239        1692 :          << ISAVersion.Major
     240        1692 :          << ISAVersion.Minor
     241        1692 :          << ISAVersion.Stepping;
     242             :   Stream.flush();
     243        1692 : }
     244             : 
     245         295 : bool hasCodeObjectV3(const FeatureBitset &Features) {
     246         295 :   return Features.test(FeatureCodeObjectV3);
     247             : }
     248             : 
     249      367244 : unsigned getWavefrontSize(const FeatureBitset &Features) {
     250      367244 :   if (Features.test(FeatureWavefrontSize16))
     251             :     return 16;
     252      367244 :   if (Features.test(FeatureWavefrontSize32))
     253             :     return 32;
     254             : 
     255      367226 :   return 64;
     256             : }
     257             : 
     258           0 : unsigned getLocalMemorySize(const FeatureBitset &Features) {
     259           0 :   if (Features.test(FeatureLocalMemorySize32768))
     260             :     return 32768;
     261           0 :   if (Features.test(FeatureLocalMemorySize65536))
     262             :     return 65536;
     263             : 
     264           0 :   return 0;
     265             : }
     266             : 
     267       66686 : unsigned getEUsPerCU(const FeatureBitset &Features) {
     268       66686 :   return 4;
     269             : }
     270             : 
     271      154172 : unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features,
     272             :                                unsigned FlatWorkGroupSize) {
     273      154172 :   if (!Features.test(FeatureGCN))
     274             :     return 8;
     275      150279 :   unsigned N = getWavesPerWorkGroup(Features, FlatWorkGroupSize);
     276      150279 :   if (N == 1)
     277             :     return 40;
     278      142186 :   N = 40 / N;
     279      284372 :   return std::min(N, 16u);
     280             : }
     281             : 
     282           0 : unsigned getMaxWavesPerCU(const FeatureBitset &Features) {
     283           0 :   return getMaxWavesPerEU(Features) * getEUsPerCU(Features);
     284             : }
     285             : 
     286       33343 : unsigned getMaxWavesPerCU(const FeatureBitset &Features,
     287             :                           unsigned FlatWorkGroupSize) {
     288       33343 :   return getWavesPerWorkGroup(Features, FlatWorkGroupSize);
     289             : }
     290             : 
     291       33343 : unsigned getMinWavesPerEU(const FeatureBitset &Features) {
     292       33343 :   return 1;
     293             : }
     294             : 
     295      301449 : unsigned getMaxWavesPerEU(const FeatureBitset &Features) {
     296      301449 :   if (!Features.test(FeatureGCN))
     297             :     return 8;
     298             :   // FIXME: Need to take scratch memory into account.
     299      289790 :   return 10;
     300             : }
     301             : 
     302       33343 : unsigned getMaxWavesPerEU(const FeatureBitset &Features,
     303             :                           unsigned FlatWorkGroupSize) {
     304       33343 :   return alignTo(getMaxWavesPerCU(Features, FlatWorkGroupSize),
     305       66686 :                  getEUsPerCU(Features)) / getEUsPerCU(Features);
     306             : }
     307             : 
     308      208720 : unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features) {
     309      208720 :   return 1;
     310             : }
     311             : 
     312      208627 : unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features) {
     313      208627 :   return 2048;
     314             : }
     315             : 
     316      183622 : unsigned getWavesPerWorkGroup(const FeatureBitset &Features,
     317             :                               unsigned FlatWorkGroupSize) {
     318      367244 :   return alignTo(FlatWorkGroupSize, getWavefrontSize(Features)) /
     319      367244 :                  getWavefrontSize(Features);
     320             : }
     321             : 
     322      288709 : unsigned getSGPRAllocGranule(const FeatureBitset &Features) {
     323      288709 :   IsaVersion Version = getIsaVersion(Features);
     324      288709 :   if (Version.Major >= 8)
     325             :     return 16;
     326      137439 :   return 8;
     327             : }
     328             : 
     329       30812 : unsigned getSGPREncodingGranule(const FeatureBitset &Features) {
     330       30812 :   return 8;
     331             : }
     332             : 
     333      288709 : unsigned getTotalNumSGPRs(const FeatureBitset &Features) {
     334      288709 :   IsaVersion Version = getIsaVersion(Features);
     335      288709 :   if (Version.Major >= 8)
     336             :     return 800;
     337      137439 :   return 512;
     338             : }
     339             : 
     340      320696 : unsigned getAddressableNumSGPRs(const FeatureBitset &Features) {
     341      320696 :   if (Features.test(FeatureSGPRInitBug))
     342             :     return FIXED_NUM_SGPRS_FOR_INIT_BUG;
     343             : 
     344      236169 :   IsaVersion Version = getIsaVersion(Features);
     345      236169 :   if (Version.Major >= 8)
     346             :     return 102;
     347      152579 :   return 104;
     348             : }
     349             : 
     350       15472 : unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
     351             :   assert(WavesPerEU != 0);
     352             : 
     353       15472 :   if (WavesPerEU >= getMaxWavesPerEU(Features))
     354             :     return 0;
     355             :   unsigned MinNumSGPRs =
     356         130 :       alignDown(getTotalNumSGPRs(Features) / (WavesPerEU + 1),
     357         260 :                 getSGPRAllocGranule(Features)) + 1;
     358         260 :   return std::min(MinNumSGPRs, getAddressableNumSGPRs(Features));
     359             : }
     360             : 
     361      288579 : unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,
     362             :                         bool Addressable) {
     363             :   assert(WavesPerEU != 0);
     364             : 
     365      288579 :   IsaVersion Version = getIsaVersion(Features);
     366      288579 :   unsigned MaxNumSGPRs = alignDown(getTotalNumSGPRs(Features) / WavesPerEU,
     367      577158 :                                    getSGPRAllocGranule(Features));
     368      288579 :   unsigned AddressableNumSGPRs = getAddressableNumSGPRs(Features);
     369      288579 :   if (Version.Major >= 8 && !Addressable)
     370       61901 :     AddressableNumSGPRs = 112;
     371      288579 :   return std::min(MaxNumSGPRs, AddressableNumSGPRs);
     372             : }
     373             : 
     374      168946 : unsigned getVGPRAllocGranule(const FeatureBitset &Features) {
     375      168946 :   return 4;
     376             : }
     377             : 
     378       30812 : unsigned getVGPREncodingGranule(const FeatureBitset &Features) {
     379       30812 :   return getVGPRAllocGranule(Features);
     380             : }
     381             : 
     382      292849 : unsigned getTotalNumVGPRs(const FeatureBitset &Features) {
     383      292849 :   return 256;
     384             : }
     385             : 
     386      154715 : unsigned getAddressableNumVGPRs(const FeatureBitset &Features) {
     387      154715 :   return getTotalNumVGPRs(Features);
     388             : }
     389             : 
     390       15430 : unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
     391             :   assert(WavesPerEU != 0);
     392             : 
     393       15430 :   if (WavesPerEU >= getMaxWavesPerEU(Features))
     394             :     return 0;
     395             :   unsigned MinNumVGPRs =
     396         130 :       alignDown(getTotalNumVGPRs(Features) / (WavesPerEU + 1),
     397         260 :                 getVGPRAllocGranule(Features)) + 1;
     398         260 :   return std::min(MinNumVGPRs, getAddressableNumVGPRs(Features));
     399             : }
     400             : 
     401      138004 : unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
     402             :   assert(WavesPerEU != 0);
     403             : 
     404      138004 :   unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(Features) / WavesPerEU,
     405      276008 :                                    getVGPRAllocGranule(Features));
     406      138004 :   unsigned AddressableNumVGPRs = getAddressableNumVGPRs(Features);
     407      138004 :   return std::min(MaxNumVGPRs, AddressableNumVGPRs);
     408             : }
     409             : 
     410             : } // end namespace IsaInfo
     411             : 
     412        1884 : void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
     413             :                                const FeatureBitset &Features) {
     414        1884 :   IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(Features);
     415             : 
     416        1884 :   memset(&Header, 0, sizeof(Header));
     417             : 
     418        1884 :   Header.amd_kernel_code_version_major = 1;
     419        1884 :   Header.amd_kernel_code_version_minor = 1;
     420        1884 :   Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
     421        1884 :   Header.amd_machine_version_major = ISA.Major;
     422        1884 :   Header.amd_machine_version_minor = ISA.Minor;
     423        1884 :   Header.amd_machine_version_stepping = ISA.Stepping;
     424        1884 :   Header.kernel_code_entry_byte_offset = sizeof(Header);
     425             :   // wavefront_size is specified as a power of 2: 2^6 = 64 threads.
     426        1884 :   Header.wavefront_size = 6;
     427             : 
     428             :   // If the code object does not support indirect functions, then the value must
     429             :   // be 0xffffffff.
     430        1884 :   Header.call_convention = -1;
     431             : 
     432             :   // These alignment values are specified in powers of two, so alignment =
     433             :   // 2^n.  The minimum alignment is 2^4 = 16.
     434        1884 :   Header.kernarg_segment_alignment = 4;
     435        1884 :   Header.group_segment_alignment = 4;
     436        1884 :   Header.private_segment_alignment = 4;
     437        1884 : }
     438             : 
     439         380 : bool isGroupSegment(const GlobalValue *GV) {
     440         380 :   return GV->getType()->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
     441             : }
     442             : 
     443           0 : bool isGlobalSegment(const GlobalValue *GV) {
     444           0 :   return GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
     445             : }
     446             : 
     447          37 : bool isReadOnlySegment(const GlobalValue *GV) {
     448          37 :   return GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
     449          37 :          GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT;
     450             : }
     451             : 
     452         114 : bool shouldEmitConstantsToTextSection(const Triple &TT) {
     453         114 :   return TT.getOS() != Triple::AMDHSA;
     454             : }
     455             : 
     456      209374 : int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
     457      209374 :   Attribute A = F.getFnAttribute(Name);
     458             :   int Result = Default;
     459             : 
     460      209374 :   if (A.isStringAttribute()) {
     461         209 :     StringRef Str = A.getValueAsString();
     462             :     if (Str.getAsInteger(0, Result)) {
     463          18 :       LLVMContext &Ctx = F.getContext();
     464          18 :       Ctx.emitError("can't parse integer attribute " + Name);
     465             :     }
     466             :   }
     467             : 
     468      209374 :   return Result;
     469             : }
     470             : 
     471      242063 : std::pair<int, int> getIntegerPairAttribute(const Function &F,
     472             :                                             StringRef Name,
     473             :                                             std::pair<int, int> Default,
     474             :                                             bool OnlyFirstRequired) {
     475      242063 :   Attribute A = F.getFnAttribute(Name);
     476      242063 :   if (!A.isStringAttribute())
     477      240941 :     return Default;
     478             : 
     479        1122 :   LLVMContext &Ctx = F.getContext();
     480        1122 :   std::pair<int, int> Ints = Default;
     481        1122 :   std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
     482        2244 :   if (Strs.first.trim().getAsInteger(0, Ints.first)) {
     483          20 :     Ctx.emitError("can't parse first integer attribute " + Name);
     484          20 :     return Default;
     485             :   }
     486        2168 :   if (Strs.second.trim().getAsInteger(0, Ints.second)) {
     487          42 :     if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
     488          30 :       Ctx.emitError("can't parse second integer attribute " + Name);
     489          30 :       return Default;
     490             :     }
     491             :   }
     492             : 
     493        1072 :   return Ints;
     494             : }
     495             : 
     496       57038 : unsigned getVmcntBitMask(const IsaInfo::IsaVersion &Version) {
     497             :   unsigned VmcntLo = (1 << getVmcntBitWidthLo()) - 1;
     498       57038 :   if (Version.Major < 9)
     499             :     return VmcntLo;
     500             : 
     501             :   unsigned VmcntHi = ((1 << getVmcntBitWidthHi()) - 1) << getVmcntBitWidthLo();
     502        7909 :   return VmcntLo | VmcntHi;
     503             : }
     504             : 
     505       73611 : unsigned getExpcntBitMask(const IsaInfo::IsaVersion &Version) {
     506       73611 :   return (1 << getExpcntBitWidth()) - 1;
     507             : }
     508             : 
     509       73609 : unsigned getLgkmcntBitMask(const IsaInfo::IsaVersion &Version) {
     510       73609 :   return (1 << getLgkmcntBitWidth()) - 1;
     511             : }
     512             : 
     513       53904 : unsigned getWaitcntBitMask(const IsaInfo::IsaVersion &Version) {
     514             :   unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(), getVmcntBitWidthLo());
     515             :   unsigned Expcnt = getBitMask(getExpcntBitShift(), getExpcntBitWidth());
     516             :   unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(), getLgkmcntBitWidth());
     517             :   unsigned Waitcnt = VmcntLo | Expcnt | Lgkmcnt;
     518       53904 :   if (Version.Major < 9)
     519             :     return Waitcnt;
     520             : 
     521             :   unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(), getVmcntBitWidthHi());
     522        7009 :   return Waitcnt | VmcntHi;
     523             : }
     524             : 
     525       42756 : unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
     526             :   unsigned VmcntLo =
     527             :       unpackBits(Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
     528       42756 :   if (Version.Major < 9)
     529             :     return VmcntLo;
     530             : 
     531             :   unsigned VmcntHi =
     532             :       unpackBits(Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
     533        5946 :   VmcntHi <<= getVmcntBitWidthLo();
     534        5946 :   return VmcntLo | VmcntHi;
     535             : }
     536             : 
     537       42710 : unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
     538       42710 :   return unpackBits(Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
     539             : }
     540             : 
     541       42736 : unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
     542       42736 :   return unpackBits(Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
     543             : }
     544             : 
     545       39070 : void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
     546             :                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
     547       39070 :   Vmcnt = decodeVmcnt(Version, Waitcnt);
     548       39070 :   Expcnt = decodeExpcnt(Version, Waitcnt);
     549       39070 :   Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
     550       39070 : }
     551             : 
     552       53849 : unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
     553             :                      unsigned Vmcnt) {
     554             :   Waitcnt =
     555             :       packBits(Vmcnt, Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
     556       53849 :   if (Version.Major < 9)
     557             :     return Waitcnt;
     558             : 
     559        7003 :   Vmcnt >>= getVmcntBitWidthLo();
     560        7003 :   return packBits(Vmcnt, Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
     561             : }
     562             : 
     563       53832 : unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
     564             :                       unsigned Expcnt) {
     565       53832 :   return packBits(Expcnt, Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
     566             : }
     567             : 
     568       53842 : unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
     569             :                        unsigned Lgkmcnt) {
     570       53842 :   return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
     571             : }
     572             : 
     573       53780 : unsigned encodeWaitcnt(const IsaInfo::IsaVersion &Version,
     574             :                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
     575       53780 :   unsigned Waitcnt = getWaitcntBitMask(Version);
     576       53780 :   Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
     577       53780 :   Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
     578       53780 :   Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
     579       53780 :   return Waitcnt;
     580             : }
     581             : 
     582         564 : unsigned getInitialPSInputAddr(const Function &F) {
     583         564 :   return getIntegerAttribute(F, "InitialPSInputAddr", 0);
     584             : }
     585             : 
     586      513792 : bool isShader(CallingConv::ID cc) {
     587             :   switch(cc) {
     588             :     case CallingConv::AMDGPU_VS:
     589             :     case CallingConv::AMDGPU_LS:
     590             :     case CallingConv::AMDGPU_HS:
     591             :     case CallingConv::AMDGPU_ES:
     592             :     case CallingConv::AMDGPU_GS:
     593             :     case CallingConv::AMDGPU_PS:
     594             :     case CallingConv::AMDGPU_CS:
     595             :       return true;
     596      486026 :     default:
     597      486026 :       return false;
     598             :   }
     599             : }
     600             : 
     601       88249 : bool isCompute(CallingConv::ID cc) {
     602       88249 :   return !isShader(cc) || cc == CallingConv::AMDGPU_CS;
     603             : }
     604             : 
     605       69369 : bool isEntryFunctionCC(CallingConv::ID CC) {
     606             :   switch (CC) {
     607             :   case CallingConv::AMDGPU_KERNEL:
     608             :   case CallingConv::SPIR_KERNEL:
     609             :   case CallingConv::AMDGPU_VS:
     610             :   case CallingConv::AMDGPU_GS:
     611             :   case CallingConv::AMDGPU_PS:
     612             :   case CallingConv::AMDGPU_CS:
     613             :   case CallingConv::AMDGPU_ES:
     614             :   case CallingConv::AMDGPU_HS:
     615             :   case CallingConv::AMDGPU_LS:
     616             :     return true;
     617        5559 :   default:
     618        5559 :     return false;
     619             :   }
     620             : }
     621             : 
     622         150 : bool hasXNACK(const MCSubtargetInfo &STI) {
     623         150 :   return STI.getFeatureBits()[AMDGPU::FeatureXNACK];
     624             : }
     625             : 
     626          72 : bool hasMIMG_R128(const MCSubtargetInfo &STI) {
     627          72 :   return STI.getFeatureBits()[AMDGPU::FeatureMIMG_R128];
     628             : }
     629             : 
     630         122 : bool hasPackedD16(const MCSubtargetInfo &STI) {
     631         122 :   return !STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem];
     632             : }
     633             : 
     634      232726 : bool isSI(const MCSubtargetInfo &STI) {
     635      232726 :   return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
     636             : }
     637             : 
     638      329686 : bool isCI(const MCSubtargetInfo &STI) {
     639      329686 :   return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
     640             : }
     641             : 
     642       41591 : bool isVI(const MCSubtargetInfo &STI) {
     643       41591 :   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
     644             : }
     645             : 
     646       39056 : bool isGFX9(const MCSubtargetInfo &STI) {
     647       39056 :   return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
     648             : }
     649             : 
     650       88839 : bool isGCN3Encoding(const MCSubtargetInfo &STI) {
     651       88839 :   return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding];
     652             : }
     653             : 
     654      184753 : bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
     655      184753 :   const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
     656      184753 :   const unsigned FirstSubReg = TRI->getSubReg(Reg, 1);
     657      363007 :   return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
     658      184753 :     Reg == AMDGPU::SCC;
     659             : }
     660             : 
     661        1084 : bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
     662      101280 :   for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) {
     663       49590 :     if (*R == Reg1) return true;
     664             :   }
     665        1050 :   return false;
     666             : }
     667             : 
     668             : #define MAP_REG2REG \
     669             :   using namespace AMDGPU; \
     670             :   switch(Reg) { \
     671             :   default: return Reg; \
     672             :   CASE_CI_VI(FLAT_SCR) \
     673             :   CASE_CI_VI(FLAT_SCR_LO) \
     674             :   CASE_CI_VI(FLAT_SCR_HI) \
     675             :   CASE_VI_GFX9(TTMP0) \
     676             :   CASE_VI_GFX9(TTMP1) \
     677             :   CASE_VI_GFX9(TTMP2) \
     678             :   CASE_VI_GFX9(TTMP3) \
     679             :   CASE_VI_GFX9(TTMP4) \
     680             :   CASE_VI_GFX9(TTMP5) \
     681             :   CASE_VI_GFX9(TTMP6) \
     682             :   CASE_VI_GFX9(TTMP7) \
     683             :   CASE_VI_GFX9(TTMP8) \
     684             :   CASE_VI_GFX9(TTMP9) \
     685             :   CASE_VI_GFX9(TTMP10) \
     686             :   CASE_VI_GFX9(TTMP11) \
     687             :   CASE_VI_GFX9(TTMP12) \
     688             :   CASE_VI_GFX9(TTMP13) \
     689             :   CASE_VI_GFX9(TTMP14) \
     690             :   CASE_VI_GFX9(TTMP15) \
     691             :   CASE_VI_GFX9(TTMP0_TTMP1) \
     692             :   CASE_VI_GFX9(TTMP2_TTMP3) \
     693             :   CASE_VI_GFX9(TTMP4_TTMP5) \
     694             :   CASE_VI_GFX9(TTMP6_TTMP7) \
     695             :   CASE_VI_GFX9(TTMP8_TTMP9) \
     696             :   CASE_VI_GFX9(TTMP10_TTMP11) \
     697             :   CASE_VI_GFX9(TTMP12_TTMP13) \
     698             :   CASE_VI_GFX9(TTMP14_TTMP15) \
     699             :   CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3) \
     700             :   CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7) \
     701             :   CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11) \
     702             :   CASE_VI_GFX9(TTMP12_TTMP13_TTMP14_TTMP15) \
     703             :   CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
     704             :   CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
     705             :   CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
     706             :   CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
     707             :   }
     708             : 
     709             : #define CASE_CI_VI(node) \
     710             :   assert(!isSI(STI)); \
     711             :   case node: return isCI(STI) ? node##_ci : node##_vi;
     712             : 
     713             : #define CASE_VI_GFX9(node) \
     714             :   case node: return isGFX9(STI) ? node##_gfx9 : node##_vi;
     715             : 
     716     1232763 : unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
     717     1232763 :   MAP_REG2REG
     718             : }
     719             : 
     720             : #undef CASE_CI_VI
     721             : #undef CASE_VI_GFX9
     722             : 
     723             : #define CASE_CI_VI(node)   case node##_ci: case node##_vi:   return node;
     724             : #define CASE_VI_GFX9(node) case node##_vi: case node##_gfx9: return node;
     725             : 
     726      224547 : unsigned mc2PseudoReg(unsigned Reg) {
     727      224547 :   MAP_REG2REG
     728             : }
     729             : 
     730             : #undef CASE_CI_VI
     731             : #undef CASE_VI_GFX9
     732             : #undef MAP_REG2REG
     733             : 
     734      697205 : bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
     735             :   assert(OpNo < Desc.NumOperands);
     736      697205 :   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
     737      697205 :   return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
     738      697205 :          OpType <= AMDGPU::OPERAND_SRC_LAST;
     739             : }
     740             : 
     741          62 : bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
     742             :   assert(OpNo < Desc.NumOperands);
     743          62 :   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
     744             :   switch (OpType) {
     745             :   case AMDGPU::OPERAND_REG_IMM_FP32:
     746             :   case AMDGPU::OPERAND_REG_IMM_FP64:
     747             :   case AMDGPU::OPERAND_REG_IMM_FP16:
     748             :   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
     749             :   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
     750             :   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
     751             :   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
     752             :     return true;
     753           0 :   default:
     754           0 :     return false;
     755             :   }
     756             : }
     757             : 
     758           0 : bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
     759             :   assert(OpNo < Desc.NumOperands);
     760           0 :   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
     761           0 :   return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
     762           0 :          OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST;
     763             : }
     764             : 
     765             : // Avoid using MCRegisterClass::getSize, since that function will go away
     766             : // (move from MC* level to Target* level). Return size in bits.
     767       49338 : unsigned getRegBitWidth(unsigned RCID) {
     768       49338 :   switch (RCID) {
     769             :   case AMDGPU::SGPR_32RegClassID:
     770             :   case AMDGPU::VGPR_32RegClassID:
     771             :   case AMDGPU::VS_32RegClassID:
     772             :   case AMDGPU::SReg_32RegClassID:
     773             :   case AMDGPU::SReg_32_XM0RegClassID:
     774             :     return 32;
     775       14205 :   case AMDGPU::SGPR_64RegClassID:
     776             :   case AMDGPU::VS_64RegClassID:
     777             :   case AMDGPU::SReg_64RegClassID:
     778             :   case AMDGPU::VReg_64RegClassID:
     779       14205 :     return 64;
     780         290 :   case AMDGPU::VReg_96RegClassID:
     781         290 :     return 96;
     782       18780 :   case AMDGPU::SGPR_128RegClassID:
     783             :   case AMDGPU::SReg_128RegClassID:
     784             :   case AMDGPU::VReg_128RegClassID:
     785       18780 :     return 128;
     786          75 :   case AMDGPU::SReg_256RegClassID:
     787             :   case AMDGPU::VReg_256RegClassID:
     788          75 :     return 256;
     789          23 :   case AMDGPU::SReg_512RegClassID:
     790             :   case AMDGPU::VReg_512RegClassID:
     791          23 :     return 512;
     792           0 :   default:
     793           0 :     llvm_unreachable("Unexpected register class");
     794             :   }
     795             : }
     796             : 
     797        9650 : unsigned getRegBitWidth(const MCRegisterClass &RC) {
     798       19300 :   return getRegBitWidth(RC.getID());
     799             : }
     800             : 
     801        1577 : unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
     802             :                            unsigned OpNo) {
     803             :   assert(OpNo < Desc.NumOperands);
     804        1577 :   unsigned RCID = Desc.OpInfo[OpNo].RegClass;
     805        3154 :   return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
     806             : }
     807             : 
     808       66839 : bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
     809       66839 :   if (Literal >= -16 && Literal <= 64)
     810             :     return true;
     811             : 
     812             :   uint64_t Val = static_cast<uint64_t>(Literal);
     813       31202 :   return (Val == DoubleToBits(0.0)) ||
     814       19198 :          (Val == DoubleToBits(1.0)) ||
     815       17950 :          (Val == DoubleToBits(-1.0)) ||
     816       13954 :          (Val == DoubleToBits(0.5)) ||
     817       13772 :          (Val == DoubleToBits(-0.5)) ||
     818       10470 :          (Val == DoubleToBits(2.0)) ||
     819       10288 :          (Val == DoubleToBits(-2.0)) ||
     820        8766 :          (Val == DoubleToBits(4.0)) ||
     821       36115 :          (Val == DoubleToBits(-4.0)) ||
     822        4913 :          (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
     823             : }
     824             : 
     825     4091318 : bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
     826     4091318 :   if (Literal >= -16 && Literal <= 64)
     827             :     return true;
     828             : 
     829             :   // The actual type of the operand does not seem to matter as long
     830             :   // as the bits match one of the inline immediate values.  For example:
     831             :   //
     832             :   // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
     833             :   // so it is a legal inline immediate.
     834             :   //
     835             :   // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
     836             :   // floating-point, so it is a legal inline immediate.
     837             : 
     838             :   uint32_t Val = static_cast<uint32_t>(Literal);
     839      342971 :   return (Val == FloatToBits(0.0f)) ||
     840      295077 :          (Val == FloatToBits(1.0f)) ||
     841      289272 :          (Val == FloatToBits(-1.0f)) ||
     842      276755 :          (Val == FloatToBits(0.5f)) ||
     843      275431 :          (Val == FloatToBits(-0.5f)) ||
     844      256055 :          (Val == FloatToBits(2.0f)) ||
     845      251929 :          (Val == FloatToBits(-2.0f)) ||
     846      237188 :          (Val == FloatToBits(4.0f)) ||
     847      570382 :          (Val == FloatToBits(-4.0f)) ||
     848      227411 :          (Val == 0x3e22f983 && HasInv2Pi);
     849             : }
     850             : 
     851      172767 : bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) {
     852      172767 :   if (!HasInv2Pi)
     853             :     return false;
     854             : 
     855      172567 :   if (Literal >= -16 && Literal <= 64)
     856             :     return true;
     857             : 
     858             :   uint16_t Val = static_cast<uint16_t>(Literal);
     859       34968 :   return Val == 0x3C00 || // 1.0
     860       17484 :          Val == 0xBC00 || // -1.0
     861       26470 :          Val == 0x3800 || // 0.5
     862       13235 :          Val == 0xB800 || // -0.5
     863       21360 :          Val == 0x4000 || // 2.0
     864       10680 :          Val == 0xC000 || // -2.0
     865       11454 :          Val == 0x4400 || // 4.0
     866       25768 :          Val == 0xC400 || // -4.0
     867             :          Val == 0x3118;   // 1/2pi
     868             : }
     869             : 
     870        3432 : bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi) {
     871             :   assert(HasInv2Pi);
     872             : 
     873        3432 :   if (!EnablePackedInlinableLiterals)
     874             :     return false;
     875             : 
     876        3186 :   int16_t Lo16 = static_cast<int16_t>(Literal);
     877        3186 :   int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
     878        3186 :   return Lo16 == Hi16 && isInlinableLiteral16(Lo16, HasInv2Pi);
     879             : }
     880             : 
     881        2329 : bool isArgPassedInSGPR(const Argument *A) {
     882        2329 :   const Function *F = A->getParent();
     883             : 
     884             :   // Arguments to compute shaders are never a source of divergence.
     885             :   CallingConv::ID CC = F->getCallingConv();
     886             :   switch (CC) {
     887             :   case CallingConv::AMDGPU_KERNEL:
     888             :   case CallingConv::SPIR_KERNEL:
     889             :     return true;
     890         170 :   case CallingConv::AMDGPU_VS:
     891             :   case CallingConv::AMDGPU_LS:
     892             :   case CallingConv::AMDGPU_HS:
     893             :   case CallingConv::AMDGPU_ES:
     894             :   case CallingConv::AMDGPU_GS:
     895             :   case CallingConv::AMDGPU_PS:
     896             :   case CallingConv::AMDGPU_CS:
     897             :     // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
     898             :     // Everything else is in VGPRs.
     899         340 :     return F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::InReg) ||
     900         170 :            F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::ByVal);
     901          84 :   default:
     902             :     // TODO: Should calls support inreg for SGPR inputs?
     903          84 :     return false;
     904             :   }
     905             : }
     906             : 
     907       59418 : int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
     908       59418 :   if (isGCN3Encoding(ST))
     909             :     return ByteOffset;
     910       28375 :   return ByteOffset >> 2;
     911             : }
     912             : 
     913       29421 : bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
     914       29421 :   int64_t EncodedOffset = getSMRDEncodedOffset(ST, ByteOffset);
     915       29421 :   return isGCN3Encoding(ST) ?
     916       58842 :     isUInt<20>(EncodedOffset) : isUInt<8>(EncodedOffset);
     917             : }
     918             : 
     919             : } // end namespace AMDGPU
     920             : 
     921             : } // end namespace llvm
     922             : 
     923             : namespace llvm {
     924             : namespace AMDGPU {
     925             : 
     926       32625 : AMDGPUAS getAMDGPUAS(Triple T) {
     927             :   AMDGPUAS AS;
     928             :   AS.FLAT_ADDRESS = 0;
     929             :   AS.PRIVATE_ADDRESS = 5;
     930             :   AS.REGION_ADDRESS = 2;
     931       32625 :   return AS;
     932             : }
     933             : 
     934        4285 : AMDGPUAS getAMDGPUAS(const TargetMachine &M) {
     935        8570 :   return getAMDGPUAS(M.getTargetTriple());
     936             : }
     937             : 
     938       21669 : AMDGPUAS getAMDGPUAS(const Module &M) {
     939       43338 :   return getAMDGPUAS(Triple(M.getTargetTriple()));
     940             : }
     941             : } // namespace AMDGPU
     942      291513 : } // namespace llvm

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