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Current view: top level - lib/Target/AMDGPU/Utils - AMDGPUBaseInfo.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 4 6 66.7 %
Date: 2017-09-14 15:23:50 Functions: 0 0 -
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          Line data    Source code
       1             : //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : 
      10             : #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
      11             : #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
      12             : 
      13             : #include "AMDGPU.h"
      14             : #include "AMDKernelCodeT.h"
      15             : #include "SIDefines.h"
      16             : #include "llvm/ADT/StringRef.h"
      17             : #include "llvm/IR/CallingConv.h"
      18             : #include "llvm/MC/MCInstrDesc.h"
      19             : #include "llvm/Support/Compiler.h"
      20             : #include "llvm/Support/ErrorHandling.h"
      21             : #include <cstdint>
      22             : #include <utility>
      23             : 
      24             : namespace llvm {
      25             : 
      26             : class Argument;
      27             : class FeatureBitset;
      28             : class Function;
      29             : class GlobalValue;
      30             : class MachineMemOperand;
      31             : class MCContext;
      32             : class MCRegisterClass;
      33             : class MCRegisterInfo;
      34             : class MCSection;
      35             : class MCSubtargetInfo;
      36             : class Triple;
      37             : 
      38             : namespace AMDGPU {
      39             : namespace IsaInfo {
      40             : 
      41             : enum {
      42             :   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
      43             :   // doesn't spill SGPRs as much as when 80 is set.
      44             :   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96
      45             : };
      46             : 
      47             : /// \brief Instruction set architecture version.
      48             : struct IsaVersion {
      49             :   unsigned Major;
      50             :   unsigned Minor;
      51             :   unsigned Stepping;
      52             : };
      53             : 
      54             : /// \returns Isa version for given subtarget \p Features.
      55             : IsaVersion getIsaVersion(const FeatureBitset &Features);
      56             : 
      57             : /// \returns Wavefront size for given subtarget \p Features.
      58             : unsigned getWavefrontSize(const FeatureBitset &Features);
      59             : 
      60             : /// \returns Local memory size in bytes for given subtarget \p Features.
      61             : unsigned getLocalMemorySize(const FeatureBitset &Features);
      62             : 
      63             : /// \returns Number of execution units per compute unit for given subtarget \p
      64             : /// Features.
      65             : unsigned getEUsPerCU(const FeatureBitset &Features);
      66             : 
      67             : /// \returns Maximum number of work groups per compute unit for given subtarget
      68             : /// \p Features and limited by given \p FlatWorkGroupSize.
      69             : unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features,
      70             :                                unsigned FlatWorkGroupSize);
      71             : 
      72             : /// \returns Maximum number of waves per compute unit for given subtarget \p
      73             : /// Features without any kind of limitation.
      74             : unsigned getMaxWavesPerCU(const FeatureBitset &Features);
      75             : 
      76             : /// \returns Maximum number of waves per compute unit for given subtarget \p
      77             : /// Features and limited by given \p FlatWorkGroupSize.
      78             : unsigned getMaxWavesPerCU(const FeatureBitset &Features,
      79             :                           unsigned FlatWorkGroupSize);
      80             : 
      81             : /// \returns Minimum number of waves per execution unit for given subtarget \p
      82             : /// Features.
      83             : unsigned getMinWavesPerEU(const FeatureBitset &Features);
      84             : 
      85             : /// \returns Maximum number of waves per execution unit for given subtarget \p
      86             : /// Features without any kind of limitation.
      87             : unsigned getMaxWavesPerEU(const FeatureBitset &Features);
      88             : 
      89             : /// \returns Maximum number of waves per execution unit for given subtarget \p
      90             : /// Features and limited by given \p FlatWorkGroupSize.
      91             : unsigned getMaxWavesPerEU(const FeatureBitset &Features,
      92             :                           unsigned FlatWorkGroupSize);
      93             : 
      94             : /// \returns Minimum flat work group size for given subtarget \p Features.
      95             : unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features);
      96             : 
      97             : /// \returns Maximum flat work group size for given subtarget \p Features.
      98             : unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features);
      99             : 
     100             : /// \returns Number of waves per work group for given subtarget \p Features and
     101             : /// limited by given \p FlatWorkGroupSize.
     102             : unsigned getWavesPerWorkGroup(const FeatureBitset &Features,
     103             :                               unsigned FlatWorkGroupSize);
     104             : 
     105             : /// \returns SGPR allocation granularity for given subtarget \p Features.
     106             : unsigned getSGPRAllocGranule(const FeatureBitset &Features);
     107             : 
     108             : /// \returns SGPR encoding granularity for given subtarget \p Features.
     109             : unsigned getSGPREncodingGranule(const FeatureBitset &Features);
     110             : 
     111             : /// \returns Total number of SGPRs for given subtarget \p Features.
     112             : unsigned getTotalNumSGPRs(const FeatureBitset &Features);
     113             : 
     114             : /// \returns Addressable number of SGPRs for given subtarget \p Features.
     115             : unsigned getAddressableNumSGPRs(const FeatureBitset &Features);
     116             : 
     117             : /// \returns Minimum number of SGPRs that meets the given number of waves per
     118             : /// execution unit requirement for given subtarget \p Features.
     119             : unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
     120             : 
     121             : /// \returns Maximum number of SGPRs that meets the given number of waves per
     122             : /// execution unit requirement for given subtarget \p Features.
     123             : unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,
     124             :                         bool Addressable);
     125             : 
     126             : /// \returns VGPR allocation granularity for given subtarget \p Features.
     127             : unsigned getVGPRAllocGranule(const FeatureBitset &Features);
     128             : 
     129             : /// \returns VGPR encoding granularity for given subtarget \p Features.
     130             : unsigned getVGPREncodingGranule(const FeatureBitset &Features);
     131             : 
     132             : /// \returns Total number of VGPRs for given subtarget \p Features.
     133             : unsigned getTotalNumVGPRs(const FeatureBitset &Features);
     134             : 
     135             : /// \returns Addressable number of VGPRs for given subtarget \p Features.
     136             : unsigned getAddressableNumVGPRs(const FeatureBitset &Features);
     137             : 
     138             : /// \returns Minimum number of VGPRs that meets given number of waves per
     139             : /// execution unit requirement for given subtarget \p Features.
     140             : unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
     141             : 
     142             : /// \returns Maximum number of VGPRs that meets given number of waves per
     143             : /// execution unit requirement for given subtarget \p Features.
     144             : unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
     145             : 
     146             : } // end namespace IsaInfo
     147             : 
     148             : LLVM_READONLY
     149             : int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
     150             : 
     151             : void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
     152             :                                const FeatureBitset &Features);
     153             : 
     154             : bool isGroupSegment(const GlobalValue *GV, AMDGPUAS AS);
     155             : bool isGlobalSegment(const GlobalValue *GV, AMDGPUAS AS);
     156             : bool isReadOnlySegment(const GlobalValue *GV, AMDGPUAS AS);
     157             : 
     158             : /// \returns True if constants should be emitted to .text section for given
     159             : /// target triple \p TT, false otherwise.
     160             : bool shouldEmitConstantsToTextSection(const Triple &TT);
     161             : 
     162             : /// \returns Integer value requested using \p F's \p Name attribute.
     163             : ///
     164             : /// \returns \p Default if attribute is not present.
     165             : ///
     166             : /// \returns \p Default and emits error if requested value cannot be converted
     167             : /// to integer.
     168             : int getIntegerAttribute(const Function &F, StringRef Name, int Default);
     169             : 
     170             : /// \returns A pair of integer values requested using \p F's \p Name attribute
     171             : /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
     172             : /// is false).
     173             : ///
     174             : /// \returns \p Default if attribute is not present.
     175             : ///
     176             : /// \returns \p Default and emits error if one of the requested values cannot be
     177             : /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
     178             : /// not present.
     179             : std::pair<int, int> getIntegerPairAttribute(const Function &F,
     180             :                                             StringRef Name,
     181             :                                             std::pair<int, int> Default,
     182             :                                             bool OnlyFirstRequired = false);
     183             : 
     184             : /// \returns Vmcnt bit mask for given isa \p Version.
     185             : unsigned getVmcntBitMask(const IsaInfo::IsaVersion &Version);
     186             : 
     187             : /// \returns Expcnt bit mask for given isa \p Version.
     188             : unsigned getExpcntBitMask(const IsaInfo::IsaVersion &Version);
     189             : 
     190             : /// \returns Lgkmcnt bit mask for given isa \p Version.
     191             : unsigned getLgkmcntBitMask(const IsaInfo::IsaVersion &Version);
     192             : 
     193             : /// \returns Waitcnt bit mask for given isa \p Version.
     194             : unsigned getWaitcntBitMask(const IsaInfo::IsaVersion &Version);
     195             : 
     196             : /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
     197             : unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
     198             : 
     199             : /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
     200             : unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
     201             : 
     202             : /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
     203             : unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
     204             : 
     205             : /// \brief Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
     206             : /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
     207             : /// \p Lgkmcnt respectively.
     208             : ///
     209             : /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
     210             : ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
     211             : ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
     212             : ///     \p Expcnt = \p Waitcnt[6:4]
     213             : ///     \p Lgkmcnt = \p Waitcnt[11:8]
     214             : void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
     215             :                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
     216             : 
     217             : /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
     218             : unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
     219             :                      unsigned Vmcnt);
     220             : 
     221             : /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
     222             : unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
     223             :                       unsigned Expcnt);
     224             : 
     225             : /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
     226             : unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
     227             :                        unsigned Lgkmcnt);
     228             : 
     229             : /// \brief Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
     230             : /// \p Version.
     231             : ///
     232             : /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
     233             : ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
     234             : ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
     235             : ///     Waitcnt[6:4]   = \p Expcnt
     236             : ///     Waitcnt[11:8]  = \p Lgkmcnt
     237             : ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
     238             : ///
     239             : /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
     240             : /// isa \p Version.
     241             : unsigned encodeWaitcnt(const IsaInfo::IsaVersion &Version,
     242             :                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
     243             : 
     244             : unsigned getInitialPSInputAddr(const Function &F);
     245             : 
     246             : LLVM_READNONE
     247             : bool isShader(CallingConv::ID CC);
     248             : 
     249             : LLVM_READNONE
     250             : bool isCompute(CallingConv::ID CC);
     251             : 
     252             : LLVM_READNONE
     253             : bool isEntryFunctionCC(CallingConv::ID CC);
     254             : 
     255             : // FIXME: Remove this when calling conventions cleaned up
     256             : LLVM_READNONE
     257             : inline bool isKernel(CallingConv::ID CC) {
     258       29590 :   switch (CC) {
     259             :   case CallingConv::AMDGPU_KERNEL:
     260             :   case CallingConv::SPIR_KERNEL:
     261             :     return true;
     262        1206 :   default:
     263             :     return false;
     264             :   }
     265             : }
     266             : 
     267             : bool isSI(const MCSubtargetInfo &STI);
     268             : bool isCI(const MCSubtargetInfo &STI);
     269             : bool isVI(const MCSubtargetInfo &STI);
     270             : bool isGFX9(const MCSubtargetInfo &STI);
     271             : 
     272             : /// \brief Is Reg - scalar register
     273             : bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
     274             : 
     275             : /// \brief Is there any intersection between registers
     276             : bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
     277             : 
     278             : /// If \p Reg is a pseudo reg, return the correct hardware register given
     279             : /// \p STI otherwise return \p Reg.
     280             : unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
     281             : 
     282             : /// \brief Convert hardware register \p Reg to a pseudo register
     283             : LLVM_READNONE
     284             : unsigned mc2PseudoReg(unsigned Reg);
     285             : 
     286             : /// \brief Can this operand also contain immediate values?
     287             : bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
     288             : 
     289             : /// \brief Is this floating-point operand?
     290             : bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
     291             : 
     292             : /// \brief Does this opearnd support only inlinable literals?
     293             : bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
     294             : 
     295             : /// \brief Get the size in bits of a register from the register class \p RC.
     296             : unsigned getRegBitWidth(unsigned RCID);
     297             : 
     298             : /// \brief Get the size in bits of a register from the register class \p RC.
     299             : unsigned getRegBitWidth(const MCRegisterClass &RC);
     300             : 
     301             : /// \brief Get size of register operand
     302             : unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
     303             :                            unsigned OpNo);
     304             : 
     305             : LLVM_READNONE
     306             : inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
     307       15751 :   switch (OpInfo.OperandType) {
     308             :   case AMDGPU::OPERAND_REG_IMM_INT32:
     309             :   case AMDGPU::OPERAND_REG_IMM_FP32:
     310             :   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
     311             :   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
     312             :     return 4;
     313             : 
     314             :   case AMDGPU::OPERAND_REG_IMM_INT64:
     315             :   case AMDGPU::OPERAND_REG_IMM_FP64:
     316             :   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
     317             :   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
     318             :     return 8;
     319             : 
     320             :   case AMDGPU::OPERAND_REG_IMM_INT16:
     321             :   case AMDGPU::OPERAND_REG_IMM_FP16:
     322             :   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
     323             :   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
     324             :   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
     325             :   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
     326             :     return 2;
     327             : 
     328           0 :   default:
     329           0 :     llvm_unreachable("unhandled operand type");
     330             :   }
     331             : }
     332             : 
     333             : LLVM_READNONE
     334             : inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
     335       31491 :   return getOperandSize(Desc.OpInfo[OpNo]);
     336             : }
     337             : 
     338             : /// \brief Is this literal inlinable
     339             : LLVM_READNONE
     340             : bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
     341             : 
     342             : LLVM_READNONE
     343             : bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
     344             : 
     345             : LLVM_READNONE
     346             : bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
     347             : 
     348             : LLVM_READNONE
     349             : bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
     350             : 
     351             : bool isArgPassedInSGPR(const Argument *Arg);
     352             : bool isUniformMMO(const MachineMemOperand *MMO);
     353             : 
     354             : /// \returns The encoding that will be used for \p ByteOffset in the SMRD
     355             : /// offset field.
     356             : int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
     357             : 
     358             : /// \returns true if this offset is small enough to fit in the SMRD
     359             : /// offset field.  \p ByteOffset should be the offset in bytes and
     360             : /// not the encoded offset.
     361             : bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
     362             : 
     363             : } // end namespace AMDGPU
     364             : } // end namespace llvm
     365             : 
     366             : #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H

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