LCOV - code coverage report
Current view: top level - lib/Target/ARM - ARMAsmPrinter.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 893 969 92.2 %
Date: 2018-06-17 00:07:59 Functions: 25 25 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains a printer that converts from our internal representation
      11             : // of machine-dependent LLVM code to GAS-format ARM assembly language.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "ARMAsmPrinter.h"
      16             : #include "ARM.h"
      17             : #include "ARMConstantPoolValue.h"
      18             : #include "ARMMachineFunctionInfo.h"
      19             : #include "ARMTargetMachine.h"
      20             : #include "ARMTargetObjectFile.h"
      21             : #include "InstPrinter/ARMInstPrinter.h"
      22             : #include "MCTargetDesc/ARMAddressingModes.h"
      23             : #include "MCTargetDesc/ARMMCExpr.h"
      24             : #include "llvm/ADT/SetVector.h"
      25             : #include "llvm/ADT/SmallString.h"
      26             : #include "llvm/BinaryFormat/COFF.h"
      27             : #include "llvm/CodeGen/MachineFunctionPass.h"
      28             : #include "llvm/CodeGen/MachineJumpTableInfo.h"
      29             : #include "llvm/CodeGen/MachineModuleInfoImpls.h"
      30             : #include "llvm/IR/Constants.h"
      31             : #include "llvm/IR/DataLayout.h"
      32             : #include "llvm/IR/Mangler.h"
      33             : #include "llvm/IR/Module.h"
      34             : #include "llvm/IR/Type.h"
      35             : #include "llvm/MC/MCAsmInfo.h"
      36             : #include "llvm/MC/MCAssembler.h"
      37             : #include "llvm/MC/MCContext.h"
      38             : #include "llvm/MC/MCELFStreamer.h"
      39             : #include "llvm/MC/MCInst.h"
      40             : #include "llvm/MC/MCInstBuilder.h"
      41             : #include "llvm/MC/MCObjectStreamer.h"
      42             : #include "llvm/MC/MCStreamer.h"
      43             : #include "llvm/MC/MCSymbol.h"
      44             : #include "llvm/Support/ARMBuildAttributes.h"
      45             : #include "llvm/Support/Debug.h"
      46             : #include "llvm/Support/ErrorHandling.h"
      47             : #include "llvm/Support/TargetParser.h"
      48             : #include "llvm/Support/TargetRegistry.h"
      49             : #include "llvm/Support/raw_ostream.h"
      50             : #include "llvm/Target/TargetMachine.h"
      51             : using namespace llvm;
      52             : 
      53             : #define DEBUG_TYPE "asm-printer"
      54             : 
      55        2719 : ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
      56        2719 :                              std::unique_ptr<MCStreamer> Streamer)
      57             :     : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
      58       13595 :       InConstantPool(false), OptimizationGoals(-1) {}
      59             : 
      60       13634 : void ARMAsmPrinter::EmitFunctionBodyEnd() {
      61             :   // Make sure to terminate any constant pools that were at the end
      62             :   // of the function.
      63       13634 :   if (!InConstantPool)
      64             :     return;
      65        1405 :   InConstantPool = false;
      66        1405 :   OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
      67             : }
      68             : 
      69       13634 : void ARMAsmPrinter::EmitFunctionEntryLabel() {
      70       13634 :   if (AFI->isThumbFunction()) {
      71        5581 :     OutStreamer->EmitAssemblerFlag(MCAF_Code16);
      72        5581 :     OutStreamer->EmitThumbFunc(CurrentFnSym);
      73             :   } else {
      74        8053 :     OutStreamer->EmitAssemblerFlag(MCAF_Code32);
      75             :   }
      76       13634 :   OutStreamer->EmitLabel(CurrentFnSym);
      77       13634 : }
      78             : 
      79          19 : void ARMAsmPrinter::EmitXXStructor(const DataLayout &DL, const Constant *CV) {
      80          19 :   uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType());
      81             :   assert(Size && "C++ constructor pointer had zero size!");
      82             : 
      83             :   const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
      84             :   assert(GV && "C++ constructor pointer was not a GlobalValue!");
      85             : 
      86          57 :   const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
      87             :                                                            ARMII::MO_NO_FLAG),
      88          19 :                                             (Subtarget->isTargetELF()
      89             :                                              ? MCSymbolRefExpr::VK_ARM_TARGET1
      90             :                                              : MCSymbolRefExpr::VK_None),
      91          38 :                                             OutContext);
      92             : 
      93          19 :   OutStreamer->EmitValue(E, Size);
      94          19 : }
      95             : 
      96        1819 : void ARMAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
      97        1819 :   if (PromotedGlobals.count(GV))
      98             :     // The global was promoted into a constant pool. It should not be emitted.
      99             :     return;
     100        1762 :   AsmPrinter::EmitGlobalVariable(GV);
     101             : }
     102             : 
     103             : /// runOnMachineFunction - This uses the EmitInstruction()
     104             : /// method to print assembly for each instruction.
     105             : ///
     106       13634 : bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
     107       13634 :   AFI = MF.getInfo<ARMFunctionInfo>();
     108       13634 :   MCP = MF.getConstantPool();
     109       13634 :   Subtarget = &MF.getSubtarget<ARMSubtarget>();
     110             : 
     111       13634 :   SetupMachineFunction(MF);
     112       13634 :   const Function &F = MF.getFunction();
     113       13634 :   const TargetMachine& TM = MF.getTarget();
     114             : 
     115             :   // Collect all globals that had their storage promoted to a constant pool.
     116             :   // Functions are emitted before variables, so this accumulates promoted
     117             :   // globals from all functions in PromotedGlobals.
     118       13634 :   for (auto *GV : AFI->getGlobalsPromotedToConstantPool())
     119          94 :     PromotedGlobals.insert(GV);
     120             :   
     121             :   // Calculate this function's optimization goal.
     122             :   unsigned OptimizationGoal;
     123       13634 :   if (F.hasFnAttribute(Attribute::OptimizeNone))
     124             :     // For best debugging illusion, speed and small size sacrificed
     125             :     OptimizationGoal = 6;
     126       13595 :   else if (F.optForMinSize())
     127             :     // Aggressively for small size, speed and debug illusion sacrificed
     128             :     OptimizationGoal = 4;
     129       13457 :   else if (F.optForSize())
     130             :     // For small size, but speed and debugging illusion preserved
     131             :     OptimizationGoal = 3;
     132       13292 :   else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
     133             :     // Aggressively for speed, small size and debug illusion sacrificed
     134             :     OptimizationGoal = 2;
     135       13207 :   else if (TM.getOptLevel() > CodeGenOpt::None)
     136             :     // For speed, but small size and good debug illusion preserved
     137             :     OptimizationGoal = 1;
     138             :   else // TM.getOptLevel() == CodeGenOpt::None
     139             :     // For good debugging, but speed and small size preserved
     140             :     OptimizationGoal = 5;
     141             : 
     142             :   // Combine a new optimization goal with existing ones.
     143       13634 :   if (OptimizationGoals == -1) // uninitialized goals
     144        2651 :     OptimizationGoals = OptimizationGoal;
     145       10983 :   else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
     146         203 :     OptimizationGoals = 0;
     147             : 
     148       27268 :   if (Subtarget->isTargetCOFF()) {
     149             :     bool Internal = F.hasInternalLinkage();
     150         162 :     COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
     151             :                                             : COFF::IMAGE_SYM_CLASS_EXTERNAL;
     152             :     int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
     153             : 
     154         162 :     OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
     155         162 :     OutStreamer->EmitCOFFSymbolStorageClass(Scl);
     156         162 :     OutStreamer->EmitCOFFSymbolType(Type);
     157         162 :     OutStreamer->EndCOFFSymbolDef();
     158             :   }
     159             : 
     160             :   // Emit the rest of the function body.
     161       13634 :   EmitFunctionBody();
     162             : 
     163             :   // Emit the XRay table for this function.
     164       13634 :   emitXRayTable();
     165             : 
     166             :   // If we need V4T thumb mode Register Indirect Jump pads, emit them.
     167             :   // These are created per function, rather than per TU, since it's
     168             :   // relatively easy to exceed the thumb branch range within a TU.
     169       13634 :   if (! ThumbIndirectPads.empty()) {
     170          33 :     OutStreamer->EmitAssemblerFlag(MCAF_Code16);
     171          33 :     EmitAlignment(1);
     172         119 :     for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
     173          43 :       OutStreamer->EmitLabel(TIP.second);
     174          86 :       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
     175          43 :         .addReg(TIP.first)
     176             :         // Add predicate operands.
     177             :         .addImm(ARMCC::AL)
     178          43 :         .addReg(0));
     179             :     }
     180             :     ThumbIndirectPads.clear();
     181             :   }
     182             : 
     183             :   // We didn't modify anything.
     184       13634 :   return false;
     185             : }
     186             : 
     187         449 : void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
     188             :                                  raw_ostream &O) {
     189         449 :   const MachineOperand &MO = MI->getOperand(OpNum);
     190             :   unsigned TF = MO.getTargetFlags();
     191             : 
     192         449 :   switch (MO.getType()) {
     193           0 :   default: llvm_unreachable("<unknown operand type>");
     194         414 :   case MachineOperand::MO_Register: {
     195         414 :     unsigned Reg = MO.getReg();
     196             :     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
     197             :     assert(!MO.getSubReg() && "Subregs should be eliminated!");
     198         828 :     if(ARM::GPRPairRegClass.contains(Reg)) {
     199          88 :       const MachineFunction &MF = *MI->getParent()->getParent();
     200          88 :       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
     201          88 :       Reg = TRI->getSubReg(Reg, ARM::gsub_0);
     202             :     }
     203         414 :     O << ARMInstPrinter::getRegisterName(Reg);
     204         414 :     break;
     205             :   }
     206          33 :   case MachineOperand::MO_Immediate: {
     207          33 :     int64_t Imm = MO.getImm();
     208             :     O << '#';
     209          33 :     if (TF == ARMII::MO_LO16)
     210           0 :       O << ":lower16:";
     211          33 :     else if (TF == ARMII::MO_HI16)
     212           0 :       O << ":upper16:";
     213          33 :     O << Imm;
     214          33 :     break;
     215             :   }
     216           0 :   case MachineOperand::MO_MachineBasicBlock:
     217           0 :     MO.getMBB()->getSymbol()->print(O, MAI);
     218           0 :     return;
     219           2 :   case MachineOperand::MO_GlobalAddress: {
     220           2 :     const GlobalValue *GV = MO.getGlobal();
     221           2 :     if (TF & ARMII::MO_LO16)
     222           0 :       O << ":lower16:";
     223           2 :     else if (TF & ARMII::MO_HI16)
     224           0 :       O << ":upper16:";
     225           2 :     GetARMGVSymbol(GV, TF)->print(O, MAI);
     226             : 
     227           4 :     printOffset(MO.getOffset(), O);
     228           2 :     break;
     229             :   }
     230           0 :   case MachineOperand::MO_ConstantPoolIndex:
     231           0 :     if (Subtarget->genExecuteOnly())
     232           0 :       llvm_unreachable("execute-only should not generate constant pools");
     233           0 :     GetCPISymbol(MO.getIndex())->print(O, MAI);
     234           0 :     break;
     235             :   }
     236             : }
     237             : 
     238             : //===--------------------------------------------------------------------===//
     239             : 
     240         107 : MCSymbol *ARMAsmPrinter::
     241             : GetARMJTIPICJumpTableLabel(unsigned uid) const {
     242         107 :   const DataLayout &DL = getDataLayout();
     243             :   SmallString<60> Name;
     244         214 :   raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
     245         107 :                             << getFunctionNumber() << '_' << uid;
     246         321 :   return OutContext.getOrCreateSymbol(Name);
     247             : }
     248             : 
     249         550 : bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
     250             :                                     unsigned AsmVariant, const char *ExtraCode,
     251             :                                     raw_ostream &O) {
     252             :   // Does this asm operand have a single letter operand modifier?
     253         550 :   if (ExtraCode && ExtraCode[0]) {
     254         106 :     if (ExtraCode[1] != 0) return true; // Unknown modifier.
     255             : 
     256         106 :     switch (ExtraCode[0]) {
     257           0 :     default:
     258             :       // See if this is a generic print operand
     259           0 :       return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
     260           2 :     case 'a': // Print as a memory address.
     261           4 :       if (MI->getOperand(OpNum).isReg()) {
     262           1 :         O << "["
     263           2 :           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
     264           1 :           << "]";
     265           1 :         return false;
     266             :       }
     267             :       LLVM_FALLTHROUGH;
     268             :     case 'c': // Don't print "#" before an immediate operand.
     269           6 :       if (!MI->getOperand(OpNum).isImm())
     270             :         return true;
     271           3 :       O << MI->getOperand(OpNum).getImm();
     272           3 :       return false;
     273           5 :     case 'P': // Print a VFP double precision register.
     274             :     case 'q': // Print a NEON quad precision register.
     275           5 :       printOperand(MI, OpNum, O);
     276           5 :       return false;
     277           3 :     case 'y': // Print a VFP single precision register as indexed double.
     278           6 :       if (MI->getOperand(OpNum).isReg()) {
     279           3 :         unsigned Reg = MI->getOperand(OpNum).getReg();
     280           3 :         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
     281             :         // Find the 'd' register that has this 's' register as a sub-register,
     282             :         // and determine the lane number.
     283           6 :         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
     284           6 :           if (!ARM::DPRRegClass.contains(*SR))
     285             :             continue;
     286           3 :           bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
     287           3 :           O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
     288             :           return false;
     289             :         }
     290             :       }
     291             :       return true;
     292           1 :     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
     293           2 :       if (!MI->getOperand(OpNum).isImm())
     294             :         return true;
     295           1 :       O << ~(MI->getOperand(OpNum).getImm());
     296           1 :       return false;
     297           1 :     case 'L': // The low 16 bits of an immediate constant.
     298           2 :       if (!MI->getOperand(OpNum).isImm())
     299             :         return true;
     300           1 :       O << (MI->getOperand(OpNum).getImm() & 0xffff);
     301           1 :       return false;
     302           2 :     case 'M': { // A register range suitable for LDM/STM.
     303           4 :       if (!MI->getOperand(OpNum).isReg())
     304             :         return true;
     305             :       const MachineOperand &MO = MI->getOperand(OpNum);
     306           2 :       unsigned RegBegin = MO.getReg();
     307             :       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
     308             :       // already got the operands in registers that are operands to the
     309             :       // inline asm statement.
     310           2 :       O << "{";
     311           4 :       if (ARM::GPRPairRegClass.contains(RegBegin)) {
     312           2 :         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
     313           2 :         unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
     314           2 :         O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
     315           2 :         RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
     316             :       }
     317           2 :       O << ARMInstPrinter::getRegisterName(RegBegin);
     318             : 
     319             :       // FIXME: The register allocator not only may not have given us the
     320             :       // registers in sequence, but may not be in ascending registers. This
     321             :       // will require changes in the register allocator that'll need to be
     322             :       // propagated down here if the operands change.
     323           2 :       unsigned RegOps = OpNum + 1;
     324           4 :       while (MI->getOperand(RegOps).isReg()) {
     325           0 :         O << ", "
     326           0 :           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
     327           0 :         RegOps++;
     328             :       }
     329             : 
     330           2 :       O << "}";
     331             : 
     332           2 :       return false;
     333             :     }
     334          14 :     case 'R': // The most significant register of a pair.
     335             :     case 'Q': { // The least significant register of a pair.
     336          14 :       if (OpNum == 0)
     337             :         return true;
     338          14 :       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
     339          14 :       if (!FlagsOP.isImm())
     340             :         return true;
     341          14 :       unsigned Flags = FlagsOP.getImm();
     342             : 
     343             :       // This operand may not be the one that actually provides the register. If
     344             :       // it's tied to a previous one then we should refer instead to that one
     345             :       // for registers and their classes.
     346             :       unsigned TiedIdx;
     347             :       if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
     348          20 :         for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
     349           8 :           unsigned OpFlags = MI->getOperand(OpNum).getImm();
     350           8 :           OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
     351             :         }
     352           4 :         Flags = MI->getOperand(OpNum).getImm();
     353             : 
     354             :         // Later code expects OpNum to be pointing at the register rather than
     355             :         // the flags.
     356           4 :         OpNum += 1;
     357             :       }
     358             : 
     359             :       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
     360             :       unsigned RC;
     361             :       InlineAsm::hasRegClassConstraint(Flags, RC);
     362          14 :       if (RC == ARM::GPRPairRegClassID) {
     363          14 :         if (NumVals != 1)
     364             :           return true;
     365             :         const MachineOperand &MO = MI->getOperand(OpNum);
     366          14 :         if (!MO.isReg())
     367             :           return true;
     368          14 :         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
     369          14 :         unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
     370          14 :             ARM::gsub_0 : ARM::gsub_1);
     371          14 :         O << ARMInstPrinter::getRegisterName(Reg);
     372          14 :         return false;
     373             :       }
     374           0 :       if (NumVals != 2)
     375             :         return true;
     376           0 :       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
     377           0 :       if (RegOp >= MI->getNumOperands())
     378             :         return true;
     379             :       const MachineOperand &MO = MI->getOperand(RegOp);
     380           0 :       if (!MO.isReg())
     381             :         return true;
     382           0 :       unsigned Reg = MO.getReg();
     383           0 :       O << ARMInstPrinter::getRegisterName(Reg);
     384           0 :       return false;
     385             :     }
     386             : 
     387           2 :     case 'e': // The low doubleword register of a NEON quad register.
     388             :     case 'f': { // The high doubleword register of a NEON quad register.
     389           4 :       if (!MI->getOperand(OpNum).isReg())
     390             :         return true;
     391           2 :       unsigned Reg = MI->getOperand(OpNum).getReg();
     392           4 :       if (!ARM::QPRRegClass.contains(Reg))
     393             :         return true;
     394           2 :       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
     395           2 :       unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
     396           2 :                                        ARM::dsub_0 : ARM::dsub_1);
     397           2 :       O << ARMInstPrinter::getRegisterName(SubReg);
     398           2 :       return false;
     399             :     }
     400             : 
     401             :     // This modifier is not yet supported.
     402             :     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
     403             :       return true;
     404          74 :     case 'H': { // The highest-numbered register of a pair.
     405          74 :       const MachineOperand &MO = MI->getOperand(OpNum);
     406          74 :       if (!MO.isReg())
     407             :         return true;
     408          74 :       const MachineFunction &MF = *MI->getParent()->getParent();
     409          74 :       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
     410          74 :       unsigned Reg = MO.getReg();
     411         148 :       if(!ARM::GPRPairRegClass.contains(Reg))
     412             :         return false;
     413          74 :       Reg = TRI->getSubReg(Reg, ARM::gsub_1);
     414          74 :       O << ARMInstPrinter::getRegisterName(Reg);
     415          74 :       return false;
     416             :     }
     417             :     }
     418             :   }
     419             : 
     420         444 :   printOperand(MI, OpNum, O);
     421         444 :   return false;
     422             : }
     423             : 
     424          19 : bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
     425             :                                           unsigned OpNum, unsigned AsmVariant,
     426             :                                           const char *ExtraCode,
     427             :                                           raw_ostream &O) {
     428             :   // Does this asm operand have a single letter operand modifier?
     429          19 :   if (ExtraCode && ExtraCode[0]) {
     430           3 :     if (ExtraCode[1] != 0) return true; // Unknown modifier.
     431             : 
     432           3 :     switch (ExtraCode[0]) {
     433             :       case 'A': // A memory operand for a VLD1/VST1 instruction.
     434             :       default: return true;  // Unknown modifier.
     435           3 :       case 'm': // The base register of a memory operand.
     436           6 :         if (!MI->getOperand(OpNum).isReg())
     437             :           return true;
     438           3 :         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
     439           3 :         return false;
     440             :     }
     441             :   }
     442             : 
     443          16 :   const MachineOperand &MO = MI->getOperand(OpNum);
     444             :   assert(MO.isReg() && "unexpected inline asm memory operand");
     445          16 :   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
     446          16 :   return false;
     447             : }
     448             : 
     449             : static bool isThumb(const MCSubtargetInfo& STI) {
     450             :   return STI.getFeatureBits()[ARM::ModeThumb];
     451             : }
     452             : 
     453         335 : void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
     454             :                                      const MCSubtargetInfo *EndInfo) const {
     455             :   // If either end mode is unknown (EndInfo == NULL) or different than
     456             :   // the start mode, then restore the start mode.
     457             :   const bool WasThumb = isThumb(StartInfo);
     458         554 :   if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
     459         122 :     OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
     460             :   }
     461         335 : }
     462             : 
     463        2715 : void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
     464        2715 :   const Triple &TT = TM.getTargetTriple();
     465             :   // Use unified assembler syntax.
     466        2715 :   OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
     467             : 
     468             :   // Emit ARM Build Attributes
     469        2715 :   if (TT.isOSBinFormatELF())
     470        1879 :     emitAttributes();
     471             : 
     472             :   // Use the triple's architecture and subarchitecture to determine
     473             :   // if we're thumb for the purposes of the top level code16 assembler
     474             :   // flag.
     475        2715 :   if (!M.getModuleInlineAsm().empty() && TT.isThumb())
     476           3 :     OutStreamer->EmitAssemblerFlag(MCAF_Code16);
     477        2715 : }
     478             : 
     479             : static void
     480         429 : emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
     481             :                          MachineModuleInfoImpl::StubValueTy &MCSym) {
     482             :   // L_foo$stub:
     483         429 :   OutStreamer.EmitLabel(StubLabel);
     484             :   //   .indirect_symbol _foo
     485         858 :   OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
     486             : 
     487         429 :   if (MCSym.getInt())
     488             :     // External to current translation unit.
     489         427 :     OutStreamer.EmitIntValue(0, 4/*size*/);
     490             :   else
     491             :     // Internal to current translation unit.
     492             :     //
     493             :     // When we place the LSDA into the TEXT section, the type info
     494             :     // pointers need to be indirect and pc-rel. We accomplish this by
     495             :     // using NLPs; however, sometimes the types are local to the file.
     496             :     // We need to fill in the value for the NLP in those cases.
     497           2 :     OutStreamer.EmitValue(
     498           2 :         MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
     499           2 :         4 /*size*/);
     500         429 : }
     501             : 
     502             : 
     503        2688 : void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
     504        2688 :   const Triple &TT = TM.getTargetTriple();
     505        2688 :   if (TT.isOSBinFormatMachO()) {
     506             :     // All darwin targets use mach-o.
     507             :     const TargetLoweringObjectFileMachO &TLOFMacho =
     508         764 :       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
     509             :     MachineModuleInfoMachO &MMIMacho =
     510         764 :       MMI->getObjFileInfo<MachineModuleInfoMachO>();
     511             : 
     512             :     // Output non-lazy-pointers for external and common global variables.
     513             :     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
     514             : 
     515         764 :     if (!Stubs.empty()) {
     516             :       // Switch with ".non_lazy_symbol_pointer" directive.
     517         188 :       OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
     518         188 :       EmitAlignment(2);
     519             : 
     520         608 :       for (auto &Stub : Stubs)
     521         840 :         emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
     522             : 
     523             :       Stubs.clear();
     524         188 :       OutStreamer->AddBlankLine();
     525             :     }
     526             : 
     527         764 :     Stubs = MMIMacho.GetThreadLocalGVStubList();
     528         764 :     if (!Stubs.empty()) {
     529             :       // Switch with ".non_lazy_symbol_pointer" directive.
     530           5 :       OutStreamer->SwitchSection(TLOFMacho.getThreadLocalPointerSection());
     531           5 :       EmitAlignment(2);
     532             : 
     533          14 :       for (auto &Stub : Stubs)
     534          18 :         emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
     535             : 
     536             :       Stubs.clear();
     537           5 :       OutStreamer->AddBlankLine();
     538             :     }
     539             : 
     540             :     // Funny Darwin hack: This flag tells the linker that no global symbols
     541             :     // contain code that falls through to other global symbols (e.g. the obvious
     542             :     // implementation of multiple entry points).  If this doesn't occur, the
     543             :     // linker can safely perform dead code stripping.  Since LLVM never
     544             :     // generates code that does this, it is always safe to set.
     545         764 :     OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
     546             :   }
     547             : 
     548             :   // The last attribute to be emitted is ABI_optimization_goals
     549             :   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
     550             :   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
     551             : 
     552        2688 :   if (OptimizationGoals > 0 &&
     553        2582 :       (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
     554             :        Subtarget->isTargetMuslAEABI()))
     555        1459 :     ATS.emitAttribute(ARMBuildAttrs::ABI_optimization_goals, OptimizationGoals);
     556        2688 :   OptimizationGoals = -1;
     557             : 
     558        2688 :   ATS.finishAttributeSection();
     559        2688 : }
     560             : 
     561             : //===----------------------------------------------------------------------===//
     562             : // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
     563             : // FIXME:
     564             : // The following seem like one-off assembler flags, but they actually need
     565             : // to appear in the .ARM.attributes section in ELF.
     566             : // Instead of subclassing the MCELFStreamer, we do the work here.
     567             : 
     568             : // Returns true if all functions have the same function attribute value.
     569             : // It also returns true when the module has no functions.
     570             : static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr,
     571             :                                                StringRef Value) {
     572       11161 :   return !any_of(M, [&](const Function &F) {
     573       16668 :     return F.getFnAttribute(Attr).getValueAsString() != Value;
     574        5556 :   });
     575             : }
     576             : 
     577        1879 : void ARMAsmPrinter::emitAttributes() {
     578             :   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
     579             :   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
     580             : 
     581        3758 :   ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
     582             : 
     583        3758 :   ATS.switchVendor("aeabi");
     584             : 
     585             :   // Compute ARM ELF Attributes based on the default subtarget that
     586             :   // we'd have constructed. The existing ARM behavior isn't LTO clean
     587             :   // anyhow.
     588             :   // FIXME: For ifunc related functions we could iterate over and look
     589             :   // for a feature string that doesn't match the default one.
     590        1879 :   const Triple &TT = TM.getTargetTriple();
     591             :   StringRef CPU = TM.getTargetCPU();
     592        1879 :   StringRef FS = TM.getTargetFeatureString();
     593        1879 :   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
     594        1879 :   if (!FS.empty()) {
     595         611 :     if (!ArchFS.empty())
     596         604 :       ArchFS = (Twine(ArchFS) + "," + FS).str();
     597             :     else
     598         618 :       ArchFS = FS;
     599             :   }
     600        1879 :   const ARMBaseTargetMachine &ATM =
     601             :       static_cast<const ARMBaseTargetMachine &>(TM);
     602        7516 :   const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
     603             : 
     604             :   // Emit build attributes for the available hardware.
     605        1879 :   ATS.emitTargetAttributes(STI);
     606             : 
     607             :   // RW data addressing.
     608        1879 :   if (isPositionIndependent()) {
     609          50 :     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
     610          50 :                       ARMBuildAttrs::AddressRWPCRel);
     611        1829 :   } else if (STI.isRWPI()) {
     612             :     // RWPI specific attributes.
     613          24 :     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
     614          24 :                       ARMBuildAttrs::AddressRWSBRel);
     615             :   }
     616             : 
     617             :   // RO data addressing.
     618        1879 :   if (isPositionIndependent() || STI.isROPI()) {
     619          77 :     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
     620          77 :                       ARMBuildAttrs::AddressROPCRel);
     621             :   }
     622             : 
     623             :   // GOT use.
     624        1879 :   if (isPositionIndependent()) {
     625          50 :     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
     626          50 :                       ARMBuildAttrs::AddressGOT);
     627             :   } else {
     628        1829 :     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
     629        1829 :                       ARMBuildAttrs::AddressDirect);
     630             :   }
     631             : 
     632             :   // Set FP Denormals.
     633        1879 :   if (checkFunctionsAttributeConsistency(*MMI->getModule(),
     634             :                                          "denormal-fp-math",
     635        3727 :                                          "preserve-sign") ||
     636        1848 :       TM.Options.FPDenormalMode == FPDenormal::PreserveSign)
     637          32 :     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
     638          32 :                       ARMBuildAttrs::PreserveFPSign);
     639        1847 :   else if (checkFunctionsAttributeConsistency(*MMI->getModule(),
     640             :                                               "denormal-fp-math",
     641        3693 :                                               "positive-zero") ||
     642        1846 :            TM.Options.FPDenormalMode == FPDenormal::PositiveZero)
     643           2 :     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
     644           2 :                       ARMBuildAttrs::PositiveZero);
     645        1845 :   else if (!TM.Options.UnsafeFPMath)
     646        1779 :     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
     647        1779 :                       ARMBuildAttrs::IEEEDenormals);
     648             :   else {
     649          66 :     if (!STI.hasVFP2()) {
     650             :       // When the target doesn't have an FPU (by design or
     651             :       // intention), the assumptions made on the software support
     652             :       // mirror that of the equivalent hardware support *if it
     653             :       // existed*. For v7 and better we indicate that denormals are
     654             :       // flushed preserving sign, and for V6 we indicate that
     655             :       // denormals are flushed to positive zero.
     656          15 :       if (STI.hasV7Ops())
     657           8 :         ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
     658           8 :                           ARMBuildAttrs::PreserveFPSign);
     659          51 :     } else if (STI.hasVFP3()) {
     660             :       // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
     661             :       // the sign bit of the zero matches the sign bit of the input or
     662             :       // result that is being flushed to zero.
     663          49 :       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
     664          49 :                         ARMBuildAttrs::PreserveFPSign);
     665             :     }
     666             :     // For VFPv2 implementations it is implementation defined as
     667             :     // to whether denormals are flushed to positive zero or to
     668             :     // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
     669             :     // LLVM has chosen to flush this to positive zero (most likely for
     670             :     // GCC compatibility), so that's the chosen value here (the
     671             :     // absence of its emission implies zero).
     672             :   }
     673             : 
     674             :   // Set FP exceptions and rounding
     675        1879 :   if (checkFunctionsAttributeConsistency(*MMI->getModule(),
     676        3727 :                                          "no-trapping-math", "true") ||
     677        1848 :       TM.Options.NoTrappingFPMath)
     678          32 :     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
     679          32 :                       ARMBuildAttrs::Not_Allowed);
     680        1847 :   else if (!TM.Options.UnsafeFPMath) {
     681        1781 :     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
     682             : 
     683             :     // If the user has permitted this code to choose the IEEE 754
     684             :     // rounding at run-time, emit the rounding attribute.
     685        1781 :     if (TM.Options.HonorSignDependentRoundingFPMathOption)
     686          35 :       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
     687             :   }
     688             : 
     689             :   // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
     690             :   // equivalent of GCC's -ffinite-math-only flag.
     691        1879 :   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
     692          45 :     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
     693          45 :                       ARMBuildAttrs::Allowed);
     694             :   else
     695        1834 :     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
     696        1834 :                       ARMBuildAttrs::AllowIEEE754);
     697             : 
     698             :   // FIXME: add more flags to ARMBuildAttributes.h
     699             :   // 8-bytes alignment stuff.
     700        1879 :   ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
     701        1879 :   ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
     702             : 
     703             :   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
     704        1879 :   if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
     705         190 :     ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
     706             : 
     707             :   // FIXME: To support emitting this build attribute as GCC does, the
     708             :   // -mfp16-format option and associated plumbing must be
     709             :   // supported. For now the __fp16 type is exposed by default, so this
     710             :   // attribute should be emitted with value 1.
     711        1879 :   ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
     712        1879 :                     ARMBuildAttrs::FP16FormatIEEE);
     713             : 
     714        1879 :   if (MMI) {
     715        1879 :     if (const Module *SourceModule = MMI->getModule()) {
     716             :       // ABI_PCS_wchar_t to indicate wchar_t width
     717             :       // FIXME: There is no way to emit value 0 (wchar_t prohibited).
     718          53 :       if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
     719        3758 :               SourceModule->getModuleFlag("wchar_size"))) {
     720             :         int WCharWidth = WCharWidthValue->getZExtValue();
     721             :         assert((WCharWidth == 2 || WCharWidth == 4) &&
     722             :                "wchar_t width must be 2 or 4 bytes");
     723          53 :         ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
     724             :       }
     725             : 
     726             :       // ABI_enum_size to indicate enum width
     727             :       // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
     728             :       //        (all enums contain a value needing 32 bits to encode).
     729          52 :       if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
     730        3758 :               SourceModule->getModuleFlag("min_enum_size"))) {
     731          52 :         int EnumWidth = EnumWidthValue->getZExtValue();
     732             :         assert((EnumWidth == 1 || EnumWidth == 4) &&
     733             :                "Minimum enum width must be 1 or 4 bytes");
     734          52 :         int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
     735          52 :         ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
     736             :       }
     737             :     }
     738             :   }
     739             : 
     740             :   // We currently do not support using R9 as the TLS pointer.
     741        1879 :   if (STI.isRWPI())
     742          24 :     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
     743          24 :                       ARMBuildAttrs::R9IsSB);
     744        1855 :   else if (STI.isR9Reserved())
     745           1 :     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
     746           1 :                       ARMBuildAttrs::R9Reserved);
     747             :   else
     748        1854 :     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
     749        1854 :                       ARMBuildAttrs::R9IsGPR);
     750        1879 : }
     751             : 
     752             : //===----------------------------------------------------------------------===//
     753             : 
     754        2760 : static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
     755             :                              unsigned LabelId, MCContext &Ctx) {
     756             : 
     757        2760 :   MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
     758        5520 :                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
     759        2760 :   return Label;
     760             : }
     761             : 
     762             : static MCSymbolRefExpr::VariantKind
     763             : getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
     764         565 :   switch (Modifier) {
     765             :   case ARMCP::no_modifier:
     766             :     return MCSymbolRefExpr::VK_None;
     767          15 :   case ARMCP::TLSGD:
     768             :     return MCSymbolRefExpr::VK_TLSGD;
     769          21 :   case ARMCP::TPOFF:
     770             :     return MCSymbolRefExpr::VK_TPOFF;
     771          18 :   case ARMCP::GOTTPOFF:
     772             :     return MCSymbolRefExpr::VK_GOTTPOFF;
     773          22 :   case ARMCP::SBREL:
     774             :     return MCSymbolRefExpr::VK_ARM_SBREL;
     775          63 :   case ARMCP::GOT_PREL:
     776             :     return MCSymbolRefExpr::VK_ARM_GOT_PREL;
     777           7 :   case ARMCP::SECREL:
     778             :     return MCSymbolRefExpr::VK_SECREL;
     779             :   }
     780           0 :   llvm_unreachable("Invalid ARMCPModifier!");
     781             : }
     782             : 
     783        8077 : MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
     784             :                                         unsigned char TargetFlags) {
     785       16154 :   if (Subtarget->isTargetMachO()) {
     786             :     bool IsIndirect =
     787        4107 :         (TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
     788             : 
     789             :     if (!IsIndirect)
     790        3187 :       return getSymbol(GV);
     791             : 
     792             :     // FIXME: Remove this when Darwin transition to @GOT like syntax.
     793        1840 :     MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
     794             :     MachineModuleInfoMachO &MMIMachO =
     795         920 :       MMI->getObjFileInfo<MachineModuleInfoMachO>();
     796             :     MachineModuleInfoImpl::StubValueTy &StubSym =
     797         920 :         GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(MCSym)
     798             :                             : MMIMachO.getGVStubEntry(MCSym);
     799             : 
     800         920 :     if (!StubSym.getPointer())
     801         842 :       StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
     802         421 :                                                    !GV->hasInternalLinkage());
     803             :     return MCSym;
     804        3970 :   } else if (Subtarget->isTargetCOFF()) {
     805             :     assert(Subtarget->isTargetWindows() &&
     806             :            "Windows is the only supported COFF target");
     807             : 
     808             :     bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
     809         152 :     if (!IsIndirect)
     810         142 :       return getSymbol(GV);
     811             : 
     812             :     SmallString<128> Name;
     813             :     Name = "__imp_";
     814          10 :     getNameWithPrefix(Name, GV);
     815             : 
     816          20 :     return OutContext.getOrCreateSymbol(Name);
     817        3818 :   } else if (Subtarget->isTargetELF()) {
     818        3818 :     return getSymbol(GV);
     819             :   }
     820           0 :   llvm_unreachable("unexpected target");
     821             : }
     822             : 
     823         658 : void ARMAsmPrinter::
     824             : EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
     825         658 :   const DataLayout &DL = getDataLayout();
     826         658 :   int Size = DL.getTypeAllocSize(MCPV->getType());
     827             : 
     828             :   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
     829             : 
     830         658 :   if (ACPV->isPromotedGlobal()) {
     831             :     // This constant pool entry is actually a global whose storage has been
     832             :     // promoted into the constant pool. This global may be referenced still
     833             :     // by debug information, and due to the way AsmPrinter is set up, the debug
     834             :     // info is immutable by the time we decide to promote globals to constant
     835             :     // pools. Because of this, we need to ensure we emit a symbol for the global
     836             :     // with private linkage (the default) so debug info can refer to it.
     837             :     //
     838             :     // However, if this global is promoted into several functions we must ensure
     839             :     // we don't try and emit duplicate symbols!
     840             :     auto *ACPC = cast<ARMConstantPoolConstant>(ACPV);
     841          93 :     for (const auto *GV : ACPC->promotedGlobals()) {
     842          94 :       if (!EmittedPromotedGlobalLabels.count(GV)) {
     843          57 :         MCSymbol *GVSym = getSymbol(GV);
     844          57 :         OutStreamer->EmitLabel(GVSym);
     845          57 :         EmittedPromotedGlobalLabels.insert(GV);
     846             :       }
     847             :     }
     848          93 :     return EmitGlobalConstant(DL, ACPC->getPromotedGlobalInit());
     849             :   }
     850             : 
     851             :   MCSymbol *MCSym;
     852         565 :   if (ACPV->isLSDA()) {
     853          32 :     MCSym = getCurExceptionSym();
     854         533 :   } else if (ACPV->isBlockAddress()) {
     855             :     const BlockAddress *BA =
     856          18 :       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
     857          18 :     MCSym = GetBlockAddressSymbol(BA);
     858         515 :   } else if (ACPV->isGlobalValue()) {
     859         448 :     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
     860             : 
     861             :     // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
     862             :     // flag the global as MO_NONLAZY.
     863         896 :     unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
     864         448 :     MCSym = GetARMGVSymbol(GV, TF);
     865          67 :   } else if (ACPV->isMachineBasicBlock()) {
     866          32 :     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
     867          32 :     MCSym = MBB->getSymbol();
     868             :   } else {
     869             :     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
     870          35 :     auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
     871          35 :     MCSym = GetExternalSymbolSymbol(Sym);
     872             :   }
     873             : 
     874             :   // Create an MCSymbol for the reference.
     875             :   const MCExpr *Expr =
     876        1695 :     MCSymbolRefExpr::create(MCSym, getModifierVariantKind(ACPV->getModifier()),
     877        1130 :                             OutContext);
     878             : 
     879         565 :   if (ACPV->getPCAdjustment()) {
     880             :     MCSymbol *PCLabel =
     881         444 :         getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
     882         444 :                     ACPV->getLabelId(), OutContext);
     883         444 :     const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
     884             :     PCRelExpr =
     885         444 :       MCBinaryExpr::createAdd(PCRelExpr,
     886         444 :                               MCConstantExpr::create(ACPV->getPCAdjustment(),
     887             :                                                      OutContext),
     888             :                               OutContext);
     889         444 :     if (ACPV->mustAddCurrentAddress()) {
     890             :       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
     891             :       // label, so just emit a local label end reference that instead.
     892          96 :       MCSymbol *DotSym = OutContext.createTempSymbol();
     893          96 :       OutStreamer->EmitLabel(DotSym);
     894          96 :       const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
     895          96 :       PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
     896             :     }
     897         444 :     Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
     898             :   }
     899         565 :   OutStreamer->EmitValue(Expr, Size);
     900             : }
     901             : 
     902          31 : void ARMAsmPrinter::EmitJumpTableAddrs(const MachineInstr *MI) {
     903          31 :   const MachineOperand &MO1 = MI->getOperand(1);
     904          31 :   unsigned JTI = MO1.getIndex();
     905             : 
     906             :   // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
     907             :   // ARM mode tables.
     908          31 :   EmitAlignment(2);
     909             : 
     910             :   // Emit a label for the jump table.
     911          31 :   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
     912          31 :   OutStreamer->EmitLabel(JTISymbol);
     913             : 
     914             :   // Mark the jump table as data-in-code.
     915          31 :   OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
     916             : 
     917             :   // Emit each entry of the table.
     918          31 :   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
     919             :   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
     920          31 :   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
     921             : 
     922          31 :   for (MachineBasicBlock *MBB : JTBBs) {
     923             :     // Construct an MCExpr for the entry. We want a value of the form:
     924             :     // (BasicBlockAddr - TableBeginAddr)
     925             :     //
     926             :     // For example, a table with entries jumping to basic blocks BB0 and BB1
     927             :     // would look like:
     928             :     // LJTI_0_0:
     929             :     //    .word (LBB0 - LJTI_0_0)
     930             :     //    .word (LBB1 - LJTI_0_0)
     931         243 :     const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
     932             : 
     933         243 :     if (isPositionIndependent() || Subtarget->isROPI())
     934         109 :       Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
     935             :                                                                    OutContext),
     936             :                                      OutContext);
     937             :     // If we're generating a table of Thumb addresses in static relocation
     938             :     // model, we need to add one to keep interworking correctly.
     939         134 :     else if (AFI->isThumbFunction())
     940         122 :       Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(1,OutContext),
     941             :                                      OutContext);
     942         243 :     OutStreamer->EmitValue(Expr, 4);
     943             :   }
     944             :   // Mark the end of jump table data-in-code region.
     945          31 :   OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
     946          31 : }
     947             : 
     948           6 : void ARMAsmPrinter::EmitJumpTableInsts(const MachineInstr *MI) {
     949           6 :   const MachineOperand &MO1 = MI->getOperand(1);
     950           6 :   unsigned JTI = MO1.getIndex();
     951             : 
     952             :   // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
     953             :   // ARM mode tables.
     954           6 :   EmitAlignment(2);
     955             : 
     956             :   // Emit a label for the jump table.
     957           6 :   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
     958           6 :   OutStreamer->EmitLabel(JTISymbol);
     959             : 
     960             :   // Emit each entry of the table.
     961           6 :   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
     962             :   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
     963           6 :   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
     964             : 
     965           6 :   for (MachineBasicBlock *MBB : JTBBs) {
     966         162 :     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
     967             :                                                           OutContext);
     968             :     // If this isn't a TBB or TBH, the entries are direct branch instructions.
     969         324 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2B)
     970             :         .addExpr(MBBSymbolExpr)
     971             :         .addImm(ARMCC::AL)
     972         162 :         .addReg(0));
     973             :   }
     974           6 : }
     975             : 
     976          32 : void ARMAsmPrinter::EmitJumpTableTBInst(const MachineInstr *MI,
     977             :                                         unsigned OffsetWidth) {
     978             :   assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
     979          32 :   const MachineOperand &MO1 = MI->getOperand(1);
     980          32 :   unsigned JTI = MO1.getIndex();
     981             : 
     982          32 :   if (Subtarget->isThumb1Only())
     983           9 :     EmitAlignment(2);
     984             :   
     985          32 :   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
     986          32 :   OutStreamer->EmitLabel(JTISymbol);
     987             : 
     988             :   // Emit each entry of the table.
     989          32 :   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
     990             :   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
     991          32 :   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
     992             : 
     993             :   // Mark the jump table as data-in-code.
     994          32 :   OutStreamer->EmitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
     995          32 :                                                : MCDR_DataRegionJT16);
     996             : 
     997          32 :   for (auto MBB : JTBBs) {
     998         377 :     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
     999             :                                                           OutContext);
    1000             :     // Otherwise it's an offset from the dispatch instruction. Construct an
    1001             :     // MCExpr for the entry. We want a value of the form:
    1002             :     // (BasicBlockAddr - TBBInstAddr + 4) / 2
    1003             :     //
    1004             :     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
    1005             :     // would look like:
    1006             :     // LJTI_0_0:
    1007             :     //    .byte (LBB0 - (LCPI0_0 + 4)) / 2
    1008             :     //    .byte (LBB1 - (LCPI0_0 + 4)) / 2
    1009             :     // where LCPI0_0 is a label defined just before the TBB instruction using
    1010             :     // this table.
    1011         377 :     MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
    1012         377 :     const MCExpr *Expr = MCBinaryExpr::createAdd(
    1013         377 :         MCSymbolRefExpr::create(TBInstPC, OutContext),
    1014         377 :         MCConstantExpr::create(4, OutContext), OutContext);
    1015         377 :     Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
    1016         377 :     Expr = MCBinaryExpr::createDiv(Expr, MCConstantExpr::create(2, OutContext),
    1017             :                                    OutContext);
    1018         377 :     OutStreamer->EmitValue(Expr, OffsetWidth);
    1019             :   }
    1020             :   // Mark the end of jump table data-in-code region. 32-bit offsets use
    1021             :   // actual branch instructions here, so we don't mark those as a data-region
    1022             :   // at all.
    1023          32 :   OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
    1024             : 
    1025             :   // Make sure the next instruction is 2-byte aligned.
    1026          32 :   EmitAlignment(1);
    1027          32 : }
    1028             : 
    1029        4258 : void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
    1030             :   assert(MI->getFlag(MachineInstr::FrameSetup) &&
    1031             :       "Only instruction which are involved into frame setup code are allowed");
    1032             : 
    1033             :   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
    1034             :   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
    1035        4258 :   const MachineFunction &MF = *MI->getParent()->getParent();
    1036        4258 :   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
    1037             :   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
    1038             : 
    1039        4258 :   unsigned FramePtr = RegInfo->getFrameRegister(MF);
    1040        4258 :   unsigned Opc = MI->getOpcode();
    1041             :   unsigned SrcReg, DstReg;
    1042             : 
    1043        4258 :   if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
    1044             :     // Two special cases:
    1045             :     // 1) tPUSH does not have src/dst regs.
    1046             :     // 2) for Thumb1 code we sometimes materialize the constant via constpool
    1047             :     // load. Yes, this is pretty fragile, but for now I don't see better
    1048             :     // way... :(
    1049         863 :     SrcReg = DstReg = ARM::SP;
    1050             :   } else {
    1051        3395 :     SrcReg = MI->getOperand(1).getReg();
    1052        3395 :     DstReg = MI->getOperand(0).getReg();
    1053             :   }
    1054             : 
    1055             :   // Try to figure out the unwinding opcode out of src / dst regs.
    1056        4258 :   if (MI->mayStore()) {
    1057             :     // Register saves.
    1058             :     assert(DstReg == ARM::SP &&
    1059             :            "Only stack pointer as a destination reg is supported");
    1060             : 
    1061             :     SmallVector<unsigned, 4> RegList;
    1062             :     // Skip src & dst reg, and pred ops.
    1063             :     unsigned StartOp = 2 + 2;
    1064             :     // Use all the operands.
    1065             :     unsigned NumOffset = 0;
    1066             :     // Amount of SP adjustment folded into a push.
    1067             :     unsigned Pad = 0;
    1068             : 
    1069        2642 :     switch (Opc) {
    1070           0 :     default:
    1071           0 :       MI->print(errs());
    1072           0 :       llvm_unreachable("Unsupported opcode for unwinding information");
    1073         843 :     case ARM::tPUSH:
    1074             :       // Special case here: no src & dst reg, but two extra imp ops.
    1075             :       StartOp = 2; NumOffset = 2;
    1076             :       LLVM_FALLTHROUGH;
    1077        2634 :     case ARM::STMDB_UPD:
    1078             :     case ARM::t2STMDB_UPD:
    1079             :     case ARM::VSTMDDB_UPD:
    1080             :       assert(SrcReg == ARM::SP &&
    1081             :              "Only stack pointer as a source reg is supported");
    1082        9902 :       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
    1083        9902 :            i != NumOps; ++i) {
    1084        7268 :         const MachineOperand &MO = MI->getOperand(i);
    1085             :         // Actually, there should never be any impdef stuff here. Skip it
    1086             :         // temporary to workaround PR11902.
    1087        7268 :         if (MO.isImplicit())
    1088           0 :           continue;
    1089             :         // Registers, pushed as a part of folding an SP update into the
    1090             :         // push instruction are marked as undef and should not be
    1091             :         // restored when unwinding, because the function can modify the
    1092             :         // corresponding stack slots.
    1093        7305 :         if (MO.isUndef()) {
    1094             :           assert(RegList.empty() &&
    1095             :                  "Pad registers must come before restored ones");
    1096          37 :           Pad += 4;
    1097          37 :           continue;
    1098             :         }
    1099        7231 :         RegList.push_back(MO.getReg());
    1100        2634 :       }
    1101             :       break;
    1102           8 :     case ARM::STR_PRE_IMM:
    1103             :     case ARM::STR_PRE_REG:
    1104             :     case ARM::t2STR_PRE:
    1105             :       assert(MI->getOperand(2).getReg() == ARM::SP &&
    1106             :              "Only stack pointer as a source reg is supported");
    1107           8 :       RegList.push_back(SrcReg);
    1108           8 :       break;
    1109             :     }
    1110        2642 :     if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
    1111        2613 :       ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
    1112             :       // Account for the SP adjustment, folded into the push.
    1113        2613 :       if (Pad)
    1114           9 :         ATS.emitPad(Pad);
    1115             :     }
    1116             :   } else {
    1117             :     // Changes of stack / frame pointer.
    1118        1616 :     if (SrcReg == ARM::SP) {
    1119             :       int64_t Offset = 0;
    1120        1616 :       switch (Opc) {
    1121           0 :       default:
    1122           0 :         MI->print(errs());
    1123           0 :         llvm_unreachable("Unsupported opcode for unwinding information");
    1124             :       case ARM::MOVr:
    1125             :       case ARM::tMOVr:
    1126             :         Offset = 0;
    1127             :         break;
    1128         153 :       case ARM::ADDri:
    1129             :       case ARM::t2ADDri:
    1130         153 :         Offset = -MI->getOperand(2).getImm();
    1131         153 :         break;
    1132         685 :       case ARM::SUBri:
    1133             :       case ARM::t2SUBri:
    1134         685 :         Offset = MI->getOperand(2).getImm();
    1135         685 :         break;
    1136         461 :       case ARM::tSUBspi:
    1137         461 :         Offset = MI->getOperand(2).getImm()*4;
    1138         461 :         break;
    1139         160 :       case ARM::tADDspi:
    1140             :       case ARM::tADDrSPi:
    1141         160 :         Offset = -MI->getOperand(2).getImm()*4;
    1142         160 :         break;
    1143          20 :       case ARM::tLDRpci: {
    1144             :         // Grab the constpool index and check, whether it corresponds to
    1145             :         // original or cloned constpool entry.
    1146          20 :         unsigned CPI = MI->getOperand(1).getIndex();
    1147          20 :         const MachineConstantPool *MCP = MF.getConstantPool();
    1148          40 :         if (CPI >= MCP->getConstants().size())
    1149             :           CPI = AFI.getOriginalCPIdx(CPI);
    1150             :         assert(CPI != -1U && "Invalid constpool index");
    1151             : 
    1152             :         // Derive the actual offset.
    1153          20 :         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
    1154             :         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
    1155             :         // FIXME: Check for user, it should be "add" instruction!
    1156          40 :         Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
    1157          20 :         break;
    1158             :       }
    1159             :       }
    1160             : 
    1161        1616 :       if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
    1162        1587 :         if (DstReg == FramePtr && FramePtr != ARM::SP)
    1163             :           // Set-up of the frame pointer. Positive values correspond to "add"
    1164             :           // instruction.
    1165         439 :           ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
    1166        1148 :         else if (DstReg == ARM::SP) {
    1167             :           // Change of SP by an offset. Positive values correspond to "sub"
    1168             :           // instruction.
    1169        1148 :           ATS.emitPad(Offset);
    1170             :         } else {
    1171             :           // Move of SP to a register.  Positive values correspond to an "add"
    1172             :           // instruction.
    1173           0 :           ATS.emitMovSP(DstReg, -Offset);
    1174             :         }
    1175             :       }
    1176           0 :     } else if (DstReg == ARM::SP) {
    1177           0 :       MI->print(errs());
    1178           0 :       llvm_unreachable("Unsupported opcode for unwinding information");
    1179             :     }
    1180             :     else {
    1181           0 :       MI->print(errs());
    1182           0 :       llvm_unreachable("Unsupported opcode for unwinding information");
    1183             :     }
    1184             :   }
    1185        4258 : }
    1186             : 
    1187             : // Simple pseudo-instructions have their lowering (with expansion to real
    1188             : // instructions) auto-generated.
    1189             : #include "ARMGenMCPseudoLowering.inc"
    1190             : 
    1191      136529 : void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
    1192      136529 :   const DataLayout &DL = getDataLayout();
    1193             :   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
    1194             :   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
    1195             : 
    1196      136529 :   const MachineFunction &MF = *MI->getParent()->getParent();
    1197      136529 :   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
    1198             :   unsigned FramePtr = STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
    1199             : 
    1200             :   // If we just ended a constant pool, mark it as such.
    1201      137897 :   if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
    1202          37 :     OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
    1203          37 :     InConstantPool = false;
    1204             :   }
    1205             : 
    1206             :   // Emit unwinding stuff for frame-related instructions
    1207      207925 :   if (Subtarget->isTargetEHABICompatible() &&
    1208       71396 :        MI->getFlag(MachineInstr::FrameSetup))
    1209        4258 :     EmitUnwindingInstruction(MI);
    1210             : 
    1211             :   // Do any auto-generated pseudo lowerings.
    1212      136529 :   if (emitPseudoExpansionLowering(*OutStreamer, MI))
    1213       13448 :     return;
    1214             : 
    1215             :   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
    1216             :          "Pseudo flag setting opcode should be expanded early");
    1217             : 
    1218             :   // Check for manual lowerings.
    1219      128810 :   unsigned Opc = MI->getOpcode();
    1220      128810 :   switch (Opc) {
    1221           0 :   case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
    1222           0 :   case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
    1223         278 :   case ARM::LEApcrel:
    1224             :   case ARM::tLEApcrel:
    1225             :   case ARM::t2LEApcrel: {
    1226             :     // FIXME: Need to also handle globals and externals
    1227         278 :     MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
    1228        1112 :     EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
    1229         166 :                                                ARM::t2LEApcrel ? ARM::t2ADR
    1230             :                   : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
    1231             :                      : ARM::ADR))
    1232         278 :       .addReg(MI->getOperand(0).getReg())
    1233         278 :       .addExpr(MCSymbolRefExpr::create(CPISymbol, OutContext))
    1234             :       // Add predicate operands.
    1235         278 :       .addImm(MI->getOperand(2).getImm())
    1236         278 :       .addReg(MI->getOperand(3).getReg()));
    1237         278 :     return;
    1238             :   }
    1239          38 :   case ARM::LEApcrelJT:
    1240             :   case ARM::tLEApcrelJT:
    1241             :   case ARM::t2LEApcrelJT: {
    1242             :     MCSymbol *JTIPICSymbol =
    1243          38 :       GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
    1244         152 :     EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
    1245          34 :                                                ARM::t2LEApcrelJT ? ARM::t2ADR
    1246             :                   : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
    1247             :                      : ARM::ADR))
    1248          38 :       .addReg(MI->getOperand(0).getReg())
    1249          38 :       .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
    1250             :       // Add predicate operands.
    1251          38 :       .addImm(MI->getOperand(2).getImm())
    1252          38 :       .addReg(MI->getOperand(3).getReg()));
    1253          38 :     return;
    1254             :   }
    1255             :   // Darwin call instructions are just normal call instructions with different
    1256             :   // clobber semantics (they clobber R9).
    1257           2 :   case ARM::BX_CALL: {
    1258           4 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
    1259           2 :       .addReg(ARM::LR)
    1260           2 :       .addReg(ARM::PC)
    1261             :       // Add predicate operands.
    1262             :       .addImm(ARMCC::AL)
    1263           2 :       .addReg(0)
    1264             :       // Add 's' bit operand (always reg0 for this)
    1265           2 :       .addReg(0));
    1266             : 
    1267             :     assert(Subtarget->hasV4TOps());
    1268           4 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
    1269           2 :       .addReg(MI->getOperand(0).getReg()));
    1270           2 :     return;
    1271             :   }
    1272          63 :   case ARM::tBX_CALL: {
    1273          63 :     if (Subtarget->hasV5TOps())
    1274           0 :       llvm_unreachable("Expected BLX to be selected for v5t+");
    1275             : 
    1276             :     // On ARM v4t, when doing a call from thumb mode, we need to ensure
    1277             :     // that the saved lr has its LSB set correctly (the arch doesn't
    1278             :     // have blx).
    1279             :     // So here we generate a bl to a small jump pad that does bx rN.
    1280             :     // The jump pads are emitted after the function body.
    1281             : 
    1282          63 :     unsigned TReg = MI->getOperand(0).getReg();
    1283             :     MCSymbol *TRegSym = nullptr;
    1284          97 :     for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
    1285          37 :       if (TIP.first == TReg) {
    1286          20 :         TRegSym = TIP.second;
    1287          20 :         break;
    1288             :       }
    1289             :     }
    1290             : 
    1291          63 :     if (!TRegSym) {
    1292          43 :       TRegSym = OutContext.createTempSymbol();
    1293          43 :       ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
    1294             :     }
    1295             : 
    1296             :     // Create a link-saving branch to the Reg Indirect Jump Pad.
    1297         126 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBL)
    1298             :         // Predicate comes first here.
    1299          63 :         .addImm(ARMCC::AL).addReg(0)
    1300          63 :         .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
    1301             :     return;
    1302             :   }
    1303           9 :   case ARM::BMOVPCRX_CALL: {
    1304          18 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
    1305           9 :       .addReg(ARM::LR)
    1306           9 :       .addReg(ARM::PC)
    1307             :       // Add predicate operands.
    1308             :       .addImm(ARMCC::AL)
    1309           9 :       .addReg(0)
    1310             :       // Add 's' bit operand (always reg0 for this)
    1311           9 :       .addReg(0));
    1312             : 
    1313          18 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
    1314           9 :       .addReg(ARM::PC)
    1315           9 :       .addReg(MI->getOperand(0).getReg())
    1316             :       // Add predicate operands.
    1317             :       .addImm(ARMCC::AL)
    1318           9 :       .addReg(0)
    1319             :       // Add 's' bit operand (always reg0 for this)
    1320           9 :       .addReg(0));
    1321           9 :     return;
    1322             :   }
    1323          14 :   case ARM::BMOVPCB_CALL: {
    1324          28 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
    1325          14 :       .addReg(ARM::LR)
    1326          14 :       .addReg(ARM::PC)
    1327             :       // Add predicate operands.
    1328             :       .addImm(ARMCC::AL)
    1329          14 :       .addReg(0)
    1330             :       // Add 's' bit operand (always reg0 for this)
    1331          14 :       .addReg(0));
    1332             : 
    1333          14 :     const MachineOperand &Op = MI->getOperand(0);
    1334          14 :     const GlobalValue *GV = Op.getGlobal();
    1335             :     const unsigned TF = Op.getTargetFlags();
    1336          14 :     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
    1337          14 :     const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
    1338          28 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc)
    1339             :       .addExpr(GVSymExpr)
    1340             :       // Add predicate operands.
    1341             :       .addImm(ARMCC::AL)
    1342          14 :       .addReg(0));
    1343          14 :     return;
    1344             :   }
    1345             :   case ARM::MOVi16_ga_pcrel:
    1346             :   case ARM::t2MOVi16_ga_pcrel: {
    1347             :     MCInst TmpInst;
    1348         624 :     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
    1349        1872 :     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
    1350             : 
    1351         624 :     unsigned TF = MI->getOperand(1).getTargetFlags();
    1352         624 :     const GlobalValue *GV = MI->getOperand(1).getGlobal();
    1353         624 :     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
    1354         624 :     const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
    1355             : 
    1356             :     MCSymbol *LabelSym =
    1357        1248 :         getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
    1358        1248 :                     MI->getOperand(2).getImm(), OutContext);
    1359         624 :     const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
    1360         624 :     unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
    1361             :     const MCExpr *PCRelExpr =
    1362         624 :       ARMMCExpr::createLower16(MCBinaryExpr::createSub(GVSymExpr,
    1363             :                                       MCBinaryExpr::createAdd(LabelSymExpr,
    1364         624 :                                       MCConstantExpr::create(PCAdj, OutContext),
    1365         624 :                                       OutContext), OutContext), OutContext);
    1366        1248 :       TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
    1367             : 
    1368             :     // Add predicate operands.
    1369        1248 :     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
    1370        1248 :     TmpInst.addOperand(MCOperand::createReg(0));
    1371             :     // Add 's' bit operand (always reg0 for this)
    1372        1248 :     TmpInst.addOperand(MCOperand::createReg(0));
    1373         624 :     EmitToStreamer(*OutStreamer, TmpInst);
    1374             :     return;
    1375             :   }
    1376             :   case ARM::MOVTi16_ga_pcrel:
    1377             :   case ARM::t2MOVTi16_ga_pcrel: {
    1378             :     MCInst TmpInst;
    1379         624 :     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
    1380             :                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
    1381        1872 :     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
    1382        1872 :     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
    1383             : 
    1384         624 :     unsigned TF = MI->getOperand(2).getTargetFlags();
    1385         624 :     const GlobalValue *GV = MI->getOperand(2).getGlobal();
    1386         624 :     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
    1387         624 :     const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
    1388             : 
    1389             :     MCSymbol *LabelSym =
    1390        1248 :         getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
    1391        1248 :                     MI->getOperand(3).getImm(), OutContext);
    1392         624 :     const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
    1393         624 :     unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
    1394             :     const MCExpr *PCRelExpr =
    1395         624 :         ARMMCExpr::createUpper16(MCBinaryExpr::createSub(GVSymExpr,
    1396             :                                    MCBinaryExpr::createAdd(LabelSymExpr,
    1397         624 :                                       MCConstantExpr::create(PCAdj, OutContext),
    1398         624 :                                           OutContext), OutContext), OutContext);
    1399        1248 :       TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
    1400             :     // Add predicate operands.
    1401        1248 :     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
    1402        1248 :     TmpInst.addOperand(MCOperand::createReg(0));
    1403             :     // Add 's' bit operand (always reg0 for this)
    1404        1248 :     TmpInst.addOperand(MCOperand::createReg(0));
    1405         624 :     EmitToStreamer(*OutStreamer, TmpInst);
    1406             :     return;
    1407             :   }
    1408         622 :   case ARM::tPICADD: {
    1409             :     // This is a pseudo op for a label + instruction sequence, which looks like:
    1410             :     // LPC0:
    1411             :     //     add r0, pc
    1412             :     // This adds the address of LPC0 to r0.
    1413             : 
    1414             :     // Emit the label.
    1415        1244 :     OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
    1416             :                                        getFunctionNumber(),
    1417        1244 :                                        MI->getOperand(2).getImm(), OutContext));
    1418             : 
    1419             :     // Form and emit the add.
    1420        1244 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
    1421         622 :       .addReg(MI->getOperand(0).getReg())
    1422         622 :       .addReg(MI->getOperand(0).getReg())
    1423         622 :       .addReg(ARM::PC)
    1424             :       // Add predicate operands.
    1425             :       .addImm(ARMCC::AL)
    1426         622 :       .addReg(0));
    1427         622 :     return;
    1428             :   }
    1429         204 :   case ARM::PICADD: {
    1430             :     // This is a pseudo op for a label + instruction sequence, which looks like:
    1431             :     // LPC0:
    1432             :     //     add r0, pc, r0
    1433             :     // This adds the address of LPC0 to r0.
    1434             : 
    1435             :     // Emit the label.
    1436         408 :     OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
    1437             :                                        getFunctionNumber(),
    1438         408 :                                        MI->getOperand(2).getImm(), OutContext));
    1439             : 
    1440             :     // Form and emit the add.
    1441         408 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
    1442         204 :       .addReg(MI->getOperand(0).getReg())
    1443         204 :       .addReg(ARM::PC)
    1444         204 :       .addReg(MI->getOperand(1).getReg())
    1445             :       // Add predicate operands.
    1446         204 :       .addImm(MI->getOperand(3).getImm())
    1447         204 :       .addReg(MI->getOperand(4).getReg())
    1448             :       // Add 's' bit operand (always reg0 for this)
    1449         204 :       .addReg(0));
    1450         204 :     return;
    1451             :   }
    1452         242 :   case ARM::PICSTR:
    1453             :   case ARM::PICSTRB:
    1454             :   case ARM::PICSTRH:
    1455             :   case ARM::PICLDR:
    1456             :   case ARM::PICLDRB:
    1457             :   case ARM::PICLDRH:
    1458             :   case ARM::PICLDRSB:
    1459             :   case ARM::PICLDRSH: {
    1460             :     // This is a pseudo op for a label + instruction sequence, which looks like:
    1461             :     // LPC0:
    1462             :     //     OP r0, [pc, r0]
    1463             :     // The LCP0 label is referenced by a constant pool entry in order to get
    1464             :     // a PC-relative address at the ldr instruction.
    1465             : 
    1466             :     // Emit the label.
    1467         484 :     OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
    1468             :                                        getFunctionNumber(),
    1469         484 :                                        MI->getOperand(2).getImm(), OutContext));
    1470             : 
    1471             :     // Form and emit the load
    1472             :     unsigned Opcode;
    1473         484 :     switch (MI->getOpcode()) {
    1474           0 :     default:
    1475           0 :       llvm_unreachable("Unexpected opcode!");
    1476             :     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
    1477           0 :     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
    1478           0 :     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
    1479         242 :     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
    1480           0 :     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
    1481           0 :     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
    1482           0 :     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
    1483           0 :     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
    1484             :     }
    1485         484 :     EmitToStreamer(*OutStreamer, MCInstBuilder(Opcode)
    1486         242 :       .addReg(MI->getOperand(0).getReg())
    1487         242 :       .addReg(ARM::PC)
    1488         242 :       .addReg(MI->getOperand(1).getReg())
    1489             :       .addImm(0)
    1490             :       // Add predicate operands.
    1491         242 :       .addImm(MI->getOperand(3).getImm())
    1492         242 :       .addReg(MI->getOperand(4).getReg()));
    1493             : 
    1494         242 :     return;
    1495             :   }
    1496        2773 :   case ARM::CONSTPOOL_ENTRY: {
    1497        2773 :     if (Subtarget->genExecuteOnly())
    1498           0 :       llvm_unreachable("execute-only should not generate constant pools");
    1499             : 
    1500             :     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
    1501             :     /// in the function.  The first operand is the ID# for this instruction, the
    1502             :     /// second is the index into the MachineConstantPool that this is, the third
    1503             :     /// is the size in bytes of this constant pool entry.
    1504             :     /// The required alignment is specified on the basic block holding this MI.
    1505        2773 :     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
    1506        2773 :     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
    1507             : 
    1508             :     // If this is the first entry of the pool, mark it.
    1509        2773 :     if (!InConstantPool) {
    1510        1442 :       OutStreamer->EmitDataRegion(MCDR_DataRegion);
    1511        1442 :       InConstantPool = true;
    1512             :     }
    1513             : 
    1514        2773 :     OutStreamer->EmitLabel(GetCPISymbol(LabelId));
    1515             : 
    1516        2773 :     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
    1517        5546 :     if (MCPE.isMachineConstantPoolEntry())
    1518         658 :       EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
    1519             :     else
    1520        2115 :       EmitGlobalConstant(DL, MCPE.Val.ConstVal);
    1521             :     return;
    1522             :   }
    1523          31 :   case ARM::JUMPTABLE_ADDRS:
    1524          31 :     EmitJumpTableAddrs(MI);
    1525          31 :     return;
    1526           6 :   case ARM::JUMPTABLE_INSTS:
    1527           6 :     EmitJumpTableInsts(MI);
    1528           6 :     return;
    1529          32 :   case ARM::JUMPTABLE_TBB:
    1530             :   case ARM::JUMPTABLE_TBH:
    1531          32 :     EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
    1532          32 :     return;
    1533           6 :   case ARM::t2BR_JT: {
    1534          12 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
    1535           6 :       .addReg(ARM::PC)
    1536           6 :       .addReg(MI->getOperand(0).getReg())
    1537             :       // Add predicate operands.
    1538             :       .addImm(ARMCC::AL)
    1539           6 :       .addReg(0));
    1540           6 :     return;
    1541             :   }
    1542          23 :   case ARM::t2TBB_JT:
    1543             :   case ARM::t2TBH_JT: {
    1544          23 :     unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
    1545             :     // Lower and emit the PC label, then the instruction itself.
    1546          23 :     OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
    1547          46 :     EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
    1548          23 :                                      .addReg(MI->getOperand(0).getReg())
    1549          23 :                                      .addReg(MI->getOperand(1).getReg())
    1550             :                                      // Add predicate operands.
    1551             :                                      .addImm(ARMCC::AL)
    1552          23 :                                      .addReg(0));
    1553          23 :     return;
    1554             :   }
    1555           9 :   case ARM::tTBB_JT:
    1556             :   case ARM::tTBH_JT: {
    1557             : 
    1558             :     bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
    1559           9 :     unsigned Base = MI->getOperand(0).getReg();
    1560           9 :     unsigned Idx = MI->getOperand(1).getReg();
    1561             :     assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
    1562             : 
    1563             :     // Multiply up idx if necessary.
    1564           9 :     if (!Is8Bit)
    1565           2 :       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri)
    1566           1 :                                        .addReg(Idx)
    1567           1 :                                        .addReg(ARM::CPSR)
    1568           1 :                                        .addReg(Idx)
    1569             :                                        .addImm(1)
    1570             :                                        // Add predicate operands.
    1571             :                                        .addImm(ARMCC::AL)
    1572           1 :                                        .addReg(0));
    1573             : 
    1574           9 :     if (Base == ARM::PC) {
    1575             :       // TBB [base, idx] =
    1576             :       //    ADDS idx, idx, base
    1577             :       //    LDRB idx, [idx, #4] ; or LDRH if TBH
    1578             :       //    LSLS idx, #1
    1579             :       //    ADDS pc, pc, idx
    1580             : 
    1581             :       // When using PC as the base, it's important that there is no padding
    1582             :       // between the last ADDS and the start of the jump table. The jump table
    1583             :       // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
    1584             :       //
    1585             :       // FIXME: Ideally we could vary the LDRB index based on the padding
    1586             :       // between the sequence and jump table, however that relies on MCExprs
    1587             :       // for load indexes which are currently not supported.
    1588           9 :       OutStreamer->EmitCodeAlignment(4);
    1589          18 :       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
    1590           9 :                                        .addReg(Idx)
    1591           9 :                                        .addReg(Idx)
    1592           9 :                                        .addReg(Base)
    1593             :                                        // Add predicate operands.
    1594             :                                        .addImm(ARMCC::AL)
    1595           9 :                                        .addReg(0));
    1596             : 
    1597           9 :       unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
    1598          18 :       EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
    1599           9 :                                        .addReg(Idx)
    1600           9 :                                        .addReg(Idx)
    1601           9 :                                        .addImm(Is8Bit ? 4 : 2)
    1602             :                                        // Add predicate operands.
    1603             :                                        .addImm(ARMCC::AL)
    1604           9 :                                        .addReg(0));
    1605             :     } else {
    1606             :       // TBB [base, idx] =
    1607             :       //    LDRB idx, [base, idx] ; or LDRH if TBH
    1608             :       //    LSLS idx, #1
    1609             :       //    ADDS pc, pc, idx
    1610             : 
    1611           0 :       unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
    1612           0 :       EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
    1613           0 :                                        .addReg(Idx)
    1614           0 :                                        .addReg(Base)
    1615           0 :                                        .addReg(Idx)
    1616             :                                        // Add predicate operands.
    1617             :                                        .addImm(ARMCC::AL)
    1618           0 :                                        .addReg(0));
    1619             :     }
    1620             : 
    1621          18 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri)
    1622           9 :                                      .addReg(Idx)
    1623           9 :                                      .addReg(ARM::CPSR)
    1624           9 :                                      .addReg(Idx)
    1625             :                                      .addImm(1)
    1626             :                                      // Add predicate operands.
    1627             :                                      .addImm(ARMCC::AL)
    1628           9 :                                      .addReg(0));
    1629             : 
    1630           9 :     OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
    1631          18 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
    1632           9 :                                      .addReg(ARM::PC)
    1633           9 :                                      .addReg(ARM::PC)
    1634           9 :                                      .addReg(Idx)
    1635             :                                      // Add predicate operands.
    1636             :                                      .addImm(ARMCC::AL)
    1637           9 :                                      .addReg(0));
    1638           9 :     return;
    1639             :   }
    1640             :   case ARM::tBR_JTr:
    1641             :   case ARM::BR_JTr: {
    1642             :     // mov pc, target
    1643             :     MCInst TmpInst;
    1644          10 :     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
    1645             :       ARM::MOVr : ARM::tMOVr;
    1646             :     TmpInst.setOpcode(Opc);
    1647          20 :     TmpInst.addOperand(MCOperand::createReg(ARM::PC));
    1648          30 :     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
    1649             :     // Add predicate operands.
    1650          20 :     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
    1651          20 :     TmpInst.addOperand(MCOperand::createReg(0));
    1652             :     // Add 's' bit operand (always reg0 for this)
    1653          10 :     if (Opc == ARM::MOVr)
    1654           8 :       TmpInst.addOperand(MCOperand::createReg(0));
    1655          10 :     EmitToStreamer(*OutStreamer, TmpInst);
    1656             :     return;
    1657             :   }
    1658             :   case ARM::BR_JTm_i12: {
    1659             :     // ldr pc, target
    1660             :     MCInst TmpInst;
    1661             :     TmpInst.setOpcode(ARM::LDRi12);
    1662           0 :     TmpInst.addOperand(MCOperand::createReg(ARM::PC));
    1663           0 :     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
    1664           0 :     TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
    1665             :     // Add predicate operands.
    1666           0 :     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
    1667           0 :     TmpInst.addOperand(MCOperand::createReg(0));
    1668           0 :     EmitToStreamer(*OutStreamer, TmpInst);
    1669             :     return;
    1670             :   }
    1671             :   case ARM::BR_JTm_rs: {
    1672             :     // ldr pc, target
    1673             :     MCInst TmpInst;
    1674             :     TmpInst.setOpcode(ARM::LDRrs);
    1675           4 :     TmpInst.addOperand(MCOperand::createReg(ARM::PC));
    1676           6 :     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
    1677           6 :     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
    1678           6 :     TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
    1679             :     // Add predicate operands.
    1680           4 :     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
    1681           4 :     TmpInst.addOperand(MCOperand::createReg(0));
    1682           2 :     EmitToStreamer(*OutStreamer, TmpInst);
    1683             :     return;
    1684             :   }
    1685          19 :   case ARM::BR_JTadd: {
    1686             :     // add pc, target, idx
    1687          38 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
    1688          19 :       .addReg(ARM::PC)
    1689          19 :       .addReg(MI->getOperand(0).getReg())
    1690          19 :       .addReg(MI->getOperand(1).getReg())
    1691             :       // Add predicate operands.
    1692             :       .addImm(ARMCC::AL)
    1693          19 :       .addReg(0)
    1694             :       // Add 's' bit operand (always reg0 for this)
    1695          19 :       .addReg(0));
    1696          19 :     return;
    1697             :   }
    1698          10 :   case ARM::SPACE:
    1699          10 :     OutStreamer->EmitZeros(MI->getOperand(1).getImm());
    1700          10 :     return;
    1701         154 :   case ARM::TRAP: {
    1702             :     // Non-Darwin binutils don't yet support the "trap" mnemonic.
    1703             :     // FIXME: Remove this special case when they do.
    1704         308 :     if (!Subtarget->isTargetMachO()) {
    1705             :       uint32_t Val = 0xe7ffdefeUL;
    1706          74 :       OutStreamer->AddComment("trap");
    1707          37 :       ATS.emitInst(Val);
    1708          37 :       return;
    1709             :     }
    1710             :     break;
    1711             :   }
    1712           6 :   case ARM::TRAPNaCl: {
    1713             :     uint32_t Val = 0xe7fedef0UL;
    1714          12 :     OutStreamer->AddComment("trap");
    1715           6 :     ATS.emitInst(Val);
    1716           6 :     return;
    1717             :   }
    1718         147 :   case ARM::tTRAP: {
    1719             :     // Non-Darwin binutils don't yet support the "trap" mnemonic.
    1720             :     // FIXME: Remove this special case when they do.
    1721         294 :     if (!Subtarget->isTargetMachO()) {
    1722             :       uint16_t Val = 0xdefe;
    1723          24 :       OutStreamer->AddComment("trap");
    1724          12 :       ATS.emitInst(Val, 'n');
    1725          12 :       return;
    1726             :     }
    1727             :     break;
    1728             :   }
    1729           4 :   case ARM::t2Int_eh_sjlj_setjmp:
    1730             :   case ARM::t2Int_eh_sjlj_setjmp_nofp:
    1731             :   case ARM::tInt_eh_sjlj_setjmp: {
    1732             :     // Two incoming args: GPR:$src, GPR:$val
    1733             :     // mov $val, pc
    1734             :     // adds $val, #7
    1735             :     // str $val, [$src, #4]
    1736             :     // movs r0, #0
    1737             :     // b LSJLJEH
    1738             :     // movs r0, #1
    1739             :     // LSJLJEH:
    1740           4 :     unsigned SrcReg = MI->getOperand(0).getReg();
    1741           4 :     unsigned ValReg = MI->getOperand(1).getReg();
    1742           8 :     MCSymbol *Label = OutContext.createTempSymbol("SJLJEH", false, true);
    1743           8 :     OutStreamer->AddComment("eh_setjmp begin");
    1744           8 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
    1745           4 :       .addReg(ValReg)
    1746           4 :       .addReg(ARM::PC)
    1747             :       // Predicate.
    1748             :       .addImm(ARMCC::AL)
    1749           4 :       .addReg(0));
    1750             : 
    1751           8 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi3)
    1752           4 :       .addReg(ValReg)
    1753             :       // 's' bit operand
    1754           4 :       .addReg(ARM::CPSR)
    1755           4 :       .addReg(ValReg)
    1756             :       .addImm(7)
    1757             :       // Predicate.
    1758             :       .addImm(ARMCC::AL)
    1759           4 :       .addReg(0));
    1760             : 
    1761           8 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSTRi)
    1762           4 :       .addReg(ValReg)
    1763           4 :       .addReg(SrcReg)
    1764             :       // The offset immediate is #4. The operand value is scaled by 4 for the
    1765             :       // tSTR instruction.
    1766             :       .addImm(1)
    1767             :       // Predicate.
    1768             :       .addImm(ARMCC::AL)
    1769           4 :       .addReg(0));
    1770             : 
    1771           8 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
    1772           4 :       .addReg(ARM::R0)
    1773           4 :       .addReg(ARM::CPSR)
    1774             :       .addImm(0)
    1775             :       // Predicate.
    1776             :       .addImm(ARMCC::AL)
    1777           4 :       .addReg(0));
    1778             : 
    1779           4 :     const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
    1780           8 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tB)
    1781             :       .addExpr(SymbolExpr)
    1782             :       .addImm(ARMCC::AL)
    1783           4 :       .addReg(0));
    1784             : 
    1785           8 :     OutStreamer->AddComment("eh_setjmp end");
    1786           8 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
    1787           4 :       .addReg(ARM::R0)
    1788           4 :       .addReg(ARM::CPSR)
    1789             :       .addImm(1)
    1790             :       // Predicate.
    1791             :       .addImm(ARMCC::AL)
    1792           4 :       .addReg(0));
    1793             : 
    1794           4 :     OutStreamer->EmitLabel(Label);
    1795           4 :     return;
    1796             :   }
    1797             : 
    1798           4 :   case ARM::Int_eh_sjlj_setjmp_nofp:
    1799             :   case ARM::Int_eh_sjlj_setjmp: {
    1800             :     // Two incoming args: GPR:$src, GPR:$val
    1801             :     // add $val, pc, #8
    1802             :     // str $val, [$src, #+4]
    1803             :     // mov r0, #0
    1804             :     // add pc, pc, #0
    1805             :     // mov r0, #1
    1806           4 :     unsigned SrcReg = MI->getOperand(0).getReg();
    1807           4 :     unsigned ValReg = MI->getOperand(1).getReg();
    1808             : 
    1809           8 :     OutStreamer->AddComment("eh_setjmp begin");
    1810           8 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
    1811           4 :       .addReg(ValReg)
    1812           4 :       .addReg(ARM::PC)
    1813             :       .addImm(8)
    1814             :       // Predicate.
    1815             :       .addImm(ARMCC::AL)
    1816           4 :       .addReg(0)
    1817             :       // 's' bit operand (always reg0 for this).
    1818           4 :       .addReg(0));
    1819             : 
    1820           8 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STRi12)
    1821           4 :       .addReg(ValReg)
    1822           4 :       .addReg(SrcReg)
    1823             :       .addImm(4)
    1824             :       // Predicate.
    1825             :       .addImm(ARMCC::AL)
    1826           4 :       .addReg(0));
    1827             : 
    1828           8 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
    1829           4 :       .addReg(ARM::R0)
    1830             :       .addImm(0)
    1831             :       // Predicate.
    1832             :       .addImm(ARMCC::AL)
    1833           4 :       .addReg(0)
    1834             :       // 's' bit operand (always reg0 for this).
    1835           4 :       .addReg(0));
    1836             : 
    1837           8 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
    1838           4 :       .addReg(ARM::PC)
    1839           4 :       .addReg(ARM::PC)
    1840             :       .addImm(0)
    1841             :       // Predicate.
    1842             :       .addImm(ARMCC::AL)
    1843           4 :       .addReg(0)
    1844             :       // 's' bit operand (always reg0 for this).
    1845           4 :       .addReg(0));
    1846             : 
    1847           8 :     OutStreamer->AddComment("eh_setjmp end");
    1848           8 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
    1849           4 :       .addReg(ARM::R0)
    1850             :       .addImm(1)
    1851             :       // Predicate.
    1852             :       .addImm(ARMCC::AL)
    1853           4 :       .addReg(0)
    1854             :       // 's' bit operand (always reg0 for this).
    1855           4 :       .addReg(0));
    1856           4 :     return;
    1857             :   }
    1858           4 :   case ARM::Int_eh_sjlj_longjmp: {
    1859             :     // ldr sp, [$src, #8]
    1860             :     // ldr $scratch, [$src, #4]
    1861             :     // ldr r7, [$src]
    1862             :     // bx $scratch
    1863           4 :     unsigned SrcReg = MI->getOperand(0).getReg();
    1864           4 :     unsigned ScratchReg = MI->getOperand(1).getReg();
    1865           8 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
    1866           4 :       .addReg(ARM::SP)
    1867           4 :       .addReg(SrcReg)
    1868             :       .addImm(8)
    1869             :       // Predicate.
    1870             :       .addImm(ARMCC::AL)
    1871           4 :       .addReg(0));
    1872             : 
    1873           8 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
    1874           4 :       .addReg(ScratchReg)
    1875           4 :       .addReg(SrcReg)
    1876             :       .addImm(4)
    1877             :       // Predicate.
    1878             :       .addImm(ARMCC::AL)
    1879           4 :       .addReg(0));
    1880             : 
    1881           2 :     if (STI.isTargetDarwin() || STI.isTargetWindows()) {
    1882             :       // These platforms always use the same frame register
    1883           4 :       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
    1884           2 :         .addReg(FramePtr)
    1885           2 :         .addReg(SrcReg)
    1886             :         .addImm(0)
    1887             :         // Predicate.
    1888             :         .addImm(ARMCC::AL)
    1889           2 :         .addReg(0));
    1890             :     } else {
    1891             :       // If the calling code might use either R7 or R11 as
    1892             :       // frame pointer register, restore it into both.
    1893           4 :       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
    1894           2 :         .addReg(ARM::R7)
    1895           2 :         .addReg(SrcReg)
    1896             :         .addImm(0)
    1897             :         // Predicate.
    1898             :         .addImm(ARMCC::AL)
    1899           2 :         .addReg(0));
    1900           4 :       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
    1901           2 :         .addReg(ARM::R11)
    1902           2 :         .addReg(SrcReg)
    1903             :         .addImm(0)
    1904             :         // Predicate.
    1905             :         .addImm(ARMCC::AL)
    1906           2 :         .addReg(0));
    1907             :     }
    1908             : 
    1909             :     assert(Subtarget->hasV4TOps());
    1910           8 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
    1911           4 :       .addReg(ScratchReg)
    1912             :       // Predicate.
    1913             :       .addImm(ARMCC::AL)
    1914           4 :       .addReg(0));
    1915           4 :     return;
    1916             :   }
    1917           2 :   case ARM::tInt_eh_sjlj_longjmp: {
    1918             :     // ldr $scratch, [$src, #8]
    1919             :     // mov sp, $scratch
    1920             :     // ldr $scratch, [$src, #4]
    1921             :     // ldr r7, [$src]
    1922             :     // bx $scratch
    1923           2 :     unsigned SrcReg = MI->getOperand(0).getReg();
    1924           2 :     unsigned ScratchReg = MI->getOperand(1).getReg();
    1925             : 
    1926           4 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
    1927           2 :       .addReg(ScratchReg)
    1928           2 :       .addReg(SrcReg)
    1929             :       // The offset immediate is #8. The operand value is scaled by 4 for the
    1930             :       // tLDR instruction.
    1931             :       .addImm(2)
    1932             :       // Predicate.
    1933             :       .addImm(ARMCC::AL)
    1934           2 :       .addReg(0));
    1935             : 
    1936           4 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
    1937           2 :       .addReg(ARM::SP)
    1938           2 :       .addReg(ScratchReg)
    1939             :       // Predicate.
    1940             :       .addImm(ARMCC::AL)
    1941           2 :       .addReg(0));
    1942             : 
    1943           4 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
    1944           2 :       .addReg(ScratchReg)
    1945           2 :       .addReg(SrcReg)
    1946             :       .addImm(1)
    1947             :       // Predicate.
    1948             :       .addImm(ARMCC::AL)
    1949           2 :       .addReg(0));
    1950             : 
    1951           0 :     if (STI.isTargetDarwin() || STI.isTargetWindows()) {
    1952             :       // These platforms always use the same frame register
    1953           4 :       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
    1954           2 :         .addReg(FramePtr)
    1955           2 :         .addReg(SrcReg)
    1956             :         .addImm(0)
    1957             :         // Predicate.
    1958             :         .addImm(ARMCC::AL)
    1959           2 :         .addReg(0));
    1960             :     } else {
    1961             :       // If the calling code might use either R7 or R11 as
    1962             :       // frame pointer register, restore it into both.
    1963           0 :       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
    1964           0 :         .addReg(ARM::R7)
    1965           0 :         .addReg(SrcReg)
    1966             :         .addImm(0)
    1967             :         // Predicate.
    1968             :         .addImm(ARMCC::AL)
    1969           0 :         .addReg(0));
    1970           0 :       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
    1971           0 :         .addReg(ARM::R11)
    1972           0 :         .addReg(SrcReg)
    1973             :         .addImm(0)
    1974             :         // Predicate.
    1975             :         .addImm(ARMCC::AL)
    1976           0 :         .addReg(0));
    1977             :     }
    1978             : 
    1979           4 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
    1980           2 :       .addReg(ScratchReg)
    1981             :       // Predicate.
    1982             :       .addImm(ARMCC::AL)
    1983           2 :       .addReg(0));
    1984           2 :     return;
    1985             :   }
    1986           3 :   case ARM::tInt_WIN_eh_sjlj_longjmp: {
    1987             :     // ldr.w r11, [$src, #0]
    1988             :     // ldr.w  sp, [$src, #8]
    1989             :     // ldr.w  pc, [$src, #4]
    1990             : 
    1991           3 :     unsigned SrcReg = MI->getOperand(0).getReg();
    1992             : 
    1993           6 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
    1994           3 :                                      .addReg(ARM::R11)
    1995           3 :                                      .addReg(SrcReg)
    1996             :                                      .addImm(0)
    1997             :                                      // Predicate
    1998             :                                      .addImm(ARMCC::AL)
    1999           3 :                                      .addReg(0));
    2000           6 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
    2001           3 :                                      .addReg(ARM::SP)
    2002           3 :                                      .addReg(SrcReg)
    2003             :                                      .addImm(8)
    2004             :                                      // Predicate
    2005             :                                      .addImm(ARMCC::AL)
    2006           3 :                                      .addReg(0));
    2007           6 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
    2008           3 :                                      .addReg(ARM::PC)
    2009           3 :                                      .addReg(SrcReg)
    2010             :                                      .addImm(4)
    2011             :                                      // Predicate
    2012             :                                      .addImm(ARMCC::AL)
    2013           3 :                                      .addReg(0));
    2014           3 :     return;
    2015             :   }
    2016           8 :   case ARM::PATCHABLE_FUNCTION_ENTER:
    2017           8 :     LowerPATCHABLE_FUNCTION_ENTER(*MI);
    2018           8 :     return;
    2019           8 :   case ARM::PATCHABLE_FUNCTION_EXIT:
    2020           8 :     LowerPATCHABLE_FUNCTION_EXIT(*MI);
    2021           8 :     return;
    2022           0 :   case ARM::PATCHABLE_TAIL_CALL:
    2023           0 :     LowerPATCHABLE_TAIL_CALL(*MI);
    2024           0 :     return;
    2025             :   }
    2026             : 
    2027             :   MCInst TmpInst;
    2028      123081 :   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
    2029             : 
    2030      123081 :   EmitToStreamer(*OutStreamer, TmpInst);
    2031             : }
    2032             : 
    2033             : //===----------------------------------------------------------------------===//
    2034             : // Target Registry Stuff
    2035             : //===----------------------------------------------------------------------===//
    2036             : 
    2037             : // Force static initialization.
    2038       63049 : extern "C" void LLVMInitializeARMAsmPrinter() {
    2039       63049 :   RegisterAsmPrinter<ARMAsmPrinter> X(getTheARMLETarget());
    2040       63049 :   RegisterAsmPrinter<ARMAsmPrinter> Y(getTheARMBETarget());
    2041       63049 :   RegisterAsmPrinter<ARMAsmPrinter> A(getTheThumbLETarget());
    2042       63049 :   RegisterAsmPrinter<ARMAsmPrinter> B(getTheThumbBETarget());
    2043       63049 : }

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