LCOV - code coverage report
Current view: top level - lib/Target/ARM - ARMAsmPrinter.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 1025 1093 93.8 %
Date: 2017-09-14 15:23:50 Functions: 25 25 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains a printer that converts from our internal representation
      11             : // of machine-dependent LLVM code to GAS-format ARM assembly language.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "ARMAsmPrinter.h"
      16             : #include "ARM.h"
      17             : #include "ARMConstantPoolValue.h"
      18             : #include "ARMMachineFunctionInfo.h"
      19             : #include "ARMTargetMachine.h"
      20             : #include "ARMTargetObjectFile.h"
      21             : #include "InstPrinter/ARMInstPrinter.h"
      22             : #include "MCTargetDesc/ARMAddressingModes.h"
      23             : #include "MCTargetDesc/ARMMCExpr.h"
      24             : #include "llvm/ADT/SetVector.h"
      25             : #include "llvm/ADT/SmallString.h"
      26             : #include "llvm/BinaryFormat/COFF.h"
      27             : #include "llvm/BinaryFormat/ELF.h"
      28             : #include "llvm/CodeGen/MachineFunctionPass.h"
      29             : #include "llvm/CodeGen/MachineJumpTableInfo.h"
      30             : #include "llvm/CodeGen/MachineModuleInfoImpls.h"
      31             : #include "llvm/IR/Constants.h"
      32             : #include "llvm/IR/DataLayout.h"
      33             : #include "llvm/IR/DebugInfo.h"
      34             : #include "llvm/IR/Mangler.h"
      35             : #include "llvm/IR/Module.h"
      36             : #include "llvm/IR/Type.h"
      37             : #include "llvm/MC/MCAsmInfo.h"
      38             : #include "llvm/MC/MCAssembler.h"
      39             : #include "llvm/MC/MCContext.h"
      40             : #include "llvm/MC/MCELFStreamer.h"
      41             : #include "llvm/MC/MCInst.h"
      42             : #include "llvm/MC/MCInstBuilder.h"
      43             : #include "llvm/MC/MCObjectStreamer.h"
      44             : #include "llvm/MC/MCSectionMachO.h"
      45             : #include "llvm/MC/MCStreamer.h"
      46             : #include "llvm/MC/MCSymbol.h"
      47             : #include "llvm/Support/ARMBuildAttributes.h"
      48             : #include "llvm/Support/Debug.h"
      49             : #include "llvm/Support/ErrorHandling.h"
      50             : #include "llvm/Support/TargetParser.h"
      51             : #include "llvm/Support/TargetRegistry.h"
      52             : #include "llvm/Support/raw_ostream.h"
      53             : #include "llvm/Target/TargetMachine.h"
      54             : #include <cctype>
      55             : using namespace llvm;
      56             : 
      57             : #define DEBUG_TYPE "asm-printer"
      58             : 
      59        2576 : ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
      60        2576 :                              std::unique_ptr<MCStreamer> Streamer)
      61        2576 :     : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
      62       15456 :       InConstantPool(false), OptimizationGoals(-1) {}
      63             : 
      64       11977 : void ARMAsmPrinter::EmitFunctionBodyEnd() {
      65             :   // Make sure to terminate any constant pools that were at the end
      66             :   // of the function.
      67       11977 :   if (!InConstantPool)
      68             :     return;
      69        1070 :   InConstantPool = false;
      70        2140 :   OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
      71             : }
      72             : 
      73       11977 : void ARMAsmPrinter::EmitFunctionEntryLabel() {
      74       11977 :   if (AFI->isThumbFunction()) {
      75        9464 :     OutStreamer->EmitAssemblerFlag(MCAF_Code16);
      76        9464 :     OutStreamer->EmitThumbFunc(CurrentFnSym);
      77             :   } else {
      78       14490 :     OutStreamer->EmitAssemblerFlag(MCAF_Code32);
      79             :   }
      80       23954 :   OutStreamer->EmitLabel(CurrentFnSym);
      81       11977 : }
      82             : 
      83          19 : void ARMAsmPrinter::EmitXXStructor(const DataLayout &DL, const Constant *CV) {
      84          19 :   uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType());
      85             :   assert(Size && "C++ constructor pointer had zero size!");
      86             : 
      87          38 :   const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
      88             :   assert(GV && "C++ constructor pointer was not a GlobalValue!");
      89             : 
      90          57 :   const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
      91             :                                                            ARMII::MO_NO_FLAG),
      92          38 :                                             (Subtarget->isTargetELF()
      93             :                                              ? MCSymbolRefExpr::VK_ARM_TARGET1
      94             :                                              : MCSymbolRefExpr::VK_None),
      95          38 :                                             OutContext);
      96             : 
      97          38 :   OutStreamer->EmitValue(E, Size);
      98          19 : }
      99             : 
     100        1664 : void ARMAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
     101        1664 :   if (PromotedGlobals.count(GV))
     102             :     // The global was promoted into a constant pool. It should not be emitted.
     103             :     return;
     104        1607 :   AsmPrinter::EmitGlobalVariable(GV);
     105             : }
     106             : 
     107             : /// runOnMachineFunction - This uses the EmitInstruction()
     108             : /// method to print assembly for each instruction.
     109             : ///
     110       11977 : bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
     111       11977 :   AFI = MF.getInfo<ARMFunctionInfo>();
     112       11977 :   MCP = MF.getConstantPool();
     113       11977 :   Subtarget = &MF.getSubtarget<ARMSubtarget>();
     114             : 
     115       11977 :   SetupMachineFunction(MF);
     116       11977 :   const Function* F = MF.getFunction();
     117       11977 :   const TargetMachine& TM = MF.getTarget();
     118             : 
     119             :   // Collect all globals that had their storage promoted to a constant pool.
     120             :   // Functions are emitted before variables, so this accumulates promoted
     121             :   // globals from all functions in PromotedGlobals.
     122       12071 :   for (auto *GV : AFI->getGlobalsPromotedToConstantPool())
     123          94 :     PromotedGlobals.insert(GV);
     124             :   
     125             :   // Calculate this function's optimization goal.
     126             :   unsigned OptimizationGoal;
     127       11977 :   if (F->hasFnAttribute(Attribute::OptimizeNone))
     128             :     // For best debugging illusion, speed and small size sacrificed
     129             :     OptimizationGoal = 6;
     130       11939 :   else if (F->optForMinSize())
     131             :     // Aggressively for small size, speed and debug illusion sacrificed
     132             :     OptimizationGoal = 4;
     133       11803 :   else if (F->optForSize())
     134             :     // For small size, but speed and debugging illusion preserved
     135             :     OptimizationGoal = 3;
     136       11640 :   else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
     137             :     // Aggressively for speed, small size and debug illusion sacrificed
     138             :     OptimizationGoal = 2;
     139       11568 :   else if (TM.getOptLevel() > CodeGenOpt::None)
     140             :     // For speed, but small size and good debug illusion preserved
     141             :     OptimizationGoal = 1;
     142             :   else // TM.getOptLevel() == CodeGenOpt::None
     143             :     // For good debugging, but speed and small size preserved
     144        1085 :     OptimizationGoal = 5;
     145             : 
     146             :   // Combine a new optimization goal with existing ones.
     147       11977 :   if (OptimizationGoals == -1) // uninitialized goals
     148        2510 :     OptimizationGoals = OptimizationGoal;
     149        9467 :   else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
     150         201 :     OptimizationGoals = 0;
     151             : 
     152       23954 :   if (Subtarget->isTargetCOFF()) {
     153         292 :     bool Internal = F->hasInternalLinkage();
     154         146 :     COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
     155             :                                             : COFF::IMAGE_SYM_CLASS_EXTERNAL;
     156         146 :     int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
     157             : 
     158         292 :     OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
     159         292 :     OutStreamer->EmitCOFFSymbolStorageClass(Scl);
     160         292 :     OutStreamer->EmitCOFFSymbolType(Type);
     161         292 :     OutStreamer->EndCOFFSymbolDef();
     162             :   }
     163             : 
     164             :   // Emit the rest of the function body.
     165       11977 :   EmitFunctionBody();
     166             : 
     167             :   // Emit the XRay table for this function.
     168       11977 :   emitXRayTable();
     169             : 
     170             :   // If we need V4T thumb mode Register Indirect Jump pads, emit them.
     171             :   // These are created per function, rather than per TU, since it's
     172             :   // relatively easy to exceed the thumb branch range within a TU.
     173       11977 :   if (! ThumbIndirectPads.empty()) {
     174          66 :     OutStreamer->EmitAssemblerFlag(MCAF_Code16);
     175          33 :     EmitAlignment(1);
     176         142 :     for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
     177          86 :       OutStreamer->EmitLabel(TIP.second);
     178         215 :       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
     179          43 :         .addReg(TIP.first)
     180             :         // Add predicate operands.
     181          43 :         .addImm(ARMCC::AL)
     182          86 :         .addReg(0));
     183             :     }
     184          33 :     ThumbIndirectPads.clear();
     185             :   }
     186             : 
     187             :   // We didn't modify anything.
     188       11977 :   return false;
     189             : }
     190             : 
     191         410 : void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
     192             :                                  raw_ostream &O) {
     193         820 :   const MachineOperand &MO = MI->getOperand(OpNum);
     194         410 :   unsigned TF = MO.getTargetFlags();
     195             : 
     196         410 :   switch (MO.getType()) {
     197           0 :   default: llvm_unreachable("<unknown operand type>");
     198         375 :   case MachineOperand::MO_Register: {
     199         375 :     unsigned Reg = MO.getReg();
     200             :     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
     201             :     assert(!MO.getSubReg() && "Subregs should be eliminated!");
     202         750 :     if(ARM::GPRPairRegClass.contains(Reg)) {
     203          88 :       const MachineFunction &MF = *MI->getParent()->getParent();
     204          88 :       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
     205          88 :       Reg = TRI->getSubReg(Reg, ARM::gsub_0);
     206             :     }
     207         375 :     O << ARMInstPrinter::getRegisterName(Reg);
     208         375 :     break;
     209             :   }
     210          33 :   case MachineOperand::MO_Immediate: {
     211          33 :     int64_t Imm = MO.getImm();
     212          33 :     O << '#';
     213          33 :     if (TF == ARMII::MO_LO16)
     214           0 :       O << ":lower16:";
     215          33 :     else if (TF == ARMII::MO_HI16)
     216           0 :       O << ":upper16:";
     217          33 :     O << Imm;
     218          33 :     break;
     219             :   }
     220           0 :   case MachineOperand::MO_MachineBasicBlock:
     221           0 :     MO.getMBB()->getSymbol()->print(O, MAI);
     222           0 :     return;
     223           2 :   case MachineOperand::MO_GlobalAddress: {
     224           2 :     const GlobalValue *GV = MO.getGlobal();
     225           2 :     if (TF & ARMII::MO_LO16)
     226           0 :       O << ":lower16:";
     227           2 :     else if (TF & ARMII::MO_HI16)
     228           0 :       O << ":upper16:";
     229           2 :     GetARMGVSymbol(GV, TF)->print(O, MAI);
     230             : 
     231           4 :     printOffset(MO.getOffset(), O);
     232           2 :     break;
     233             :   }
     234           0 :   case MachineOperand::MO_ConstantPoolIndex:
     235           0 :     if (Subtarget->genExecuteOnly())
     236           0 :       llvm_unreachable("execute-only should not generate constant pools");
     237           0 :     GetCPISymbol(MO.getIndex())->print(O, MAI);
     238           0 :     break;
     239             :   }
     240             : }
     241             : 
     242             : //===--------------------------------------------------------------------===//
     243             : 
     244         101 : MCSymbol *ARMAsmPrinter::
     245             : GetARMJTIPICJumpTableLabel(unsigned uid) const {
     246         101 :   const DataLayout &DL = getDataLayout();
     247         202 :   SmallString<60> Name;
     248         202 :   raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
     249         404 :                             << getFunctionNumber() << '_' << uid;
     250         303 :   return OutContext.getOrCreateSymbol(Name);
     251             : }
     252             : 
     253         511 : bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
     254             :                                     unsigned AsmVariant, const char *ExtraCode,
     255             :                                     raw_ostream &O) {
     256             :   // Does this asm operand have a single letter operand modifier?
     257         511 :   if (ExtraCode && ExtraCode[0]) {
     258         106 :     if (ExtraCode[1] != 0) return true; // Unknown modifier.
     259             : 
     260         106 :     switch (ExtraCode[0]) {
     261           0 :     default:
     262             :       // See if this is a generic print operand
     263           0 :       return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
     264           2 :     case 'a': // Print as a memory address.
     265           6 :       if (MI->getOperand(OpNum).isReg()) {
     266           1 :         O << "["
     267           2 :           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
     268           1 :           << "]";
     269           1 :         return false;
     270             :       }
     271             :       LLVM_FALLTHROUGH;
     272             :     case 'c': // Don't print "#" before an immediate operand.
     273           9 :       if (!MI->getOperand(OpNum).isImm())
     274             :         return true;
     275           3 :       O << MI->getOperand(OpNum).getImm();
     276           3 :       return false;
     277           5 :     case 'P': // Print a VFP double precision register.
     278             :     case 'q': // Print a NEON quad precision register.
     279           5 :       printOperand(MI, OpNum, O);
     280           5 :       return false;
     281           3 :     case 'y': // Print a VFP single precision register as indexed double.
     282           9 :       if (MI->getOperand(OpNum).isReg()) {
     283           3 :         unsigned Reg = MI->getOperand(OpNum).getReg();
     284           3 :         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
     285             :         // Find the 'd' register that has this 's' register as a sub-register,
     286             :         // and determine the lane number.
     287           6 :         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
     288           9 :           if (!ARM::DPRRegClass.contains(*SR))
     289             :             continue;
     290           3 :           bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
     291           3 :           O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
     292             :           return false;
     293             :         }
     294             :       }
     295             :       return true;
     296           1 :     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
     297           3 :       if (!MI->getOperand(OpNum).isImm())
     298             :         return true;
     299           1 :       O << ~(MI->getOperand(OpNum).getImm());
     300           1 :       return false;
     301           1 :     case 'L': // The low 16 bits of an immediate constant.
     302           3 :       if (!MI->getOperand(OpNum).isImm())
     303             :         return true;
     304           1 :       O << (MI->getOperand(OpNum).getImm() & 0xffff);
     305           1 :       return false;
     306           2 :     case 'M': { // A register range suitable for LDM/STM.
     307           6 :       if (!MI->getOperand(OpNum).isReg())
     308             :         return true;
     309           2 :       const MachineOperand &MO = MI->getOperand(OpNum);
     310           2 :       unsigned RegBegin = MO.getReg();
     311             :       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
     312             :       // already got the operands in registers that are operands to the
     313             :       // inline asm statement.
     314           2 :       O << "{";
     315           4 :       if (ARM::GPRPairRegClass.contains(RegBegin)) {
     316           2 :         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
     317           2 :         unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
     318           2 :         O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
     319           2 :         RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
     320             :       }
     321           2 :       O << ARMInstPrinter::getRegisterName(RegBegin);
     322             : 
     323             :       // FIXME: The register allocator not only may not have given us the
     324             :       // registers in sequence, but may not be in ascending registers. This
     325             :       // will require changes in the register allocator that'll need to be
     326             :       // propagated down here if the operands change.
     327           2 :       unsigned RegOps = OpNum + 1;
     328           6 :       while (MI->getOperand(RegOps).isReg()) {
     329           0 :         O << ", "
     330           0 :           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
     331           0 :         RegOps++;
     332             :       }
     333             : 
     334           2 :       O << "}";
     335             : 
     336           2 :       return false;
     337             :     }
     338          14 :     case 'R': // The most significant register of a pair.
     339             :     case 'Q': { // The least significant register of a pair.
     340          14 :       if (OpNum == 0)
     341             :         return true;
     342          28 :       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
     343          14 :       if (!FlagsOP.isImm())
     344             :         return true;
     345          14 :       unsigned Flags = FlagsOP.getImm();
     346             : 
     347             :       // This operand may not be the one that actually provides the register. If
     348             :       // it's tied to a previous one then we should refer instead to that one
     349             :       // for registers and their classes.
     350             :       unsigned TiedIdx;
     351           4 :       if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
     352          20 :         for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
     353          16 :           unsigned OpFlags = MI->getOperand(OpNum).getImm();
     354           8 :           OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
     355             :         }
     356           8 :         Flags = MI->getOperand(OpNum).getImm();
     357             : 
     358             :         // Later code expects OpNum to be pointing at the register rather than
     359             :         // the flags.
     360           4 :         OpNum += 1;
     361             :       }
     362             : 
     363          14 :       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
     364             :       unsigned RC;
     365          14 :       InlineAsm::hasRegClassConstraint(Flags, RC);
     366          14 :       if (RC == ARM::GPRPairRegClassID) {
     367          14 :         if (NumVals != 1)
     368             :           return true;
     369          28 :         const MachineOperand &MO = MI->getOperand(OpNum);
     370          14 :         if (!MO.isReg())
     371             :           return true;
     372          14 :         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
     373          14 :         unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
     374          14 :             ARM::gsub_0 : ARM::gsub_1);
     375          14 :         O << ARMInstPrinter::getRegisterName(Reg);
     376          14 :         return false;
     377             :       }
     378           0 :       if (NumVals != 2)
     379             :         return true;
     380           0 :       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
     381           0 :       if (RegOp >= MI->getNumOperands())
     382             :         return true;
     383           0 :       const MachineOperand &MO = MI->getOperand(RegOp);
     384           0 :       if (!MO.isReg())
     385             :         return true;
     386           0 :       unsigned Reg = MO.getReg();
     387           0 :       O << ARMInstPrinter::getRegisterName(Reg);
     388           0 :       return false;
     389             :     }
     390             : 
     391           2 :     case 'e': // The low doubleword register of a NEON quad register.
     392             :     case 'f': { // The high doubleword register of a NEON quad register.
     393           6 :       if (!MI->getOperand(OpNum).isReg())
     394             :         return true;
     395           2 :       unsigned Reg = MI->getOperand(OpNum).getReg();
     396           4 :       if (!ARM::QPRRegClass.contains(Reg))
     397             :         return true;
     398           2 :       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
     399           2 :       unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
     400           2 :                                        ARM::dsub_0 : ARM::dsub_1);
     401           2 :       O << ARMInstPrinter::getRegisterName(SubReg);
     402           2 :       return false;
     403             :     }
     404             : 
     405             :     // This modifier is not yet supported.
     406             :     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
     407             :       return true;
     408          74 :     case 'H': { // The highest-numbered register of a pair.
     409         148 :       const MachineOperand &MO = MI->getOperand(OpNum);
     410          74 :       if (!MO.isReg())
     411             :         return true;
     412          74 :       const MachineFunction &MF = *MI->getParent()->getParent();
     413          74 :       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
     414          74 :       unsigned Reg = MO.getReg();
     415         148 :       if(!ARM::GPRPairRegClass.contains(Reg))
     416             :         return false;
     417          74 :       Reg = TRI->getSubReg(Reg, ARM::gsub_1);
     418          74 :       O << ARMInstPrinter::getRegisterName(Reg);
     419          74 :       return false;
     420             :     }
     421             :     }
     422             :   }
     423             : 
     424         405 :   printOperand(MI, OpNum, O);
     425         405 :   return false;
     426             : }
     427             : 
     428          19 : bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
     429             :                                           unsigned OpNum, unsigned AsmVariant,
     430             :                                           const char *ExtraCode,
     431             :                                           raw_ostream &O) {
     432             :   // Does this asm operand have a single letter operand modifier?
     433          19 :   if (ExtraCode && ExtraCode[0]) {
     434           3 :     if (ExtraCode[1] != 0) return true; // Unknown modifier.
     435             : 
     436           3 :     switch (ExtraCode[0]) {
     437             :       case 'A': // A memory operand for a VLD1/VST1 instruction.
     438             :       default: return true;  // Unknown modifier.
     439           3 :       case 'm': // The base register of a memory operand.
     440           9 :         if (!MI->getOperand(OpNum).isReg())
     441             :           return true;
     442           3 :         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
     443           3 :         return false;
     444             :     }
     445             :   }
     446             : 
     447          32 :   const MachineOperand &MO = MI->getOperand(OpNum);
     448             :   assert(MO.isReg() && "unexpected inline asm memory operand");
     449          16 :   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
     450          16 :   return false;
     451             : }
     452             : 
     453             : static bool isThumb(const MCSubtargetInfo& STI) {
     454        1080 :   return STI.getFeatureBits()[ARM::ModeThumb];
     455             : }
     456             : 
     457         328 : void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
     458             :                                      const MCSubtargetInfo *EndInfo) const {
     459             :   // If either end mode is unknown (EndInfo == NULL) or different than
     460             :   // the start mode, then restore the start mode.
     461         328 :   const bool WasThumb = isThumb(StartInfo);
     462         540 :   if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
     463         244 :     OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
     464             :   }
     465         328 : }
     466             : 
     467        2572 : void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
     468        5144 :   const Triple &TT = TM.getTargetTriple();
     469             :   // Use unified assembler syntax.
     470        5144 :   OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
     471             : 
     472             :   // Emit ARM Build Attributes
     473        2572 :   if (TT.isOSBinFormatELF())
     474        1755 :     emitAttributes();
     475             : 
     476             :   // Use the triple's architecture and subarchitecture to determine
     477             :   // if we're thumb for the purposes of the top level code16 assembler
     478             :   // flag.
     479        2572 :   if (!M.getModuleInlineAsm().empty() && TT.isThumb())
     480           6 :     OutStreamer->EmitAssemblerFlag(MCAF_Code16);
     481        2572 : }
     482             : 
     483             : static void
     484         371 : emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
     485             :                          MachineModuleInfoImpl::StubValueTy &MCSym) {
     486             :   // L_foo$stub:
     487         371 :   OutStreamer.EmitLabel(StubLabel);
     488             :   //   .indirect_symbol _foo
     489         742 :   OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
     490             : 
     491         371 :   if (MCSym.getInt())
     492             :     // External to current translation unit.
     493         369 :     OutStreamer.EmitIntValue(0, 4/*size*/);
     494             :   else
     495             :     // Internal to current translation unit.
     496             :     //
     497             :     // When we place the LSDA into the TEXT section, the type info
     498             :     // pointers need to be indirect and pc-rel. We accomplish this by
     499             :     // using NLPs; however, sometimes the types are local to the file.
     500             :     // We need to fill in the value for the NLP in those cases.
     501           2 :     OutStreamer.EmitValue(
     502           6 :         MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
     503           2 :         4 /*size*/);
     504         371 : }
     505             : 
     506             : 
     507        2545 : void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
     508        5090 :   const Triple &TT = TM.getTargetTriple();
     509        2545 :   if (TT.isOSBinFormatMachO()) {
     510             :     // All darwin targets use mach-o.
     511             :     const TargetLoweringObjectFileMachO &TLOFMacho =
     512         755 :       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
     513             :     MachineModuleInfoMachO &MMIMacho =
     514         755 :       MMI->getObjFileInfo<MachineModuleInfoMachO>();
     515             : 
     516             :     // Output non-lazy-pointers for external and common global variables.
     517        1510 :     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
     518             : 
     519         755 :     if (!Stubs.empty()) {
     520             :       // Switch with ".non_lazy_symbol_pointer" directive.
     521         372 :       OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
     522         186 :       EmitAlignment(2);
     523             : 
     524        1106 :       for (auto &Stub : Stubs)
     525         724 :         emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
     526             : 
     527         186 :       Stubs.clear();
     528         372 :       OutStreamer->AddBlankLine();
     529             :     }
     530             : 
     531        2265 :     Stubs = MMIMacho.GetThreadLocalGVStubList();
     532         755 :     if (!Stubs.empty()) {
     533             :       // Switch with ".non_lazy_symbol_pointer" directive.
     534          10 :       OutStreamer->SwitchSection(TLOFMacho.getThreadLocalPointerSection());
     535           5 :       EmitAlignment(2);
     536             : 
     537          29 :       for (auto &Stub : Stubs)
     538          18 :         emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
     539             : 
     540           5 :       Stubs.clear();
     541          10 :       OutStreamer->AddBlankLine();
     542             :     }
     543             : 
     544             :     // Funny Darwin hack: This flag tells the linker that no global symbols
     545             :     // contain code that falls through to other global symbols (e.g. the obvious
     546             :     // implementation of multiple entry points).  If this doesn't occur, the
     547             :     // linker can safely perform dead code stripping.  Since LLVM never
     548             :     // generates code that does this, it is always safe to set.
     549        1510 :     OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
     550             :   }
     551             : 
     552        2545 :   if (TT.isOSBinFormatCOFF()) {
     553             :     const auto &TLOF =
     554          60 :         static_cast<const TargetLoweringObjectFileCOFF &>(getObjFileLowering());
     555             : 
     556         120 :     std::string Flags;
     557         120 :     raw_string_ostream OS(Flags);
     558             : 
     559         396 :     for (const auto &Function : M)
     560         216 :       TLOF.emitLinkerFlagsForGlobal(OS, &Function);
     561         114 :     for (const auto &Global : M.globals())
     562          54 :       TLOF.emitLinkerFlagsForGlobal(OS, &Global);
     563          72 :     for (const auto &Alias : M.aliases())
     564          12 :       TLOF.emitLinkerFlagsForGlobal(OS, &Alias);
     565             : 
     566          60 :     OS.flush();
     567             : 
     568             :     // Output collected flags
     569          60 :     if (!Flags.empty()) {
     570          10 :       OutStreamer->SwitchSection(TLOF.getDrectveSection());
     571          15 :       OutStreamer->EmitBytes(Flags);
     572             :     }
     573             :   }
     574             : 
     575             :   // The last attribute to be emitted is ABI_optimization_goals
     576        7635 :   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
     577        2545 :   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
     578             : 
     579        2545 :   if (OptimizationGoals > 0 &&
     580        4111 :       (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
     581        1085 :        Subtarget->isTargetMuslAEABI()))
     582        1387 :     ATS.emitAttribute(ARMBuildAttrs::ABI_optimization_goals, OptimizationGoals);
     583        2545 :   OptimizationGoals = -1;
     584             : 
     585        2545 :   ATS.finishAttributeSection();
     586        2545 : }
     587             : 
     588             : //===----------------------------------------------------------------------===//
     589             : // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
     590             : // FIXME:
     591             : // The following seem like one-off assembler flags, but they actually need
     592             : // to appear in the .ARM.attributes section in ELF.
     593             : // Instead of subclassing the MCELFStreamer, we do the work here.
     594             : 
     595             : // Returns true if all functions have the same function attribute value.
     596             : // It also returns true when the module has no functions.
     597             : static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr,
     598             :                                                StringRef Value) {
     599       10423 :   return !any_of(M, [&](const Function &F) {
     600       15564 :     return F.getFnAttribute(Attr).getValueAsString() != Value;
     601       10376 :   });
     602             : }
     603             : 
     604        1755 : void ARMAsmPrinter::emitAttributes() {
     605        5265 :   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
     606        1755 :   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
     607             : 
     608        3510 :   ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
     609             : 
     610        3510 :   ATS.switchVendor("aeabi");
     611             : 
     612             :   // Compute ARM ELF Attributes based on the default subtarget that
     613             :   // we'd have constructed. The existing ARM behavior isn't LTO clean
     614             :   // anyhow.
     615             :   // FIXME: For ifunc related functions we could iterate over and look
     616             :   // for a feature string that doesn't match the default one.
     617        3510 :   const Triple &TT = TM.getTargetTriple();
     618        3510 :   StringRef CPU = TM.getTargetCPU();
     619        3510 :   StringRef FS = TM.getTargetFeatureString();
     620        1755 :   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
     621        1755 :   if (!FS.empty()) {
     622         568 :     if (!ArchFS.empty())
     623        1674 :       ArchFS = (Twine(ArchFS) + "," + FS).str();
     624             :     else
     625         578 :       ArchFS = FS;
     626             :   }
     627        1755 :   const ARMBaseTargetMachine &ATM =
     628             :       static_cast<const ARMBaseTargetMachine &>(TM);
     629        7020 :   const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
     630             : 
     631             :   // Emit build attributes for the available hardware.
     632        1755 :   ATS.emitTargetAttributes(STI);
     633             : 
     634             :   // RW data addressing.
     635        1755 :   if (isPositionIndependent()) {
     636          45 :     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
     637          45 :                       ARMBuildAttrs::AddressRWPCRel);
     638        1710 :   } else if (STI.isRWPI()) {
     639             :     // RWPI specific attributes.
     640          24 :     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
     641          24 :                       ARMBuildAttrs::AddressRWSBRel);
     642             :   }
     643             : 
     644             :   // RO data addressing.
     645        1755 :   if (isPositionIndependent() || STI.isROPI()) {
     646          72 :     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
     647          72 :                       ARMBuildAttrs::AddressROPCRel);
     648             :   }
     649             : 
     650             :   // GOT use.
     651        1755 :   if (isPositionIndependent()) {
     652          45 :     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
     653          45 :                       ARMBuildAttrs::AddressGOT);
     654             :   } else {
     655        1710 :     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
     656        1710 :                       ARMBuildAttrs::AddressDirect);
     657             :   }
     658             : 
     659             :   // Set FP Denormals.
     660        3510 :   if (checkFunctionsAttributeConsistency(*MMI->getModule(),
     661             :                                          "denormal-fp-math",
     662        3481 :                                          "preserve-sign") ||
     663        1726 :       TM.Options.FPDenormalMode == FPDenormal::PreserveSign)
     664          30 :     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
     665          30 :                       ARMBuildAttrs::PreserveFPSign);
     666        3450 :   else if (checkFunctionsAttributeConsistency(*MMI->getModule(),
     667             :                                               "denormal-fp-math",
     668        3449 :                                               "positive-zero") ||
     669        1724 :            TM.Options.FPDenormalMode == FPDenormal::PositiveZero)
     670           2 :     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
     671           2 :                       ARMBuildAttrs::PositiveZero);
     672        1723 :   else if (!TM.Options.UnsafeFPMath)
     673        1661 :     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
     674        1661 :                       ARMBuildAttrs::IEEEDenormals);
     675             :   else {
     676          62 :     if (!STI.hasVFP2()) {
     677             :       // When the target doesn't have an FPU (by design or
     678             :       // intention), the assumptions made on the software support
     679             :       // mirror that of the equivalent hardware support *if it
     680             :       // existed*. For v7 and better we indicate that denormals are
     681             :       // flushed preserving sign, and for V6 we indicate that
     682             :       // denormals are flushed to positive zero.
     683          15 :       if (STI.hasV7Ops())
     684           8 :         ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
     685           8 :                           ARMBuildAttrs::PreserveFPSign);
     686          47 :     } else if (STI.hasVFP3()) {
     687             :       // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
     688             :       // the sign bit of the zero matches the sign bit of the input or
     689             :       // result that is being flushed to zero.
     690          46 :       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
     691          46 :                         ARMBuildAttrs::PreserveFPSign);
     692             :     }
     693             :     // For VFPv2 implementations it is implementation defined as
     694             :     // to whether denormals are flushed to positive zero or to
     695             :     // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
     696             :     // LLVM has chosen to flush this to positive zero (most likely for
     697             :     // GCC compatibility), so that's the chosen value here (the
     698             :     // absence of its emission implies zero).
     699             :   }
     700             : 
     701             :   // Set FP exceptions and rounding
     702        3510 :   if (checkFunctionsAttributeConsistency(*MMI->getModule(),
     703        3481 :                                          "no-trapping-math", "true") ||
     704        1726 :       TM.Options.NoTrappingFPMath)
     705          30 :     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
     706          30 :                       ARMBuildAttrs::Not_Allowed);
     707        1725 :   else if (!TM.Options.UnsafeFPMath) {
     708        1663 :     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
     709             : 
     710             :     // If the user has permitted this code to choose the IEEE 754
     711             :     // rounding at run-time, emit the rounding attribute.
     712        1663 :     if (TM.Options.HonorSignDependentRoundingFPMathOption)
     713          35 :       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
     714             :   }
     715             : 
     716             :   // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
     717             :   // equivalent of GCC's -ffinite-math-only flag.
     718        1755 :   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
     719          44 :     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
     720          44 :                       ARMBuildAttrs::Allowed);
     721             :   else
     722        1711 :     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
     723        1711 :                       ARMBuildAttrs::AllowIEEE754);
     724             : 
     725             :   // FIXME: add more flags to ARMBuildAttributes.h
     726             :   // 8-bytes alignment stuff.
     727        1755 :   ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
     728        1755 :   ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
     729             : 
     730             :   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
     731        1755 :   if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
     732         172 :     ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
     733             : 
     734             :   // FIXME: To support emitting this build attribute as GCC does, the
     735             :   // -mfp16-format option and associated plumbing must be
     736             :   // supported. For now the __fp16 type is exposed by default, so this
     737             :   // attribute should be emitted with value 1.
     738        1755 :   ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
     739        1755 :                     ARMBuildAttrs::FP16FormatIEEE);
     740             : 
     741        1755 :   if (MMI) {
     742        1755 :     if (const Module *SourceModule = MMI->getModule()) {
     743             :       // ABI_PCS_wchar_t to indicate wchar_t width
     744             :       // FIXME: There is no way to emit value 0 (wchar_t prohibited).
     745          52 :       if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
     746        3510 :               SourceModule->getModuleFlag("wchar_size"))) {
     747          52 :         int WCharWidth = WCharWidthValue->getZExtValue();
     748             :         assert((WCharWidth == 2 || WCharWidth == 4) &&
     749             :                "wchar_t width must be 2 or 4 bytes");
     750          52 :         ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
     751             :       }
     752             : 
     753             :       // ABI_enum_size to indicate enum width
     754             :       // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
     755             :       //        (all enums contain a value needing 32 bits to encode).
     756          51 :       if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
     757        3510 :               SourceModule->getModuleFlag("min_enum_size"))) {
     758          51 :         int EnumWidth = EnumWidthValue->getZExtValue();
     759             :         assert((EnumWidth == 1 || EnumWidth == 4) &&
     760             :                "Minimum enum width must be 1 or 4 bytes");
     761          51 :         int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
     762          51 :         ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
     763             :       }
     764             :     }
     765             :   }
     766             : 
     767             :   // We currently do not support using R9 as the TLS pointer.
     768        1755 :   if (STI.isRWPI())
     769          24 :     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
     770          24 :                       ARMBuildAttrs::R9IsSB);
     771        1731 :   else if (STI.isR9Reserved())
     772           1 :     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
     773           1 :                       ARMBuildAttrs::R9Reserved);
     774             :   else
     775        1730 :     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
     776        1730 :                       ARMBuildAttrs::R9IsGPR);
     777        1755 : }
     778             : 
     779             : //===----------------------------------------------------------------------===//
     780             : 
     781        2524 : static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
     782             :                              unsigned LabelId, MCContext &Ctx) {
     783             : 
     784        5048 :   MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
     785       22716 :                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
     786        2524 :   return Label;
     787             : }
     788             : 
     789             : static MCSymbolRefExpr::VariantKind
     790             : getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
     791         531 :   switch (Modifier) {
     792             :   case ARMCP::no_modifier:
     793             :     return MCSymbolRefExpr::VK_None;
     794          15 :   case ARMCP::TLSGD:
     795             :     return MCSymbolRefExpr::VK_TLSGD;
     796          21 :   case ARMCP::TPOFF:
     797             :     return MCSymbolRefExpr::VK_TPOFF;
     798          18 :   case ARMCP::GOTTPOFF:
     799             :     return MCSymbolRefExpr::VK_GOTTPOFF;
     800          22 :   case ARMCP::SBREL:
     801             :     return MCSymbolRefExpr::VK_ARM_SBREL;
     802          49 :   case ARMCP::GOT_PREL:
     803             :     return MCSymbolRefExpr::VK_ARM_GOT_PREL;
     804           7 :   case ARMCP::SECREL:
     805             :     return MCSymbolRefExpr::VK_SECREL;
     806             :   }
     807           0 :   llvm_unreachable("Invalid ARMCPModifier!");
     808             : }
     809             : 
     810        7710 : MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
     811             :                                         unsigned char TargetFlags) {
     812       15420 :   if (Subtarget->isTargetMachO()) {
     813             :     bool IsIndirect =
     814        7127 :         (TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
     815             : 
     816             :     if (!IsIndirect)
     817        3161 :       return getSymbol(GV);
     818             : 
     819             :     // FIXME: Remove this when Darwin transition to @GOT like syntax.
     820        1610 :     MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
     821             :     MachineModuleInfoMachO &MMIMachO =
     822         805 :       MMI->getObjFileInfo<MachineModuleInfoMachO>();
     823             :     MachineModuleInfoImpl::StubValueTy &StubSym =
     824        1610 :         GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(MCSym)
     825         805 :                             : MMIMachO.getGVStubEntry(MCSym);
     826             : 
     827         805 :     if (!StubSym.getPointer())
     828         726 :       StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
     829         363 :                                                    !GV->hasInternalLinkage());
     830             :     return MCSym;
     831        7488 :   } else if (Subtarget->isTargetCOFF()) {
     832             :     assert(Subtarget->isTargetWindows() &&
     833             :            "Windows is the only supported COFF target");
     834             : 
     835         109 :     bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
     836         109 :     if (!IsIndirect)
     837          99 :       return getSymbol(GV);
     838             : 
     839          10 :     SmallString<128> Name;
     840          20 :     Name = "__imp_";
     841          10 :     getNameWithPrefix(Name, GV);
     842             : 
     843          20 :     return OutContext.getOrCreateSymbol(Name);
     844        7270 :   } else if (Subtarget->isTargetELF()) {
     845        3635 :     return getSymbol(GV);
     846             :   }
     847           0 :   llvm_unreachable("unexpected target");
     848             : }
     849             : 
     850         624 : void ARMAsmPrinter::
     851             : EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
     852         624 :   const DataLayout &DL = getDataLayout();
     853         624 :   int Size = DL.getTypeAllocSize(MCPV->getType());
     854             : 
     855         624 :   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
     856             : 
     857         624 :   if (ACPV->isPromotedGlobal()) {
     858             :     // This constant pool entry is actually a global whose storage has been
     859             :     // promoted into the constant pool. This global may be referenced still
     860             :     // by debug information, and due to the way AsmPrinter is set up, the debug
     861             :     // info is immutable by the time we decide to promote globals to constant
     862             :     // pools. Because of this, we need to ensure we emit a symbol for the global
     863             :     // with private linkage (the default) so debug info can refer to it.
     864             :     //
     865             :     // However, if this global is promoted into several functions we must ensure
     866             :     // we don't try and emit duplicate symbols!
     867          93 :     auto *ACPC = cast<ARMConstantPoolConstant>(ACPV);
     868         187 :     for (const auto *GV : ACPC->promotedGlobals()) {
     869          94 :       if (!EmittedPromotedGlobalLabels.count(GV)) {
     870          57 :         MCSymbol *GVSym = getSymbol(GV);
     871         114 :         OutStreamer->EmitLabel(GVSym);
     872          57 :         EmittedPromotedGlobalLabels.insert(GV);
     873             :       }
     874             :     }
     875          93 :     return EmitGlobalConstant(DL, ACPC->getPromotedGlobalInit());
     876             :   }
     877             : 
     878             :   MCSymbol *MCSym;
     879         531 :   if (ACPV->isLSDA()) {
     880          28 :     MCSym = getCurExceptionSym();
     881         503 :   } else if (ACPV->isBlockAddress()) {
     882             :     const BlockAddress *BA =
     883          18 :       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
     884          18 :     MCSym = GetBlockAddressSymbol(BA);
     885         485 :   } else if (ACPV->isGlobalValue()) {
     886         422 :     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
     887             : 
     888             :     // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
     889             :     // flag the global as MO_NONLAZY.
     890         844 :     unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
     891         422 :     MCSym = GetARMGVSymbol(GV, TF);
     892          63 :   } else if (ACPV->isMachineBasicBlock()) {
     893          28 :     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
     894          28 :     MCSym = MBB->getSymbol();
     895             :   } else {
     896             :     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
     897          70 :     auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
     898          35 :     MCSym = GetExternalSymbolSymbol(Sym);
     899             :   }
     900             : 
     901             :   // Create an MCSymbol for the reference.
     902             :   const MCExpr *Expr =
     903        1593 :     MCSymbolRefExpr::create(MCSym, getModifierVariantKind(ACPV->getModifier()),
     904        1062 :                             OutContext);
     905             : 
     906         531 :   if (ACPV->getPCAdjustment()) {
     907             :     MCSymbol *PCLabel =
     908         413 :         getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
     909         413 :                     ACPV->getLabelId(), OutContext);
     910         826 :     const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
     911         413 :     PCRelExpr =
     912         413 :       MCBinaryExpr::createAdd(PCRelExpr,
     913         413 :                               MCConstantExpr::create(ACPV->getPCAdjustment(),
     914             :                                                      OutContext),
     915             :                               OutContext);
     916         413 :     if (ACPV->mustAddCurrentAddress()) {
     917             :       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
     918             :       // label, so just emit a local label end reference that instead.
     919          82 :       MCSymbol *DotSym = OutContext.createTempSymbol();
     920         164 :       OutStreamer->EmitLabel(DotSym);
     921         164 :       const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
     922         164 :       PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
     923             :     }
     924         826 :     Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
     925             :   }
     926        1062 :   OutStreamer->EmitValue(Expr, Size);
     927             : }
     928             : 
     929          29 : void ARMAsmPrinter::EmitJumpTableAddrs(const MachineInstr *MI) {
     930          29 :   const MachineOperand &MO1 = MI->getOperand(1);
     931          29 :   unsigned JTI = MO1.getIndex();
     932             : 
     933             :   // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
     934             :   // ARM mode tables.
     935          29 :   EmitAlignment(2);
     936             : 
     937             :   // Emit a label for the jump table.
     938          29 :   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
     939          58 :   OutStreamer->EmitLabel(JTISymbol);
     940             : 
     941             :   // Mark the jump table as data-in-code.
     942          58 :   OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
     943             : 
     944             :   // Emit each entry of the table.
     945          29 :   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
     946          29 :   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
     947          58 :   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
     948             : 
     949         357 :   for (MachineBasicBlock *MBB : JTBBs) {
     950             :     // Construct an MCExpr for the entry. We want a value of the form:
     951             :     // (BasicBlockAddr - TableBeginAddr)
     952             :     //
     953             :     // For example, a table with entries jumping to basic blocks BB0 and BB1
     954             :     // would look like:
     955             :     // LJTI_0_0:
     956             :     //    .word (LBB0 - LJTI_0_0)
     957             :     //    .word (LBB1 - LJTI_0_0)
     958         482 :     const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
     959             : 
     960         241 :     if (isPositionIndependent() || Subtarget->isROPI())
     961         327 :       Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
     962             :                                                                    OutContext),
     963             :                                      OutContext);
     964             :     // If we're generating a table of Thumb addresses in static relocation
     965             :     // model, we need to add one to keep interworking correctly.
     966         132 :     else if (AFI->isThumbFunction())
     967         244 :       Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(1,OutContext),
     968             :                                      OutContext);
     969         482 :     OutStreamer->EmitValue(Expr, 4);
     970             :   }
     971             :   // Mark the end of jump table data-in-code region.
     972          58 :   OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
     973          29 : }
     974             : 
     975           6 : void ARMAsmPrinter::EmitJumpTableInsts(const MachineInstr *MI) {
     976           6 :   const MachineOperand &MO1 = MI->getOperand(1);
     977           6 :   unsigned JTI = MO1.getIndex();
     978             : 
     979             :   // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
     980             :   // ARM mode tables.
     981           6 :   EmitAlignment(2);
     982             : 
     983             :   // Emit a label for the jump table.
     984           6 :   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
     985          12 :   OutStreamer->EmitLabel(JTISymbol);
     986             : 
     987             :   // Emit each entry of the table.
     988           6 :   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
     989           6 :   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
     990          12 :   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
     991             : 
     992         186 :   for (MachineBasicBlock *MBB : JTBBs) {
     993         162 :     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
     994         162 :                                                           OutContext);
     995             :     // If this isn't a TBB or TBH, the entries are direct branch instructions.
     996         810 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2B)
     997         162 :         .addExpr(MBBSymbolExpr)
     998         162 :         .addImm(ARMCC::AL)
     999         324 :         .addReg(0));
    1000             :   }
    1001           6 : }
    1002             : 
    1003          30 : void ARMAsmPrinter::EmitJumpTableTBInst(const MachineInstr *MI,
    1004             :                                         unsigned OffsetWidth) {
    1005             :   assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
    1006          30 :   const MachineOperand &MO1 = MI->getOperand(1);
    1007          30 :   unsigned JTI = MO1.getIndex();
    1008             : 
    1009          30 :   if (Subtarget->isThumb1Only())
    1010           9 :     EmitAlignment(2);
    1011             :   
    1012          30 :   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
    1013          60 :   OutStreamer->EmitLabel(JTISymbol);
    1014             : 
    1015             :   // Emit each entry of the table.
    1016          30 :   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
    1017          30 :   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
    1018          60 :   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
    1019             : 
    1020             :   // Mark the jump table as data-in-code.
    1021          90 :   OutStreamer->EmitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
    1022          30 :                                                : MCDR_DataRegionJT16);
    1023             : 
    1024         492 :   for (auto MBB : JTBBs) {
    1025         372 :     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
    1026         372 :                                                           OutContext);
    1027             :     // Otherwise it's an offset from the dispatch instruction. Construct an
    1028             :     // MCExpr for the entry. We want a value of the form:
    1029             :     // (BasicBlockAddr - TBBInstAddr + 4) / 2
    1030             :     //
    1031             :     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
    1032             :     // would look like:
    1033             :     // LJTI_0_0:
    1034             :     //    .byte (LBB0 - (LCPI0_0 + 4)) / 2
    1035             :     //    .byte (LBB1 - (LCPI0_0 + 4)) / 2
    1036             :     // where LCPI0_0 is a label defined just before the TBB instruction using
    1037             :     // this table.
    1038         372 :     MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
    1039         372 :     const MCExpr *Expr = MCBinaryExpr::createAdd(
    1040         744 :         MCSymbolRefExpr::create(TBInstPC, OutContext),
    1041         744 :         MCConstantExpr::create(4, OutContext), OutContext);
    1042         744 :     Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
    1043         744 :     Expr = MCBinaryExpr::createDiv(Expr, MCConstantExpr::create(2, OutContext),
    1044             :                                    OutContext);
    1045         744 :     OutStreamer->EmitValue(Expr, OffsetWidth);
    1046             :   }
    1047             :   // Mark the end of jump table data-in-code region. 32-bit offsets use
    1048             :   // actual branch instructions here, so we don't mark those as a data-region
    1049             :   // at all.
    1050          60 :   OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
    1051             : 
    1052             :   // Make sure the next instruction is 2-byte aligned.
    1053          30 :   EmitAlignment(1);
    1054          30 : }
    1055             : 
    1056        3741 : void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
    1057             :   assert(MI->getFlag(MachineInstr::FrameSetup) &&
    1058             :       "Only instruction which are involved into frame setup code are allowed");
    1059             : 
    1060       11223 :   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
    1061        3741 :   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
    1062        3741 :   const MachineFunction &MF = *MI->getParent()->getParent();
    1063        3741 :   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
    1064        3741 :   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
    1065             : 
    1066        3741 :   unsigned FramePtr = RegInfo->getFrameRegister(MF);
    1067        7482 :   unsigned Opc = MI->getOpcode();
    1068             :   unsigned SrcReg, DstReg;
    1069             : 
    1070        3741 :   if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
    1071             :     // Two special cases:
    1072             :     // 1) tPUSH does not have src/dst regs.
    1073             :     // 2) for Thumb1 code we sometimes materialize the constant via constpool
    1074             :     // load. Yes, this is pretty fragile, but for now I don't see better
    1075             :     // way... :(
    1076         729 :     SrcReg = DstReg = ARM::SP;
    1077             :   } else {
    1078        3012 :     SrcReg = MI->getOperand(1).getReg();
    1079        3012 :     DstReg = MI->getOperand(0).getReg();
    1080             :   }
    1081             : 
    1082             :   // Try to figure out the unwinding opcode out of src / dst regs.
    1083        3741 :   if (MI->mayStore()) {
    1084             :     // Register saves.
    1085             :     assert(DstReg == ARM::SP &&
    1086             :            "Only stack pointer as a destination reg is supported");
    1087             : 
    1088        4610 :     SmallVector<unsigned, 4> RegList;
    1089             :     // Skip src & dst reg, and pred ops.
    1090        2305 :     unsigned StartOp = 2 + 2;
    1091             :     // Use all the operands.
    1092        2305 :     unsigned NumOffset = 0;
    1093             : 
    1094        2305 :     switch (Opc) {
    1095           0 :     default:
    1096           0 :       MI->print(errs());
    1097           0 :       llvm_unreachable("Unsupported opcode for unwinding information");
    1098         709 :     case ARM::tPUSH:
    1099             :       // Special case here: no src & dst reg, but two extra imp ops.
    1100         709 :       StartOp = 2; NumOffset = 2;
    1101             :       LLVM_FALLTHROUGH;
    1102        2297 :     case ARM::STMDB_UPD:
    1103             :     case ARM::t2STMDB_UPD:
    1104             :     case ARM::VSTMDDB_UPD:
    1105             :       assert(SrcReg == ARM::SP &&
    1106             :              "Only stack pointer as a source reg is supported");
    1107        8671 :       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
    1108        8671 :            i != NumOps; ++i) {
    1109       12748 :         const MachineOperand &MO = MI->getOperand(i);
    1110             :         // Actually, there should never be any impdef stuff here. Skip it
    1111             :         // temporary to workaround PR11902.
    1112        6374 :         if (MO.isImplicit())
    1113           0 :           continue;
    1114        6374 :         RegList.push_back(MO.getReg());
    1115        2297 :       }
    1116             :       break;
    1117           8 :     case ARM::STR_PRE_IMM:
    1118             :     case ARM::STR_PRE_REG:
    1119             :     case ARM::t2STR_PRE:
    1120             :       assert(MI->getOperand(2).getReg() == ARM::SP &&
    1121             :              "Only stack pointer as a source reg is supported");
    1122           8 :       RegList.push_back(SrcReg);
    1123           8 :       break;
    1124             :     }
    1125        2305 :     if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
    1126        2276 :       ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
    1127             :   } else {
    1128             :     // Changes of stack / frame pointer.
    1129        1436 :     if (SrcReg == ARM::SP) {
    1130        1436 :       int64_t Offset = 0;
    1131        1436 :       switch (Opc) {
    1132           0 :       default:
    1133           0 :         MI->print(errs());
    1134           0 :         llvm_unreachable("Unsupported opcode for unwinding information");
    1135             :       case ARM::MOVr:
    1136             :       case ARM::tMOVr:
    1137             :         Offset = 0;
    1138             :         break;
    1139         157 :       case ARM::ADDri:
    1140             :       case ARM::t2ADDri:
    1141         157 :         Offset = -MI->getOperand(2).getImm();
    1142         157 :         break;
    1143         631 :       case ARM::SUBri:
    1144             :       case ARM::t2SUBri:
    1145         631 :         Offset = MI->getOperand(2).getImm();
    1146         631 :         break;
    1147         372 :       case ARM::tSUBspi:
    1148         372 :         Offset = MI->getOperand(2).getImm()*4;
    1149         372 :         break;
    1150         122 :       case ARM::tADDspi:
    1151             :       case ARM::tADDrSPi:
    1152         122 :         Offset = -MI->getOperand(2).getImm()*4;
    1153         122 :         break;
    1154          20 :       case ARM::tLDRpci: {
    1155             :         // Grab the constpool index and check, whether it corresponds to
    1156             :         // original or cloned constpool entry.
    1157          20 :         unsigned CPI = MI->getOperand(1).getIndex();
    1158          20 :         const MachineConstantPool *MCP = MF.getConstantPool();
    1159          40 :         if (CPI >= MCP->getConstants().size())
    1160           0 :           CPI = AFI.getOriginalCPIdx(CPI);
    1161             :         assert(CPI != -1U && "Invalid constpool index");
    1162             : 
    1163             :         // Derive the actual offset.
    1164          40 :         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
    1165             :         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
    1166             :         // FIXME: Check for user, it should be "add" instruction!
    1167          60 :         Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
    1168          20 :         break;
    1169             :       }
    1170             :       }
    1171             : 
    1172        1436 :       if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
    1173        1407 :         if (DstReg == FramePtr && FramePtr != ARM::SP)
    1174             :           // Set-up of the frame pointer. Positive values correspond to "add"
    1175             :           // instruction.
    1176         402 :           ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
    1177        1005 :         else if (DstReg == ARM::SP) {
    1178             :           // Change of SP by an offset. Positive values correspond to "sub"
    1179             :           // instruction.
    1180        1005 :           ATS.emitPad(Offset);
    1181             :         } else {
    1182             :           // Move of SP to a register.  Positive values correspond to an "add"
    1183             :           // instruction.
    1184           0 :           ATS.emitMovSP(DstReg, -Offset);
    1185             :         }
    1186             :       }
    1187           0 :     } else if (DstReg == ARM::SP) {
    1188           0 :       MI->print(errs());
    1189           0 :       llvm_unreachable("Unsupported opcode for unwinding information");
    1190             :     }
    1191             :     else {
    1192           0 :       MI->print(errs());
    1193           0 :       llvm_unreachable("Unsupported opcode for unwinding information");
    1194             :     }
    1195             :   }
    1196        3741 : }
    1197             : 
    1198             : // Simple pseudo-instructions have their lowering (with expansion to real
    1199             : // instructions) auto-generated.
    1200             : #include "ARMGenMCPseudoLowering.inc"
    1201             : 
    1202      124017 : void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
    1203      124017 :   const DataLayout &DL = getDataLayout();
    1204      372051 :   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
    1205      124017 :   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
    1206             : 
    1207             :   // If we just ended a constant pool, mark it as such.
    1208      125268 :   if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
    1209          80 :     OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
    1210          40 :     InConstantPool = false;
    1211             :   }
    1212             : 
    1213             :   // Emit unwinding stuff for frame-related instructions
    1214      185128 :   if (Subtarget->isTargetEHABICompatible() &&
    1215       61111 :        MI->getFlag(MachineInstr::FrameSetup))
    1216        3741 :     EmitUnwindingInstruction(MI);
    1217             : 
    1218             :   // Do any auto-generated pseudo lowerings.
    1219      248034 :   if (emitPseudoExpansionLowering(*OutStreamer, MI))
    1220       11928 :     return;
    1221             : 
    1222             :   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
    1223             :          "Pseudo flag setting opcode should be expanded early");
    1224             : 
    1225             :   // Check for manual lowerings.
    1226      234250 :   unsigned Opc = MI->getOpcode();
    1227      117125 :   switch (Opc) {
    1228           0 :   case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
    1229           0 :   case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
    1230         274 :   case ARM::LEApcrel:
    1231             :   case ARM::tLEApcrel:
    1232             :   case ARM::t2LEApcrel: {
    1233             :     // FIXME: Need to also handle globals and externals
    1234         274 :     MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
    1235        1644 :     EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
    1236         171 :                                                ARM::t2LEApcrel ? ARM::t2ADR
    1237         171 :                   : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
    1238             :                      : ARM::ADR))
    1239         274 :       .addReg(MI->getOperand(0).getReg())
    1240         822 :       .addExpr(MCSymbolRefExpr::create(CPISymbol, OutContext))
    1241             :       // Add predicate operands.
    1242         548 :       .addImm(MI->getOperand(2).getImm())
    1243         548 :       .addReg(MI->getOperand(3).getReg()));
    1244         274 :     return;
    1245             :   }
    1246          36 :   case ARM::LEApcrelJT:
    1247             :   case ARM::tLEApcrelJT:
    1248             :   case ARM::t2LEApcrelJT: {
    1249             :     MCSymbol *JTIPICSymbol =
    1250          36 :       GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
    1251         216 :     EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
    1252          32 :                                                ARM::t2LEApcrelJT ? ARM::t2ADR
    1253          32 :                   : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
    1254             :                      : ARM::ADR))
    1255          36 :       .addReg(MI->getOperand(0).getReg())
    1256         108 :       .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
    1257             :       // Add predicate operands.
    1258          72 :       .addImm(MI->getOperand(2).getImm())
    1259          72 :       .addReg(MI->getOperand(3).getReg()));
    1260          36 :     return;
    1261             :   }
    1262             :   // Darwin call instructions are just normal call instructions with different
    1263             :   // clobber semantics (they clobber R9).
    1264           2 :   case ARM::BX_CALL: {
    1265          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
    1266           2 :       .addReg(ARM::LR)
    1267           2 :       .addReg(ARM::PC)
    1268             :       // Add predicate operands.
    1269           2 :       .addImm(ARMCC::AL)
    1270           2 :       .addReg(0)
    1271             :       // Add 's' bit operand (always reg0 for this)
    1272           4 :       .addReg(0));
    1273             : 
    1274             :     assert(Subtarget->hasV4TOps());
    1275          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
    1276           4 :       .addReg(MI->getOperand(0).getReg()));
    1277           2 :     return;
    1278             :   }
    1279          63 :   case ARM::tBX_CALL: {
    1280          63 :     if (Subtarget->hasV5TOps())
    1281           0 :       llvm_unreachable("Expected BLX to be selected for v5t+");
    1282             : 
    1283             :     // On ARM v4t, when doing a call from thumb mode, we need to ensure
    1284             :     // that the saved lr has its LSB set correctly (the arch doesn't
    1285             :     // have blx).
    1286             :     // So here we generate a bl to a small jump pad that does bx rN.
    1287             :     // The jump pads are emitted after the function body.
    1288             : 
    1289          63 :     unsigned TReg = MI->getOperand(0).getReg();
    1290          63 :     MCSymbol *TRegSym = nullptr;
    1291         206 :     for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
    1292          37 :       if (TIP.first == TReg) {
    1293          20 :         TRegSym = TIP.second;
    1294          20 :         break;
    1295             :       }
    1296             :     }
    1297             : 
    1298          63 :     if (!TRegSym) {
    1299          43 :       TRegSym = OutContext.createTempSymbol();
    1300          86 :       ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
    1301             :     }
    1302             : 
    1303             :     // Create a link-saving branch to the Reg Indirect Jump Pad.
    1304         315 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBL)
    1305             :         // Predicate comes first here.
    1306          63 :         .addImm(ARMCC::AL).addReg(0)
    1307         252 :         .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
    1308             :     return;
    1309             :   }
    1310           9 :   case ARM::BMOVPCRX_CALL: {
    1311          45 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
    1312           9 :       .addReg(ARM::LR)
    1313           9 :       .addReg(ARM::PC)
    1314             :       // Add predicate operands.
    1315           9 :       .addImm(ARMCC::AL)
    1316           9 :       .addReg(0)
    1317             :       // Add 's' bit operand (always reg0 for this)
    1318          18 :       .addReg(0));
    1319             : 
    1320          45 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
    1321           9 :       .addReg(ARM::PC)
    1322           9 :       .addReg(MI->getOperand(0).getReg())
    1323             :       // Add predicate operands.
    1324           9 :       .addImm(ARMCC::AL)
    1325           9 :       .addReg(0)
    1326             :       // Add 's' bit operand (always reg0 for this)
    1327          18 :       .addReg(0));
    1328           9 :     return;
    1329             :   }
    1330          12 :   case ARM::BMOVPCB_CALL: {
    1331          60 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
    1332          12 :       .addReg(ARM::LR)
    1333          12 :       .addReg(ARM::PC)
    1334             :       // Add predicate operands.
    1335          12 :       .addImm(ARMCC::AL)
    1336          12 :       .addReg(0)
    1337             :       // Add 's' bit operand (always reg0 for this)
    1338          24 :       .addReg(0));
    1339             : 
    1340          12 :     const MachineOperand &Op = MI->getOperand(0);
    1341          12 :     const GlobalValue *GV = Op.getGlobal();
    1342          12 :     const unsigned TF = Op.getTargetFlags();
    1343          12 :     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
    1344          24 :     const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
    1345          60 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc)
    1346          12 :       .addExpr(GVSymExpr)
    1347             :       // Add predicate operands.
    1348          12 :       .addImm(ARMCC::AL)
    1349          24 :       .addReg(0));
    1350          12 :     return;
    1351             :   }
    1352         566 :   case ARM::MOVi16_ga_pcrel:
    1353             :   case ARM::t2MOVi16_ga_pcrel: {
    1354        1132 :     MCInst TmpInst;
    1355        1132 :     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
    1356        1698 :     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
    1357             : 
    1358        1132 :     unsigned TF = MI->getOperand(1).getTargetFlags();
    1359         566 :     const GlobalValue *GV = MI->getOperand(1).getGlobal();
    1360         566 :     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
    1361        1132 :     const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
    1362             : 
    1363             :     MCSymbol *LabelSym =
    1364        1132 :         getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
    1365        1132 :                     MI->getOperand(2).getImm(), OutContext);
    1366        1132 :     const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
    1367         566 :     unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
    1368             :     const MCExpr *PCRelExpr =
    1369        1698 :       ARMMCExpr::createLower16(MCBinaryExpr::createSub(GVSymExpr,
    1370         566 :                                       MCBinaryExpr::createAdd(LabelSymExpr,
    1371         566 :                                       MCConstantExpr::create(PCAdj, OutContext),
    1372         566 :                                       OutContext), OutContext), OutContext);
    1373        1132 :       TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
    1374             : 
    1375             :     // Add predicate operands.
    1376        1132 :     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
    1377        1132 :     TmpInst.addOperand(MCOperand::createReg(0));
    1378             :     // Add 's' bit operand (always reg0 for this)
    1379        1132 :     TmpInst.addOperand(MCOperand::createReg(0));
    1380        1132 :     EmitToStreamer(*OutStreamer, TmpInst);
    1381             :     return;
    1382             :   }
    1383         566 :   case ARM::MOVTi16_ga_pcrel:
    1384             :   case ARM::t2MOVTi16_ga_pcrel: {
    1385        1132 :     MCInst TmpInst;
    1386        1132 :     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
    1387             :                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
    1388        1698 :     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
    1389        1698 :     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
    1390             : 
    1391        1132 :     unsigned TF = MI->getOperand(2).getTargetFlags();
    1392         566 :     const GlobalValue *GV = MI->getOperand(2).getGlobal();
    1393         566 :     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
    1394        1132 :     const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
    1395             : 
    1396             :     MCSymbol *LabelSym =
    1397        1132 :         getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
    1398        1132 :                     MI->getOperand(3).getImm(), OutContext);
    1399        1132 :     const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
    1400         566 :     unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
    1401             :     const MCExpr *PCRelExpr =
    1402        1698 :         ARMMCExpr::createUpper16(MCBinaryExpr::createSub(GVSymExpr,
    1403         566 :                                    MCBinaryExpr::createAdd(LabelSymExpr,
    1404         566 :                                       MCConstantExpr::create(PCAdj, OutContext),
    1405         566 :                                           OutContext), OutContext), OutContext);
    1406        1132 :       TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
    1407             :     // Add predicate operands.
    1408        1132 :     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
    1409        1132 :     TmpInst.addOperand(MCOperand::createReg(0));
    1410             :     // Add 's' bit operand (always reg0 for this)
    1411        1132 :     TmpInst.addOperand(MCOperand::createReg(0));
    1412        1132 :     EmitToStreamer(*OutStreamer, TmpInst);
    1413             :     return;
    1414             :   }
    1415         563 :   case ARM::tPICADD: {
    1416             :     // This is a pseudo op for a label + instruction sequence, which looks like:
    1417             :     // LPC0:
    1418             :     //     add r0, pc
    1419             :     // This adds the address of LPC0 to r0.
    1420             : 
    1421             :     // Emit the label.
    1422        2252 :     OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
    1423             :                                        getFunctionNumber(),
    1424        1126 :                                        MI->getOperand(2).getImm(), OutContext));
    1425             : 
    1426             :     // Form and emit the add.
    1427        2815 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
    1428         563 :       .addReg(MI->getOperand(0).getReg())
    1429         563 :       .addReg(MI->getOperand(0).getReg())
    1430         563 :       .addReg(ARM::PC)
    1431             :       // Add predicate operands.
    1432         563 :       .addImm(ARMCC::AL)
    1433        1126 :       .addReg(0));
    1434         563 :     return;
    1435             :   }
    1436         191 :   case ARM::PICADD: {
    1437             :     // This is a pseudo op for a label + instruction sequence, which looks like:
    1438             :     // LPC0:
    1439             :     //     add r0, pc, r0
    1440             :     // This adds the address of LPC0 to r0.
    1441             : 
    1442             :     // Emit the label.
    1443         764 :     OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
    1444             :                                        getFunctionNumber(),
    1445         382 :                                        MI->getOperand(2).getImm(), OutContext));
    1446             : 
    1447             :     // Form and emit the add.
    1448         955 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
    1449         191 :       .addReg(MI->getOperand(0).getReg())
    1450         191 :       .addReg(ARM::PC)
    1451         191 :       .addReg(MI->getOperand(1).getReg())
    1452             :       // Add predicate operands.
    1453         382 :       .addImm(MI->getOperand(3).getImm())
    1454         191 :       .addReg(MI->getOperand(4).getReg())
    1455             :       // Add 's' bit operand (always reg0 for this)
    1456         382 :       .addReg(0));
    1457         191 :     return;
    1458             :   }
    1459         225 :   case ARM::PICSTR:
    1460             :   case ARM::PICSTRB:
    1461             :   case ARM::PICSTRH:
    1462             :   case ARM::PICLDR:
    1463             :   case ARM::PICLDRB:
    1464             :   case ARM::PICLDRH:
    1465             :   case ARM::PICLDRSB:
    1466             :   case ARM::PICLDRSH: {
    1467             :     // This is a pseudo op for a label + instruction sequence, which looks like:
    1468             :     // LPC0:
    1469             :     //     OP r0, [pc, r0]
    1470             :     // The LCP0 label is referenced by a constant pool entry in order to get
    1471             :     // a PC-relative address at the ldr instruction.
    1472             : 
    1473             :     // Emit the label.
    1474         900 :     OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
    1475             :                                        getFunctionNumber(),
    1476         450 :                                        MI->getOperand(2).getImm(), OutContext));
    1477             : 
    1478             :     // Form and emit the load
    1479             :     unsigned Opcode;
    1480         450 :     switch (MI->getOpcode()) {
    1481           0 :     default:
    1482           0 :       llvm_unreachable("Unexpected opcode!");
    1483             :     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
    1484           0 :     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
    1485           0 :     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
    1486         225 :     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
    1487           0 :     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
    1488           0 :     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
    1489           0 :     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
    1490           0 :     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
    1491             :     }
    1492        1125 :     EmitToStreamer(*OutStreamer, MCInstBuilder(Opcode)
    1493         225 :       .addReg(MI->getOperand(0).getReg())
    1494         225 :       .addReg(ARM::PC)
    1495         225 :       .addReg(MI->getOperand(1).getReg())
    1496         225 :       .addImm(0)
    1497             :       // Add predicate operands.
    1498         450 :       .addImm(MI->getOperand(3).getImm())
    1499         450 :       .addReg(MI->getOperand(4).getReg()));
    1500             : 
    1501         225 :     return;
    1502             :   }
    1503        2321 :   case ARM::CONSTPOOL_ENTRY: {
    1504        2321 :     if (Subtarget->genExecuteOnly())
    1505           0 :       llvm_unreachable("execute-only should not generate constant pools");
    1506             : 
    1507             :     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
    1508             :     /// in the function.  The first operand is the ID# for this instruction, the
    1509             :     /// second is the index into the MachineConstantPool that this is, the third
    1510             :     /// is the size in bytes of this constant pool entry.
    1511             :     /// The required alignment is specified on the basic block holding this MI.
    1512        2321 :     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
    1513        2321 :     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
    1514             : 
    1515             :     // If this is the first entry of the pool, mark it.
    1516        2321 :     if (!InConstantPool) {
    1517        2220 :       OutStreamer->EmitDataRegion(MCDR_DataRegion);
    1518        1110 :       InConstantPool = true;
    1519             :     }
    1520             : 
    1521        4642 :     OutStreamer->EmitLabel(GetCPISymbol(LabelId));
    1522             : 
    1523        4642 :     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
    1524        2321 :     if (MCPE.isMachineConstantPoolEntry())
    1525         624 :       EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
    1526             :     else
    1527        1697 :       EmitGlobalConstant(DL, MCPE.Val.ConstVal);
    1528             :     return;
    1529             :   }
    1530          29 :   case ARM::JUMPTABLE_ADDRS:
    1531          29 :     EmitJumpTableAddrs(MI);
    1532          29 :     return;
    1533           6 :   case ARM::JUMPTABLE_INSTS:
    1534           6 :     EmitJumpTableInsts(MI);
    1535           6 :     return;
    1536          30 :   case ARM::JUMPTABLE_TBB:
    1537             :   case ARM::JUMPTABLE_TBH:
    1538          30 :     EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
    1539          30 :     return;
    1540           6 :   case ARM::t2BR_JT: {
    1541             :     // Lower and emit the instruction itself, then the jump table following it.
    1542          30 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
    1543           6 :       .addReg(ARM::PC)
    1544           6 :       .addReg(MI->getOperand(0).getReg())
    1545             :       // Add predicate operands.
    1546           6 :       .addImm(ARMCC::AL)
    1547          12 :       .addReg(0));
    1548           6 :     return;
    1549             :   }
    1550          21 :   case ARM::t2TBB_JT:
    1551             :   case ARM::t2TBH_JT: {
    1552          21 :     unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
    1553             :     // Lower and emit the PC label, then the instruction itself.
    1554          42 :     OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
    1555         105 :     EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
    1556          21 :                                      .addReg(MI->getOperand(0).getReg())
    1557          21 :                                      .addReg(MI->getOperand(1).getReg())
    1558             :                                      // Add predicate operands.
    1559          21 :                                      .addImm(ARMCC::AL)
    1560          42 :                                      .addReg(0));
    1561          21 :     return;
    1562             :   }
    1563           9 :   case ARM::tTBB_JT:
    1564             :   case ARM::tTBH_JT: {
    1565             : 
    1566           9 :     bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
    1567           9 :     unsigned Base = MI->getOperand(0).getReg();
    1568           9 :     unsigned Idx = MI->getOperand(1).getReg();
    1569             :     assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
    1570             : 
    1571             :     // Multiply up idx if necessary.
    1572           9 :     if (!Is8Bit)
    1573           5 :       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri)
    1574           1 :                                        .addReg(Idx)
    1575           1 :                                        .addReg(ARM::CPSR)
    1576           1 :                                        .addReg(Idx)
    1577           1 :                                        .addImm(1)
    1578             :                                        // Add predicate operands.
    1579           1 :                                        .addImm(ARMCC::AL)
    1580           2 :                                        .addReg(0));
    1581             : 
    1582           9 :     if (Base == ARM::PC) {
    1583             :       // TBB [base, idx] =
    1584             :       //    ADDS idx, idx, base
    1585             :       //    LDRB idx, [idx, #4] ; or LDRH if TBH
    1586             :       //    LSLS idx, #1
    1587             :       //    ADDS pc, pc, idx
    1588             : 
    1589             :       // When using PC as the base, it's important that there is no padding
    1590             :       // between the last ADDS and the start of the jump table. The jump table
    1591             :       // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
    1592             :       //
    1593             :       // FIXME: Ideally we could vary the LDRB index based on the padding
    1594             :       // between the sequence and jump table, however that relies on MCExprs
    1595             :       // for load indexes which are currently not supported.
    1596          18 :       OutStreamer->EmitCodeAlignment(4);
    1597          45 :       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
    1598           9 :                                        .addReg(Idx)
    1599           9 :                                        .addReg(Idx)
    1600           9 :                                        .addReg(Base)
    1601             :                                        // Add predicate operands.
    1602           9 :                                        .addImm(ARMCC::AL)
    1603          18 :                                        .addReg(0));
    1604             : 
    1605           9 :       unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
    1606          45 :       EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
    1607           9 :                                        .addReg(Idx)
    1608           9 :                                        .addReg(Idx)
    1609          18 :                                        .addImm(Is8Bit ? 4 : 2)
    1610             :                                        // Add predicate operands.
    1611           9 :                                        .addImm(ARMCC::AL)
    1612          18 :                                        .addReg(0));
    1613             :     } else {
    1614             :       // TBB [base, idx] =
    1615             :       //    LDRB idx, [base, idx] ; or LDRH if TBH
    1616             :       //    LSLS idx, #1
    1617             :       //    ADDS pc, pc, idx
    1618             : 
    1619           0 :       unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
    1620           0 :       EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
    1621           0 :                                        .addReg(Idx)
    1622           0 :                                        .addReg(Base)
    1623           0 :                                        .addReg(Idx)
    1624             :                                        // Add predicate operands.
    1625           0 :                                        .addImm(ARMCC::AL)
    1626           0 :                                        .addReg(0));
    1627             :     }
    1628             : 
    1629          45 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri)
    1630           9 :                                      .addReg(Idx)
    1631           9 :                                      .addReg(ARM::CPSR)
    1632           9 :                                      .addReg(Idx)
    1633           9 :                                      .addImm(1)
    1634             :                                      // Add predicate operands.
    1635           9 :                                      .addImm(ARMCC::AL)
    1636          18 :                                      .addReg(0));
    1637             : 
    1638          18 :     OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
    1639          45 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
    1640           9 :                                      .addReg(ARM::PC)
    1641           9 :                                      .addReg(ARM::PC)
    1642           9 :                                      .addReg(Idx)
    1643             :                                      // Add predicate operands.
    1644           9 :                                      .addImm(ARMCC::AL)
    1645          18 :                                      .addReg(0));
    1646           9 :     return;
    1647             :   }
    1648           8 :   case ARM::tBR_JTr:
    1649             :   case ARM::BR_JTr: {
    1650             :     // Lower and emit the instruction itself, then the jump table following it.
    1651             :     // mov pc, target
    1652          16 :     MCInst TmpInst;
    1653          16 :     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
    1654           8 :       ARM::MOVr : ARM::tMOVr;
    1655          16 :     TmpInst.setOpcode(Opc);
    1656          16 :     TmpInst.addOperand(MCOperand::createReg(ARM::PC));
    1657          24 :     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
    1658             :     // Add predicate operands.
    1659          16 :     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
    1660          16 :     TmpInst.addOperand(MCOperand::createReg(0));
    1661             :     // Add 's' bit operand (always reg0 for this)
    1662           8 :     if (Opc == ARM::MOVr)
    1663           4 :       TmpInst.addOperand(MCOperand::createReg(0));
    1664          16 :     EmitToStreamer(*OutStreamer, TmpInst);
    1665             :     return;
    1666             :   }
    1667           2 :   case ARM::BR_JTm: {
    1668             :     // Lower and emit the instruction itself, then the jump table following it.
    1669             :     // ldr pc, target
    1670           4 :     MCInst TmpInst;
    1671           2 :     if (MI->getOperand(1).getReg() == 0) {
    1672             :       // literal offset
    1673           0 :       TmpInst.setOpcode(ARM::LDRi12);
    1674           0 :       TmpInst.addOperand(MCOperand::createReg(ARM::PC));
    1675           0 :       TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
    1676           0 :       TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
    1677             :     } else {
    1678           4 :       TmpInst.setOpcode(ARM::LDRrs);
    1679           4 :       TmpInst.addOperand(MCOperand::createReg(ARM::PC));
    1680           6 :       TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
    1681           6 :       TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
    1682           4 :       TmpInst.addOperand(MCOperand::createImm(0));
    1683             :     }
    1684             :     // Add predicate operands.
    1685           4 :     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
    1686           4 :     TmpInst.addOperand(MCOperand::createReg(0));
    1687           4 :     EmitToStreamer(*OutStreamer, TmpInst);
    1688             :     return;
    1689             :   }
    1690          19 :   case ARM::BR_JTadd: {
    1691             :     // Lower and emit the instruction itself, then the jump table following it.
    1692             :     // add pc, target, idx
    1693          95 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
    1694          19 :       .addReg(ARM::PC)
    1695          19 :       .addReg(MI->getOperand(0).getReg())
    1696          19 :       .addReg(MI->getOperand(1).getReg())
    1697             :       // Add predicate operands.
    1698          19 :       .addImm(ARMCC::AL)
    1699          19 :       .addReg(0)
    1700             :       // Add 's' bit operand (always reg0 for this)
    1701          38 :       .addReg(0));
    1702          19 :     return;
    1703             :   }
    1704          10 :   case ARM::SPACE:
    1705          20 :     OutStreamer->EmitZeros(MI->getOperand(1).getImm());
    1706          10 :     return;
    1707          55 :   case ARM::TRAP: {
    1708             :     // Non-Darwin binutils don't yet support the "trap" mnemonic.
    1709             :     // FIXME: Remove this special case when they do.
    1710         110 :     if (!Subtarget->isTargetMachO()) {
    1711          27 :       uint32_t Val = 0xe7ffdefeUL;
    1712          81 :       OutStreamer->AddComment("trap");
    1713          27 :       ATS.emitInst(Val);
    1714          27 :       return;
    1715             :     }
    1716             :     break;
    1717             :   }
    1718           6 :   case ARM::TRAPNaCl: {
    1719           6 :     uint32_t Val = 0xe7fedef0UL;
    1720          18 :     OutStreamer->AddComment("trap");
    1721           6 :     ATS.emitInst(Val);
    1722           6 :     return;
    1723             :   }
    1724          45 :   case ARM::tTRAP: {
    1725             :     // Non-Darwin binutils don't yet support the "trap" mnemonic.
    1726             :     // FIXME: Remove this special case when they do.
    1727          90 :     if (!Subtarget->isTargetMachO()) {
    1728          10 :       uint16_t Val = 0xdefe;
    1729          30 :       OutStreamer->AddComment("trap");
    1730          10 :       ATS.emitInst(Val, 'n');
    1731          10 :       return;
    1732             :     }
    1733             :     break;
    1734             :   }
    1735           2 :   case ARM::t2Int_eh_sjlj_setjmp:
    1736             :   case ARM::t2Int_eh_sjlj_setjmp_nofp:
    1737             :   case ARM::tInt_eh_sjlj_setjmp: {
    1738             :     // Two incoming args: GPR:$src, GPR:$val
    1739             :     // mov $val, pc
    1740             :     // adds $val, #7
    1741             :     // str $val, [$src, #4]
    1742             :     // movs r0, #0
    1743             :     // b LSJLJEH
    1744             :     // movs r0, #1
    1745             :     // LSJLJEH:
    1746           2 :     unsigned SrcReg = MI->getOperand(0).getReg();
    1747           2 :     unsigned ValReg = MI->getOperand(1).getReg();
    1748           4 :     MCSymbol *Label = OutContext.createTempSymbol("SJLJEH", false, true);
    1749           6 :     OutStreamer->AddComment("eh_setjmp begin");
    1750          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
    1751           2 :       .addReg(ValReg)
    1752           2 :       .addReg(ARM::PC)
    1753             :       // Predicate.
    1754           2 :       .addImm(ARMCC::AL)
    1755           4 :       .addReg(0));
    1756             : 
    1757          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi3)
    1758           2 :       .addReg(ValReg)
    1759             :       // 's' bit operand
    1760           2 :       .addReg(ARM::CPSR)
    1761           2 :       .addReg(ValReg)
    1762           2 :       .addImm(7)
    1763             :       // Predicate.
    1764           2 :       .addImm(ARMCC::AL)
    1765           4 :       .addReg(0));
    1766             : 
    1767          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSTRi)
    1768           2 :       .addReg(ValReg)
    1769           2 :       .addReg(SrcReg)
    1770             :       // The offset immediate is #4. The operand value is scaled by 4 for the
    1771             :       // tSTR instruction.
    1772           2 :       .addImm(1)
    1773             :       // Predicate.
    1774           2 :       .addImm(ARMCC::AL)
    1775           4 :       .addReg(0));
    1776             : 
    1777          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
    1778           2 :       .addReg(ARM::R0)
    1779           2 :       .addReg(ARM::CPSR)
    1780           2 :       .addImm(0)
    1781             :       // Predicate.
    1782           2 :       .addImm(ARMCC::AL)
    1783           4 :       .addReg(0));
    1784             : 
    1785           4 :     const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
    1786          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tB)
    1787           2 :       .addExpr(SymbolExpr)
    1788           2 :       .addImm(ARMCC::AL)
    1789           4 :       .addReg(0));
    1790             : 
    1791           6 :     OutStreamer->AddComment("eh_setjmp end");
    1792          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
    1793           2 :       .addReg(ARM::R0)
    1794           2 :       .addReg(ARM::CPSR)
    1795           2 :       .addImm(1)
    1796             :       // Predicate.
    1797           2 :       .addImm(ARMCC::AL)
    1798           4 :       .addReg(0));
    1799             : 
    1800           4 :     OutStreamer->EmitLabel(Label);
    1801           2 :     return;
    1802             :   }
    1803             : 
    1804           2 :   case ARM::Int_eh_sjlj_setjmp_nofp:
    1805             :   case ARM::Int_eh_sjlj_setjmp: {
    1806             :     // Two incoming args: GPR:$src, GPR:$val
    1807             :     // add $val, pc, #8
    1808             :     // str $val, [$src, #+4]
    1809             :     // mov r0, #0
    1810             :     // add pc, pc, #0
    1811             :     // mov r0, #1
    1812           2 :     unsigned SrcReg = MI->getOperand(0).getReg();
    1813           2 :     unsigned ValReg = MI->getOperand(1).getReg();
    1814             : 
    1815           6 :     OutStreamer->AddComment("eh_setjmp begin");
    1816          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
    1817           2 :       .addReg(ValReg)
    1818           2 :       .addReg(ARM::PC)
    1819           2 :       .addImm(8)
    1820             :       // Predicate.
    1821           2 :       .addImm(ARMCC::AL)
    1822           2 :       .addReg(0)
    1823             :       // 's' bit operand (always reg0 for this).
    1824           4 :       .addReg(0));
    1825             : 
    1826          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STRi12)
    1827           2 :       .addReg(ValReg)
    1828           2 :       .addReg(SrcReg)
    1829           2 :       .addImm(4)
    1830             :       // Predicate.
    1831           2 :       .addImm(ARMCC::AL)
    1832           4 :       .addReg(0));
    1833             : 
    1834          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
    1835           2 :       .addReg(ARM::R0)
    1836           2 :       .addImm(0)
    1837             :       // Predicate.
    1838           2 :       .addImm(ARMCC::AL)
    1839           2 :       .addReg(0)
    1840             :       // 's' bit operand (always reg0 for this).
    1841           4 :       .addReg(0));
    1842             : 
    1843          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
    1844           2 :       .addReg(ARM::PC)
    1845           2 :       .addReg(ARM::PC)
    1846           2 :       .addImm(0)
    1847             :       // Predicate.
    1848           2 :       .addImm(ARMCC::AL)
    1849           2 :       .addReg(0)
    1850             :       // 's' bit operand (always reg0 for this).
    1851           4 :       .addReg(0));
    1852             : 
    1853           6 :     OutStreamer->AddComment("eh_setjmp end");
    1854          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
    1855           2 :       .addReg(ARM::R0)
    1856           2 :       .addImm(1)
    1857             :       // Predicate.
    1858           2 :       .addImm(ARMCC::AL)
    1859           2 :       .addReg(0)
    1860             :       // 's' bit operand (always reg0 for this).
    1861           4 :       .addReg(0));
    1862           2 :     return;
    1863             :   }
    1864           2 :   case ARM::Int_eh_sjlj_longjmp: {
    1865             :     // ldr sp, [$src, #8]
    1866             :     // ldr $scratch, [$src, #4]
    1867             :     // ldr r7, [$src]
    1868             :     // bx $scratch
    1869           2 :     unsigned SrcReg = MI->getOperand(0).getReg();
    1870           2 :     unsigned ScratchReg = MI->getOperand(1).getReg();
    1871          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
    1872           2 :       .addReg(ARM::SP)
    1873           2 :       .addReg(SrcReg)
    1874           2 :       .addImm(8)
    1875             :       // Predicate.
    1876           2 :       .addImm(ARMCC::AL)
    1877           4 :       .addReg(0));
    1878             : 
    1879          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
    1880           2 :       .addReg(ScratchReg)
    1881           2 :       .addReg(SrcReg)
    1882           2 :       .addImm(4)
    1883             :       // Predicate.
    1884           2 :       .addImm(ARMCC::AL)
    1885           4 :       .addReg(0));
    1886             : 
    1887          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
    1888           2 :       .addReg(ARM::R7)
    1889           2 :       .addReg(SrcReg)
    1890           2 :       .addImm(0)
    1891             :       // Predicate.
    1892           2 :       .addImm(ARMCC::AL)
    1893           4 :       .addReg(0));
    1894             : 
    1895             :     assert(Subtarget->hasV4TOps());
    1896          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
    1897           2 :       .addReg(ScratchReg)
    1898             :       // Predicate.
    1899           2 :       .addImm(ARMCC::AL)
    1900           4 :       .addReg(0));
    1901           2 :     return;
    1902             :   }
    1903           2 :   case ARM::tInt_eh_sjlj_longjmp: {
    1904             :     // ldr $scratch, [$src, #8]
    1905             :     // mov sp, $scratch
    1906             :     // ldr $scratch, [$src, #4]
    1907             :     // ldr r7, [$src]
    1908             :     // bx $scratch
    1909           2 :     unsigned SrcReg = MI->getOperand(0).getReg();
    1910           2 :     unsigned ScratchReg = MI->getOperand(1).getReg();
    1911             : 
    1912          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
    1913           2 :       .addReg(ScratchReg)
    1914           2 :       .addReg(SrcReg)
    1915             :       // The offset immediate is #8. The operand value is scaled by 4 for the
    1916             :       // tLDR instruction.
    1917           2 :       .addImm(2)
    1918             :       // Predicate.
    1919           2 :       .addImm(ARMCC::AL)
    1920           4 :       .addReg(0));
    1921             : 
    1922          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
    1923           2 :       .addReg(ARM::SP)
    1924           2 :       .addReg(ScratchReg)
    1925             :       // Predicate.
    1926           2 :       .addImm(ARMCC::AL)
    1927           4 :       .addReg(0));
    1928             : 
    1929          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
    1930           2 :       .addReg(ScratchReg)
    1931           2 :       .addReg(SrcReg)
    1932           2 :       .addImm(1)
    1933             :       // Predicate.
    1934           2 :       .addImm(ARMCC::AL)
    1935           4 :       .addReg(0));
    1936             : 
    1937          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
    1938           2 :       .addReg(ARM::R7)
    1939           2 :       .addReg(SrcReg)
    1940           2 :       .addImm(0)
    1941             :       // Predicate.
    1942           2 :       .addImm(ARMCC::AL)
    1943           4 :       .addReg(0));
    1944             : 
    1945          10 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
    1946           2 :       .addReg(ScratchReg)
    1947             :       // Predicate.
    1948           2 :       .addImm(ARMCC::AL)
    1949           4 :       .addReg(0));
    1950           2 :     return;
    1951             :   }
    1952           1 :   case ARM::tInt_WIN_eh_sjlj_longjmp: {
    1953             :     // ldr.w r11, [$src, #0]
    1954             :     // ldr.w  sp, [$src, #8]
    1955             :     // ldr.w  pc, [$src, #4]
    1956             : 
    1957           1 :     unsigned SrcReg = MI->getOperand(0).getReg();
    1958             : 
    1959           5 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
    1960           1 :                                      .addReg(ARM::R11)
    1961           1 :                                      .addReg(SrcReg)
    1962           1 :                                      .addImm(0)
    1963             :                                      // Predicate
    1964           1 :                                      .addImm(ARMCC::AL)
    1965           2 :                                      .addReg(0));
    1966           5 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
    1967           1 :                                      .addReg(ARM::SP)
    1968           1 :                                      .addReg(SrcReg)
    1969           1 :                                      .addImm(8)
    1970             :                                      // Predicate
    1971           1 :                                      .addImm(ARMCC::AL)
    1972           2 :                                      .addReg(0));
    1973           5 :     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
    1974           1 :                                      .addReg(ARM::PC)
    1975           1 :                                      .addReg(SrcReg)
    1976           1 :                                      .addImm(4)
    1977             :                                      // Predicate
    1978           1 :                                      .addImm(ARMCC::AL)
    1979           2 :                                      .addReg(0));
    1980           1 :     return;
    1981             :   }
    1982           8 :   case ARM::PATCHABLE_FUNCTION_ENTER:
    1983           8 :     LowerPATCHABLE_FUNCTION_ENTER(*MI);
    1984           8 :     return;
    1985           8 :   case ARM::PATCHABLE_FUNCTION_EXIT:
    1986           8 :     LowerPATCHABLE_FUNCTION_EXIT(*MI);
    1987           8 :     return;
    1988           0 :   case ARM::PATCHABLE_TAIL_CALL:
    1989           0 :     LowerPATCHABLE_TAIL_CALL(*MI);
    1990           0 :     return;
    1991             :   }
    1992             : 
    1993      224178 :   MCInst TmpInst;
    1994      112089 :   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
    1995             : 
    1996      224178 :   EmitToStreamer(*OutStreamer, TmpInst);
    1997             : }
    1998             : 
    1999             : //===----------------------------------------------------------------------===//
    2000             : // Target Registry Stuff
    2001             : //===----------------------------------------------------------------------===//
    2002             : 
    2003             : // Force static initialization.
    2004       47006 : extern "C" void LLVMInitializeARMAsmPrinter() {
    2005       94012 :   RegisterAsmPrinter<ARMAsmPrinter> X(getTheARMLETarget());
    2006       94012 :   RegisterAsmPrinter<ARMAsmPrinter> Y(getTheARMBETarget());
    2007       94012 :   RegisterAsmPrinter<ARMAsmPrinter> A(getTheThumbLETarget());
    2008       94012 :   RegisterAsmPrinter<ARMAsmPrinter> B(getTheThumbBETarget());
    2009       47006 : }

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