LCOV - code coverage report
Current view: top level - lib/Target/ARM - ARMBaseRegisterInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 312 341 91.5 %
Date: 2017-09-14 15:23:50 Functions: 32 34 94.1 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains the base ARM implementation of TargetRegisterInfo class.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "ARMBaseRegisterInfo.h"
      15             : #include "ARM.h"
      16             : #include "ARMBaseInstrInfo.h"
      17             : #include "ARMFrameLowering.h"
      18             : #include "ARMMachineFunctionInfo.h"
      19             : #include "ARMSubtarget.h"
      20             : #include "MCTargetDesc/ARMAddressingModes.h"
      21             : #include "MCTargetDesc/ARMBaseInfo.h"
      22             : #include "llvm/ADT/BitVector.h"
      23             : #include "llvm/ADT/STLExtras.h"
      24             : #include "llvm/ADT/SmallVector.h"
      25             : #include "llvm/CodeGen/MachineBasicBlock.h"
      26             : #include "llvm/CodeGen/MachineConstantPool.h"
      27             : #include "llvm/CodeGen/MachineFrameInfo.h"
      28             : #include "llvm/CodeGen/MachineFunction.h"
      29             : #include "llvm/CodeGen/MachineInstr.h"
      30             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      31             : #include "llvm/CodeGen/MachineOperand.h"
      32             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      33             : #include "llvm/CodeGen/RegisterScavenging.h"
      34             : #include "llvm/CodeGen/VirtRegMap.h"
      35             : #include "llvm/IR/Attributes.h"
      36             : #include "llvm/IR/Constants.h"
      37             : #include "llvm/IR/DebugLoc.h"
      38             : #include "llvm/IR/Function.h"
      39             : #include "llvm/IR/Type.h"
      40             : #include "llvm/MC/MCInstrDesc.h"
      41             : #include "llvm/Support/Debug.h"
      42             : #include "llvm/Support/ErrorHandling.h"
      43             : #include "llvm/Support/raw_ostream.h"
      44             : #include "llvm/Target/TargetInstrInfo.h"
      45             : #include "llvm/Target/TargetMachine.h"
      46             : #include "llvm/Target/TargetOptions.h"
      47             : #include "llvm/Target/TargetRegisterInfo.h"
      48             : #include <cassert>
      49             : #include <utility>
      50             : 
      51             : #define DEBUG_TYPE "arm-register-info"
      52             : 
      53             : #define GET_REGINFO_TARGET_DESC
      54             : #include "ARMGenRegisterInfo.inc"
      55             : 
      56             : using namespace llvm;
      57             : 
      58        4487 : ARMBaseRegisterInfo::ARMBaseRegisterInfo()
      59        4487 :     : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {}
      60             : 
      61             : static unsigned getFramePointerReg(const ARMSubtarget &STI) {
      62        5868 :   return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
      63             : }
      64             : 
      65             : const MCPhysReg*
      66      169555 : ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
      67      169555 :   const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
      68      169555 :   bool UseSplitPush = STI.splitFramePushPop(*MF);
      69             :   const MCPhysReg *RegList =
      70      132699 :       STI.isTargetDarwin()
      71      132699 :           ? CSR_iOS_SaveList
      72      169555 :           : (UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList);
      73             : 
      74      169555 :   const Function *F = MF->getFunction();
      75      169555 :   if (F->getCallingConv() == CallingConv::GHC) {
      76             :     // GHC set of callee saved regs is empty as all those regs are
      77             :     // used for passing STG regs around
      78             :     return CSR_NoRegs_SaveList;
      79      339070 :   } else if (F->hasFnAttribute("interrupt")) {
      80         192 :     if (STI.isMClass()) {
      81             :       // M-class CPUs have hardware which saves the registers needed to allow a
      82             :       // function conforming to the AAPCS to function as a handler.
      83          66 :       return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList;
      84         378 :     } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") {
      85             :       // Fast interrupt mode gives the handler a private copy of R8-R14, so less
      86             :       // need to be saved to restore user-mode state.
      87             :       return CSR_FIQ_SaveList;
      88             :     } else {
      89             :       // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
      90             :       // exception handling.
      91             :       return CSR_GenericInt_SaveList;
      92             :     }
      93             :   }
      94             : 
      95      338686 :   if (STI.getTargetLowering()->supportSwiftError() &&
      96      338686 :       F->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
      97             :     return CSR_iOS_SwiftError_SaveList;
      98             : 
      99       36279 :   if (STI.isTargetDarwin() && F->getCallingConv() == CallingConv::CXX_FAST_TLS)
     100         341 :     return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
     101         341 :                ? CSR_iOS_CXX_TLS_PE_SaveList
     102             :                : CSR_iOS_CXX_TLS_SaveList;
     103             :   return RegList;
     104             : }
     105             : 
     106       10834 : const MCPhysReg *ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy(
     107             :     const MachineFunction *MF) const {
     108             :   assert(MF && "Invalid MachineFunction pointer.");
     109       21714 :   if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
     110          46 :       MF->getInfo<ARMFunctionInfo>()->isSplitCSR())
     111             :     return CSR_iOS_CXX_TLS_ViaCopy_SaveList;
     112             :   return nullptr;
     113             : }
     114             : 
     115             : const uint32_t *
     116        7471 : ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
     117             :                                           CallingConv::ID CC) const {
     118        7471 :   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
     119        7471 :   if (CC == CallingConv::GHC)
     120             :     // This is academic because all GHC calls are (supposed to be) tail calls
     121             :     return CSR_NoRegs_RegMask;
     122             : 
     123       14938 :   if (STI.getTargetLowering()->supportSwiftError() &&
     124        7508 :       MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
     125             :     return CSR_iOS_SwiftError_RegMask;
     126             : 
     127        2956 :   if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS)
     128             :     return CSR_iOS_CXX_TLS_RegMask;
     129        4474 :   return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
     130             : }
     131             : 
     132             : const uint32_t*
     133           0 : ARMBaseRegisterInfo::getNoPreservedMask() const {
     134           0 :   return CSR_NoRegs_RegMask;
     135             : }
     136             : 
     137             : const uint32_t *
     138          79 : ARMBaseRegisterInfo::getTLSCallPreservedMask(const MachineFunction &MF) const {
     139             :   assert(MF.getSubtarget<ARMSubtarget>().isTargetDarwin() &&
     140             :          "only know about special TLS call on Darwin");
     141          79 :   return CSR_iOS_TLSCall_RegMask;
     142             : }
     143             : 
     144             : const uint32_t *
     145          28 : ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(const MachineFunction &MF) const {
     146          28 :   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
     147          28 :   if (!STI.useSoftFloat() && STI.hasVFP2() && !STI.isThumb1Only())
     148             :     return CSR_NoRegs_RegMask;
     149             :   else
     150             :     return CSR_FPRegs_RegMask;
     151             : }
     152             : 
     153             : const uint32_t *
     154          50 : ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
     155             :                                                 CallingConv::ID CC) const {
     156          50 :   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
     157             :   // This should return a register mask that is the same as that returned by
     158             :   // getCallPreservedMask but that additionally preserves the register used for
     159             :   // the first i32 argument (which must also be the register used to return a
     160             :   // single i32 return value)
     161             :   //
     162             :   // In case that the calling convention does not use the same register for
     163             :   // both or otherwise does not want to enable this optimization, the function
     164             :   // should return NULL
     165          50 :   if (CC == CallingConv::GHC)
     166             :     // This is academic because all GHC calls are (supposed to be) tail calls
     167             :     return nullptr;
     168          17 :   return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
     169             :                               : CSR_AAPCS_ThisReturn_RegMask;
     170             : }
     171             : 
     172       24855 : BitVector ARMBaseRegisterInfo::
     173             : getReservedRegs(const MachineFunction &MF) const {
     174       24855 :   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
     175       24855 :   const ARMFrameLowering *TFI = getFrameLowering(MF);
     176             : 
     177             :   // FIXME: avoid re-calculating this every time.
     178       24855 :   BitVector Reserved(getNumRegs());
     179       24855 :   markSuperRegs(Reserved, ARM::SP);
     180       24855 :   markSuperRegs(Reserved, ARM::PC);
     181       24855 :   markSuperRegs(Reserved, ARM::FPSCR);
     182       24855 :   markSuperRegs(Reserved, ARM::APSR_NZCV);
     183       24855 :   if (TFI->hasFP(MF))
     184        7520 :     markSuperRegs(Reserved, getFramePointerReg(STI));
     185       24855 :   if (hasBasePointer(MF))
     186          68 :     markSuperRegs(Reserved, BasePtr);
     187             :   // Some targets reserve R9.
     188       19687 :   if (STI.isR9Reserved())
     189        1097 :     markSuperRegs(Reserved, ARM::R9);
     190             :   // Reserve D16-D31 if the subtarget doesn't support them.
     191       24855 :   if (!STI.hasVFP3() || STI.hasD16()) {
     192             :     static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
     193      330297 :     for (unsigned R = 0; R < 16; ++R)
     194      160144 :       markSuperRegs(Reserved, ARM::D16 + R);
     195             :   }
     196       24855 :   const TargetRegisterClass &RC = ARM::GPRPairRegClass;
     197      248550 :   for (unsigned Reg : RC)
     198      695940 :     for (MCSubRegIterator SI(Reg, this); SI.isValid(); ++SI)
     199     1043910 :       if (Reserved.test(*SI))
     200       29780 :         markSuperRegs(Reserved, Reg);
     201             : 
     202             :   assert(checkAllSuperRegsMarked(Reserved));
     203       24855 :   return Reserved;
     204             : }
     205             : 
     206             : const TargetRegisterClass *
     207       13041 : ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
     208             :                                                const MachineFunction &) const {
     209       13041 :   const TargetRegisterClass *Super = RC;
     210       13041 :   TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
     211             :   do {
     212       37098 :     switch (Super->getID()) {
     213             :     case ARM::GPRRegClassID:
     214             :     case ARM::SPRRegClassID:
     215             :     case ARM::DPRRegClassID:
     216             :     case ARM::QPRRegClassID:
     217             :     case ARM::QQPRRegClassID:
     218             :     case ARM::QQQQPRRegClassID:
     219             :     case ARM::GPRPairRegClassID:
     220             :       return Super;
     221             :     }
     222        6070 :     Super = *I++;
     223        6070 :   } while (Super);
     224             :   return RC;
     225             : }
     226             : 
     227             : const TargetRegisterClass *
     228         176 : ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
     229             :                                                                          const {
     230         176 :   return &ARM::GPRRegClass;
     231             : }
     232             : 
     233             : const TargetRegisterClass *
     234           4 : ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
     235           4 :   if (RC == &ARM::CCRRegClass)
     236             :     return &ARM::rGPRRegClass;  // Can't copy CCR registers.
     237           0 :   return RC;
     238             : }
     239             : 
     240             : unsigned
     241      956760 : ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
     242             :                                          MachineFunction &MF) const {
     243      956760 :   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
     244      956760 :   const ARMFrameLowering *TFI = getFrameLowering(MF);
     245             : 
     246     1913520 :   switch (RC->getID()) {
     247             :   default:
     248             :     return 0;
     249        9380 :   case ARM::tGPRRegClassID: {
     250             :     // hasFP ends up calling getMaxCallFrameComputed() which may not be
     251             :     // available when getPressureLimit() is called as part of
     252             :     // ScheduleDAGRRList.
     253        9380 :     bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
     254        9380 :                  ? TFI->hasFP(MF) : true;
     255        9380 :     return 5 - HasFP;
     256             :   }
     257        9380 :   case ARM::GPRRegClassID: {
     258        9380 :     bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
     259        9380 :                  ? TFI->hasFP(MF) : true;
     260       16239 :     return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0);
     261             :   }
     262       18760 :   case ARM::SPRRegClassID:  // Currently not used as 'rep' register class.
     263             :   case ARM::DPRRegClassID:
     264       18760 :     return 32 - 10;
     265             :   }
     266             : }
     267             : 
     268             : // Get the other register in a GPRPair.
     269        1074 : static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
     270        1074 :   for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
     271        2736 :     if (ARM::GPRPairRegClass.contains(*Supers))
     272         912 :       return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
     273         162 :   return 0;
     274             : }
     275             : 
     276             : // Resolve the RegPairEven / RegPairOdd register allocator hints.
     277             : void
     278       71840 : ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
     279             :                                            ArrayRef<MCPhysReg> Order,
     280             :                                            SmallVectorImpl<MCPhysReg> &Hints,
     281             :                                            const MachineFunction &MF,
     282             :                                            const VirtRegMap *VRM,
     283             :                                            const LiveRegMatrix *Matrix) const {
     284       71840 :   const MachineRegisterInfo &MRI = MF.getRegInfo();
     285       71840 :   std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
     286             : 
     287             :   unsigned Odd;
     288       71840 :   switch (Hint.first) {
     289             :   case ARMRI::RegPairEven:
     290             :     Odd = 0;
     291             :     break;
     292          86 :   case ARMRI::RegPairOdd:
     293          86 :     Odd = 1;
     294          86 :     break;
     295       71672 :   default:
     296       71672 :     TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
     297       71672 :     return;
     298             :   }
     299             : 
     300             :   // This register should preferably be even (Odd == 0) or odd (Odd == 1).
     301             :   // Check if the other part of the pair has already been assigned, and provide
     302             :   // the paired register as the first hint.
     303         168 :   unsigned Paired = Hint.second;
     304         168 :   if (Paired == 0)
     305             :     return;
     306             : 
     307         168 :   unsigned PairedPhys = 0;
     308         168 :   if (TargetRegisterInfo::isPhysicalRegister(Paired)) {
     309           0 :     PairedPhys = Paired;
     310         336 :   } else if (VRM && VRM->hasPhys(Paired)) {
     311         122 :     PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
     312             :   }
     313             : 
     314             :   // First prefer the paired physreg.
     315         229 :   if (PairedPhys && is_contained(Order, PairedPhys))
     316          61 :     Hints.push_back(PairedPhys);
     317             : 
     318             :   // Then prefer even or odd registers.
     319        2466 :   for (unsigned Reg : Order) {
     320        5316 :     if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
     321        1117 :       continue;
     322             :     // Don't provide hints that are paired to a reserved register.
     323        1013 :     unsigned Paired = getPairedGPR(Reg, !Odd, this);
     324        2108 :     if (!Paired || MRI.isReserved(Paired))
     325         244 :       continue;
     326         769 :     Hints.push_back(Reg);
     327             :   }
     328             : }
     329             : 
     330             : void
     331       18675 : ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg,
     332             :                                         MachineFunction &MF) const {
     333       18675 :   MachineRegisterInfo *MRI = &MF.getRegInfo();
     334       18675 :   std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
     335       18675 :   if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
     336       18721 :        Hint.first == (unsigned)ARMRI::RegPairEven) &&
     337          92 :       TargetRegisterInfo::isVirtualRegister(Hint.second)) {
     338             :     // If 'Reg' is one of the even / odd register pair and it's now changed
     339             :     // (e.g. coalesced) into a different register. The other register of the
     340             :     // pair allocation hint must be updated to reflect the relationship
     341             :     // change.
     342          46 :     unsigned OtherReg = Hint.second;
     343          92 :     Hint = MRI->getRegAllocationHint(OtherReg);
     344             :     // Make sure the pair has not already divorced.
     345          46 :     if (Hint.second == Reg) {
     346          92 :       MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
     347          46 :       if (TargetRegisterInfo::isVirtualRegister(NewReg))
     348          46 :         MRI->setRegAllocationHint(NewReg,
     349             :             Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven
     350             :             : ARMRI::RegPairOdd, OtherReg);
     351             :     }
     352             :   }
     353       18675 : }
     354             : 
     355       45878 : bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
     356       45878 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
     357       45878 :   const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     358       45878 :   const ARMFrameLowering *TFI = getFrameLowering(MF);
     359             : 
     360             :   // When outgoing call frames are so large that we adjust the stack pointer
     361             :   // around the call, we can no longer use the stack pointer to reach the
     362             :   // emergency spill slot.
     363       45878 :   if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
     364             :     return true;
     365             : 
     366             :   // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
     367             :   // negative range for ldr/str (255), and thumb1 is positive offsets only.
     368             :   // It's going to be better to use the SP or Base Pointer instead. When there
     369             :   // are variable sized objects, we can't reference off of the SP, so we
     370             :   // reserve a Base Pointer.
     371       45854 :   if (AFI->isThumbFunction() && MFI.hasVarSizedObjects()) {
     372             :     // Conservatively estimate whether the negative offset from the frame
     373             :     // pointer will be sufficient to reach. If a function has a smallish
     374             :     // frame, it's less likely to have lots of spills and callee saved
     375             :     // space, so it's all more likely to be within range of the frame pointer.
     376             :     // If it's wrong, the scavenger will still enable access to work, it just
     377             :     // won't be optimal.
     378          53 :     if (AFI->isThumb2Function() && MFI.getLocalFrameSize() < 128)
     379             :       return false;
     380             :     return true;
     381             :   }
     382             : 
     383             :   return false;
     384             : }
     385             : 
     386       13444 : bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
     387       13444 :   const MachineRegisterInfo *MRI = &MF.getRegInfo();
     388       13444 :   const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     389       13444 :   const ARMFrameLowering *TFI = getFrameLowering(MF);
     390             :   // We can't realign the stack if:
     391             :   // 1. Dynamic stack realignment is explicitly disabled,
     392             :   // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
     393             :   // 3. There are VLAs in the function and the base pointer is disabled.
     394       13444 :   if (!TargetRegisterInfo::canRealignStack(MF))
     395             :     return false;
     396             :   if (AFI->isThumb1OnlyFunction())
     397             :     return false;
     398             :   // Stack realignment requires a frame pointer.  If we already started
     399             :   // register allocation with frame pointer elimination, it is too late now.
     400       25138 :   if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>())))
     401             :     return false;
     402             :   // We may also need a base pointer if there are dynamic allocas or stack
     403             :   // pointer adjustments around calls.
     404       11475 :   if (TFI->hasReservedCallFrame(MF))
     405             :     return true;
     406             :   // A base pointer is required and allowed.  Check that it isn't too late to
     407             :   // reserve it.
     408         588 :   return MRI->canReserveReg(BasePtr);
     409             : }
     410             : 
     411        8187 : bool ARMBaseRegisterInfo::
     412             : cannotEliminateFrame(const MachineFunction &MF) const {
     413        8187 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
     414        8187 :   if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack())
     415             :     return true;
     416        8184 :   return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken()
     417       16349 :     || needsStackRealignment(MF);
     418             : }
     419             : 
     420             : unsigned
     421       44089 : ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
     422       44089 :   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
     423       44089 :   const ARMFrameLowering *TFI = getFrameLowering(MF);
     424             : 
     425       44089 :   if (TFI->hasFP(MF))
     426             :     return getFramePointerReg(STI);
     427             :   return ARM::SP;
     428             : }
     429             : 
     430             : /// emitLoadConstPool - Emits a load from constpool to materialize the
     431             : /// specified immediate.
     432           0 : void ARMBaseRegisterInfo::emitLoadConstPool(
     433             :     MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
     434             :     const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val,
     435             :     ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
     436           0 :   MachineFunction &MF = *MBB.getParent();
     437           0 :   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
     438           0 :   MachineConstantPool *ConstantPool = MF.getConstantPool();
     439             :   const Constant *C =
     440           0 :         ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
     441           0 :   unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
     442             : 
     443           0 :   BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
     444           0 :       .addReg(DestReg, getDefRegState(true), SubIdx)
     445           0 :       .addConstantPoolIndex(Idx)
     446           0 :       .addImm(0)
     447           0 :       .add(predOps(Pred, PredReg))
     448           0 :       .setMIFlags(MIFlags);
     449           0 : }
     450             : 
     451       33884 : bool ARMBaseRegisterInfo::
     452             : requiresRegisterScavenging(const MachineFunction &MF) const {
     453       33884 :   return true;
     454             : }
     455             : 
     456       21482 : bool ARMBaseRegisterInfo::
     457             : trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
     458       21482 :   return true;
     459             : }
     460             : 
     461       11976 : bool ARMBaseRegisterInfo::
     462             : requiresFrameIndexScavenging(const MachineFunction &MF) const {
     463       11976 :   return true;
     464             : }
     465             : 
     466       11973 : bool ARMBaseRegisterInfo::
     467             : requiresVirtualBaseRegisters(const MachineFunction &MF) const {
     468       11973 :   return true;
     469             : }
     470             : 
     471        5546 : int64_t ARMBaseRegisterInfo::
     472             : getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
     473        5546 :   const MCInstrDesc &Desc = MI->getDesc();
     474        5546 :   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
     475        5546 :   int64_t InstrOffs = 0;
     476        5546 :   int Scale = 1;
     477        5546 :   unsigned ImmIdx = 0;
     478        5546 :   switch (AddrMode) {
     479        4352 :   case ARMII::AddrModeT2_i8:
     480             :   case ARMII::AddrModeT2_i12:
     481             :   case ARMII::AddrMode_i12:
     482        8704 :     InstrOffs = MI->getOperand(Idx+1).getImm();
     483        4352 :     Scale = 1;
     484        4352 :     break;
     485         279 :   case ARMII::AddrMode5: {
     486             :     // VFP address mode.
     487         558 :     const MachineOperand &OffOp = MI->getOperand(Idx+1);
     488         279 :     InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
     489         279 :     if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
     490           0 :       InstrOffs = -InstrOffs;
     491             :     Scale = 4;
     492             :     break;
     493             :   }
     494           0 :   case ARMII::AddrMode2:
     495           0 :     ImmIdx = Idx+2;
     496           0 :     InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
     497           0 :     if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
     498           0 :       InstrOffs = -InstrOffs;
     499             :     break;
     500          50 :   case ARMII::AddrMode3:
     501          50 :     ImmIdx = Idx+2;
     502         100 :     InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
     503          50 :     if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
     504           0 :       InstrOffs = -InstrOffs;
     505             :     break;
     506         865 :   case ARMII::AddrModeT1_s:
     507         865 :     ImmIdx = Idx+1;
     508        1730 :     InstrOffs = MI->getOperand(ImmIdx).getImm();
     509         865 :     Scale = 4;
     510         865 :     break;
     511           0 :   default:
     512           0 :     llvm_unreachable("Unsupported addressing mode!");
     513             :   }
     514             : 
     515        5546 :   return InstrOffs * Scale;
     516             : }
     517             : 
     518             : /// needsFrameBaseReg - Returns true if the instruction's frame index
     519             : /// reference would be better served by a base register other than FP
     520             : /// or SP. Used by LocalStackFrameAllocation to determine which frame index
     521             : /// references it should create new base registers for.
     522        7207 : bool ARMBaseRegisterInfo::
     523             : needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
     524       36023 :   for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
     525             :     assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
     526             :   }
     527             : 
     528             :   // It's the load/store FI references that cause issues, as it can be difficult
     529             :   // to materialize the offset if it won't fit in the literal field. Estimate
     530             :   // based on the size of the local frame and some conservative assumptions
     531             :   // about the rest of the stack frame (note, this is pre-regalloc, so
     532             :   // we don't know everything for certain yet) whether this offset is likely
     533             :   // to be out of range of the immediate. Return true if so.
     534             : 
     535             :   // We only generate virtual base registers for loads and stores, so
     536             :   // return false for everything else.
     537       14414 :   unsigned Opc = MI->getOpcode();
     538        7207 :   switch (Opc) {
     539             :   case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
     540             :   case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
     541             :   case ARM::t2LDRi12: case ARM::t2LDRi8:
     542             :   case ARM::t2STRi12: case ARM::t2STRi8:
     543             :   case ARM::VLDRS: case ARM::VLDRD:
     544             :   case ARM::VSTRS: case ARM::VSTRD:
     545             :   case ARM::tSTRspi: case ARM::tLDRspi:
     546             :     break;
     547             :   default:
     548             :     return false;
     549             :   }
     550             : 
     551             :   // Without a virtual base register, if the function has variable sized
     552             :   // objects, all fixed-size local references will be via the frame pointer,
     553             :   // Approximate the offset and see if it's legal for the instruction.
     554             :   // Note that the incoming offset is based on the SP value at function entry,
     555             :   // so it'll be negative.
     556        5147 :   MachineFunction &MF = *MI->getParent()->getParent();
     557        5147 :   const ARMFrameLowering *TFI = getFrameLowering(MF);
     558        5147 :   MachineFrameInfo &MFI = MF.getFrameInfo();
     559        5147 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     560             : 
     561             :   // Estimate an offset from the frame pointer.
     562             :   // Conservatively assume all callee-saved registers get pushed. R4-R6
     563             :   // will be earlier than the FP, so we ignore those.
     564             :   // R7, LR
     565        5147 :   int64_t FPOffset = Offset - 8;
     566             :   // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
     567        5147 :   if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
     568        4392 :     FPOffset -= 80;
     569             :   // Estimate an offset from the stack pointer.
     570             :   // The incoming offset is relating to the SP at the start of the function,
     571             :   // but when we access the local it'll be relative to the SP after local
     572             :   // allocation, so adjust our SP-relative offset by that allocation size.
     573        5147 :   Offset += MFI.getLocalFrameSize();
     574             :   // Assume that we'll have at least some spill slots allocated.
     575             :   // FIXME: This is a total SWAG number. We should run some statistics
     576             :   //        and pick a real one.
     577        5147 :   Offset += 128; // 128 bytes of spill slots
     578             : 
     579             :   // If there's a frame pointer and the addressing mode allows it, try using it.
     580             :   // The FP is only available if there is no dynamic realignment. We
     581             :   // don't know for sure yet whether we'll need that, so we guess based
     582             :   // on whether there are any local variables that would trigger it.
     583        5147 :   unsigned StackAlign = TFI->getStackAlignment();
     584        5147 :   if (TFI->hasFP(MF) && 
     585         331 :       !((MFI.getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
     586        2764 :     if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset))
     587             :       return false;
     588             :   }
     589             :   // If we can reference via the stack pointer, try that.
     590             :   // FIXME: This (and the code that resolves the references) can be improved
     591             :   //        to only disallow SP relative references in the live range of
     592             :   //        the VLA(s). In practice, it's unclear how much difference that
     593             :   //        would make, but it may be worth doing.
     594        2710 :   if (!MFI.hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset))
     595             :     return false;
     596             : 
     597             :   // The offset likely isn't legal, we want to allocate a virtual base register.
     598             :   return true;
     599             : }
     600             : 
     601             : /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
     602             : /// be a pointer to FrameIdx at the beginning of the basic block.
     603           6 : void ARMBaseRegisterInfo::
     604             : materializeFrameBaseRegister(MachineBasicBlock *MBB,
     605             :                              unsigned BaseReg, int FrameIdx,
     606             :                              int64_t Offset) const {
     607           6 :   ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
     608           6 :   unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
     609          11 :     (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);
     610             : 
     611           6 :   MachineBasicBlock::iterator Ins = MBB->begin();
     612          12 :   DebugLoc DL;                  // Defaults to "unknown"
     613          12 :   if (Ins != MBB->end())
     614           6 :     DL = Ins->getDebugLoc();
     615             : 
     616           6 :   const MachineFunction &MF = *MBB->getParent();
     617           6 :   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
     618           6 :   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
     619          12 :   const MCInstrDesc &MCID = TII.get(ADDriOpc);
     620           6 :   MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
     621             : 
     622           6 :   MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
     623          12 :     .addFrameIndex(FrameIdx).addImm(Offset);
     624             : 
     625           6 :   if (!AFI->isThumb1OnlyFunction())
     626          10 :     MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
     627           6 : }
     628             : 
     629          30 : void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
     630             :                                             int64_t Offset) const {
     631          30 :   MachineBasicBlock &MBB = *MI.getParent();
     632          30 :   MachineFunction &MF = *MBB.getParent();
     633             :   const ARMBaseInstrInfo &TII =
     634          30 :       *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
     635          30 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     636          30 :   int Off = Offset; // ARM doesn't need the general 64-bit offsets
     637          30 :   unsigned i = 0;
     638             : 
     639             :   assert(!AFI->isThumb1OnlyFunction() &&
     640             :          "This resolveFrameIndex does not support Thumb1!");
     641             : 
     642         210 :   while (!MI.getOperand(i).isFI()) {
     643          30 :     ++i;
     644             :     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
     645             :   }
     646          30 :   bool Done = false;
     647          30 :   if (!AFI->isThumbFunction())
     648          15 :     Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
     649             :   else {
     650             :     assert(AFI->isThumb2Function());
     651          15 :     Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
     652             :   }
     653             :   assert(Done && "Unable to resolve frame index!");
     654             :   (void)Done;
     655          30 : }
     656             : 
     657        5514 : bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
     658             :                                              int64_t Offset) const {
     659        5514 :   const MCInstrDesc &Desc = MI->getDesc();
     660        5514 :   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
     661        5514 :   unsigned i = 0;
     662       33084 :   for (; !MI->getOperand(i).isFI(); ++i)
     663             :     assert(i+1 < MI->getNumOperands() && "Instr doesn't have FrameIndex operand!");
     664             : 
     665             :   // AddrMode4 and AddrMode6 cannot handle any offset.
     666        5514 :   if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
     667           0 :     return Offset == 0;
     668             : 
     669        5514 :   unsigned NumBits = 0;
     670        5514 :   unsigned Scale = 1;
     671        5514 :   bool isSigned = true;
     672        5514 :   switch (AddrMode) {
     673        1911 :   case ARMII::AddrModeT2_i8:
     674             :   case ARMII::AddrModeT2_i12:
     675             :     // i8 supports only negative, and i12 supports only positive, so
     676             :     // based on Offset sign, consider the appropriate instruction
     677        1911 :     Scale = 1;
     678        1911 :     if (Offset < 0) {
     679        1219 :       NumBits = 8;
     680        1219 :       Offset = -Offset;
     681             :     } else {
     682             :       NumBits = 12;
     683             :     }
     684             :     break;
     685             :   case ARMII::AddrMode5:
     686             :     // VFP address mode.
     687             :     NumBits = 8;
     688             :     Scale = 4;
     689             :     break;
     690        2434 :   case ARMII::AddrMode_i12:
     691             :   case ARMII::AddrMode2:
     692        2434 :     NumBits = 12;
     693        2434 :     break;
     694          50 :   case ARMII::AddrMode3:
     695          50 :     NumBits = 8;
     696          50 :     break;
     697         845 :   case ARMII::AddrModeT1_s:
     698         845 :     NumBits = (BaseReg == ARM::SP ? 8 : 5);
     699             :     Scale = 4;
     700             :     isSigned = false;
     701             :     break;
     702           0 :   default:
     703           0 :     llvm_unreachable("Unsupported addressing mode!");
     704             :   }
     705             : 
     706        5514 :   Offset += getFrameIndexInstrOffset(MI, i);
     707             :   // Make sure the offset is encodable for instructions that scale the
     708             :   // immediate.
     709        5514 :   if ((Offset & (Scale-1)) != 0)
     710             :     return false;
     711             : 
     712        5511 :   if (isSigned && Offset < 0)
     713        1465 :     Offset = -Offset;
     714             : 
     715        5511 :   unsigned Mask = (1 << NumBits) - 1;
     716        5511 :   if ((unsigned)Offset <= Mask * Scale)
     717             :     return true;
     718             : 
     719         390 :   return false;
     720             : }
     721             : 
     722             : void
     723       12853 : ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
     724             :                                          int SPAdj, unsigned FIOperandNum,
     725             :                                          RegScavenger *RS) const {
     726       12853 :   MachineInstr &MI = *II;
     727       12853 :   MachineBasicBlock &MBB = *MI.getParent();
     728       12853 :   MachineFunction &MF = *MBB.getParent();
     729             :   const ARMBaseInstrInfo &TII =
     730       12853 :       *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
     731       12853 :   const ARMFrameLowering *TFI = getFrameLowering(MF);
     732       12853 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     733             :   assert(!AFI->isThumb1OnlyFunction() &&
     734             :          "This eliminateFrameIndex does not support Thumb1!");
     735       25706 :   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
     736             :   unsigned FrameReg;
     737             : 
     738       12853 :   int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
     739             : 
     740             :   // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
     741             :   // call frame setup/destroy instructions have already been eliminated.  That
     742             :   // means the stack pointer cannot be used to access the emergency spill slot
     743             :   // when !hasReservedCallFrame().
     744             : #ifndef NDEBUG
     745             :   if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
     746             :     assert(TFI->hasReservedCallFrame(MF) &&
     747             :            "Cannot use SP to access the emergency spill slot in "
     748             :            "functions without a reserved call frame");
     749             :     assert(!MF.getFrameInfo().hasVarSizedObjects() &&
     750             :            "Cannot use SP to access the emergency spill slot in "
     751             :            "functions with variable sized frame objects");
     752             :   }
     753             : #endif // NDEBUG
     754             : 
     755             :   assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
     756             : 
     757             :   // Modify MI as necessary to handle as much of 'Offset' as possible
     758       12853 :   bool Done = false;
     759       12853 :   if (!AFI->isThumbFunction())
     760        7741 :     Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
     761             :   else {
     762             :     assert(AFI->isThumb2Function());
     763        5112 :     Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
     764             :   }
     765       12853 :   if (Done)
     766       11395 :     return;
     767             : 
     768             :   // If we get here, the immediate doesn't fit into the instruction.  We folded
     769             :   // as much as possible above, handle the rest, providing a register that is
     770             :   // SP+LargeImm.
     771             :   assert((Offset ||
     772             :           (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
     773             :           (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
     774             :          "This code isn't needed if offset already handled!");
     775             : 
     776        1458 :   unsigned ScratchReg = 0;
     777        1458 :   int PIdx = MI.findFirstPredOperandIdx();
     778             :   ARMCC::CondCodes Pred = (PIdx == -1)
     779        2916 :     ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
     780        2916 :   unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
     781        1458 :   if (Offset == 0)
     782             :     // Must be addrmode4/6.
     783          48 :     MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
     784             :   else {
     785        1434 :     ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
     786        1434 :     if (!AFI->isThumbFunction())
     787         768 :       emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
     788             :                               Offset, Pred, PredReg, TII);
     789             :     else {
     790             :       assert(AFI->isThumb2Function());
     791        2100 :       emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
     792             :                              Offset, Pred, PredReg, TII);
     793             :     }
     794             :     // Update the original instruction to use the scratch register.
     795        2868 :     MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
     796             :   }
     797             : }
     798             : 
     799       20045 : bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI,
     800             :                                   const TargetRegisterClass *SrcRC,
     801             :                                   unsigned SubReg,
     802             :                                   const TargetRegisterClass *DstRC,
     803             :                                   unsigned DstSubReg,
     804             :                                   const TargetRegisterClass *NewRC) const {
     805       20045 :   auto MBB = MI->getParent();
     806       20045 :   auto MF = MBB->getParent();
     807       20045 :   const MachineRegisterInfo &MRI = MF->getRegInfo();
     808             :   // If not copying into a sub-register this should be ok because we shouldn't
     809             :   // need to split the reg.
     810       20045 :   if (!DstSubReg)
     811             :     return true;
     812             :   // Small registers don't frequently cause a problem, so we can coalesce them.
     813       12570 :   if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 &&
     814        2984 :       getRegSizeInBits(*SrcRC) < 256)
     815             :     return true;
     816             : 
     817             :   auto NewRCWeight =
     818         317 :               MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC);
     819             :   auto SrcRCWeight =
     820         317 :               MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC);
     821             :   auto DstRCWeight =
     822         317 :               MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
     823             :   // If the source register class is more expensive than the destination, the
     824             :   // coalescing is probably profitable.
     825         317 :   if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
     826             :     return true;
     827         317 :   if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
     828             :     return true;
     829             : 
     830             :   // If the register allocator isn't constrained, we can always allow coalescing
     831             :   // unfortunately we don't know yet if we will be constrained.
     832             :   // The goal of this heuristic is to restrict how many expensive registers
     833             :   // we allow to coalesce in a given basic block.
     834         317 :   auto AFI = MF->getInfo<ARMFunctionInfo>();
     835         317 :   auto It = AFI->getCoalescedWeight(MBB);
     836             : 
     837             :   DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
     838             :     << It->second << "\n");
     839             :   DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
     840             :     << NewRCWeight.RegWeight << "\n");
     841             : 
     842             :   // This number is the largest round number that which meets the criteria:
     843             :   //  (1) addresses PR18825
     844             :   //  (2) generates better code in some test cases (like vldm-shed-a9.ll)
     845             :   //  (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
     846             :   // In practice the SizeMultiplier will only factor in for straight line code
     847             :   // that uses a lot of NEON vectors, which isn't terribly common.
     848         317 :   unsigned SizeMultiplier = MBB->size()/100;
     849         317 :   SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
     850         317 :   if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
     851         295 :     It->second += NewRCWeight.RegWeight;
     852         295 :     return true;
     853             :   }
     854             :   return false;
     855      216918 : }

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