LCOV - code coverage report
Current view: top level - lib/Target/ARM - ARMBaseRegisterInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 272 295 92.2 %
Date: 2018-07-13 00:08:38 Functions: 31 32 96.9 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains the base ARM implementation of TargetRegisterInfo class.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "ARMBaseRegisterInfo.h"
      15             : #include "ARM.h"
      16             : #include "ARMBaseInstrInfo.h"
      17             : #include "ARMFrameLowering.h"
      18             : #include "ARMMachineFunctionInfo.h"
      19             : #include "ARMSubtarget.h"
      20             : #include "MCTargetDesc/ARMAddressingModes.h"
      21             : #include "MCTargetDesc/ARMBaseInfo.h"
      22             : #include "llvm/ADT/BitVector.h"
      23             : #include "llvm/ADT/STLExtras.h"
      24             : #include "llvm/ADT/SmallVector.h"
      25             : #include "llvm/CodeGen/MachineBasicBlock.h"
      26             : #include "llvm/CodeGen/MachineConstantPool.h"
      27             : #include "llvm/CodeGen/MachineFrameInfo.h"
      28             : #include "llvm/CodeGen/MachineFunction.h"
      29             : #include "llvm/CodeGen/MachineInstr.h"
      30             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      31             : #include "llvm/CodeGen/MachineOperand.h"
      32             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      33             : #include "llvm/CodeGen/RegisterScavenging.h"
      34             : #include "llvm/CodeGen/TargetInstrInfo.h"
      35             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      36             : #include "llvm/CodeGen/VirtRegMap.h"
      37             : #include "llvm/IR/Attributes.h"
      38             : #include "llvm/IR/Constants.h"
      39             : #include "llvm/IR/DebugLoc.h"
      40             : #include "llvm/IR/Function.h"
      41             : #include "llvm/IR/Type.h"
      42             : #include "llvm/MC/MCInstrDesc.h"
      43             : #include "llvm/Support/Debug.h"
      44             : #include "llvm/Support/ErrorHandling.h"
      45             : #include "llvm/Support/raw_ostream.h"
      46             : #include "llvm/Target/TargetMachine.h"
      47             : #include "llvm/Target/TargetOptions.h"
      48             : #include <cassert>
      49             : #include <utility>
      50             : 
      51             : #define DEBUG_TYPE "arm-register-info"
      52             : 
      53             : #define GET_REGINFO_TARGET_DESC
      54             : #include "ARMGenRegisterInfo.inc"
      55             : 
      56             : using namespace llvm;
      57             : 
      58        4835 : ARMBaseRegisterInfo::ARMBaseRegisterInfo()
      59        4835 :     : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {}
      60             : 
      61             : static unsigned getFramePointerReg(const ARMSubtarget &STI) {
      62             :   return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
      63             : }
      64             : 
      65             : const MCPhysReg*
      66      191688 : ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
      67      191688 :   const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
      68      191688 :   bool UseSplitPush = STI.splitFramePushPop(*MF);
      69             :   const MCPhysReg *RegList =
      70             :       STI.isTargetDarwin()
      71      154040 :           ? CSR_iOS_SaveList
      72             :           : (UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList);
      73             : 
      74      191688 :   const Function &F = MF->getFunction();
      75      191688 :   if (F.getCallingConv() == CallingConv::GHC) {
      76             :     // GHC set of callee saved regs is empty as all those regs are
      77             :     // used for passing STG regs around
      78             :     return CSR_NoRegs_SaveList;
      79      191668 :   } else if (F.hasFnAttribute("interrupt")) {
      80         198 :     if (STI.isMClass()) {
      81             :       // M-class CPUs have hardware which saves the registers needed to allow a
      82             :       // function conforming to the AAPCS to function as a handler.
      83          66 :       return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList;
      84         198 :     } else if (F.getFnAttribute("interrupt").getValueAsString() == "FIQ") {
      85             :       // Fast interrupt mode gives the handler a private copy of R8-R14, so less
      86             :       // need to be saved to restore user-mode state.
      87             :       return CSR_FIQ_SaveList;
      88             :     } else {
      89             :       // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
      90             :       // exception handling.
      91             :       return CSR_GenericInt_SaveList;
      92             :     }
      93             :   }
      94             : 
      95      382940 :   if (STI.getTargetLowering()->supportSwiftError() &&
      96      382940 :       F.getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
      97             :     if (STI.isTargetDarwin())
      98             :       return CSR_iOS_SwiftError_SaveList;
      99             : 
     100             :     return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList :
     101         435 :       CSR_AAPCS_SwiftError_SaveList;
     102             :   }
     103             : 
     104       37055 :   if (STI.isTargetDarwin() && F.getCallingConv() == CallingConv::CXX_FAST_TLS)
     105         341 :     return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
     106         341 :                ? CSR_iOS_CXX_TLS_PE_SaveList
     107             :                : CSR_iOS_CXX_TLS_SaveList;
     108             :   return RegList;
     109             : }
     110             : 
     111       12610 : const MCPhysReg *ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy(
     112             :     const MachineFunction *MF) const {
     113             :   assert(MF && "Invalid MachineFunction pointer.");
     114       25266 :   if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
     115          46 :       MF->getInfo<ARMFunctionInfo>()->isSplitCSR())
     116             :     return CSR_iOS_CXX_TLS_ViaCopy_SaveList;
     117             :   return nullptr;
     118             : }
     119             : 
     120             : const uint32_t *
     121        8358 : ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
     122             :                                           CallingConv::ID CC) const {
     123        8358 :   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
     124        8358 :   if (CC == CallingConv::GHC)
     125             :     // This is academic because all GHC calls are (supposed to be) tail calls
     126             :     return CSR_NoRegs_RegMask;
     127             : 
     128       16712 :   if (STI.getTargetLowering()->supportSwiftError() &&
     129       16712 :       MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
     130             :     return STI.isTargetDarwin() ? CSR_iOS_SwiftError_RegMask
     131             :                                 : CSR_AAPCS_SwiftError_RegMask;
     132             : 
     133        2989 :   if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS)
     134             :     return CSR_iOS_CXX_TLS_RegMask;
     135             :   return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
     136             : }
     137             : 
     138             : const uint32_t*
     139           1 : ARMBaseRegisterInfo::getNoPreservedMask() const {
     140           1 :   return CSR_NoRegs_RegMask;
     141             : }
     142             : 
     143             : const uint32_t *
     144          79 : ARMBaseRegisterInfo::getTLSCallPreservedMask(const MachineFunction &MF) const {
     145             :   assert(MF.getSubtarget<ARMSubtarget>().isTargetDarwin() &&
     146             :          "only know about special TLS call on Darwin");
     147          79 :   return CSR_iOS_TLSCall_RegMask;
     148             : }
     149             : 
     150             : const uint32_t *
     151          32 : ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(const MachineFunction &MF) const {
     152          32 :   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
     153          32 :   if (!STI.useSoftFloat() && STI.hasVFP2() && !STI.isThumb1Only())
     154             :     return CSR_NoRegs_RegMask;
     155             :   else
     156             :     return CSR_FPRegs_RegMask;
     157             : }
     158             : 
     159             : const uint32_t *
     160          52 : ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
     161             :                                                 CallingConv::ID CC) const {
     162          52 :   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
     163             :   // This should return a register mask that is the same as that returned by
     164             :   // getCallPreservedMask but that additionally preserves the register used for
     165             :   // the first i32 argument (which must also be the register used to return a
     166             :   // single i32 return value)
     167             :   //
     168             :   // In case that the calling convention does not use the same register for
     169             :   // both or otherwise does not want to enable this optimization, the function
     170             :   // should return NULL
     171          52 :   if (CC == CallingConv::GHC)
     172             :     // This is academic because all GHC calls are (supposed to be) tail calls
     173             :     return nullptr;
     174             :   return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
     175             :                               : CSR_AAPCS_ThisReturn_RegMask;
     176             : }
     177             : 
     178       28707 : BitVector ARMBaseRegisterInfo::
     179             : getReservedRegs(const MachineFunction &MF) const {
     180       28707 :   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
     181       28707 :   const ARMFrameLowering *TFI = getFrameLowering(MF);
     182             : 
     183             :   // FIXME: avoid re-calculating this every time.
     184       28707 :   BitVector Reserved(getNumRegs());
     185       28707 :   markSuperRegs(Reserved, ARM::SP);
     186       28707 :   markSuperRegs(Reserved, ARM::PC);
     187       28707 :   markSuperRegs(Reserved, ARM::FPSCR);
     188       28707 :   markSuperRegs(Reserved, ARM::APSR_NZCV);
     189       28707 :   if (TFI->hasFP(MF))
     190        3880 :     markSuperRegs(Reserved, getFramePointerReg(STI));
     191       28707 :   if (hasBasePointer(MF))
     192          78 :     markSuperRegs(Reserved, BasePtr);
     193             :   // Some targets reserve R9.
     194       23442 :   if (STI.isR9Reserved())
     195        1119 :     markSuperRegs(Reserved, ARM::R9);
     196             :   // Reserve D16-D31 if the subtarget doesn't support them.
     197       28707 :   if (!STI.hasVFP3() || STI.hasD16()) {
     198             :     static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
     199      378708 :     for (unsigned R = 0; R < 16; ++R)
     200      183616 :       markSuperRegs(Reserved, ARM::D16 + R);
     201             :   }
     202             :   const TargetRegisterClass &RC = ARM::GPRPairRegClass;
     203      430605 :   for (unsigned Reg : RC)
     204      602847 :     for (MCSubRegIterator SI(Reg, this); SI.isValid(); ++SI)
     205      401898 :       if (Reserved.test(*SI))
     206       33784 :         markSuperRegs(Reserved, Reg);
     207             : 
     208             :   assert(checkAllSuperRegsMarked(Reserved));
     209       28707 :   return Reserved;
     210             : }
     211             : 
     212             : const TargetRegisterClass *
     213       14721 : ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
     214             :                                                const MachineFunction &) const {
     215             :   const TargetRegisterClass *Super = RC;
     216       14721 :   TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
     217             :   do {
     218       41344 :     switch (Super->getID()) {
     219             :     case ARM::GPRRegClassID:
     220             :     case ARM::SPRRegClassID:
     221             :     case ARM::DPRRegClassID:
     222             :     case ARM::QPRRegClassID:
     223             :     case ARM::QQPRRegClassID:
     224             :     case ARM::QQQQPRRegClassID:
     225             :     case ARM::GPRPairRegClassID:
     226             :       return Super;
     227             :     }
     228        6662 :     Super = *I++;
     229        6662 :   } while (Super);
     230             :   return RC;
     231             : }
     232             : 
     233             : const TargetRegisterClass *
     234         186 : ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
     235             :                                                                          const {
     236         186 :   return &ARM::GPRRegClass;
     237             : }
     238             : 
     239             : const TargetRegisterClass *
     240           8 : ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
     241           8 :   if (RC == &ARM::CCRRegClass)
     242             :     return &ARM::rGPRRegClass;  // Can't copy CCR registers.
     243           0 :   return RC;
     244             : }
     245             : 
     246             : unsigned
     247     1085105 : ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
     248             :                                          MachineFunction &MF) const {
     249     1085105 :   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
     250     1085105 :   const ARMFrameLowering *TFI = getFrameLowering(MF);
     251             : 
     252     2170210 :   switch (RC->getID()) {
     253             :   default:
     254             :     return 0;
     255       10535 :   case ARM::tGPRRegClassID: {
     256             :     // hasFP ends up calling getMaxCallFrameComputed() which may not be
     257             :     // available when getPressureLimit() is called as part of
     258             :     // ScheduleDAGRRList.
     259       10535 :     bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
     260       10535 :                  ? TFI->hasFP(MF) : true;
     261       10535 :     return 5 - HasFP;
     262             :   }
     263       10535 :   case ARM::GPRRegClassID: {
     264       10535 :     bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
     265       10535 :                  ? TFI->hasFP(MF) : true;
     266       18512 :     return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0);
     267             :   }
     268       21070 :   case ARM::SPRRegClassID:  // Currently not used as 'rep' register class.
     269             :   case ARM::DPRRegClassID:
     270       21070 :     return 32 - 10;
     271             :   }
     272             : }
     273             : 
     274             : // Get the other register in a GPRPair.
     275        1158 : static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
     276        1158 :   for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
     277         990 :     if (ARM::GPRPairRegClass.contains(*Supers))
     278         990 :       return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
     279         168 :   return 0;
     280             : }
     281             : 
     282             : // Resolve the RegPairEven / RegPairOdd register allocator hints.
     283             : bool
     284       89878 : ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
     285             :                                            ArrayRef<MCPhysReg> Order,
     286             :                                            SmallVectorImpl<MCPhysReg> &Hints,
     287             :                                            const MachineFunction &MF,
     288             :                                            const VirtRegMap *VRM,
     289             :                                            const LiveRegMatrix *Matrix) const {
     290       89878 :   const MachineRegisterInfo &MRI = MF.getRegInfo();
     291             :   std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
     292             : 
     293             :   unsigned Odd;
     294       89878 :   switch (Hint.first) {
     295             :   case ARMRI::RegPairEven:
     296             :     Odd = 0;
     297             :     break;
     298          92 :   case ARMRI::RegPairOdd:
     299             :     Odd = 1;
     300          92 :     break;
     301       89698 :   default:
     302       89698 :     TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
     303       89698 :     return false;
     304             :   }
     305             : 
     306             :   // This register should preferably be even (Odd == 0) or odd (Odd == 1).
     307             :   // Check if the other part of the pair has already been assigned, and provide
     308             :   // the paired register as the first hint.
     309             :   unsigned Paired = Hint.second;
     310         180 :   if (Paired == 0)
     311             :     return false;
     312             : 
     313         180 :   unsigned PairedPhys = 0;
     314         180 :   if (TargetRegisterInfo::isPhysicalRegister(Paired)) {
     315           0 :     PairedPhys = Paired;
     316         360 :   } else if (VRM && VRM->hasPhys(Paired)) {
     317          67 :     PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
     318             :   }
     319             : 
     320             :   // First prefer the paired physreg.
     321         247 :   if (PairedPhys && is_contained(Order, PairedPhys))
     322          67 :     Hints.push_back(PairedPhys);
     323             : 
     324             :   // Then prefer even or odd registers.
     325        4776 :   for (unsigned Reg : Order) {
     326        5736 :     if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
     327        1207 :       continue;
     328             :     // Don't provide hints that are paired to a reserved register.
     329        1091 :     unsigned Paired = getPairedGPR(Reg, !Odd, this);
     330        2270 :     if (!Paired || MRI.isReserved(Paired))
     331         256 :       continue;
     332         835 :     Hints.push_back(Reg);
     333             :   }
     334             :   return false;
     335             : }
     336             : 
     337             : void
     338       20070 : ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg,
     339             :                                         MachineFunction &MF) const {
     340       20070 :   MachineRegisterInfo *MRI = &MF.getRegInfo();
     341             :   std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
     342       20070 :   if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
     343       20116 :        Hint.first == (unsigned)ARMRI::RegPairEven) &&
     344             :       TargetRegisterInfo::isVirtualRegister(Hint.second)) {
     345             :     // If 'Reg' is one of the even / odd register pair and it's now changed
     346             :     // (e.g. coalesced) into a different register. The other register of the
     347             :     // pair allocation hint must be updated to reflect the relationship
     348             :     // change.
     349             :     unsigned OtherReg = Hint.second;
     350             :     Hint = MRI->getRegAllocationHint(OtherReg);
     351             :     // Make sure the pair has not already divorced.
     352          46 :     if (Hint.second == Reg) {
     353             :       MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
     354          46 :       if (TargetRegisterInfo::isVirtualRegister(NewReg))
     355          46 :         MRI->setRegAllocationHint(NewReg,
     356             :             Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven
     357             :             : ARMRI::RegPairOdd, OtherReg);
     358             :     }
     359             :   }
     360       20070 : }
     361             : 
     362       53432 : bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
     363       53432 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
     364             :   const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     365       53432 :   const ARMFrameLowering *TFI = getFrameLowering(MF);
     366             : 
     367             :   // When outgoing call frames are so large that we adjust the stack pointer
     368             :   // around the call, we can no longer use the stack pointer to reach the
     369             :   // emergency spill slot.
     370       53432 :   if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
     371             :     return true;
     372             : 
     373             :   // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
     374             :   // negative range for ldr/str (255), and thumb1 is positive offsets only.
     375             :   // It's going to be better to use the SP or Base Pointer instead. When there
     376             :   // are variable sized objects, we can't reference off of the SP, so we
     377             :   // reserve a Base Pointer.
     378       53404 :   if (AFI->isThumbFunction() && MFI.hasVarSizedObjects()) {
     379             :     // Conservatively estimate whether the negative offset from the frame
     380             :     // pointer will be sufficient to reach. If a function has a smallish
     381             :     // frame, it's less likely to have lots of spills and callee saved
     382             :     // space, so it's all more likely to be within range of the frame pointer.
     383             :     // If it's wrong, the scavenger will still enable access to work, it just
     384             :     // won't be optimal.
     385          68 :     if (AFI->isThumb2Function() && MFI.getLocalFrameSize() < 128)
     386             :       return false;
     387             :     return true;
     388             :   }
     389             : 
     390             :   return false;
     391             : }
     392             : 
     393       14482 : bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
     394       14482 :   const MachineRegisterInfo *MRI = &MF.getRegInfo();
     395       14482 :   const ARMFrameLowering *TFI = getFrameLowering(MF);
     396             :   // We can't realign the stack if:
     397             :   // 1. Dynamic stack realignment is explicitly disabled,
     398             :   // 2. There are VLAs in the function and the base pointer is disabled.
     399       14482 :   if (!TargetRegisterInfo::canRealignStack(MF))
     400             :     return false;
     401             :   // Stack realignment requires a frame pointer.  If we already started
     402             :   // register allocation with frame pointer elimination, it is too late now.
     403       14481 :   if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>())))
     404             :     return false;
     405             :   // We may also need a base pointer if there are dynamic allocas or stack
     406             :   // pointer adjustments around calls.
     407       13363 :   if (TFI->hasReservedCallFrame(MF))
     408             :     return true;
     409             :   // A base pointer is required and allowed.  Check that it isn't too late to
     410             :   // reserve it.
     411         648 :   return MRI->canReserveReg(BasePtr);
     412             : }
     413             : 
     414        9622 : bool ARMBaseRegisterInfo::
     415             : cannotEliminateFrame(const MachineFunction &MF) const {
     416        9622 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
     417        9622 :   if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack())
     418             :     return true;
     419       19238 :   return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken()
     420       19219 :     || needsStackRealignment(MF);
     421             : }
     422             : 
     423             : unsigned
     424       50341 : ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
     425       50341 :   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
     426       50341 :   const ARMFrameLowering *TFI = getFrameLowering(MF);
     427             : 
     428       50341 :   if (TFI->hasFP(MF))
     429             :     return getFramePointerReg(STI);
     430             :   return ARM::SP;
     431             : }
     432             : 
     433             : /// emitLoadConstPool - Emits a load from constpool to materialize the
     434             : /// specified immediate.
     435           0 : void ARMBaseRegisterInfo::emitLoadConstPool(
     436             :     MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
     437             :     const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val,
     438             :     ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
     439           0 :   MachineFunction &MF = *MBB.getParent();
     440           0 :   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
     441           0 :   MachineConstantPool *ConstantPool = MF.getConstantPool();
     442             :   const Constant *C =
     443           0 :         ConstantInt::get(Type::getInt32Ty(MF.getFunction().getContext()), Val);
     444           0 :   unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
     445             : 
     446           0 :   BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
     447           0 :       .addReg(DestReg, getDefRegState(true), SubIdx)
     448             :       .addConstantPoolIndex(Idx)
     449             :       .addImm(0)
     450           0 :       .add(predOps(Pred, PredReg))
     451             :       .setMIFlags(MIFlags);
     452           0 : }
     453             : 
     454       38885 : bool ARMBaseRegisterInfo::
     455             : requiresRegisterScavenging(const MachineFunction &MF) const {
     456       38885 :   return true;
     457             : }
     458             : 
     459       24686 : bool ARMBaseRegisterInfo::
     460             : trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
     461       24686 :   return true;
     462             : }
     463             : 
     464       13741 : bool ARMBaseRegisterInfo::
     465             : requiresFrameIndexScavenging(const MachineFunction &MF) const {
     466       13741 :   return true;
     467             : }
     468             : 
     469       13734 : bool ARMBaseRegisterInfo::
     470             : requiresVirtualBaseRegisters(const MachineFunction &MF) const {
     471       13734 :   return true;
     472             : }
     473             : 
     474        5715 : int64_t ARMBaseRegisterInfo::
     475             : getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
     476        5715 :   const MCInstrDesc &Desc = MI->getDesc();
     477        5715 :   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
     478             :   int64_t InstrOffs = 0;
     479             :   int Scale = 1;
     480             :   unsigned ImmIdx = 0;
     481        5715 :   switch (AddrMode) {
     482        4486 :   case ARMII::AddrModeT2_i8:
     483             :   case ARMII::AddrModeT2_i12:
     484             :   case ARMII::AddrMode_i12:
     485        8972 :     InstrOffs = MI->getOperand(Idx+1).getImm();
     486             :     Scale = 1;
     487        4486 :     break;
     488         281 :   case ARMII::AddrMode5: {
     489             :     // VFP address mode.
     490         281 :     const MachineOperand &OffOp = MI->getOperand(Idx+1);
     491         281 :     InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
     492             :     if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
     493           0 :       InstrOffs = -InstrOffs;
     494             :     Scale = 4;
     495             :     break;
     496             :   }
     497           0 :   case ARMII::AddrMode2:
     498           0 :     ImmIdx = Idx+2;
     499           0 :     InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
     500             :     if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
     501           0 :       InstrOffs = -InstrOffs;
     502             :     break;
     503          59 :   case ARMII::AddrMode3:
     504          59 :     ImmIdx = Idx+2;
     505         118 :     InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
     506             :     if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
     507           0 :       InstrOffs = -InstrOffs;
     508             :     break;
     509         889 :   case ARMII::AddrModeT1_s:
     510         889 :     ImmIdx = Idx+1;
     511        1778 :     InstrOffs = MI->getOperand(ImmIdx).getImm();
     512             :     Scale = 4;
     513         889 :     break;
     514           0 :   default:
     515           0 :     llvm_unreachable("Unsupported addressing mode!");
     516             :   }
     517             : 
     518        5715 :   return InstrOffs * Scale;
     519             : }
     520             : 
     521             : /// needsFrameBaseReg - Returns true if the instruction's frame index
     522             : /// reference would be better served by a base register other than FP
     523             : /// or SP. Used by LocalStackFrameAllocation to determine which frame index
     524             : /// references it should create new base registers for.
     525        7477 : bool ARMBaseRegisterInfo::
     526             : needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
     527       29896 :   for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
     528             :     assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
     529             :   }
     530             : 
     531             :   // It's the load/store FI references that cause issues, as it can be difficult
     532             :   // to materialize the offset if it won't fit in the literal field. Estimate
     533             :   // based on the size of the local frame and some conservative assumptions
     534             :   // about the rest of the stack frame (note, this is pre-regalloc, so
     535             :   // we don't know everything for certain yet) whether this offset is likely
     536             :   // to be out of range of the immediate. Return true if so.
     537             : 
     538             :   // We only generate virtual base registers for loads and stores, so
     539             :   // return false for everything else.
     540        7477 :   unsigned Opc = MI->getOpcode();
     541        7477 :   switch (Opc) {
     542             :   case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
     543             :   case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
     544             :   case ARM::t2LDRi12: case ARM::t2LDRi8:
     545             :   case ARM::t2STRi12: case ARM::t2STRi8:
     546             :   case ARM::VLDRS: case ARM::VLDRD:
     547             :   case ARM::VSTRS: case ARM::VSTRD:
     548             :   case ARM::tSTRspi: case ARM::tLDRspi:
     549             :     break;
     550             :   default:
     551             :     return false;
     552             :   }
     553             : 
     554             :   // Without a virtual base register, if the function has variable sized
     555             :   // objects, all fixed-size local references will be via the frame pointer,
     556             :   // Approximate the offset and see if it's legal for the instruction.
     557             :   // Note that the incoming offset is based on the SP value at function entry,
     558             :   // so it'll be negative.
     559        5315 :   MachineFunction &MF = *MI->getParent()->getParent();
     560        5315 :   const ARMFrameLowering *TFI = getFrameLowering(MF);
     561        5315 :   MachineFrameInfo &MFI = MF.getFrameInfo();
     562        5315 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     563             : 
     564             :   // Estimate an offset from the frame pointer.
     565             :   // Conservatively assume all callee-saved registers get pushed. R4-R6
     566             :   // will be earlier than the FP, so we ignore those.
     567             :   // R7, LR
     568        5315 :   int64_t FPOffset = Offset - 8;
     569             :   // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
     570        5315 :   if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
     571        4535 :     FPOffset -= 80;
     572             :   // Estimate an offset from the stack pointer.
     573             :   // The incoming offset is relating to the SP at the start of the function,
     574             :   // but when we access the local it'll be relative to the SP after local
     575             :   // allocation, so adjust our SP-relative offset by that allocation size.
     576        5315 :   Offset += MFI.getLocalFrameSize();
     577             :   // Assume that we'll have at least some spill slots allocated.
     578             :   // FIXME: This is a total SWAG number. We should run some statistics
     579             :   //        and pick a real one.
     580        5315 :   Offset += 128; // 128 bytes of spill slots
     581             : 
     582             :   // If there's a frame pointer and the addressing mode allows it, try using it.
     583             :   // The FP is only available if there is no dynamic realignment. We
     584             :   // don't know for sure yet whether we'll need that, so we guess based
     585             :   // on whether there are any local variables that would trigger it.
     586        5315 :   unsigned StackAlign = TFI->getStackAlignment();
     587        8615 :   if (TFI->hasFP(MF) && 
     588        3771 :       !((MFI.getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
     589        2829 :     if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset))
     590             :       return false;
     591             :   }
     592             :   // If we can reference via the stack pointer, try that.
     593             :   // FIXME: This (and the code that resolves the references) can be improved
     594             :   //        to only disallow SP relative references in the live range of
     595             :   //        the VLA(s). In practice, it's unclear how much difference that
     596             :   //        would make, but it may be worth doing.
     597        2813 :   if (!MFI.hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset))
     598             :     return false;
     599             : 
     600             :   // The offset likely isn't legal, we want to allocate a virtual base register.
     601             :   return true;
     602             : }
     603             : 
     604             : /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
     605             : /// be a pointer to FrameIdx at the beginning of the basic block.
     606           7 : void ARMBaseRegisterInfo::
     607             : materializeFrameBaseRegister(MachineBasicBlock *MBB,
     608             :                              unsigned BaseReg, int FrameIdx,
     609             :                              int64_t Offset) const {
     610           7 :   ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
     611           7 :   unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
     612             :     (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);
     613             : 
     614             :   MachineBasicBlock::iterator Ins = MBB->begin();
     615           7 :   DebugLoc DL;                  // Defaults to "unknown"
     616           7 :   if (Ins != MBB->end())
     617             :     DL = Ins->getDebugLoc();
     618             : 
     619           7 :   const MachineFunction &MF = *MBB->getParent();
     620           7 :   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
     621           7 :   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
     622           7 :   const MCInstrDesc &MCID = TII.get(ADDriOpc);
     623           7 :   MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
     624             : 
     625           7 :   MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
     626             :     .addFrameIndex(FrameIdx).addImm(Offset);
     627             : 
     628           7 :   if (!AFI->isThumb1OnlyFunction())
     629           2 :     MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
     630           7 : }
     631             : 
     632          30 : void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
     633             :                                             int64_t Offset) const {
     634          30 :   MachineBasicBlock &MBB = *MI.getParent();
     635          30 :   MachineFunction &MF = *MBB.getParent();
     636             :   const ARMBaseInstrInfo &TII =
     637          30 :       *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
     638          30 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     639          30 :   int Off = Offset; // ARM doesn't need the general 64-bit offsets
     640             :   unsigned i = 0;
     641             : 
     642             :   assert(!AFI->isThumb1OnlyFunction() &&
     643             :          "This resolveFrameIndex does not support Thumb1!");
     644             : 
     645         150 :   while (!MI.getOperand(i).isFI()) {
     646          30 :     ++i;
     647             :     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
     648             :   }
     649             :   bool Done = false;
     650          30 :   if (!AFI->isThumbFunction())
     651          15 :     Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
     652             :   else {
     653             :     assert(AFI->isThumb2Function());
     654          15 :     Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
     655             :   }
     656             :   assert(Done && "Unable to resolve frame index!");
     657             :   (void)Done;
     658          30 : }
     659             : 
     660        5681 : bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
     661             :                                              int64_t Offset) const {
     662        5681 :   const MCInstrDesc &Desc = MI->getDesc();
     663        5681 :   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
     664             :   unsigned i = 0;
     665       22724 :   for (; !MI->getOperand(i).isFI(); ++i)
     666             :     assert(i+1 < MI->getNumOperands() && "Instr doesn't have FrameIndex operand!");
     667             : 
     668             :   // AddrMode4 and AddrMode6 cannot handle any offset.
     669        5681 :   if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
     670           0 :     return Offset == 0;
     671             : 
     672             :   unsigned NumBits = 0;
     673             :   unsigned Scale = 1;
     674             :   bool isSigned = true;
     675        5681 :   switch (AddrMode) {
     676        1980 :   case ARMII::AddrModeT2_i8:
     677             :   case ARMII::AddrModeT2_i12:
     678             :     // i8 supports only negative, and i12 supports only positive, so
     679             :     // based on Offset sign, consider the appropriate instruction
     680             :     Scale = 1;
     681        1980 :     if (Offset < 0) {
     682             :       NumBits = 8;
     683        1264 :       Offset = -Offset;
     684             :     } else {
     685             :       NumBits = 12;
     686             :     }
     687             :     break;
     688             :   case ARMII::AddrMode5:
     689             :     // VFP address mode.
     690             :     NumBits = 8;
     691             :     Scale = 4;
     692             :     break;
     693        2499 :   case ARMII::AddrMode_i12:
     694             :   case ARMII::AddrMode2:
     695             :     NumBits = 12;
     696        2499 :     break;
     697          59 :   case ARMII::AddrMode3:
     698             :     NumBits = 8;
     699          59 :     break;
     700         867 :   case ARMII::AddrModeT1_s:
     701         867 :     NumBits = (BaseReg == ARM::SP ? 8 : 5);
     702             :     Scale = 4;
     703             :     isSigned = false;
     704             :     break;
     705           0 :   default:
     706           0 :     llvm_unreachable("Unsupported addressing mode!");
     707             :   }
     708             : 
     709        5681 :   Offset += getFrameIndexInstrOffset(MI, i);
     710             :   // Make sure the offset is encodable for instructions that scale the
     711             :   // immediate.
     712        5681 :   if ((Offset & (Scale-1)) != 0)
     713             :     return false;
     714             : 
     715        5678 :   if (isSigned && Offset < 0)
     716        1487 :     Offset = -Offset;
     717             : 
     718        5678 :   unsigned Mask = (1 << NumBits) - 1;
     719        5678 :   if ((unsigned)Offset <= Mask * Scale)
     720             :     return true;
     721             : 
     722         390 :   return false;
     723             : }
     724             : 
     725             : void
     726       13281 : ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
     727             :                                          int SPAdj, unsigned FIOperandNum,
     728             :                                          RegScavenger *RS) const {
     729             :   MachineInstr &MI = *II;
     730       13281 :   MachineBasicBlock &MBB = *MI.getParent();
     731       13281 :   MachineFunction &MF = *MBB.getParent();
     732             :   const ARMBaseInstrInfo &TII =
     733       13281 :       *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
     734       13281 :   const ARMFrameLowering *TFI = getFrameLowering(MF);
     735       13281 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     736             :   assert(!AFI->isThumb1OnlyFunction() &&
     737             :          "This eliminateFrameIndex does not support Thumb1!");
     738       26562 :   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
     739             :   unsigned FrameReg;
     740             : 
     741       13281 :   int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
     742             : 
     743             :   // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
     744             :   // call frame setup/destroy instructions have already been eliminated.  That
     745             :   // means the stack pointer cannot be used to access the emergency spill slot
     746             :   // when !hasReservedCallFrame().
     747             : #ifndef NDEBUG
     748             :   if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
     749             :     assert(TFI->hasReservedCallFrame(MF) &&
     750             :            "Cannot use SP to access the emergency spill slot in "
     751             :            "functions without a reserved call frame");
     752             :     assert(!MF.getFrameInfo().hasVarSizedObjects() &&
     753             :            "Cannot use SP to access the emergency spill slot in "
     754             :            "functions with variable sized frame objects");
     755             :   }
     756             : #endif // NDEBUG
     757             : 
     758             :   assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
     759             : 
     760             :   // Modify MI as necessary to handle as much of 'Offset' as possible
     761             :   bool Done = false;
     762       13281 :   if (!AFI->isThumbFunction())
     763        7929 :     Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
     764             :   else {
     765             :     assert(AFI->isThumb2Function());
     766        5352 :     Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
     767             :   }
     768       13281 :   if (Done)
     769       11732 :     return;
     770             : 
     771             :   // If we get here, the immediate doesn't fit into the instruction.  We folded
     772             :   // as much as possible above, handle the rest, providing a register that is
     773             :   // SP+LargeImm.
     774             :   assert((Offset ||
     775             :           (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
     776             :           (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
     777             :          "This code isn't needed if offset already handled!");
     778             : 
     779             :   unsigned ScratchReg = 0;
     780        1549 :   int PIdx = MI.findFirstPredOperandIdx();
     781             :   ARMCC::CondCodes Pred = (PIdx == -1)
     782        3098 :     ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
     783        3098 :   unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
     784        1549 :   if (Offset == 0)
     785             :     // Must be addrmode4/6.
     786          46 :     MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
     787             :   else {
     788        3052 :     ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
     789        1526 :     if (!AFI->isThumbFunction())
     790         768 :       emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
     791             :                               Offset, Pred, PredReg, TII);
     792             :     else {
     793             :       assert(AFI->isThumb2Function());
     794        2284 :       emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
     795             :                              Offset, Pred, PredReg, TII);
     796             :     }
     797             :     // Update the original instruction to use the scratch register.
     798        3052 :     MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
     799             :   }
     800             : }
     801             : 
     802       21479 : bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI,
     803             :                                   const TargetRegisterClass *SrcRC,
     804             :                                   unsigned SubReg,
     805             :                                   const TargetRegisterClass *DstRC,
     806             :                                   unsigned DstSubReg,
     807             :                                   const TargetRegisterClass *NewRC,
     808             :                                   LiveIntervals &LIS) const {
     809       21479 :   auto MBB = MI->getParent();
     810       21479 :   auto MF = MBB->getParent();
     811       21479 :   const MachineRegisterInfo &MRI = MF->getRegInfo();
     812             :   // If not copying into a sub-register this should be ok because we shouldn't
     813             :   // need to split the reg.
     814       21479 :   if (!DstSubReg)
     815             :     return true;
     816             :   // Small registers don't frequently cause a problem, so we can coalesce them.
     817        9562 :   if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 &&
     818             :       getRegSizeInBits(*SrcRC) < 256)
     819             :     return true;
     820             : 
     821             :   auto NewRCWeight =
     822         884 :               MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC);
     823             :   auto SrcRCWeight =
     824         884 :               MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC);
     825             :   auto DstRCWeight =
     826         884 :               MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
     827             :   // If the source register class is more expensive than the destination, the
     828             :   // coalescing is probably profitable.
     829         442 :   if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
     830             :     return true;
     831         442 :   if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
     832             :     return true;
     833             : 
     834             :   // If the register allocator isn't constrained, we can always allow coalescing
     835             :   // unfortunately we don't know yet if we will be constrained.
     836             :   // The goal of this heuristic is to restrict how many expensive registers
     837             :   // we allow to coalesce in a given basic block.
     838         442 :   auto AFI = MF->getInfo<ARMFunctionInfo>();
     839         442 :   auto It = AFI->getCoalescedWeight(MBB);
     840             : 
     841             :   LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
     842             :                     << It->second << "\n");
     843             :   LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
     844             :                     << NewRCWeight.RegWeight << "\n");
     845             : 
     846             :   // This number is the largest round number that which meets the criteria:
     847             :   //  (1) addresses PR18825
     848             :   //  (2) generates better code in some test cases (like vldm-shed-a9.ll)
     849             :   //  (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
     850             :   // In practice the SizeMultiplier will only factor in for straight line code
     851             :   // that uses a lot of NEON vectors, which isn't terribly common.
     852         442 :   unsigned SizeMultiplier = MBB->size()/100;
     853         442 :   SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
     854         442 :   if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
     855         422 :     It->second += NewRCWeight.RegWeight;
     856         422 :     return true;
     857             :   }
     858             :   return false;
     859             : }

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