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1 : //===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // This file contains the base ARM implementation of TargetRegisterInfo class.
11 : //
12 : //===----------------------------------------------------------------------===//
13 :
14 : #ifndef LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
15 : #define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
16 :
17 : #include "MCTargetDesc/ARMBaseInfo.h"
18 : #include "llvm/CodeGen/MachineBasicBlock.h"
19 : #include "llvm/CodeGen/MachineInstr.h"
20 : #include "llvm/CodeGen/TargetRegisterInfo.h"
21 : #include "llvm/IR/CallingConv.h"
22 : #include "llvm/MC/MCRegisterInfo.h"
23 : #include <cstdint>
24 :
25 : #define GET_REGINFO_HEADER
26 : #include "ARMGenRegisterInfo.inc"
27 :
28 : namespace llvm {
29 :
30 : class LiveIntervals;
31 :
32 : /// Register allocation hints.
33 : namespace ARMRI {
34 :
35 : enum {
36 : RegPairOdd = 1,
37 : RegPairEven = 2
38 : };
39 :
40 : } // end namespace ARMRI
41 :
42 : /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
43 : /// or a stack/pc register that we should push/pop.
44 23118 : static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
45 : using namespace ARM;
46 :
47 23118 : switch (Reg) {
48 : case R0: case R1: case R2: case R3:
49 : case R4: case R5: case R6: case R7:
50 : case LR: case SP: case PC:
51 : return true;
52 4319 : case R8: case R9: case R10: case R11: case R12:
53 : // For iOS we want r7 and lr to be next to each other.
54 4319 : return !isIOS;
55 2654 : default:
56 2654 : return false;
57 : }
58 : }
59 :
60 23118 : static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
61 : using namespace ARM;
62 :
63 23118 : switch (Reg) {
64 : case R8: case R9: case R10: case R11: case R12:
65 : // iOS has this second area.
66 : return isIOS;
67 18799 : default:
68 18799 : return false;
69 : }
70 : }
71 :
72 23172 : static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
73 : using namespace ARM;
74 :
75 23172 : switch (Reg) {
76 : case D15: case D14: case D13: case D12:
77 : case D11: case D10: case D9: case D8:
78 : case D7: case D6: case D5: case D4:
79 : case D3: case D2: case D1: case D0:
80 : case D31: case D30: case D29: case D28:
81 : case D27: case D26: case D25: case D24:
82 : case D23: case D22: case D21: case D20:
83 : case D19: case D18: case D17: case D16:
84 : return true;
85 20464 : default:
86 20464 : return false;
87 : }
88 : }
89 :
90 : static inline bool isCalleeSavedRegister(unsigned Reg,
91 : const MCPhysReg *CSRegs) {
92 2373 : for (unsigned i = 0; CSRegs[i]; ++i)
93 2256 : if (Reg == CSRegs[i])
94 : return true;
95 : return false;
96 : }
97 :
98 : class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
99 : protected:
100 : /// BasePtr - ARM physical register used as a base ptr in complex stack
101 : /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
102 : /// variable size stack objects.
103 : unsigned BasePtr = ARM::R6;
104 :
105 : // Can be only subclassed.
106 : explicit ARMBaseRegisterInfo();
107 :
108 : // Return the opcode that implements 'Op', or 0 if no opcode
109 : unsigned getOpcode(int Op) const;
110 :
111 : public:
112 : /// Code Generation virtual methods...
113 : const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
114 : const MCPhysReg *
115 : getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
116 : const uint32_t *getCallPreservedMask(const MachineFunction &MF,
117 : CallingConv::ID) const override;
118 : const uint32_t *getNoPreservedMask() const override;
119 : const uint32_t *getTLSCallPreservedMask(const MachineFunction &MF) const;
120 : const uint32_t *getSjLjDispatchPreservedMask(const MachineFunction &MF) const;
121 :
122 : /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
123 : /// case that 'returned' is on an i32 first argument if the calling convention
124 : /// is one that can (partially) model this attribute with a preserved mask
125 : /// (i.e. it is a calling convention that uses the same register for the first
126 : /// i32 argument and an i32 return value)
127 : ///
128 : /// Should return NULL in the case that the calling convention does not have
129 : /// this property
130 : const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
131 : CallingConv::ID) const;
132 :
133 : BitVector getReservedRegs(const MachineFunction &MF) const override;
134 : bool isAsmClobberable(const MachineFunction &MF,
135 : unsigned PhysReg) const override;
136 :
137 : const TargetRegisterClass *
138 : getPointerRegClass(const MachineFunction &MF,
139 : unsigned Kind = 0) const override;
140 : const TargetRegisterClass *
141 : getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
142 :
143 : const TargetRegisterClass *
144 : getLargestLegalSuperClass(const TargetRegisterClass *RC,
145 : const MachineFunction &MF) const override;
146 :
147 : unsigned getRegPressureLimit(const TargetRegisterClass *RC,
148 : MachineFunction &MF) const override;
149 :
150 : bool getRegAllocationHints(unsigned VirtReg,
151 : ArrayRef<MCPhysReg> Order,
152 : SmallVectorImpl<MCPhysReg> &Hints,
153 : const MachineFunction &MF,
154 : const VirtRegMap *VRM,
155 : const LiveRegMatrix *Matrix) const override;
156 :
157 : void updateRegAllocHint(unsigned Reg, unsigned NewReg,
158 : MachineFunction &MF) const override;
159 :
160 : bool hasBasePointer(const MachineFunction &MF) const;
161 :
162 : bool canRealignStack(const MachineFunction &MF) const override;
163 : int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
164 : int Idx) const override;
165 : bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
166 : void materializeFrameBaseRegister(MachineBasicBlock *MBB,
167 : unsigned BaseReg, int FrameIdx,
168 : int64_t Offset) const override;
169 : void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
170 : int64_t Offset) const override;
171 : bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
172 : int64_t Offset) const override;
173 :
174 : bool cannotEliminateFrame(const MachineFunction &MF) const;
175 :
176 : // Debug information queries.
177 : unsigned getFrameRegister(const MachineFunction &MF) const override;
178 0 : unsigned getBaseRegister() const { return BasePtr; }
179 :
180 : bool isLowRegister(unsigned Reg) const;
181 :
182 :
183 : /// emitLoadConstPool - Emits a load from constpool to materialize the
184 : /// specified immediate.
185 : virtual void
186 : emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
187 : const DebugLoc &dl, unsigned DestReg, unsigned SubIdx,
188 : int Val, ARMCC::CondCodes Pred = ARMCC::AL,
189 : unsigned PredReg = 0,
190 : unsigned MIFlags = MachineInstr::NoFlags) const;
191 :
192 : /// Code Generation virtual methods...
193 : bool requiresRegisterScavenging(const MachineFunction &MF) const override;
194 :
195 : bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
196 :
197 : bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
198 :
199 : bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
200 :
201 : void eliminateFrameIndex(MachineBasicBlock::iterator II,
202 : int SPAdj, unsigned FIOperandNum,
203 : RegScavenger *RS = nullptr) const override;
204 :
205 : /// SrcRC and DstRC will be morphed into NewRC if this returns true
206 : bool shouldCoalesce(MachineInstr *MI,
207 : const TargetRegisterClass *SrcRC,
208 : unsigned SubReg,
209 : const TargetRegisterClass *DstRC,
210 : unsigned DstSubReg,
211 : const TargetRegisterClass *NewRC,
212 : LiveIntervals &LIS) const override;
213 : };
214 :
215 : } // end namespace llvm
216 :
217 : #endif // LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
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