LCOV - code coverage report
Current view: top level - lib/Target/ARM - ARMFastISel.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 1353 1486 91.0 %
Date: 2017-09-14 15:23:50 Functions: 56 57 98.2 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file defines the ARM-specific support for the FastISel class. Some
      11             : // of the target-specific code is generated by tablegen in the file
      12             : // ARMGenFastISel.inc, which is #included here.
      13             : //
      14             : //===----------------------------------------------------------------------===//
      15             : 
      16             : #include "ARM.h"
      17             : #include "ARMBaseInstrInfo.h"
      18             : #include "ARMBaseRegisterInfo.h"
      19             : #include "ARMCallingConv.h"
      20             : #include "ARMConstantPoolValue.h"
      21             : #include "ARMISelLowering.h"
      22             : #include "ARMMachineFunctionInfo.h"
      23             : #include "ARMSubtarget.h"
      24             : #include "MCTargetDesc/ARMAddressingModes.h"
      25             : #include "MCTargetDesc/ARMBaseInfo.h"
      26             : #include "llvm/ADT/APFloat.h"
      27             : #include "llvm/ADT/APInt.h"
      28             : #include "llvm/ADT/DenseMap.h"
      29             : #include "llvm/ADT/STLExtras.h"
      30             : #include "llvm/ADT/SmallVector.h"
      31             : #include "llvm/CodeGen/CallingConvLower.h"
      32             : #include "llvm/CodeGen/FastISel.h"
      33             : #include "llvm/CodeGen/FunctionLoweringInfo.h"
      34             : #include "llvm/CodeGen/ISDOpcodes.h"
      35             : #include "llvm/CodeGen/MachineConstantPool.h"
      36             : #include "llvm/CodeGen/MachineFrameInfo.h"
      37             : #include "llvm/CodeGen/MachineInstr.h"
      38             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      39             : #include "llvm/CodeGen/MachineMemOperand.h"
      40             : #include "llvm/CodeGen/MachineOperand.h"
      41             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      42             : #include "llvm/CodeGen/MachineValueType.h"
      43             : #include "llvm/CodeGen/RuntimeLibcalls.h"
      44             : #include "llvm/CodeGen/ValueTypes.h"
      45             : #include "llvm/IR/Argument.h"
      46             : #include "llvm/IR/Attributes.h"
      47             : #include "llvm/IR/CallSite.h"
      48             : #include "llvm/IR/CallingConv.h"
      49             : #include "llvm/IR/Constant.h"
      50             : #include "llvm/IR/Constants.h"
      51             : #include "llvm/IR/DataLayout.h"
      52             : #include "llvm/IR/DerivedTypes.h"
      53             : #include "llvm/IR/Function.h"
      54             : #include "llvm/IR/GetElementPtrTypeIterator.h"
      55             : #include "llvm/IR/GlobalValue.h"
      56             : #include "llvm/IR/GlobalVariable.h"
      57             : #include "llvm/IR/InstrTypes.h"
      58             : #include "llvm/IR/Instruction.h"
      59             : #include "llvm/IR/Instructions.h"
      60             : #include "llvm/IR/IntrinsicInst.h"
      61             : #include "llvm/IR/Module.h"
      62             : #include "llvm/IR/Operator.h"
      63             : #include "llvm/IR/Type.h"
      64             : #include "llvm/IR/User.h"
      65             : #include "llvm/IR/Value.h"
      66             : #include "llvm/MC/MCInstrDesc.h"
      67             : #include "llvm/MC/MCRegisterInfo.h"
      68             : #include "llvm/Support/Casting.h"
      69             : #include "llvm/Support/Compiler.h"
      70             : #include "llvm/Support/ErrorHandling.h"
      71             : #include "llvm/Support/MathExtras.h"
      72             : #include "llvm/Target/TargetInstrInfo.h"
      73             : #include "llvm/Target/TargetLowering.h"
      74             : #include "llvm/Target/TargetMachine.h"
      75             : #include "llvm/Target/TargetOptions.h"
      76             : #include <cassert>
      77             : #include <cstdint>
      78             : #include <utility>
      79             : 
      80             : using namespace llvm;
      81             : 
      82             : namespace {
      83             : 
      84             :   // All possible address modes, plus some.
      85             :   typedef struct Address {
      86             :     enum {
      87             :       RegBase,
      88             :       FrameIndexBase
      89             :     } BaseType = RegBase;
      90             : 
      91             :     union {
      92             :       unsigned Reg;
      93             :       int FI;
      94             :     } Base;
      95             : 
      96             :     int Offset = 0;
      97             : 
      98             :     // Innocuous defaults for our address.
      99        1549 :     Address() {
     100         999 :       Base.Reg = 0;
     101             :     }
     102             :   } Address;
     103             : 
     104         901 : class ARMFastISel final : public FastISel {
     105             :   /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
     106             :   /// make the right decision when generating code for different targets.
     107             :   const ARMSubtarget *Subtarget;
     108             :   Module &M;
     109             :   const TargetMachine &TM;
     110             :   const TargetInstrInfo &TII;
     111             :   const TargetLowering &TLI;
     112             :   ARMFunctionInfo *AFI;
     113             : 
     114             :   // Convenience variables to avoid some queries.
     115             :   bool isThumb2;
     116             :   LLVMContext *Context;
     117             : 
     118             :   public:
     119         901 :     explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
     120             :                          const TargetLibraryInfo *libInfo)
     121         901 :         : FastISel(funcInfo, libInfo),
     122             :           Subtarget(
     123         901 :               &static_cast<const ARMSubtarget &>(funcInfo.MF->getSubtarget())),
     124         901 :           M(const_cast<Module &>(*funcInfo.Fn->getParent())),
     125        1802 :           TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()),
     126        4505 :           TLI(*Subtarget->getTargetLowering()) {
     127         901 :       AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
     128         901 :       isThumb2 = AFI->isThumbFunction();
     129         901 :       Context = &funcInfo.Fn->getContext();
     130         901 :     }
     131             : 
     132             :   private:
     133             :     // Code from FastISel.cpp.
     134             : 
     135             :     unsigned fastEmitInst_r(unsigned MachineInstOpcode,
     136             :                             const TargetRegisterClass *RC,
     137             :                             unsigned Op0, bool Op0IsKill);
     138             :     unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
     139             :                              const TargetRegisterClass *RC,
     140             :                              unsigned Op0, bool Op0IsKill,
     141             :                              unsigned Op1, bool Op1IsKill);
     142             :     unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
     143             :                              const TargetRegisterClass *RC,
     144             :                              unsigned Op0, bool Op0IsKill,
     145             :                              uint64_t Imm);
     146             :     unsigned fastEmitInst_i(unsigned MachineInstOpcode,
     147             :                             const TargetRegisterClass *RC,
     148             :                             uint64_t Imm);
     149             : 
     150             :     // Backend specific FastISel code.
     151             : 
     152             :     bool fastSelectInstruction(const Instruction *I) override;
     153             :     unsigned fastMaterializeConstant(const Constant *C) override;
     154             :     unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
     155             :     bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
     156             :                              const LoadInst *LI) override;
     157             :     bool fastLowerArguments() override;
     158             : 
     159             :   #include "ARMGenFastISel.inc"
     160             : 
     161             :     // Instruction selection routines.
     162             : 
     163             :     bool SelectLoad(const Instruction *I);
     164             :     bool SelectStore(const Instruction *I);
     165             :     bool SelectBranch(const Instruction *I);
     166             :     bool SelectIndirectBr(const Instruction *I);
     167             :     bool SelectCmp(const Instruction *I);
     168             :     bool SelectFPExt(const Instruction *I);
     169             :     bool SelectFPTrunc(const Instruction *I);
     170             :     bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
     171             :     bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
     172             :     bool SelectIToFP(const Instruction *I, bool isSigned);
     173             :     bool SelectFPToI(const Instruction *I, bool isSigned);
     174             :     bool SelectDiv(const Instruction *I, bool isSigned);
     175             :     bool SelectRem(const Instruction *I, bool isSigned);
     176             :     bool SelectCall(const Instruction *I, const char *IntrMemName);
     177             :     bool SelectIntrinsicCall(const IntrinsicInst &I);
     178             :     bool SelectSelect(const Instruction *I);
     179             :     bool SelectRet(const Instruction *I);
     180             :     bool SelectTrunc(const Instruction *I);
     181             :     bool SelectIntExt(const Instruction *I);
     182             :     bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
     183             : 
     184             :     // Utility routines.
     185             : 
     186             :     bool isPositionIndependent() const;
     187             :     bool isTypeLegal(Type *Ty, MVT &VT);
     188             :     bool isLoadTypeLegal(Type *Ty, MVT &VT);
     189             :     bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
     190             :                     bool isZExt, bool isEquality);
     191             :     bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
     192             :                      unsigned Alignment = 0, bool isZExt = true,
     193             :                      bool allocReg = true);
     194             :     bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
     195             :                       unsigned Alignment = 0);
     196             :     bool ARMComputeAddress(const Value *Obj, Address &Addr);
     197             :     void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
     198             :     bool ARMIsMemCpySmall(uint64_t Len);
     199             :     bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
     200             :                                unsigned Alignment);
     201             :     unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
     202             :     unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
     203             :     unsigned ARMMaterializeInt(const Constant *C, MVT VT);
     204             :     unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
     205             :     unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
     206             :     unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
     207             :     unsigned ARMSelectCallOp(bool UseReg);
     208             :     unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
     209             : 
     210             :     const TargetLowering *getTargetLowering() { return &TLI; }
     211             : 
     212             :     // Call handling routines.
     213             : 
     214             :     CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
     215             :                                   bool Return,
     216             :                                   bool isVarArg);
     217             :     bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
     218             :                          SmallVectorImpl<unsigned> &ArgRegs,
     219             :                          SmallVectorImpl<MVT> &ArgVTs,
     220             :                          SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
     221             :                          SmallVectorImpl<unsigned> &RegArgs,
     222             :                          CallingConv::ID CC,
     223             :                          unsigned &NumBytes,
     224             :                          bool isVarArg);
     225             :     unsigned getLibcallReg(const Twine &Name);
     226             :     bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
     227             :                     const Instruction *I, CallingConv::ID CC,
     228             :                     unsigned &NumBytes, bool isVarArg);
     229             :     bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
     230             : 
     231             :     // OptionalDef handling routines.
     232             : 
     233             :     bool isARMNEONPred(const MachineInstr *MI);
     234             :     bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
     235             :     const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
     236             :     void AddLoadStoreOperands(MVT VT, Address &Addr,
     237             :                               const MachineInstrBuilder &MIB,
     238             :                               MachineMemOperand::Flags Flags, bool useAM3);
     239             : };
     240             : 
     241             : } // end anonymous namespace
     242             : 
     243             : #include "ARMGenCallingConv.inc"
     244             : 
     245             : // DefinesOptionalPredicate - This is different from DefinesPredicate in that
     246             : // we don't care about implicit defs here, just places we'll need to add a
     247             : // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
     248        5899 : bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
     249        5899 :   if (!MI->hasOptionalDef())
     250             :     return false;
     251             : 
     252             :   // Look to see if our OptionalDef is defining CPSR or CCR.
     253        4902 :   for (const MachineOperand &MO : MI->operands()) {
     254        6357 :     if (!MO.isReg() || !MO.isDef()) continue;
     255         848 :     if (MO.getReg() == ARM::CPSR)
     256           0 :       *CPSR = true;
     257             :   }
     258             :   return true;
     259             : }
     260             : 
     261        5899 : bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
     262        5899 :   const MCInstrDesc &MCID = MI->getDesc();
     263             : 
     264             :   // If we're a thumb2 or not NEON function we'll be handled via isPredicable.
     265        5899 :   if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
     266           2 :        AFI->isThumb2Function())
     267        5897 :     return MI->isPredicable();
     268             : 
     269          12 :   for (const MCOperandInfo &opInfo : MCID.operands())
     270           6 :     if (opInfo.isPredicate())
     271             :       return true;
     272             : 
     273             :   return false;
     274             : }
     275             : 
     276             : // If the machine is predicable go ahead and add the predicate operands, if
     277             : // it needs default CC operands add those.
     278             : // TODO: If we want to support thumb1 then we'll need to deal with optional
     279             : // CPSR defs that need to be added before the remaining operands. See s_cc_out
     280             : // for descriptions why.
     281             : const MachineInstrBuilder &
     282        5899 : ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
     283        5899 :   MachineInstr *MI = &*MIB;
     284             : 
     285             :   // Do we use a predicate? or...
     286             :   // Are we NEON in ARM mode and have a predicate operand? If so, I know
     287             :   // we're not predicable but add it anyways.
     288        5899 :   if (isARMNEONPred(MI))
     289       16914 :     MIB.add(predOps(ARMCC::AL));
     290             : 
     291             :   // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
     292             :   // defines CPSR. All other OptionalDefines in ARM are the CCR register.
     293        5899 :   bool CPSR = false;
     294        5899 :   if (DefinesOptionalPredicate(MI, &CPSR))
     295        1696 :     MIB.add(CPSR ? t1CondCodeOp() : condCodeOp());
     296        5899 :   return MIB;
     297             : }
     298             : 
     299          83 : unsigned ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
     300             :                                      const TargetRegisterClass *RC,
     301             :                                      unsigned Op0, bool Op0IsKill) {
     302          83 :   unsigned ResultReg = createResultReg(RC);
     303         166 :   const MCInstrDesc &II = TII.get(MachineInstOpcode);
     304             : 
     305             :   // Make sure the input operand is sufficiently constrained to be legal
     306             :   // for this instruction.
     307          83 :   Op0 = constrainOperandRegClass(II, Op0, 1);
     308          83 :   if (II.getNumDefs() >= 1) {
     309         166 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
     310         166 :                             ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
     311             :   } else {
     312           0 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
     313           0 :                    .addReg(Op0, Op0IsKill * RegState::Kill));
     314           0 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     315           0 :                    TII.get(TargetOpcode::COPY), ResultReg)
     316           0 :                    .addReg(II.ImplicitDefs[0]));
     317             :   }
     318          83 :   return ResultReg;
     319             : }
     320             : 
     321         150 : unsigned ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
     322             :                                       const TargetRegisterClass *RC,
     323             :                                       unsigned Op0, bool Op0IsKill,
     324             :                                       unsigned Op1, bool Op1IsKill) {
     325         150 :   unsigned ResultReg = createResultReg(RC);
     326         300 :   const MCInstrDesc &II = TII.get(MachineInstOpcode);
     327             : 
     328             :   // Make sure the input operands are sufficiently constrained to be legal
     329             :   // for this instruction.
     330         150 :   Op0 = constrainOperandRegClass(II, Op0, 1);
     331         150 :   Op1 = constrainOperandRegClass(II, Op1, 2);
     332             : 
     333         150 :   if (II.getNumDefs() >= 1) {
     334         150 :     AddOptionalDefs(
     335         300 :         BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
     336         150 :             .addReg(Op0, Op0IsKill * RegState::Kill)
     337         150 :             .addReg(Op1, Op1IsKill * RegState::Kill));
     338             :   } else {
     339           0 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
     340           0 :                    .addReg(Op0, Op0IsKill * RegState::Kill)
     341           0 :                    .addReg(Op1, Op1IsKill * RegState::Kill));
     342           0 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     343           0 :                            TII.get(TargetOpcode::COPY), ResultReg)
     344           0 :                    .addReg(II.ImplicitDefs[0]));
     345             :   }
     346         150 :   return ResultReg;
     347             : }
     348             : 
     349         465 : unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
     350             :                                       const TargetRegisterClass *RC,
     351             :                                       unsigned Op0, bool Op0IsKill,
     352             :                                       uint64_t Imm) {
     353         465 :   unsigned ResultReg = createResultReg(RC);
     354         930 :   const MCInstrDesc &II = TII.get(MachineInstOpcode);
     355             : 
     356             :   // Make sure the input operand is sufficiently constrained to be legal
     357             :   // for this instruction.
     358         465 :   Op0 = constrainOperandRegClass(II, Op0, 1);
     359         465 :   if (II.getNumDefs() >= 1) {
     360         465 :     AddOptionalDefs(
     361         930 :         BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
     362         465 :             .addReg(Op0, Op0IsKill * RegState::Kill)
     363         930 :             .addImm(Imm));
     364             :   } else {
     365           0 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
     366           0 :                    .addReg(Op0, Op0IsKill * RegState::Kill)
     367           0 :                    .addImm(Imm));
     368           0 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     369           0 :                            TII.get(TargetOpcode::COPY), ResultReg)
     370           0 :                    .addReg(II.ImplicitDefs[0]));
     371             :   }
     372         465 :   return ResultReg;
     373             : }
     374             : 
     375          15 : unsigned ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode,
     376             :                                      const TargetRegisterClass *RC,
     377             :                                      uint64_t Imm) {
     378          15 :   unsigned ResultReg = createResultReg(RC);
     379          30 :   const MCInstrDesc &II = TII.get(MachineInstOpcode);
     380             : 
     381          15 :   if (II.getNumDefs() >= 1) {
     382          30 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
     383          45 :                             ResultReg).addImm(Imm));
     384             :   } else {
     385           0 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
     386           0 :                    .addImm(Imm));
     387           0 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     388           0 :                            TII.get(TargetOpcode::COPY), ResultReg)
     389           0 :                    .addReg(II.ImplicitDefs[0]));
     390             :   }
     391          15 :   return ResultReg;
     392             : }
     393             : 
     394             : // TODO: Don't worry about 64-bit now, but when this is fixed remove the
     395             : // checks from the various callers.
     396          37 : unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
     397          74 :   if (VT == MVT::f64) return 0;
     398             : 
     399          37 :   unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
     400          74 :   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     401          74 :                           TII.get(ARM::VMOVSR), MoveReg)
     402          37 :                   .addReg(SrcReg));
     403          37 :   return MoveReg;
     404             : }
     405             : 
     406          12 : unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
     407          24 :   if (VT == MVT::i64) return 0;
     408             : 
     409          12 :   unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
     410          24 :   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     411          24 :                           TII.get(ARM::VMOVRS), MoveReg)
     412          12 :                   .addReg(SrcReg));
     413          12 :   return MoveReg;
     414             : }
     415             : 
     416             : // For double width floating point we need to materialize two constants
     417             : // (the high and the low) into integer registers then use a move to get
     418             : // the combined constant into an FP reg.
     419         309 : unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
     420         927 :   const APFloat Val = CFP->getValueAPF();
     421         618 :   bool is64bit = VT == MVT::f64;
     422             : 
     423             :   // This checks to see if we can use VFP3 instructions to materialize
     424             :   // a constant, otherwise we have to go through the constant pool.
     425         618 :   if (TLI.isFPImmLegal(Val, VT)) {
     426             :     int Imm;
     427             :     unsigned Opc;
     428          47 :     if (is64bit) {
     429           1 :       Imm = ARM_AM::getFP64Imm(Val);
     430           1 :       Opc = ARM::FCONSTD;
     431             :     } else {
     432          46 :       Imm = ARM_AM::getFP32Imm(Val);
     433          46 :       Opc = ARM::FCONSTS;
     434             :     }
     435          47 :     unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
     436          94 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     437         188 :                             TII.get(Opc), DestReg).addImm(Imm));
     438          47 :     return DestReg;
     439             :   }
     440             : 
     441             :   // Require VFP2 for loading fp constants.
     442         262 :   if (!Subtarget->hasVFP2()) return false;
     443             : 
     444             :   // MachineConstantPool wants an explicit alignment.
     445         262 :   unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
     446         262 :   if (Align == 0) {
     447             :     // TODO: Figure out if this is correct.
     448           0 :     Align = DL.getTypeAllocSize(CFP->getType());
     449             :   }
     450         524 :   unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
     451         262 :   unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
     452         262 :   unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
     453             : 
     454             :   // The extra reg is for addrmode5.
     455         262 :   AddOptionalDefs(
     456         786 :       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
     457         262 :           .addConstantPoolIndex(Idx)
     458         262 :           .addReg(0));
     459         262 :   return DestReg;
     460             : }
     461             : 
     462         519 : unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
     463         519 :   if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
     464             :     return 0;
     465             : 
     466             :   // If we can do this in a single instruction without a constant pool entry
     467             :   // do so now.
     468         519 :   const ConstantInt *CI = cast<ConstantInt>(C);
     469        1034 :   if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
     470         306 :     unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
     471         306 :     const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
     472             :       &ARM::GPRRegClass;
     473         306 :     unsigned ImmReg = createResultReg(RC);
     474         612 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     475         612 :                             TII.get(Opc), ImmReg)
     476         612 :                     .addImm(CI->getZExtValue()));
     477         306 :     return ImmReg;
     478             :   }
     479             : 
     480             :   // Use MVN to emit negative constants.
     481         635 :   if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
     482         207 :     unsigned Imm = (unsigned)~(CI->getSExtValue());
     483         318 :     bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
     484         318 :       (ARM_AM::getSOImmVal(Imm) != -1);
     485         207 :     if (UseImm) {
     486         192 :       unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
     487         192 :       const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
     488             :                                                  &ARM::GPRRegClass;
     489         192 :       unsigned ImmReg = createResultReg(RC);
     490         384 :       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     491         384 :                               TII.get(Opc), ImmReg)
     492         384 :                       .addImm(Imm));
     493         192 :       return ImmReg;
     494             :     }
     495             :   }
     496             : 
     497          21 :   unsigned ResultReg = 0;
     498          21 :   if (Subtarget->useMovt(*FuncInfo.MF))
     499          12 :     ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
     500             : 
     501           6 :   if (ResultReg)
     502             :     return ResultReg;
     503             : 
     504             :   // Load from constant pool.  For now 32-bit only.
     505          17 :   if (VT != MVT::i32)
     506             :     return 0;
     507             : 
     508             :   // MachineConstantPool wants an explicit alignment.
     509          17 :   unsigned Align = DL.getPrefTypeAlignment(C->getType());
     510          17 :   if (Align == 0) {
     511             :     // TODO: Figure out if this is correct.
     512           0 :     Align = DL.getTypeAllocSize(C->getType());
     513             :   }
     514          17 :   unsigned Idx = MCP.getConstantPoolIndex(C, Align);
     515          17 :   ResultReg = createResultReg(TLI.getRegClassFor(VT));
     516          17 :   if (isThumb2)
     517          14 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     518          14 :                             TII.get(ARM::t2LDRpci), ResultReg)
     519           7 :                       .addConstantPoolIndex(Idx));
     520             :   else {
     521             :     // The extra immediate is for addrmode2.
     522          20 :     ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);
     523          20 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     524          20 :                             TII.get(ARM::LDRcp), ResultReg)
     525          10 :                       .addConstantPoolIndex(Idx)
     526          10 :                       .addImm(0));
     527             :   }
     528             :   return ResultReg;
     529             : }
     530             : 
     531             : bool ARMFastISel::isPositionIndependent() const {
     532         251 :   return TLI.isPositionIndependent();
     533             : }
     534             : 
     535         262 : unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
     536             :   // For now 32-bit only.
     537         786 :   if (VT != MVT::i32 || GV->isThreadLocal()) return 0;
     538             : 
     539             :   // ROPI/RWPI not currently supported.
     540         251 :   if (Subtarget->isROPI() || Subtarget->isRWPI())
     541             :     return 0;
     542             : 
     543         251 :   bool IsIndirect = Subtarget->isGVIndirectSymbol(GV);
     544         251 :   const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
     545             :                                            : &ARM::GPRRegClass;
     546         251 :   unsigned DestReg = createResultReg(RC);
     547             : 
     548             :   // FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
     549         183 :   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
     550         366 :   bool IsThreadLocal = GVar && GVar->isThreadLocal();
     551         502 :   if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0;
     552             : 
     553         502 :   bool IsPositionIndependent = isPositionIndependent();
     554             :   // Use movw+movt when possible, it avoids constant pool entries.
     555             :   // Non-darwin targets only support static movt relocations in FastISel.
     556         497 :   if (Subtarget->useMovt(*FuncInfo.MF) &&
     557         563 :       (Subtarget->isTargetMachO() || !IsPositionIndependent)) {
     558             :     unsigned Opc;
     559         241 :     unsigned char TF = 0;
     560         482 :     if (Subtarget->isTargetMachO())
     561         175 :       TF = ARMII::MO_NONLAZY;
     562             : 
     563         241 :     if (IsPositionIndependent)
     564          60 :       Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
     565             :     else
     566         181 :       Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
     567         482 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     568         964 :                             TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF));
     569             :   } else {
     570             :     // MachineConstantPool wants an explicit alignment.
     571          20 :     unsigned Align = DL.getPrefTypeAlignment(GV->getType());
     572          10 :     if (Align == 0) {
     573             :       // TODO: Figure out if this is correct.
     574           0 :       Align = DL.getTypeAllocSize(GV->getType());
     575             :     }
     576             : 
     577          20 :     if (Subtarget->isTargetELF() && IsPositionIndependent)
     578          12 :       return ARMLowerPICELF(GV, Align, VT);
     579             : 
     580             :     // Grab index.
     581          10 :     unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
     582          10 :     unsigned Id = AFI->createPICLabelUId();
     583           5 :     ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
     584             :                                                                 ARMCP::CPValue,
     585           5 :                                                                 PCAdj);
     586           5 :     unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
     587             : 
     588             :     // Load value.
     589           5 :     MachineInstrBuilder MIB;
     590           5 :     if (isThumb2) {
     591           3 :       unsigned Opc = IsPositionIndependent ? ARM::t2LDRpci_pic : ARM::t2LDRpci;
     592           9 :       MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
     593           9 :                     DestReg).addConstantPoolIndex(Idx);
     594           3 :       if (IsPositionIndependent)
     595           3 :         MIB.addImm(Id);
     596           3 :       AddOptionalDefs(MIB);
     597             :     } else {
     598             :       // The extra immediate is for addrmode2.
     599           4 :       DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
     600           4 :       MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     601           4 :                     TII.get(ARM::LDRcp), DestReg)
     602           2 :                 .addConstantPoolIndex(Idx)
     603           2 :                 .addImm(0);
     604           2 :       AddOptionalDefs(MIB);
     605             : 
     606           2 :       if (IsPositionIndependent) {
     607           2 :         unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
     608           2 :         unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
     609             : 
     610           4 :         MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
     611           4 :                                           DbgLoc, TII.get(Opc), NewDestReg)
     612           2 :                                   .addReg(DestReg)
     613           4 :                                   .addImm(Id);
     614           2 :         AddOptionalDefs(MIB);
     615             :         return NewDestReg;
     616             :       }
     617             :     }
     618             :   }
     619             : 
     620         244 :   if (IsIndirect) {
     621          86 :     MachineInstrBuilder MIB;
     622          86 :     unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
     623          86 :     if (isThumb2)
     624         102 :       MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     625         102 :                     TII.get(ARM::t2LDRi12), NewDestReg)
     626          51 :             .addReg(DestReg)
     627          51 :             .addImm(0);
     628             :     else
     629          70 :       MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     630          70 :                     TII.get(ARM::LDRi12), NewDestReg)
     631          35 :                 .addReg(DestReg)
     632          35 :                 .addImm(0);
     633          86 :     DestReg = NewDestReg;
     634          86 :     AddOptionalDefs(MIB);
     635             :   }
     636             : 
     637             :   return DestReg;
     638             : }
     639             : 
     640        1190 : unsigned ARMFastISel::fastMaterializeConstant(const Constant *C) {
     641        1190 :   EVT CEVT = TLI.getValueType(DL, C->getType(), true);
     642             : 
     643             :   // Only handle simple types.
     644        1190 :   if (!CEVT.isSimple()) return 0;
     645        1190 :   MVT VT = CEVT.getSimpleVT();
     646             : 
     647        1499 :   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
     648         309 :     return ARMMaterializeFP(CFP, VT);
     649        1131 :   else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
     650         250 :     return ARMMaterializeGV(GV, VT);
     651        1262 :   else if (isa<ConstantInt>(C))
     652         519 :     return ARMMaterializeInt(C, VT);
     653             : 
     654             :   return 0;
     655             : }
     656             : 
     657             : // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
     658             : 
     659         206 : unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
     660             :   // Don't handle dynamic allocas.
     661         412 :   if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
     662             : 
     663         206 :   MVT VT;
     664         206 :   if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
     665             : 
     666             :   DenseMap<const AllocaInst*, int>::iterator SI =
     667         206 :     FuncInfo.StaticAllocaMap.find(AI);
     668             : 
     669             :   // This will get lowered later into the correct offsets and registers
     670             :   // via rewriteXFrameIndex.
     671         618 :   if (SI != FuncInfo.StaticAllocaMap.end()) {
     672         206 :     unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
     673         206 :     const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
     674         206 :     unsigned ResultReg = createResultReg(RC);
     675         412 :     ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
     676             : 
     677         412 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     678         412 :                             TII.get(Opc), ResultReg)
     679         412 :                             .addFrameIndex(SI->second)
     680         206 :                             .addImm(0));
     681         206 :     return ResultReg;
     682             :   }
     683             : 
     684             :   return 0;
     685             : }
     686             : 
     687        3024 : bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
     688        3024 :   EVT evt = TLI.getValueType(DL, Ty, true);
     689             : 
     690             :   // Only handle simple types.
     691        6037 :   if (evt == MVT::Other || !evt.isSimple()) return false;
     692        3013 :   VT = evt.getSimpleVT();
     693             : 
     694             :   // Handle all legal types, i.e. a register that will directly hold this
     695             :   // value.
     696        9039 :   return TLI.isTypeLegal(VT);
     697             : }
     698             : 
     699        1314 : bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
     700        1314 :   if (isTypeLegal(Ty, VT)) return true;
     701             : 
     702             :   // If this is a type than can be sign or zero-extended to a basic operation
     703             :   // go ahead and accept it now.
     704         350 :   if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
     705             :     return true;
     706             : 
     707             :   return false;
     708             : }
     709             : 
     710             : // Computes the address to get to an object.
     711        1556 : bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
     712             :   // Some boilerplate from the X86 FastISel.
     713        1556 :   const User *U = nullptr;
     714        1556 :   unsigned Opcode = Instruction::UserOp1;
     715        1119 :   if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
     716             :     // Don't walk into other basic blocks unless the object is an alloca from
     717             :     // another block, otherwise it may not have a virtual register assigned.
     718        2233 :     if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
     719        1172 :         FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
     720        1061 :       Opcode = I->getOpcode();
     721        1061 :       U = I;
     722             :     }
     723         106 :   } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
     724         106 :     Opcode = C->getOpcode();
     725         106 :     U = C;
     726             :   }
     727             : 
     728        3109 :   if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
     729        1553 :     if (Ty->getAddressSpace() > 255)
     730             :       // Fast instruction selection doesn't support the special
     731             :       // address spaces.
     732             :       return false;
     733             : 
     734        1556 :   switch (Opcode) {
     735             :     default:
     736             :     break;
     737          22 :     case Instruction::BitCast:
     738             :       // Look through bitcasts.
     739          22 :       return ARMComputeAddress(U->getOperand(0), Addr);
     740           3 :     case Instruction::IntToPtr:
     741             :       // Look past no-op inttoptrs.
     742          12 :       if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
     743           3 :           TLI.getPointerTy(DL))
     744           3 :         return ARMComputeAddress(U->getOperand(0), Addr);
     745             :       break;
     746           0 :     case Instruction::PtrToInt:
     747             :       // Look past no-op ptrtoints.
     748           0 :       if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
     749           0 :         return ARMComputeAddress(U->getOperand(0), Addr);
     750             :       break;
     751         542 :     case Instruction::GetElementPtr: {
     752         542 :       Address SavedAddr = Addr;
     753         542 :       int TmpOffset = Addr.Offset;
     754             : 
     755             :       // Iterate through the GEP folding the constants into offsets where
     756             :       // we can.
     757         542 :       gep_type_iterator GTI = gep_type_begin(U);
     758        2112 :       for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
     759        1570 :            i != e; ++i, ++GTI) {
     760        1038 :         const Value *Op = *i;
     761         305 :         if (StructType *STy = GTI.getStructTypeOrNull()) {
     762         305 :           const StructLayout *SL = DL.getStructLayout(STy);
     763         610 :           unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
     764         305 :           TmpOffset += SL->getElementOffset(Idx);
     765             :         } else {
     766         733 :           uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
     767             :           while (true) {
     768         723 :             if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
     769             :               // Constant-offset addressing.
     770         723 :               TmpOffset += CI->getSExtValue() * S;
     771         723 :               break;
     772             :             }
     773          10 :             if (canFoldAddIntoGEP(U, Op)) {
     774             :               // A compatible add with a constant operand. Fold the constant.
     775             :               ConstantInt *CI =
     776           0 :               cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
     777           0 :               TmpOffset += CI->getSExtValue() * S;
     778             :               // Iterate on the other operand.
     779           0 :               Op = cast<AddOperator>(Op)->getOperand(0);
     780           0 :               continue;
     781             :             }
     782             :             // Unsupported
     783             :             goto unsupported_gep;
     784           0 :           }
     785             :         }
     786             :       }
     787             : 
     788             :       // Try to grab the base operand now.
     789         532 :       Addr.Offset = TmpOffset;
     790         532 :       if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
     791             : 
     792             :       // We failed, restore everything and try the other options.
     793           2 :       Addr = SavedAddr;
     794             : 
     795          12 :       unsupported_gep:
     796          12 :       break;
     797             :     }
     798         562 :     case Instruction::Alloca: {
     799         562 :       const AllocaInst *AI = cast<AllocaInst>(Obj);
     800             :       DenseMap<const AllocaInst*, int>::iterator SI =
     801         562 :         FuncInfo.StaticAllocaMap.find(AI);
     802        1686 :       if (SI != FuncInfo.StaticAllocaMap.end()) {
     803         562 :         Addr.BaseType = Address::FrameIndexBase;
     804         562 :         Addr.Base.FI = SI->second;
     805         562 :         return true;
     806             :       }
     807           0 :       break;
     808             :     }
     809             :   }
     810             : 
     811             :   // Try to get this in a register if nothing else has worked.
     812         439 :   if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
     813         439 :   return Addr.Base.Reg != 0;
     814             : }
     815             : 
     816        1719 : void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
     817        1719 :   bool needsLowering = false;
     818        1719 :   switch (VT.SimpleTy) {
     819           0 :     default: llvm_unreachable("Unhandled load/store type!");
     820        1147 :     case MVT::i1:
     821             :     case MVT::i8:
     822             :     case MVT::i16:
     823             :     case MVT::i32:
     824        1147 :       if (!useAM3) {
     825             :         // Integer loads/stores handle 12-bit offsets.
     826        1031 :         needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
     827             :         // Handle negative offsets.
     828        1031 :         if (needsLowering && isThumb2)
     829          19 :           needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
     830             :                             Addr.Offset > -256);
     831             :       } else {
     832             :         // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
     833         116 :         needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
     834             :       }
     835             :       break;
     836         572 :     case MVT::f32:
     837             :     case MVT::f64:
     838             :       // Floating point operands handle 8-bit offsets.
     839         572 :       needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
     840         572 :       break;
     841             :   }
     842             : 
     843             :   // If this is a stack pointer and the offset needs to be simplified then
     844             :   // put the alloca address into a register, set the base type back to
     845             :   // register and continue. This should almost never happen.
     846        1700 :   if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
     847           0 :     const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
     848             :                                              : &ARM::GPRRegClass;
     849           0 :     unsigned ResultReg = createResultReg(RC);
     850           0 :     unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
     851           0 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
     852           0 :                             TII.get(Opc), ResultReg)
     853           0 :                             .addFrameIndex(Addr.Base.FI)
     854           0 :                             .addImm(0));
     855           0 :     Addr.Base.Reg = ResultReg;
     856           0 :     Addr.BaseType = Address::RegBase;
     857             :   }
     858             : 
     859             :   // Since the offset is too large for the load/store instruction
     860             :   // get the reg+offset into a register.
     861        1719 :   if (needsLowering) {
     862        1212 :     Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
     863         808 :                                  /*Op0IsKill*/false, Addr.Offset, MVT::i32);
     864         404 :     Addr.Offset = 0;
     865             :   }
     866        1719 : }
     867             : 
     868        1719 : void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
     869             :                                        const MachineInstrBuilder &MIB,
     870             :                                        MachineMemOperand::Flags Flags,
     871             :                                        bool useAM3) {
     872             :   // addrmode5 output depends on the selection dag addressing dividing the
     873             :   // offset by 4 that it then later multiplies. Do this here as well.
     874        1719 :   if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
     875         572 :     Addr.Offset /= 4;
     876             : 
     877             :   // Frame base works a bit differently. Handle it separately.
     878        1719 :   if (Addr.BaseType == Address::FrameIndexBase) {
     879         565 :     int FI = Addr.Base.FI;
     880         565 :     int Offset = Addr.Offset;
     881        3390 :     MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
     882         565 :         MachinePointerInfo::getFixedStack(*FuncInfo.MF, FI, Offset), Flags,
     883        2260 :         MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
     884             :     // Now add the rest of the operands.
     885         565 :     MIB.addFrameIndex(FI);
     886             : 
     887             :     // ARM halfword load/stores and signed byte loads need an additional
     888             :     // operand.
     889         565 :     if (useAM3) {
     890           6 :       int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
     891           6 :       MIB.addReg(0);
     892           6 :       MIB.addImm(Imm);
     893             :     } else {
     894         559 :       MIB.addImm(Addr.Offset);
     895             :     }
     896             :     MIB.addMemOperand(MMO);
     897             :   } else {
     898             :     // Now add the rest of the operands.
     899        1154 :     MIB.addReg(Addr.Base.Reg);
     900             : 
     901             :     // ARM halfword load/stores and signed byte loads need an additional
     902             :     // operand.
     903        1154 :     if (useAM3) {
     904         110 :       int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
     905         110 :       MIB.addReg(0);
     906         110 :       MIB.addImm(Imm);
     907             :     } else {
     908        1044 :       MIB.addImm(Addr.Offset);
     909             :     }
     910             :   }
     911        1719 :   AddOptionalDefs(MIB);
     912        1719 : }
     913             : 
     914         489 : bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
     915             :                               unsigned Alignment, bool isZExt, bool allocReg) {
     916             :   unsigned Opc;
     917         489 :   bool useAM3 = false;
     918         489 :   bool needVMOV = false;
     919             :   const TargetRegisterClass *RC;
     920         489 :   switch (VT.SimpleTy) {
     921             :     // This is mostly going to be Neon/vector support.
     922             :     default: return false;
     923          96 :     case MVT::i1:
     924             :     case MVT::i8:
     925          96 :       if (isThumb2) {
     926          31 :         if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
     927           2 :           Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
     928             :         else
     929          29 :           Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
     930             :       } else {
     931          65 :         if (isZExt) {
     932             :           Opc = ARM::LDRBi12;
     933             :         } else {
     934           8 :           Opc = ARM::LDRSB;
     935           8 :           useAM3 = true;
     936             :         }
     937             :       }
     938          96 :       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
     939             :       break;
     940          85 :     case MVT::i16:
     941          85 :       if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
     942             :         return false;
     943             : 
     944          81 :       if (isThumb2) {
     945          24 :         if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
     946           2 :           Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
     947             :         else
     948          22 :           Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
     949             :       } else {
     950          57 :         Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
     951             :         useAM3 = true;
     952             :       }
     953          81 :       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
     954             :       break;
     955         284 :     case MVT::i32:
     956         284 :       if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
     957             :         return false;
     958             : 
     959         280 :       if (isThumb2) {
     960         141 :         if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
     961             :           Opc = ARM::t2LDRi8;
     962             :         else
     963             :           Opc = ARM::t2LDRi12;
     964             :       } else {
     965             :         Opc = ARM::LDRi12;
     966             :       }
     967         280 :       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
     968             :       break;
     969          18 :     case MVT::f32:
     970          18 :       if (!Subtarget->hasVFP2()) return false;
     971             :       // Unaligned loads need special handling. Floats require word-alignment.
     972          18 :       if (Alignment && Alignment < 4) {
     973           8 :         needVMOV = true;
     974           8 :         VT = MVT::i32;
     975           8 :         Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
     976           8 :         RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
     977             :       } else {
     978          10 :         Opc = ARM::VLDRS;
     979          10 :         RC = TLI.getRegClassFor(VT);
     980             :       }
     981             :       break;
     982           2 :     case MVT::f64:
     983           2 :       if (!Subtarget->hasVFP2()) return false;
     984             :       // FIXME: Unaligned loads need special handling.  Doublewords require
     985             :       // word-alignment.
     986           2 :       if (Alignment && Alignment < 4)
     987             :         return false;
     988             : 
     989           2 :       Opc = ARM::VLDRD;
     990           2 :       RC = TLI.getRegClassFor(VT);
     991           2 :       break;
     992             :   }
     993             :   // Simplify this down to something we can handle.
     994         477 :   ARMSimplifyAddress(Addr, VT, useAM3);
     995             : 
     996             :   // Create the base instruction, then add the operands.
     997         477 :   if (allocReg)
     998         426 :     ResultReg = createResultReg(RC);
     999             :   assert(ResultReg > 255 && "Expected an allocated virtual register.");
    1000         477 :   MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    1001        1431 :                                     TII.get(Opc), ResultReg);
    1002         477 :   AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
    1003             : 
    1004             :   // If we had an unaligned load of a float we've converted it to an regular
    1005             :   // load.  Now we must move from the GRP to the FP register.
    1006         477 :   if (needVMOV) {
    1007          16 :     unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
    1008          16 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    1009          16 :                             TII.get(ARM::VMOVSR), MoveReg)
    1010           8 :                     .addReg(ResultReg));
    1011           8 :     ResultReg = MoveReg;
    1012             :   }
    1013             :   return true;
    1014             : }
    1015             : 
    1016         322 : bool ARMFastISel::SelectLoad(const Instruction *I) {
    1017             :   // Atomic loads need special handling.
    1018         322 :   if (cast<LoadInst>(I)->isAtomic())
    1019             :     return false;
    1020             : 
    1021         642 :   const Value *SV = I->getOperand(0);
    1022         321 :   if (TLI.supportSwiftError()) {
    1023             :     // Swifterror values can come from either a function parameter with
    1024             :     // swifterror attribute or an alloca with swifterror attribute.
    1025          28 :     if (const Argument *Arg = dyn_cast<Argument>(SV)) {
    1026          28 :       if (Arg->hasSwiftErrorAttr())
    1027             :         return false;
    1028             :     }
    1029             : 
    1030         126 :     if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
    1031         126 :       if (Alloca->isSwiftError())
    1032             :         return false;
    1033             :     }
    1034             :   }
    1035             : 
    1036             :   // Verify we have a legal type before going any further.
    1037         316 :   MVT VT;
    1038         316 :   if (!isLoadTypeLegal(I->getType(), VT))
    1039             :     return false;
    1040             : 
    1041             :   // See if we can handle this address.
    1042         315 :   Address Addr;
    1043         630 :   if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
    1044             : 
    1045             :   unsigned ResultReg;
    1046         620 :   if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
    1047             :     return false;
    1048         298 :   updateValueMap(I, ResultReg);
    1049         298 :   return true;
    1050             : }
    1051             : 
    1052        1255 : bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
    1053             :                                unsigned Alignment) {
    1054             :   unsigned StrOpc;
    1055        1255 :   bool useAM3 = false;
    1056        1255 :   switch (VT.SimpleTy) {
    1057             :     // This is mostly going to be Neon/vector support.
    1058             :     default: return false;
    1059          11 :     case MVT::i1: {
    1060          11 :       unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass
    1061          11 :                                               : &ARM::GPRRegClass);
    1062          11 :       unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
    1063          22 :       SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
    1064          22 :       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    1065          22 :                               TII.get(Opc), Res)
    1066          22 :                       .addReg(SrcReg).addImm(1));
    1067          11 :       SrcReg = Res;
    1068             :       LLVM_FALLTHROUGH;
    1069             :     }
    1070         102 :     case MVT::i8:
    1071         102 :       if (isThumb2) {
    1072          35 :         if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
    1073             :           StrOpc = ARM::t2STRBi8;
    1074             :         else
    1075             :           StrOpc = ARM::t2STRBi12;
    1076             :       } else {
    1077             :         StrOpc = ARM::STRBi12;
    1078             :       }
    1079             :       break;
    1080          78 :     case MVT::i16:
    1081          78 :       if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
    1082             :         return false;
    1083             : 
    1084          74 :       if (isThumb2) {
    1085          23 :         if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
    1086             :           StrOpc = ARM::t2STRHi8;
    1087             :         else
    1088             :           StrOpc = ARM::t2STRHi12;
    1089             :       } else {
    1090             :         StrOpc = ARM::STRH;
    1091             :         useAM3 = true;
    1092             :       }
    1093             :       break;
    1094         502 :     case MVT::i32:
    1095         502 :       if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
    1096             :         return false;
    1097             : 
    1098         498 :       if (isThumb2) {
    1099         302 :         if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
    1100             :           StrOpc = ARM::t2STRi8;
    1101             :         else
    1102             :           StrOpc = ARM::t2STRi12;
    1103             :       } else {
    1104             :         StrOpc = ARM::STRi12;
    1105             :       }
    1106             :       break;
    1107         119 :     case MVT::f32:
    1108         119 :       if (!Subtarget->hasVFP2()) return false;
    1109             :       // Unaligned stores need special handling. Floats require word-alignment.
    1110         119 :       if (Alignment && Alignment < 4) {
    1111          16 :         unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
    1112          16 :         AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    1113          16 :                                 TII.get(ARM::VMOVRS), MoveReg)
    1114           8 :                         .addReg(SrcReg));
    1115           8 :         SrcReg = MoveReg;
    1116           8 :         VT = MVT::i32;
    1117           8 :         StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
    1118             :       } else {
    1119             :         StrOpc = ARM::VSTRS;
    1120             :       }
    1121             :       break;
    1122         449 :     case MVT::f64:
    1123         449 :       if (!Subtarget->hasVFP2()) return false;
    1124             :       // FIXME: Unaligned stores need special handling.  Doublewords require
    1125             :       // word-alignment.
    1126         449 :       if (Alignment && Alignment < 4)
    1127             :           return false;
    1128             : 
    1129             :       StrOpc = ARM::VSTRD;
    1130             :       break;
    1131             :   }
    1132             :   // Simplify this down to something we can handle.
    1133        1242 :   ARMSimplifyAddress(Addr, VT, useAM3);
    1134             : 
    1135             :   // Create the base instruction, then add the operands.
    1136        2484 :   SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);
    1137        2484 :   MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    1138        2484 :                                     TII.get(StrOpc))
    1139        1242 :                             .addReg(SrcReg);
    1140        1242 :   AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
    1141        1242 :   return true;
    1142             : }
    1143             : 
    1144         593 : bool ARMFastISel::SelectStore(const Instruction *I) {
    1145        1186 :   Value *Op0 = I->getOperand(0);
    1146         593 :   unsigned SrcReg = 0;
    1147             : 
    1148             :   // Atomic stores need special handling.
    1149         593 :   if (cast<StoreInst>(I)->isAtomic())
    1150             :     return false;
    1151             : 
    1152        1180 :   const Value *PtrV = I->getOperand(1);
    1153         590 :   if (TLI.supportSwiftError()) {
    1154             :     // Swifterror values can come from either a function parameter with
    1155             :     // swifterror attribute or an alloca with swifterror attribute.
    1156          63 :     if (const Argument *Arg = dyn_cast<Argument>(PtrV)) {
    1157          63 :       if (Arg->hasSwiftErrorAttr())
    1158             :         return false;
    1159             :     }
    1160             : 
    1161         254 :     if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
    1162         254 :       if (Alloca->isSwiftError())
    1163             :         return false;
    1164             :     }
    1165             :   }
    1166             : 
    1167             :   // Verify we have a legal type before going any further.
    1168         588 :   MVT VT;
    1169        1176 :   if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
    1170             :     return false;
    1171             : 
    1172             :   // Get the value to be stored into a register.
    1173         581 :   SrcReg = getRegForValue(Op0);
    1174         581 :   if (SrcReg == 0) return false;
    1175             : 
    1176             :   // See if we can handle this address.
    1177         581 :   Address Addr;
    1178        1162 :   if (!ARMComputeAddress(I->getOperand(1), Addr))
    1179             :     return false;
    1180             : 
    1181        1154 :   if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
    1182             :     return false;
    1183         564 :   return true;
    1184             : }
    1185             : 
    1186             : static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
    1187             :   switch (Pred) {
    1188             :     // Needs two compares...
    1189             :     case CmpInst::FCMP_ONE:
    1190             :     case CmpInst::FCMP_UEQ:
    1191             :     default:
    1192             :       // AL is our "false" for now. The other two need more compares.
    1193             :       return ARMCC::AL;
    1194             :     case CmpInst::ICMP_EQ:
    1195             :     case CmpInst::FCMP_OEQ:
    1196             :       return ARMCC::EQ;
    1197             :     case CmpInst::ICMP_SGT:
    1198             :     case CmpInst::FCMP_OGT:
    1199             :       return ARMCC::GT;
    1200             :     case CmpInst::ICMP_SGE:
    1201             :     case CmpInst::FCMP_OGE:
    1202             :       return ARMCC::GE;
    1203             :     case CmpInst::ICMP_UGT:
    1204             :     case CmpInst::FCMP_UGT:
    1205             :       return ARMCC::HI;
    1206             :     case CmpInst::FCMP_OLT:
    1207             :       return ARMCC::MI;
    1208             :     case CmpInst::ICMP_ULE:
    1209             :     case CmpInst::FCMP_OLE:
    1210             :       return ARMCC::LS;
    1211             :     case CmpInst::FCMP_ORD:
    1212             :       return ARMCC::VC;
    1213             :     case CmpInst::FCMP_UNO:
    1214             :       return ARMCC::VS;
    1215             :     case CmpInst::FCMP_UGE:
    1216             :       return ARMCC::PL;
    1217             :     case CmpInst::ICMP_SLT:
    1218             :     case CmpInst::FCMP_ULT:
    1219             :       return ARMCC::LT;
    1220             :     case CmpInst::ICMP_SLE:
    1221             :     case CmpInst::FCMP_ULE:
    1222             :       return ARMCC::LE;
    1223             :     case CmpInst::FCMP_UNE:
    1224             :     case CmpInst::ICMP_NE:
    1225             :       return ARMCC::NE;
    1226             :     case CmpInst::ICMP_UGE:
    1227             :       return ARMCC::HS;
    1228             :     case CmpInst::ICMP_ULT:
    1229             :       return ARMCC::LO;
    1230             :   }
    1231             : }
    1232             : 
    1233          79 : bool ARMFastISel::SelectBranch(const Instruction *I) {
    1234          79 :   const BranchInst *BI = cast<BranchInst>(I);
    1235         158 :   MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
    1236         158 :   MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
    1237             : 
    1238             :   // Simple branch support.
    1239             : 
    1240             :   // If we can, avoid recomputing the compare - redoing it could lead to wonky
    1241             :   // behavior.
    1242         137 :   if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
    1243         116 :     if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
    1244             :       // Get the compare predicate.
    1245             :       // Try to take advantage of fallthrough opportunities.
    1246          58 :       CmpInst::Predicate Predicate = CI->getPredicate();
    1247          58 :       if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
    1248          52 :         std::swap(TBB, FBB);
    1249          52 :         Predicate = CmpInst::getInversePredicate(Predicate);
    1250             :       }
    1251             : 
    1252          58 :       ARMCC::CondCodes ARMPred = getComparePred(Predicate);
    1253             : 
    1254             :       // We may not handle every CC for now.
    1255          58 :       if (ARMPred == ARMCC::AL) return false;
    1256             : 
    1257             :       // Emit the compare.
    1258         232 :       if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
    1259          58 :                       CI->isEquality()))
    1260             :         return false;
    1261             : 
    1262          58 :       unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
    1263         174 :       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
    1264         174 :       .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
    1265          58 :       finishCondBranch(BI->getParent(), TBB, FBB);
    1266          58 :       return true;
    1267             :     }
    1268          24 :   } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
    1269           3 :     MVT SourceVT;
    1270           9 :     if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
    1271           6 :         (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
    1272           3 :       unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
    1273           6 :       unsigned OpReg = getRegForValue(TI->getOperand(0));
    1274           6 :       OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
    1275           6 :       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    1276           6 :                               TII.get(TstOpc))
    1277           6 :                       .addReg(OpReg).addImm(1));
    1278             : 
    1279           3 :       unsigned CCMode = ARMCC::NE;
    1280           3 :       if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
    1281           3 :         std::swap(TBB, FBB);
    1282           3 :         CCMode = ARMCC::EQ;
    1283             :       }
    1284             : 
    1285           3 :       unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
    1286           9 :       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
    1287           9 :       .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
    1288             : 
    1289           3 :       finishCondBranch(BI->getParent(), TBB, FBB);
    1290           3 :       return true;
    1291             :     }
    1292             :   } else if (const ConstantInt *CI =
    1293          30 :              dyn_cast<ConstantInt>(BI->getCondition())) {
    1294          12 :     uint64_t Imm = CI->getZExtValue();
    1295          12 :     MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
    1296          12 :     fastEmitBranch(Target, DbgLoc);
    1297          12 :     return true;
    1298             :   }
    1299             : 
    1300          12 :   unsigned CmpReg = getRegForValue(BI->getCondition());
    1301           6 :   if (CmpReg == 0) return false;
    1302             : 
    1303             :   // We've been divorced from our compare!  Our block was split, and
    1304             :   // now our compare lives in a predecessor block.  We musn't
    1305             :   // re-compare here, as the children of the compare aren't guaranteed
    1306             :   // live across the block boundary (we *could* check for this).
    1307             :   // Regardless, the compare has been done in the predecessor block,
    1308             :   // and it left a value for us in a virtual register.  Ergo, we test
    1309             :   // the one-bit value left in the virtual register.
    1310           6 :   unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
    1311          12 :   CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);
    1312           6 :   AddOptionalDefs(
    1313          18 :       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
    1314           6 :           .addReg(CmpReg)
    1315           6 :           .addImm(1));
    1316             : 
    1317           6 :   unsigned CCMode = ARMCC::NE;
    1318           6 :   if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
    1319           3 :     std::swap(TBB, FBB);
    1320           3 :     CCMode = ARMCC::EQ;
    1321             :   }
    1322             : 
    1323           6 :   unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
    1324          18 :   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
    1325          18 :                   .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
    1326           6 :   finishCondBranch(BI->getParent(), TBB, FBB);
    1327           6 :   return true;
    1328             : }
    1329             : 
    1330           4 : bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
    1331           8 :   unsigned AddrReg = getRegForValue(I->getOperand(0));
    1332           4 :   if (AddrReg == 0) return false;
    1333             : 
    1334           4 :   unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
    1335             :   assert(isThumb2 || Subtarget->hasV4TOps());
    1336             : 
    1337           8 :   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    1338          12 :                           TII.get(Opc)).addReg(AddrReg));
    1339             : 
    1340           4 :   const IndirectBrInst *IB = cast<IndirectBrInst>(I);
    1341          28 :   for (const BasicBlock *SuccBB : IB->successors())
    1342          24 :     FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[SuccBB]);
    1343             : 
    1344           4 :   return true;
    1345             : }
    1346             : 
    1347          84 : bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
    1348             :                              bool isZExt, bool isEquality) {
    1349          84 :   Type *Ty = Src1Value->getType();
    1350          84 :   EVT SrcEVT = TLI.getValueType(DL, Ty, true);
    1351          84 :   if (!SrcEVT.isSimple()) return false;
    1352          84 :   MVT SrcVT = SrcEVT.getSimpleVT();
    1353             : 
    1354          84 :   if (Ty->isFloatTy() && !Subtarget->hasVFP2())
    1355             :     return false;
    1356             : 
    1357          84 :   if (Ty->isDoubleTy() && (!Subtarget->hasVFP2() || Subtarget->isFPOnlySP()))
    1358             :     return false;
    1359             : 
    1360             :   // Check to see if the 2nd operand is a constant that we can encode directly
    1361             :   // in the compare.
    1362          83 :   int Imm = 0;
    1363          83 :   bool UseImm = false;
    1364          83 :   bool isNegativeImm = false;
    1365             :   // FIXME: At -O0 we don't have anything that canonicalizes operand order.
    1366             :   // Thus, Src1Value may be a ConstantInt, but we're missing it.
    1367          40 :   if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
    1368          40 :     if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
    1369           0 :         SrcVT == MVT::i1) {
    1370          40 :       const APInt &CIVal = ConstInt->getValue();
    1371          80 :       Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
    1372             :       // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
    1373             :       // then a cmn, because there is no way to represent 2147483648 as a
    1374             :       // signed 32-bit int.
    1375          40 :       if (Imm < 0 && Imm != (int)0x80000000) {
    1376           9 :         isNegativeImm = true;
    1377           9 :         Imm = -Imm;
    1378             :       }
    1379          64 :       UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
    1380          24 :         (ARM_AM::getSOImmVal(Imm) != -1);
    1381             :     }
    1382          22 :   } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
    1383          22 :     if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
    1384          42 :       if (ConstFP->isZero() && !ConstFP->isNegative())
    1385             :         UseImm = true;
    1386             :   }
    1387             : 
    1388             :   unsigned CmpOpc;
    1389          83 :   bool isICmp = true;
    1390          83 :   bool needsExt = false;
    1391          83 :   switch (SrcVT.SimpleTy) {
    1392             :     default: return false;
    1393             :     // TODO: Verify compares.
    1394          16 :     case MVT::f32:
    1395          16 :       isICmp = false;
    1396             :       // Equality comparisons shouldn't raise Invalid on uordered inputs.
    1397          16 :       if (isEquality)
    1398          14 :         CmpOpc = UseImm ? ARM::VCMPZS : ARM::VCMPS;
    1399             :       else
    1400           2 :         CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
    1401             :       break;
    1402           6 :     case MVT::f64:
    1403           6 :       isICmp = false;
    1404             :       // Equality comparisons shouldn't raise Invalid on uordered inputs.
    1405           6 :       if (isEquality)
    1406           6 :         CmpOpc = UseImm ? ARM::VCMPZD : ARM::VCMPD;
    1407             :       else
    1408           0 :       CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
    1409             :       break;
    1410          30 :     case MVT::i1:
    1411             :     case MVT::i8:
    1412             :     case MVT::i16:
    1413          30 :       needsExt = true;
    1414             :     // Intentional fall-through.
    1415          61 :     case MVT::i32:
    1416          61 :       if (isThumb2) {
    1417          22 :         if (!UseImm)
    1418             :           CmpOpc = ARM::t2CMPrr;
    1419             :         else
    1420          15 :           CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
    1421             :       } else {
    1422          39 :         if (!UseImm)
    1423             :           CmpOpc = ARM::CMPrr;
    1424             :         else
    1425          24 :           CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
    1426             :       }
    1427             :       break;
    1428             :   }
    1429             : 
    1430          83 :   unsigned SrcReg1 = getRegForValue(Src1Value);
    1431          83 :   if (SrcReg1 == 0) return false;
    1432             : 
    1433          83 :   unsigned SrcReg2 = 0;
    1434          83 :   if (!UseImm) {
    1435          30 :     SrcReg2 = getRegForValue(Src2Value);
    1436          30 :     if (SrcReg2 == 0) return false;
    1437             :   }
    1438             : 
    1439             :   // We have i1, i8, or i16, we need to either zero extend or sign extend.
    1440          83 :   if (needsExt) {
    1441          60 :     SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
    1442          30 :     if (SrcReg1 == 0) return false;
    1443          30 :     if (!UseImm) {
    1444          30 :       SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
    1445          15 :       if (SrcReg2 == 0) return false;
    1446             :     }
    1447             :   }
    1448             : 
    1449         166 :   const MCInstrDesc &II = TII.get(CmpOpc);
    1450          83 :   SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
    1451          83 :   if (!UseImm) {
    1452          30 :     SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
    1453          60 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
    1454          30 :                     .addReg(SrcReg1).addReg(SrcReg2));
    1455             :   } else {
    1456          53 :     MachineInstrBuilder MIB;
    1457         106 :     MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
    1458          53 :       .addReg(SrcReg1);
    1459             : 
    1460             :     // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
    1461          53 :     if (isICmp)
    1462          39 :       MIB.addImm(Imm);
    1463          53 :     AddOptionalDefs(MIB);
    1464             :   }
    1465             : 
    1466             :   // For floating point we need to move the result to a comparison register
    1467             :   // that we can then use for branches.
    1468         150 :   if (Ty->isFloatTy() || Ty->isDoubleTy())
    1469          22 :     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    1470          44 :                             TII.get(ARM::FMSTAT)));
    1471             :   return true;
    1472             : }
    1473             : 
    1474          26 : bool ARMFastISel::SelectCmp(const Instruction *I) {
    1475          26 :   const CmpInst *CI = cast<CmpInst>(I);
    1476             : 
    1477             :   // Get the compare predicate.
    1478          26 :   ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
    1479             : 
    1480             :   // We may not handle every CC for now.
    1481          26 :   if (ARMPred == ARMCC::AL) return false;
    1482             : 
    1483             :   // Emit the compare.
    1484         104 :   if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
    1485          26 :                   CI->isEquality()))
    1486             :     return false;
    1487             : 
    1488             :   // Now set a register based on the comparison. Explicitly set the predicates
    1489             :   // here.
    1490          25 :   unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
    1491          25 :   const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
    1492             :                                            : &ARM::GPRRegClass;
    1493          25 :   unsigned DestReg = createResultReg(RC);
    1494          25 :   Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
    1495          25 :   unsigned ZeroReg = fastMaterializeConstant(Zero);
    1496             :   // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
    1497          75 :   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg)
    1498          50 :           .addReg(ZeroReg).addImm(1)
    1499          50 :           .addImm(ARMPred).addReg(ARM::CPSR);
    1500             : 
    1501          25 :   updateValueMap(I, DestReg);
    1502          25 :   return true;
    1503             : }
    1504             : 
    1505           1 : bool ARMFastISel::SelectFPExt(const Instruction *I) {
    1506             :   // Make sure we have VFP and that we're extending float to double.
    1507           1 :   if (!Subtarget->hasVFP2() || Subtarget->isFPOnlySP()) return false;
    1508             : 
    1509           0 :   Value *V = I->getOperand(0);
    1510           0 :   if (!I->getType()->isDoubleTy() ||
    1511           0 :       !V->getType()->isFloatTy()) return false;
    1512             : 
    1513           0 :   unsigned Op = getRegForValue(V);
    1514           0 :   if (Op == 0) return false;
    1515             : 
    1516           0 :   unsigned Result = createResultReg(&ARM::DPRRegClass);
    1517           0 :   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    1518           0 :                           TII.get(ARM::VCVTDS), Result)
    1519           0 :                   .addReg(Op));
    1520           0 :   updateValueMap(I, Result);
    1521           0 :   return true;
    1522             : }
    1523             : 
    1524           1 : bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
    1525             :   // Make sure we have VFP and that we're truncating double to float.
    1526           1 :   if (!Subtarget->hasVFP2() || Subtarget->isFPOnlySP()) return false;
    1527             : 
    1528           0 :   Value *V = I->getOperand(0);
    1529           0 :   if (!(I->getType()->isFloatTy() &&
    1530           0 :         V->getType()->isDoubleTy())) return false;
    1531             : 
    1532           0 :   unsigned Op = getRegForValue(V);
    1533           0 :   if (Op == 0) return false;
    1534             : 
    1535           0 :   unsigned Result = createResultReg(&ARM::SPRRegClass);
    1536           0 :   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    1537           0 :                           TII.get(ARM::VCVTSD), Result)
    1538           0 :                   .addReg(Op));
    1539           0 :   updateValueMap(I, Result);
    1540           0 :   return true;
    1541             : }
    1542             : 
    1543          37 : bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
    1544             :   // Make sure we have VFP.
    1545          37 :   if (!Subtarget->hasVFP2()) return false;
    1546             : 
    1547          37 :   MVT DstVT;
    1548          37 :   Type *Ty = I->getType();
    1549          37 :   if (!isTypeLegal(Ty, DstVT))
    1550             :     return false;
    1551             : 
    1552          74 :   Value *Src = I->getOperand(0);
    1553          37 :   EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
    1554          37 :   if (!SrcEVT.isSimple())
    1555             :     return false;
    1556          37 :   MVT SrcVT = SrcEVT.getSimpleVT();
    1557          37 :   if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
    1558             :     return false;
    1559             : 
    1560          37 :   unsigned SrcReg = getRegForValue(Src);
    1561          37 :   if (SrcReg == 0) return false;
    1562             : 
    1563             :   // Handle sign-extension.
    1564          37 :   if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
    1565          48 :     SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
    1566          48 :                                        /*isZExt*/!isSigned);
    1567          24 :     if (SrcReg == 0) return false;
    1568             :   }
    1569             : 
    1570             :   // The conversion routine works on fp-reg to fp-reg and the operand above
    1571             :   // was an integer, move it to the fp registers if possible.
    1572          37 :   unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
    1573          37 :   if (FP == 0) return false;
    1574             : 
    1575             :   unsigned Opc;
    1576          37 :   if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
    1577          19 :   else if (Ty->isDoubleTy() && !Subtarget->isFPOnlySP())
    1578          18 :     Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
    1579             :   else return false;
    1580             : 
    1581          36 :   unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
    1582          72 :   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    1583         108 :                           TII.get(Opc), ResultReg).addReg(FP));
    1584          36 :   updateValueMap(I, ResultReg);
    1585          36 :   return true;
    1586             : }
    1587             : 
    1588          13 : bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
    1589             :   // Make sure we have VFP.
    1590          13 :   if (!Subtarget->hasVFP2()) return false;
    1591             : 
    1592          13 :   MVT DstVT;
    1593          13 :   Type *RetTy = I->getType();
    1594          13 :   if (!isTypeLegal(RetTy, DstVT))
    1595             :     return false;
    1596             : 
    1597          26 :   unsigned Op = getRegForValue(I->getOperand(0));
    1598          13 :   if (Op == 0) return false;
    1599             : 
    1600             :   unsigned Opc;
    1601          26 :   Type *OpTy = I->getOperand(0)->getType();
    1602          13 :   if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
    1603           7 :   else if (OpTy->isDoubleTy() && !Subtarget->isFPOnlySP())
    1604           6 :     Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
    1605             :   else return false;
    1606             : 
    1607             :   // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
    1608          24 :   unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
    1609          24 :   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    1610          36 :                           TII.get(Opc), ResultReg).addReg(Op));
    1611             : 
    1612             :   // This result needs to be in an integer register, but the conversion only
    1613             :   // takes place in fp-regs.
    1614          12 :   unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
    1615          12 :   if (IntReg == 0) return false;
    1616             : 
    1617          12 :   updateValueMap(I, IntReg);
    1618          12 :   return true;
    1619             : }
    1620             : 
    1621          24 : bool ARMFastISel::SelectSelect(const Instruction *I) {
    1622          24 :   MVT VT;
    1623          24 :   if (!isTypeLegal(I->getType(), VT))
    1624             :     return false;
    1625             : 
    1626             :   // Things need to be register sized for register moves.
    1627          48 :   if (VT != MVT::i32) return false;
    1628             : 
    1629          48 :   unsigned CondReg = getRegForValue(I->getOperand(0));
    1630          24 :   if (CondReg == 0) return false;
    1631          48 :   unsigned Op1Reg = getRegForValue(I->getOperand(1));
    1632          24 :   if (Op1Reg == 0) return false;
    1633             : 
    1634             :   // Check to see if we can use an immediate in the conditional move.
    1635          24 :   int Imm = 0;
    1636          24 :   bool UseImm = false;
    1637          24 :   bool isNegativeImm = false;
    1638          68 :   if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
    1639             :     assert(VT == MVT::i32 && "Expecting an i32.");
    1640          40 :     Imm = (int)ConstInt->getValue().getZExtValue();
    1641          20 :     if (Imm < 0) {
    1642          12 :       isNegativeImm = true;
    1643          12 :       Imm = ~Imm;
    1644             :     }
    1645          30 :     UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
    1646          10 :       (ARM_AM::getSOImmVal(Imm) != -1);
    1647             :   }
    1648             : 
    1649          24 :   unsigned Op2Reg = 0;
    1650          24 :   if (!UseImm) {
    1651           8 :     Op2Reg = getRegForValue(I->getOperand(2));
    1652           4 :     if (Op2Reg == 0) return false;
    1653             :   }
    1654             : 
    1655          24 :   unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
    1656          48 :   CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0);
    1657          24 :   AddOptionalDefs(
    1658          72 :       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
    1659          24 :           .addReg(CondReg)
    1660          24 :           .addImm(1));
    1661             : 
    1662             :   unsigned MovCCOpc;
    1663             :   const TargetRegisterClass *RC;
    1664          24 :   if (!UseImm) {
    1665           4 :     RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
    1666           4 :     MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
    1667             :   } else {
    1668          20 :     RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
    1669          20 :     if (!isNegativeImm)
    1670           8 :       MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
    1671             :     else
    1672          12 :       MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
    1673             :   }
    1674          24 :   unsigned ResultReg = createResultReg(RC);
    1675          24 :   if (!UseImm) {
    1676           8 :     Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
    1677           8 :     Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
    1678          12 :     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
    1679           8 :             ResultReg)
    1680           4 :         .addReg(Op2Reg)
    1681           4 :         .addReg(Op1Reg)
    1682           4 :         .addImm(ARMCC::NE)
    1683           4 :         .addReg(ARM::CPSR);
    1684             :   } else {
    1685          40 :     Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
    1686          60 :     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
    1687          40 :             ResultReg)
    1688          20 :         .addReg(Op1Reg)
    1689          40 :         .addImm(Imm)
    1690          20 :         .addImm(ARMCC::EQ)
    1691          20 :         .addReg(ARM::CPSR);
    1692             :   }
    1693          24 :   updateValueMap(I, ResultReg);
    1694          24 :   return true;
    1695             : }
    1696             : 
    1697          14 : bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
    1698          14 :   MVT VT;
    1699          14 :   Type *Ty = I->getType();
    1700          14 :   if (!isTypeLegal(Ty, VT))
    1701             :     return false;
    1702             : 
    1703             :   // If we have integer div support we should have selected this automagically.
    1704             :   // In case we have a real miss go ahead and return false and we'll pick
    1705             :   // it up later.
    1706          14 :   if (Subtarget->hasDivideInThumbMode())
    1707             :     return false;
    1708             : 
    1709             :   // Otherwise emit a libcall.
    1710          14 :   RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
    1711          28 :   if (VT == MVT::i8)
    1712           0 :     LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
    1713          14 :   else if (VT == MVT::i16)
    1714           0 :     LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
    1715          14 :   else if (VT == MVT::i32)
    1716          14 :     LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
    1717           0 :   else if (VT == MVT::i64)
    1718           0 :     LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
    1719           0 :   else if (VT == MVT::i128)
    1720           0 :     LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
    1721             :   assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
    1722             : 
    1723          14 :   return ARMEmitLibcall(I, LC);
    1724             : }
    1725             : 
    1726          36 : bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
    1727          36 :   MVT VT;
    1728          36 :   Type *Ty = I->getType();
    1729          36 :   if (!isTypeLegal(Ty, VT))
    1730             :     return false;
    1731             : 
    1732             :   // Many ABIs do not provide a libcall for standalone remainder, so we need to
    1733             :   // use divrem (see the RTABI 4.3.1). Since FastISel can't handle non-double
    1734             :   // multi-reg returns, we'll have to bail out.
    1735          64 :   if (!TLI.hasStandaloneRem(VT)) {
    1736             :     return false;
    1737             :   }
    1738             : 
    1739          11 :   RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
    1740          22 :   if (VT == MVT::i8)
    1741           0 :     LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
    1742          11 :   else if (VT == MVT::i16)
    1743           0 :     LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
    1744          11 :   else if (VT == MVT::i32)
    1745          11 :     LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
    1746           0 :   else if (VT == MVT::i64)
    1747           0 :     LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
    1748           0 :   else if (VT == MVT::i128)
    1749           0 :     LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
    1750             :   assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
    1751             : 
    1752          11 :   return ARMEmitLibcall(I, LC);
    1753             : }
    1754             : 
    1755          37 : bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
    1756          37 :   EVT DestVT = TLI.getValueType(DL, I->getType(), true);
    1757             : 
    1758             :   // We can get here in the case when we have a binary operation on a non-legal
    1759             :   // type and the target independent selector doesn't know how to handle it.
    1760          64 :   if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
    1761             :     return false;
    1762             : 
    1763             :   unsigned Opc;
    1764          36 :   switch (ISDOpcode) {
    1765             :     default: return false;
    1766          21 :     case ISD::ADD:
    1767          21 :       Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
    1768             :       break;
    1769           6 :     case ISD::OR:
    1770           6 :       Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
    1771             :       break;
    1772           9 :     case ISD::SUB:
    1773           9 :       Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
    1774             :       break;
    1775             :   }
    1776             : 
    1777          72 :   unsigned SrcReg1 = getRegForValue(I->getOperand(0));
    1778          36 :   if (SrcReg1 == 0) return false;
    1779             : 
    1780             :   // TODO: Often the 2nd operand is an immediate, which can be encoded directly
    1781             :   // in the instruction, rather then materializing the value in a register.
    1782          72 :   unsigned SrcReg2 = getRegForValue(I->getOperand(1));
    1783          36 :   if (SrcReg2 == 0) return false;
    1784             : 
    1785          36 :   unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
    1786          72 :   SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
    1787          72 :   SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
    1788          72 :   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    1789          72 :                           TII.get(Opc), ResultReg)
    1790          36 :                   .addReg(SrcReg1).addReg(SrcReg2));
    1791          36 :   updateValueMap(I, ResultReg);
    1792          36 :   return true;
    1793             : }
    1794             : 
    1795           2 : bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
    1796           2 :   EVT FPVT = TLI.getValueType(DL, I->getType(), true);
    1797           2 :   if (!FPVT.isSimple()) return false;
    1798           2 :   MVT VT = FPVT.getSimpleVT();
    1799             : 
    1800             :   // FIXME: Support vector types where possible.
    1801           2 :   if (VT.isVector())
    1802             :     return false;
    1803             : 
    1804             :   // We can get here in the case when we want to use NEON for our fp
    1805             :   // operations, but can't figure out how to. Just use the vfp instructions
    1806             :   // if we have them.
    1807             :   // FIXME: It'd be nice to use NEON instructions.
    1808           1 :   Type *Ty = I->getType();
    1809           1 :   if (Ty->isFloatTy() && !Subtarget->hasVFP2())
    1810             :     return false;
    1811           1 :   if (Ty->isDoubleTy() && (!Subtarget->hasVFP2() || Subtarget->isFPOnlySP()))
    1812             :     return false;
    1813             : 
    1814             :   unsigned Opc;
    1815           0 :   bool is64bit = VT == MVT::f64 || VT == MVT::i64;
    1816           0 :   switch (ISDOpcode) {
    1817             :     default: return false;
    1818           0 :     case ISD::FADD:
    1819           0 :       Opc = is64bit ? ARM::VADDD : ARM::VADDS;
    1820             :       break;
    1821           0 :     case ISD::FSUB:
    1822           0 :       Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
    1823             :       break;
    1824           0 :     case ISD::FMUL:
    1825           0 :       Opc = is64bit ? ARM::VMULD : ARM::VMULS;
    1826             :       break;
    1827             :   }
    1828           0 :   unsigned Op1 = getRegForValue(I->getOperand(0));
    1829           0 :   if (Op1 == 0) return false;
    1830             : 
    1831           0 :   unsigned Op2 = getRegForValue(I->getOperand(1));
    1832           0 :   if (Op2 == 0) return false;
    1833             : 
    1834           0 :   unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
    1835           0 :   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    1836           0 :                           TII.get(Opc), ResultReg)
    1837           0 :                   .addReg(Op1).addReg(Op2));
    1838           0 :   updateValueMap(I, ResultReg);
    1839           0 :   return true;
    1840             : }
    1841             : 
    1842             : // Call Handling Code
    1843             : 
    1844             : // This is largely taken directly from CCAssignFnForNode
    1845             : // TODO: We may not support all of this.
    1846        1153 : CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
    1847             :                                            bool Return,
    1848             :                                            bool isVarArg) {
    1849        1153 :   switch (CC) {
    1850           0 :   default:
    1851           0 :     report_fatal_error("Unsupported calling convention");
    1852           7 :   case CallingConv::Fast:
    1853           7 :     if (Subtarget->hasVFP2() && !isVarArg) {
    1854           7 :       if (!Subtarget->isAAPCS_ABI())
    1855           5 :         return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
    1856             :       // For AAPCS ABI targets, just use VFP variant of the calling convention.
    1857           2 :       return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
    1858             :     }
    1859             :     LLVM_FALLTHROUGH;
    1860             :   case CallingConv::C:
    1861             :   case CallingConv::CXX_FAST_TLS:
    1862             :     // Use target triple & subtarget features to do actual dispatch.
    1863        1109 :     if (Subtarget->isAAPCS_ABI()) {
    1864         551 :       if (Subtarget->hasVFP2() &&
    1865         307 :           TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
    1866          10 :         return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
    1867             :       else
    1868         287 :         return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
    1869             :     } else {
    1870         812 :       return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
    1871             :     }
    1872          30 :   case CallingConv::ARM_AAPCS_VFP:
    1873             :   case CallingConv::Swift:
    1874          30 :     if (!isVarArg)
    1875          30 :       return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
    1876             :     // Fall through to soft float variant, variadic functions don't
    1877             :     // use hard floating point ABI.
    1878             :     LLVM_FALLTHROUGH;
    1879             :   case CallingConv::ARM_AAPCS:
    1880           6 :     return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
    1881           1 :   case CallingConv::ARM_APCS:
    1882           1 :     return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
    1883           0 :   case CallingConv::GHC:
    1884           0 :     if (Return)
    1885           0 :       report_fatal_error("Can't return in GHC call convention");
    1886             :     else
    1887             :       return CC_ARM_APCS_GHC;
    1888             :   }
    1889             : }
    1890             : 
    1891         476 : bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
    1892             :                                   SmallVectorImpl<unsigned> &ArgRegs,
    1893             :                                   SmallVectorImpl<MVT> &ArgVTs,
    1894             :                                   SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
    1895             :                                   SmallVectorImpl<unsigned> &RegArgs,
    1896             :                                   CallingConv::ID CC,
    1897             :                                   unsigned &NumBytes,
    1898             :                                   bool isVarArg) {
    1899         952 :   SmallVector<CCValAssign, 16> ArgLocs;
    1900         952 :   CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context);
    1901         476 :   CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
    1902             :                              CCAssignFnForCall(CC, false, isVarArg));
    1903             : 
    1904             :   // Check that we can handle all of the arguments. If we can't, then bail out
    1905             :   // now before we add code to the MBB.
    1906        2261 :   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
    1907        2630 :     CCValAssign &VA = ArgLocs[i];
    1908        2630 :     MVT ArgVT = ArgVTs[VA.getValNo()];
    1909             : 
    1910             :     // We don't handle NEON/vector parameters yet.
    1911        1315 :     if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
    1912           6 :       return false;
    1913             : 
    1914             :     // Now copy/store arg to correct locations.
    1915        2803 :     if (VA.isRegLoc() && !VA.needsCustom()) {
    1916         746 :       continue;
    1917         564 :     } else if (VA.needsCustom()) {
    1918             :       // TODO: We need custom lowering for vector (v2f64) args.
    1919           2 :       if (VA.getLocVT() != MVT::f64 ||
    1920             :           // TODO: Only handle register args for now.
    1921           4 :           !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
    1922             :         return false;
    1923             :     } else {
    1924         563 :       switch (ArgVT.SimpleTy) {
    1925             :       default:
    1926             :         return false;
    1927             :       case MVT::i1:
    1928             :       case MVT::i8:
    1929             :       case MVT::i16:
    1930             :       case MVT::i32:
    1931             :         break;
    1932           4 :       case MVT::f32:
    1933           4 :         if (!Subtarget->hasVFP2())
    1934             :           return false;
    1935             :         break;
    1936         417 :       case MVT::f64:
    1937         417 :         if (!Subtarget->hasVFP2())
    1938             :           return false;
    1939             :         break;
    1940             :       }
    1941             :     }
    1942             :   }
    1943             : 
    1944             :   // At the point, we are able to handle the call's arguments in fast isel.
    1945             : 
    1946             :   // Get a count of how many bytes are to be pushed on the stack.
    1947         470 :   NumBytes = CCInfo.getNextStackOffset();
    1948             : 
    1949             :   // Issue CALLSEQ_START
    1950         470 :   unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
    1951         940 :   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    1952         940 :                           TII.get(AdjStackDown))
    1953        1410 :                   .addImm(NumBytes).addImm(0));
    1954             : 
    1955             :   // Process the args.
    1956        2240 :   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
    1957        2600 :     CCValAssign &VA = ArgLocs[i];
    1958        2600 :     const Value *ArgVal = Args[VA.getValNo()];
    1959        2600 :     unsigned Arg = ArgRegs[VA.getValNo()];
    1960        2600 :     MVT ArgVT = ArgVTs[VA.getValNo()];
    1961             : 
    1962             :     assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
    1963             :            "We don't handle NEON/vector parameters yet.");
    1964             : 
    1965             :     // Handle arg promotion, etc.
    1966        1300 :     switch (VA.getLocInfo()) {
    1967             :       case CCValAssign::Full: break;
    1968          18 :       case CCValAssign::SExt: {
    1969          18 :         MVT DestVT = VA.getLocVT();
    1970          18 :         Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
    1971             :         assert(Arg != 0 && "Failed to emit a sext");
    1972          18 :         ArgVT = DestVT;
    1973             :         break;
    1974             :       }
    1975         115 :       case CCValAssign::AExt:
    1976             :       // Intentional fall-through.  Handle AExt and ZExt.
    1977             :       case CCValAssign::ZExt: {
    1978         115 :         MVT DestVT = VA.getLocVT();
    1979         115 :         Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
    1980             :         assert(Arg != 0 && "Failed to emit a zext");
    1981         115 :         ArgVT = DestVT;
    1982             :         break;
    1983             :       }
    1984          81 :       case CCValAssign::BCvt: {
    1985             :         unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
    1986          81 :                                  /*TODO: Kill=*/false);
    1987             :         assert(BC != 0 && "Failed to emit a bitcast!");
    1988          81 :         Arg = BC;
    1989          81 :         ArgVT = VA.getLocVT();
    1990          81 :         break;
    1991             :       }
    1992           0 :       default: llvm_unreachable("Unknown arg promotion!");
    1993             :     }
    1994             : 
    1995             :     // Now copy/store arg to correct locations.
    1996        2039 :     if (VA.isRegLoc() && !VA.needsCustom()) {
    1997        1478 :       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    1998        2217 :               TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
    1999         739 :       RegArgs.push_back(VA.getLocReg());
    2000         561 :     } else if (VA.needsCustom()) {
    2001             :       // TODO: We need custom lowering for vector (v2f64) args.
    2002             :       assert(VA.getLocVT() == MVT::f64 &&
    2003             :              "Custom lowering for v2f64 args not available");
    2004             : 
    2005             :       // FIXME: ArgLocs[++i] may extend beyond ArgLocs.size()
    2006           0 :       CCValAssign &NextVA = ArgLocs[++i];
    2007             : 
    2008             :       assert(VA.isRegLoc() && NextVA.isRegLoc() &&
    2009             :              "We only handle register args!");
    2010             : 
    2011           0 :       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    2012           0 :                               TII.get(ARM::VMOVRRD), VA.getLocReg())
    2013           0 :                       .addReg(NextVA.getLocReg(), RegState::Define)
    2014           0 :                       .addReg(Arg));
    2015           0 :       RegArgs.push_back(VA.getLocReg());
    2016           0 :       RegArgs.push_back(NextVA.getLocReg());
    2017             :     } else {
    2018             :       assert(VA.isMemLoc());
    2019             :       // Need to store on the stack.
    2020             : 
    2021             :       // Don't emit stores for undef values.
    2022        1122 :       if (isa<UndefValue>(ArgVal))
    2023          11 :         continue;
    2024             : 
    2025         550 :       Address Addr;
    2026             :       Addr.BaseType = Address::RegBase;
    2027         550 :       Addr.Base.Reg = ARM::SP;
    2028         550 :       Addr.Offset = VA.getLocMemOffset();
    2029             : 
    2030         550 :       bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
    2031             :       assert(EmitRet && "Could not emit a store for argument!");
    2032             :     }
    2033             :   }
    2034             : 
    2035             :   return true;
    2036             : }
    2037             : 
    2038         470 : bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
    2039             :                              const Instruction *I, CallingConv::ID CC,
    2040             :                              unsigned &NumBytes, bool isVarArg) {
    2041             :   // Issue CALLSEQ_END
    2042         470 :   unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
    2043         940 :   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    2044         940 :                           TII.get(AdjStackUp))
    2045        1410 :                   .addImm(NumBytes).addImm(0));
    2046             : 
    2047             :   // Now the return value.
    2048         470 :   if (RetVT != MVT::isVoid) {
    2049         458 :     SmallVector<CCValAssign, 16> RVLocs;
    2050         458 :     CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
    2051         229 :     CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
    2052             : 
    2053             :     // Copy all of the result registers out of their specified physreg.
    2054         229 :     if (RVLocs.size() == 2 && RetVT == MVT::f64) {
    2055             :       // For this move we copy into two registers and then move into the
    2056             :       // double fp reg we want.
    2057           0 :       MVT DestVT = RVLocs[0].getValVT();
    2058           0 :       const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
    2059           0 :       unsigned ResultReg = createResultReg(DstRC);
    2060           0 :       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    2061           0 :                               TII.get(ARM::VMOVDRR), ResultReg)
    2062           0 :                       .addReg(RVLocs[0].getLocReg())
    2063           0 :                       .addReg(RVLocs[1].getLocReg()));
    2064             : 
    2065           0 :       UsedRegs.push_back(RVLocs[0].getLocReg());
    2066           0 :       UsedRegs.push_back(RVLocs[1].getLocReg());
    2067             : 
    2068             :       // Finally update the result.
    2069           0 :       updateValueMap(I, ResultReg);
    2070             :     } else {
    2071             :       assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
    2072         229 :       MVT CopyVT = RVLocs[0].getValVT();
    2073             : 
    2074             :       // Special handling for extended integers.
    2075         229 :       if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
    2076          45 :         CopyVT = MVT::i32;
    2077             : 
    2078         229 :       const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
    2079             : 
    2080         229 :       unsigned ResultReg = createResultReg(DstRC);
    2081         458 :       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    2082         229 :               TII.get(TargetOpcode::COPY),
    2083         687 :               ResultReg).addReg(RVLocs[0].getLocReg());
    2084         458 :       UsedRegs.push_back(RVLocs[0].getLocReg());
    2085             : 
    2086             :       // Finally update the result.
    2087         229 :       updateValueMap(I, ResultReg);
    2088             :     }
    2089             :   }
    2090             : 
    2091         470 :   return true;
    2092             : }
    2093             : 
    2094         889 : bool ARMFastISel::SelectRet(const Instruction *I) {
    2095         889 :   const ReturnInst *Ret = cast<ReturnInst>(I);
    2096         889 :   const Function &F = *I->getParent()->getParent();
    2097             : 
    2098         889 :   if (!FuncInfo.CanLowerReturn)
    2099             :     return false;
    2100             : 
    2101        1774 :   if (TLI.supportSwiftError() &&
    2102         899 :       F.getAttributes().hasAttrSomewhere(Attribute::SwiftError))
    2103             :     return false;
    2104             : 
    2105         875 :   if (TLI.supportSplitCSR(FuncInfo.MF))
    2106             :     return false;
    2107             : 
    2108             :   // Build a list of return value registers.
    2109         869 :   SmallVector<unsigned, 4> RetRegs;
    2110             : 
    2111         869 :   CallingConv::ID CC = F.getCallingConv();
    2112         869 :   if (Ret->getNumOperands() > 0) {
    2113         856 :     SmallVector<ISD::OutputArg, 4> Outs;
    2114         890 :     GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
    2115             : 
    2116             :     // Analyze operands of the call, assigning locations to each operand.
    2117         856 :     SmallVector<CCValAssign, 16> ValLocs;
    2118        1301 :     CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
    2119         445 :     CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
    2120         445 :                                                  F.isVarArg()));
    2121             : 
    2122         445 :     const Value *RV = Ret->getOperand(0);
    2123         445 :     unsigned Reg = getRegForValue(RV);
    2124         445 :     if (Reg == 0)
    2125          34 :       return false;
    2126             : 
    2127             :     // Only handle a single return value for now.
    2128         419 :     if (ValLocs.size() != 1)
    2129             :       return false;
    2130             : 
    2131         418 :     CCValAssign &VA = ValLocs[0];
    2132             : 
    2133             :     // Don't bother handling odd stuff for now.
    2134         418 :     if (VA.getLocInfo() != CCValAssign::Full)
    2135             :       return false;
    2136             :     // Only handle register returns for now.
    2137         411 :     if (!VA.isRegLoc())
    2138             :       return false;
    2139             : 
    2140         411 :     unsigned SrcReg = Reg + VA.getValNo();
    2141         411 :     EVT RVEVT = TLI.getValueType(DL, RV->getType());
    2142         411 :     if (!RVEVT.isSimple()) return false;
    2143         411 :     MVT RVVT = RVEVT.getSimpleVT();
    2144         411 :     MVT DestVT = VA.getValVT();
    2145             :     // Special handling for extended integers.
    2146         411 :     if (RVVT != DestVT) {
    2147          99 :       if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
    2148             :         return false;
    2149             : 
    2150             :       assert(DestVT == MVT::i32 && "ARM should always ext to i32");
    2151             : 
    2152             :       // Perform extension if flagged as either zext or sext.  Otherwise, do
    2153             :       // nothing.
    2154         308 :       if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
    2155         120 :         SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
    2156          60 :         if (SrcReg == 0) return false;
    2157             :       }
    2158             :     }
    2159             : 
    2160             :     // Make the copy.
    2161         411 :     unsigned DstReg = VA.getLocReg();
    2162         822 :     const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
    2163             :     // Avoid a cross-class copy. This is very unlikely.
    2164         822 :     if (!SrcRC->contains(DstReg))
    2165             :       return false;
    2166         822 :     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    2167        1233 :             TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
    2168             : 
    2169             :     // Add register to return instruction.
    2170         411 :     RetRegs.push_back(VA.getLocReg());
    2171             :   }
    2172             : 
    2173         835 :   MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    2174        3340 :                                     TII.get(Subtarget->getReturnOpcode()));
    2175         835 :   AddOptionalDefs(MIB);
    2176        2916 :   for (unsigned R : RetRegs)
    2177         411 :     MIB.addReg(R, RegState::Implicit);
    2178             :   return true;
    2179             : }
    2180             : 
    2181             : unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
    2182         470 :   if (UseReg)
    2183          82 :     return isThumb2 ? ARM::tBLXr : ARM::BLX;
    2184             :   else
    2185         388 :     return isThumb2 ? ARM::tBL : ARM::BL;
    2186             : }
    2187             : 
    2188          12 : unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
    2189             :   // Manually compute the global's type to avoid building it when unnecessary.
    2190          12 :   Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0);
    2191          12 :   EVT LCREVT = TLI.getValueType(DL, GVTy);
    2192          12 :   if (!LCREVT.isSimple()) return 0;
    2193             : 
    2194          12 :   GlobalValue *GV = new GlobalVariable(M, Type::getInt32Ty(*Context), false,
    2195             :                                        GlobalValue::ExternalLinkage, nullptr,
    2196          12 :                                        Name);
    2197             :   assert(GV->getType() == GVTy && "We miscomputed the type for the global!");
    2198          12 :   return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
    2199             : }
    2200             : 
    2201             : // A quick function that will emit a call for a named libcall in F with the
    2202             : // vector of passed arguments for the Instruction in I. We can assume that we
    2203             : // can emit a call for any libcall we can produce. This is an abridged version
    2204             : // of the full call infrastructure since we won't need to worry about things
    2205             : // like computed function pointers or strange arguments at call sites.
    2206             : // TODO: Try to unify this and the normal call bits for ARM, then try to unify
    2207             : // with X86.
    2208          25 : bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
    2209          50 :   CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
    2210             : 
    2211             :   // Handle *simple* calls for now.
    2212          25 :   Type *RetTy = I->getType();
    2213          25 :   MVT RetVT;
    2214          25 :   if (RetTy->isVoidTy())
    2215           0 :     RetVT = MVT::isVoid;
    2216          25 :   else if (!isTypeLegal(RetTy, RetVT))
    2217             :     return false;
    2218             : 
    2219             :   // Can't handle non-double multi-reg retvals.
    2220          50 :   if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
    2221           0 :     SmallVector<CCValAssign, 16> RVLocs;
    2222           0 :     CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
    2223           0 :     CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
    2224           0 :     if (RVLocs.size() >= 2 && RetVT != MVT::f64)
    2225           0 :       return false;
    2226             :   }
    2227             : 
    2228             :   // Set up the argument vectors.
    2229          25 :   SmallVector<Value*, 8> Args;
    2230          50 :   SmallVector<unsigned, 8> ArgRegs;
    2231          50 :   SmallVector<MVT, 8> ArgVTs;
    2232          50 :   SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
    2233          50 :   Args.reserve(I->getNumOperands());
    2234          50 :   ArgRegs.reserve(I->getNumOperands());
    2235          75 :   ArgVTs.reserve(I->getNumOperands());
    2236          50 :   ArgFlags.reserve(I->getNumOperands());
    2237         100 :   for (Value *Op :  I->operands()) {
    2238          50 :     unsigned Arg = getRegForValue(Op);
    2239          50 :     if (Arg == 0) return false;
    2240             : 
    2241          50 :     Type *ArgTy = Op->getType();
    2242          50 :     MVT ArgVT;
    2243          50 :     if (!isTypeLegal(ArgTy, ArgVT)) return false;
    2244             : 
    2245          50 :     ISD::ArgFlagsTy Flags;
    2246          50 :     unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
    2247          50 :     Flags.setOrigAlign(OriginalAlignment);
    2248             : 
    2249          50 :     Args.push_back(Op);
    2250          50 :     ArgRegs.push_back(Arg);
    2251          50 :     ArgVTs.push_back(ArgVT);
    2252          50 :     ArgFlags.push_back(Flags);
    2253             :   }
    2254             : 
    2255             :   // Handle the arguments now that we've gotten them.
    2256          25 :   SmallVector<unsigned, 4> RegArgs;
    2257             :   unsigned NumBytes;
    2258          25 :   if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
    2259             :                        RegArgs, CC, NumBytes, false))
    2260             :     return false;
    2261             : 
    2262          25 :   unsigned CalleeReg = 0;
    2263          25 :   if (Subtarget->genLongCalls()) {
    2264           9 :     CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
    2265           3 :     if (CalleeReg == 0) return false;
    2266             :   }
    2267             : 
    2268             :   // Issue the call.
    2269          50 :   unsigned CallOpc = ARMSelectCallOp(Subtarget->genLongCalls());
    2270          25 :   MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
    2271          75 :                                     DbgLoc, TII.get(CallOpc));
    2272             :   // BL / BLX don't take a predicate, but tBL / tBLX do.
    2273          25 :   if (isThumb2)
    2274           9 :     MIB.add(predOps(ARMCC::AL));
    2275          25 :   if (Subtarget->genLongCalls())
    2276           3 :     MIB.addReg(CalleeReg);
    2277             :   else
    2278          44 :     MIB.addExternalSymbol(TLI.getLibcallName(Call));
    2279             : 
    2280             :   // Add implicit physical register uses to the call.
    2281         125 :   for (unsigned R : RegArgs)
    2282          50 :     MIB.addReg(R, RegState::Implicit);
    2283             : 
    2284             :   // Add a register mask with the call-preserved registers.
    2285             :   // Proper defs for return values will be added by setPhysRegsDeadExcept().
    2286          50 :   MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
    2287             : 
    2288             :   // Finish off the call including any return values.
    2289          25 :   SmallVector<unsigned, 4> UsedRegs;
    2290          25 :   if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
    2291             : 
    2292             :   // Set all unused physreg defs as dead.
    2293          50 :   static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
    2294             : 
    2295          25 :   return true;
    2296             : }
    2297             : 
    2298         627 : bool ARMFastISel::SelectCall(const Instruction *I,
    2299             :                              const char *IntrMemName = nullptr) {
    2300         627 :   const CallInst *CI = cast<CallInst>(I);
    2301         627 :   const Value *Callee = CI->getCalledValue();
    2302             : 
    2303             :   // Can't handle inline asm.
    2304        1254 :   if (isa<InlineAsm>(Callee)) return false;
    2305             : 
    2306             :   // Allow SelectionDAG isel to handle tail calls.
    2307         616 :   if (CI->isTailCall()) return false;
    2308             : 
    2309             :   // Check the calling convention.
    2310         525 :   ImmutableCallSite CS(CI);
    2311         525 :   CallingConv::ID CC = CS.getCallingConv();
    2312             : 
    2313             :   // TODO: Avoid some calling conventions?
    2314             : 
    2315         525 :   FunctionType *FTy = CS.getFunctionType();
    2316         525 :   bool isVarArg = FTy->isVarArg();
    2317             : 
    2318             :   // Handle *simple* calls for now.
    2319         525 :   Type *RetTy = I->getType();
    2320         525 :   MVT RetVT;
    2321         525 :   if (RetTy->isVoidTy())
    2322         305 :     RetVT = MVT::isVoid;
    2323         358 :   else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
    2324         270 :            RetVT != MVT::i8  && RetVT != MVT::i1)
    2325             :     return false;
    2326             : 
    2327             :   // Can't handle non-double multi-reg retvals.
    2328        1435 :   if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
    2329         872 :       RetVT != MVT::i16 && RetVT != MVT::i32) {
    2330           3 :     SmallVector<CCValAssign, 16> RVLocs;
    2331           3 :     CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
    2332           3 :     CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
    2333           6 :     if (RVLocs.size() >= 2 && RetVT != MVT::f64)
    2334           3 :       return false;
    2335             :   }
    2336             : 
    2337             :   // Set up the argument vectors.
    2338         515 :   SmallVector<Value*, 8> Args;
    2339        1030 :   SmallVector<unsigned, 8> ArgRegs;
    2340        1030 :   SmallVector<MVT, 8> ArgVTs;
    2341        1030 :   SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
    2342         515 :   unsigned arg_size = CS.arg_size();
    2343         515 :   Args.reserve(arg_size);
    2344         515 :   ArgRegs.reserve(arg_size);
    2345        1030 :   ArgVTs.reserve(arg_size);
    2346         515 :   ArgFlags.reserve(arg_size);
    2347        1793 :   for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
    2348        1793 :        i != e; ++i) {
    2349             :     // If we're lowering a memory intrinsic instead of a regular call, skip the
    2350             :     // last two arguments, which shouldn't be passed to the underlying function.
    2351        1362 :     if (IntrMemName && e-i <= 2)
    2352             :       break;
    2353             : 
    2354        1342 :     ISD::ArgFlagsTy Flags;
    2355        2684 :     unsigned ArgIdx = i - CS.arg_begin();
    2356        1342 :     if (CS.paramHasAttr(ArgIdx, Attribute::SExt))
    2357             :       Flags.setSExt();
    2358        1342 :     if (CS.paramHasAttr(ArgIdx, Attribute::ZExt))
    2359             :       Flags.setZExt();
    2360             : 
    2361             :     // FIXME: Only handle *easy* calls for now.
    2362        2684 :     if (CS.paramHasAttr(ArgIdx, Attribute::InReg) ||
    2363        2640 :         CS.paramHasAttr(ArgIdx, Attribute::StructRet) ||
    2364        2590 :         CS.paramHasAttr(ArgIdx, Attribute::SwiftSelf) ||
    2365        2583 :         CS.paramHasAttr(ArgIdx, Attribute::SwiftError) ||
    2366        3924 :         CS.paramHasAttr(ArgIdx, Attribute::Nest) ||
    2367        1291 :         CS.paramHasAttr(ArgIdx, Attribute::ByVal))
    2368          64 :       return false;
    2369             : 
    2370        1291 :     Type *ArgTy = (*i)->getType();
    2371        1291 :     MVT ArgVT;
    2372        1462 :     if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
    2373          24 :         ArgVT != MVT::i1)
    2374             :       return false;
    2375             : 
    2376        1278 :     unsigned Arg = getRegForValue(*i);
    2377        1278 :     if (Arg == 0)
    2378             :       return false;
    2379             : 
    2380        1278 :     unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
    2381        1278 :     Flags.setOrigAlign(OriginalAlignment);
    2382             : 
    2383        1278 :     Args.push_back(*i);
    2384        1278 :     ArgRegs.push_back(Arg);
    2385        1278 :     ArgVTs.push_back(ArgVT);
    2386        1278 :     ArgFlags.push_back(Flags);
    2387             :   }
    2388             : 
    2389             :   // Handle the arguments now that we've gotten them.
    2390         451 :   SmallVector<unsigned, 4> RegArgs;
    2391             :   unsigned NumBytes;
    2392         451 :   if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
    2393             :                        RegArgs, CC, NumBytes, isVarArg))
    2394             :     return false;
    2395             : 
    2396         445 :   bool UseReg = false;
    2397         876 :   const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
    2398         431 :   if (!GV || Subtarget->genLongCalls()) UseReg = true;
    2399             : 
    2400          79 :   unsigned CalleeReg = 0;
    2401             :   if (UseReg) {
    2402          79 :     if (IntrMemName)
    2403           9 :       CalleeReg = getLibcallReg(IntrMemName);
    2404             :     else
    2405          70 :       CalleeReg = getRegForValue(Callee);
    2406             : 
    2407          79 :     if (CalleeReg == 0) return false;
    2408             :   }
    2409             : 
    2410             :   // Issue the call.
    2411         890 :   unsigned CallOpc = ARMSelectCallOp(UseReg);
    2412         445 :   MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
    2413        1335 :                                     DbgLoc, TII.get(CallOpc));
    2414             : 
    2415             :   // ARM calls don't take a predicate, but tBL / tBLX do.
    2416         445 :   if(isThumb2)
    2417         546 :     MIB.add(predOps(ARMCC::AL));
    2418         445 :   if (UseReg)
    2419          79 :     MIB.addReg(CalleeReg);
    2420         366 :   else if (!IntrMemName)
    2421             :     MIB.addGlobalAddress(GV, 0, 0);
    2422             :   else
    2423             :     MIB.addExternalSymbol(IntrMemName, 0);
    2424             : 
    2425             :   // Add implicit physical register uses to the call.
    2426        2024 :   for (unsigned R : RegArgs)
    2427         689 :     MIB.addReg(R, RegState::Implicit);
    2428             : 
    2429             :   // Add a register mask with the call-preserved registers.
    2430             :   // Proper defs for return values will be added by setPhysRegsDeadExcept().
    2431         890 :   MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
    2432             : 
    2433             :   // Finish off the call including any return values.
    2434         445 :   SmallVector<unsigned, 4> UsedRegs;
    2435         445 :   if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
    2436             :     return false;
    2437             : 
    2438             :   // Set all unused physreg defs as dead.
    2439         890 :   static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
    2440             : 
    2441         445 :   return true;
    2442             : }
    2443             : 
    2444             : bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
    2445             :   return Len <= 16;
    2446             : }
    2447             : 
    2448          26 : bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
    2449             :                                         uint64_t Len, unsigned Alignment) {
    2450             :   // Make sure we don't bloat code by inlining very large memcpy's.
    2451          26 :   if (!ARMIsMemCpySmall(Len))
    2452             :     return false;
    2453             : 
    2454         282 :   while (Len) {
    2455         128 :     MVT VT;
    2456         128 :     if (!Alignment || Alignment >= 4) {
    2457          26 :       if (Len >= 4)
    2458          20 :         VT = MVT::i32;
    2459           6 :       else if (Len >= 2)
    2460           6 :         VT = MVT::i16;
    2461             :       else {
    2462             :         assert(Len == 1 && "Expected a length of 1!");
    2463           0 :         VT = MVT::i8;
    2464             :       }
    2465             :     } else {
    2466             :       // Bound based on alignment.
    2467         102 :       if (Len >= 2 && Alignment == 2)
    2468          36 :         VT = MVT::i16;
    2469             :       else {
    2470          66 :         VT = MVT::i8;
    2471             :       }
    2472             :     }
    2473             : 
    2474             :     bool RV;
    2475             :     unsigned ResultReg;
    2476         128 :     RV = ARMEmitLoad(VT, ResultReg, Src);
    2477             :     assert(RV && "Should be able to handle this load.");
    2478         128 :     RV = ARMEmitStore(VT, ResultReg, Dest);
    2479             :     assert(RV && "Should be able to handle this store.");
    2480             :     (void)RV;
    2481             : 
    2482         128 :     unsigned Size = VT.getSizeInBits()/8;
    2483         128 :     Len -= Size;
    2484         128 :     Dest.Offset += Size;
    2485         128 :     Src.Offset += Size;
    2486             :   }
    2487             : 
    2488             :   return true;
    2489             : }
    2490             : 
    2491          73 : bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
    2492             :   // FIXME: Handle more intrinsics.
    2493          73 :   switch (I.getIntrinsicID()) {
    2494             :   default: return false;
    2495           9 :   case Intrinsic::frameaddress: {
    2496           9 :     MachineFrameInfo &MFI = FuncInfo.MF->getFrameInfo();
    2497           9 :     MFI.setFrameAddressIsTaken(true);
    2498             : 
    2499           9 :     unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
    2500           9 :     const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
    2501             :                                              : &ARM::GPRRegClass;
    2502             : 
    2503             :     const ARMBaseRegisterInfo *RegInfo =
    2504           9 :         static_cast<const ARMBaseRegisterInfo *>(Subtarget->getRegisterInfo());
    2505           9 :     unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
    2506           9 :     unsigned SrcReg = FramePtr;
    2507             : 
    2508             :     // Recursively load frame address
    2509             :     // ldr r0 [fp]
    2510             :     // ldr r0 [r0]
    2511             :     // ldr r0 [r0]
    2512             :     // ...
    2513             :     unsigned DestReg;
    2514          36 :     unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
    2515          33 :     while (Depth--) {
    2516          12 :       DestReg = createResultReg(RC);
    2517          24 :       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    2518          24 :                               TII.get(LdrOpc), DestReg)
    2519          24 :                       .addReg(SrcReg).addImm(0));
    2520          12 :       SrcReg = DestReg;
    2521             :     }
    2522           9 :     updateValueMap(&I, SrcReg);
    2523           9 :     return true;
    2524             :   }
    2525          40 :   case Intrinsic::memcpy:
    2526             :   case Intrinsic::memmove: {
    2527          40 :     const MemTransferInst &MTI = cast<MemTransferInst>(I);
    2528             :     // Don't handle volatile.
    2529          40 :     if (MTI.isVolatile())
    2530             :       return false;
    2531             : 
    2532             :     // Disable inlining for memmove before calls to ComputeAddress.  Otherwise,
    2533             :     // we would emit dead code because we don't currently handle memmoves.
    2534          40 :     bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
    2535         120 :     if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
    2536             :       // Small memcpy's are common enough that we want to do them without a call
    2537             :       // if possible.
    2538         136 :       uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
    2539          34 :       if (ARMIsMemCpySmall(Len)) {
    2540          52 :         Address Dest, Src;
    2541          78 :         if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
    2542          26 :             !ARMComputeAddress(MTI.getRawSource(), Src))
    2543          26 :           return false;
    2544          52 :         unsigned Alignment = MTI.getAlignment();
    2545          26 :         if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
    2546             :           return true;
    2547             :       }
    2548             :     }
    2549             : 
    2550          28 :     if (!MTI.getLength()->getType()->isIntegerTy(32))
    2551             :       return false;
    2552             : 
    2553          28 :     if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
    2554             :       return false;
    2555             : 
    2556          14 :     const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
    2557          14 :     return SelectCall(&I, IntrMemName);
    2558             :   }
    2559           6 :   case Intrinsic::memset: {
    2560           6 :     const MemSetInst &MSI = cast<MemSetInst>(I);
    2561             :     // Don't handle volatile.
    2562           6 :     if (MSI.isVolatile())
    2563             :       return false;
    2564             : 
    2565          12 :     if (!MSI.getLength()->getType()->isIntegerTy(32))
    2566             :       return false;
    2567             : 
    2568          12 :     if (MSI.getDestAddressSpace() > 255)
    2569             :       return false;
    2570             : 
    2571           6 :     return SelectCall(&I, "memset");
    2572             :   }
    2573           4 :   case Intrinsic::trap: {
    2574           8 :     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(
    2575           8 :       Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
    2576           4 :     return true;
    2577             :   }
    2578             :   }
    2579             : }
    2580             : 
    2581          22 : bool ARMFastISel::SelectTrunc(const Instruction *I) {
    2582             :   // The high bits for a type smaller than the register size are assumed to be
    2583             :   // undefined.
    2584          44 :   Value *Op = I->getOperand(0);
    2585             : 
    2586          22 :   EVT SrcVT, DestVT;
    2587          22 :   SrcVT = TLI.getValueType(DL, Op->getType(), true);
    2588          22 :   DestVT = TLI.getValueType(DL, I->getType(), true);
    2589             : 
    2590          36 :   if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
    2591             :     return false;
    2592          33 :   if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
    2593             :     return false;
    2594             : 
    2595          21 :   unsigned SrcReg = getRegForValue(Op);
    2596          21 :   if (!SrcReg) return false;
    2597             : 
    2598             :   // Because the high bits are undefined, a truncate doesn't generate
    2599             :   // any code.
    2600          21 :   updateValueMap(I, SrcReg);
    2601          21 :   return true;
    2602             : }
    2603             : 
    2604         396 : unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
    2605             :                                     bool isZExt) {
    2606         792 :   if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
    2607             :     return 0;
    2608         792 :   if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
    2609             :     return 0;
    2610             : 
    2611             :   // Table of which combinations can be emitted as a single instruction,
    2612             :   // and which will require two.
    2613             :   static const uint8_t isSingleInstrTbl[3][2][2][2] = {
    2614             :     //            ARM                     Thumb
    2615             :     //           !hasV6Ops  hasV6Ops     !hasV6Ops  hasV6Ops
    2616             :     //    ext:     s  z      s  z          s  z      s  z
    2617             :     /*  1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
    2618             :     /*  8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
    2619             :     /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
    2620             :   };
    2621             : 
    2622             :   // Target registers for:
    2623             :   //  - For ARM can never be PC.
    2624             :   //  - For 16-bit Thumb are restricted to lower 8 registers.
    2625             :   //  - For 32-bit Thumb are restricted to non-SP and non-PC.
    2626             :   static const TargetRegisterClass *RCTbl[2][2] = {
    2627             :     // Instructions: Two                     Single
    2628             :     /* ARM      */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
    2629             :     /* Thumb    */ { &ARM::tGPRRegClass,    &ARM::rGPRRegClass    }
    2630             :   };
    2631             : 
    2632             :   // Table governing the instruction(s) to be emitted.
    2633             :   static const struct InstructionTable {
    2634             :     uint32_t Opc   : 16;
    2635             :     uint32_t hasS  :  1; // Some instructions have an S bit, always set it to 0.
    2636             :     uint32_t Shift :  7; // For shift operand addressing mode, used by MOVsi.
    2637             :     uint32_t Imm   :  8; // All instructions have either a shift or a mask.
    2638             :   } IT[2][2][3][2] = {
    2639             :     { // Two instructions (first is left shift, second is in this table).
    2640             :       { // ARM                Opc           S  Shift             Imm
    2641             :         /*  1 bit sext */ { { ARM::MOVsi  , 1, ARM_AM::asr     ,  31 },
    2642             :         /*  1 bit zext */   { ARM::MOVsi  , 1, ARM_AM::lsr     ,  31 } },
    2643             :         /*  8 bit sext */ { { ARM::MOVsi  , 1, ARM_AM::asr     ,  24 },
    2644             :         /*  8 bit zext */   { ARM::MOVsi  , 1, ARM_AM::lsr     ,  24 } },
    2645             :         /* 16 bit sext */ { { ARM::MOVsi  , 1, ARM_AM::asr     ,  16 },
    2646             :         /* 16 bit zext */   { ARM::MOVsi  , 1, ARM_AM::lsr     ,  16 } }
    2647             :       },
    2648             :       { // Thumb              Opc           S  Shift             Imm
    2649             :         /*  1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  31 },
    2650             :         /*  1 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  31 } },
    2651             :         /*  8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  24 },
    2652             :         /*  8 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  24 } },
    2653             :         /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  16 },
    2654             :         /* 16 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  16 } }
    2655             :       }
    2656             :     },
    2657             :     { // Single instruction.
    2658             :       { // ARM                Opc           S  Shift             Imm
    2659             :         /*  1 bit sext */ { { ARM::KILL   , 0, ARM_AM::no_shift,   0 },
    2660             :         /*  1 bit zext */   { ARM::ANDri  , 1, ARM_AM::no_shift,   1 } },
    2661             :         /*  8 bit sext */ { { ARM::SXTB   , 0, ARM_AM::no_shift,   0 },
    2662             :         /*  8 bit zext */   { ARM::ANDri  , 1, ARM_AM::no_shift, 255 } },
    2663             :         /* 16 bit sext */ { { ARM::SXTH   , 0, ARM_AM::no_shift,   0 },
    2664             :         /* 16 bit zext */   { ARM::UXTH   , 0, ARM_AM::no_shift,   0 } }
    2665             :       },
    2666             :       { // Thumb              Opc           S  Shift             Imm
    2667             :         /*  1 bit sext */ { { ARM::KILL   , 0, ARM_AM::no_shift,   0 },
    2668             :         /*  1 bit zext */   { ARM::t2ANDri, 1, ARM_AM::no_shift,   1 } },
    2669             :         /*  8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift,   0 },
    2670             :         /*  8 bit zext */   { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
    2671             :         /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift,   0 },
    2672             :         /* 16 bit zext */   { ARM::t2UXTH , 0, ARM_AM::no_shift,   0 } }
    2673             :       }
    2674             :     }
    2675             :   };
    2676             : 
    2677         396 :   unsigned SrcBits = SrcVT.getSizeInBits();
    2678         396 :   unsigned DestBits = DestVT.getSizeInBits();
    2679             :   (void) DestBits;
    2680             :   assert((SrcBits < DestBits) && "can only extend to larger types");
    2681             :   assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
    2682             :          "other sizes unimplemented");
    2683             :   assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
    2684             :          "other sizes unimplemented");
    2685             : 
    2686         396 :   bool hasV6Ops = Subtarget->hasV6Ops();
    2687         396 :   unsigned Bitness = SrcBits / 8;  // {1,8,16}=>{0,1,2}
    2688             :   assert((Bitness < 3) && "sanity-check table bounds");
    2689             : 
    2690         396 :   bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
    2691         396 :   const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
    2692         396 :   const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
    2693         396 :   unsigned Opc = ITP->Opc;
    2694             :   assert(ARM::KILL != Opc && "Invalid table entry");
    2695         396 :   unsigned hasS = ITP->hasS;
    2696         396 :   ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
    2697             :   assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
    2698             :          "only MOVsi has shift operand addressing mode");
    2699         396 :   unsigned Imm = ITP->Imm;
    2700             : 
    2701             :   // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
    2702         396 :   bool setsCPSR = &ARM::tGPRRegClass == RC;
    2703         396 :   unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
    2704             :   unsigned ResultReg;
    2705             :   // MOVsi encodes shift and immediate in shift operand addressing mode.
    2706             :   // The following condition has the same value when emitting two
    2707             :   // instruction sequences: both are shifts.
    2708         396 :   bool ImmIsSO = (Shift != ARM_AM::no_shift);
    2709             : 
    2710             :   // Either one or two instructions are emitted.
    2711             :   // They're always of the form:
    2712             :   //   dst = in OP imm
    2713             :   // CPSR is set only by 16-bit Thumb instructions.
    2714             :   // Predicate, if any, is AL.
    2715             :   // S bit, if available, is always 0.
    2716             :   // When two are emitted the first's result will feed as the second's input,
    2717             :   // that value is then dead.
    2718         396 :   unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
    2719         801 :   for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
    2720         405 :     ResultReg = createResultReg(RC);
    2721         405 :     bool isLsl = (0 == Instr) && !isSingleInstr;
    2722         405 :     unsigned Opcode = isLsl ? LSLOpc : Opc;
    2723         405 :     ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
    2724         417 :     unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
    2725         405 :     bool isKill = 1 == Instr;
    2726             :     MachineInstrBuilder MIB = BuildMI(
    2727         810 :         *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg);
    2728         405 :     if (setsCPSR)
    2729           6 :       MIB.addReg(ARM::CPSR, RegState::Define);
    2730         810 :     SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
    2731         405 :     MIB.addReg(SrcReg, isKill * RegState::Kill)
    2732         810 :         .addImm(ImmEnc)
    2733        1215 :         .add(predOps(ARMCC::AL));
    2734         405 :     if (hasS)
    2735         414 :       MIB.add(condCodeOp());
    2736             :     // Second instruction consumes the first's result.
    2737         405 :     SrcReg = ResultReg;
    2738             :   }
    2739             : 
    2740             :   return ResultReg;
    2741             : }
    2742             : 
    2743         136 : bool ARMFastISel::SelectIntExt(const Instruction *I) {
    2744             :   // On ARM, in general, integer casts don't involve legal types; this code
    2745             :   // handles promotable integers.
    2746         136 :   Type *DestTy = I->getType();
    2747         272 :   Value *Src = I->getOperand(0);
    2748         136 :   Type *SrcTy = Src->getType();
    2749             : 
    2750         272 :   bool isZExt = isa<ZExtInst>(I);
    2751         136 :   unsigned SrcReg = getRegForValue(Src);
    2752         136 :   if (!SrcReg) return false;
    2753             : 
    2754         134 :   EVT SrcEVT, DestEVT;
    2755         134 :   SrcEVT = TLI.getValueType(DL, SrcTy, true);
    2756         134 :   DestEVT = TLI.getValueType(DL, DestTy, true);
    2757         134 :   if (!SrcEVT.isSimple()) return false;
    2758         134 :   if (!DestEVT.isSimple()) return false;
    2759             : 
    2760         134 :   MVT SrcVT = SrcEVT.getSimpleVT();
    2761         134 :   MVT DestVT = DestEVT.getSimpleVT();
    2762         134 :   unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
    2763         134 :   if (ResultReg == 0) return false;
    2764         134 :   updateValueMap(I, ResultReg);
    2765         134 :   return true;
    2766             : }
    2767             : 
    2768          12 : bool ARMFastISel::SelectShift(const Instruction *I,
    2769             :                               ARM_AM::ShiftOpc ShiftTy) {
    2770             :   // We handle thumb2 mode by target independent selector
    2771             :   // or SelectionDAG ISel.
    2772          12 :   if (isThumb2)
    2773             :     return false;
    2774             : 
    2775             :   // Only handle i32 now.
    2776          12 :   EVT DestVT = TLI.getValueType(DL, I->getType(), true);
    2777          12 :   if (DestVT != MVT::i32)
    2778             :     return false;
    2779             : 
    2780          12 :   unsigned Opc = ARM::MOVsr;
    2781             :   unsigned ShiftImm;
    2782          24 :   Value *Src2Value = I->getOperand(1);
    2783           6 :   if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
    2784           6 :     ShiftImm = CI->getZExtValue();
    2785             : 
    2786             :     // Fall back to selection DAG isel if the shift amount
    2787             :     // is zero or greater than the width of the value type.
    2788           6 :     if (ShiftImm == 0 || ShiftImm >=32)
    2789             :       return false;
    2790             : 
    2791             :     Opc = ARM::MOVsi;
    2792             :   }
    2793             : 
    2794          24 :   Value *Src1Value = I->getOperand(0);
    2795          12 :   unsigned Reg1 = getRegForValue(Src1Value);
    2796          12 :   if (Reg1 == 0) return false;
    2797             : 
    2798          12 :   unsigned Reg2 = 0;
    2799          12 :   if (Opc == ARM::MOVsr) {
    2800           6 :     Reg2 = getRegForValue(Src2Value);
    2801           6 :     if (Reg2 == 0) return false;
    2802             :   }
    2803             : 
    2804          12 :   unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
    2805          12 :   if(ResultReg == 0) return false;
    2806             : 
    2807          24 :   MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    2808          24 :                                     TII.get(Opc), ResultReg)
    2809          12 :                             .addReg(Reg1);
    2810             : 
    2811          12 :   if (Opc == ARM::MOVsi)
    2812           6 :     MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
    2813             :   else if (Opc == ARM::MOVsr) {
    2814           6 :     MIB.addReg(Reg2);
    2815           6 :     MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
    2816             :   }
    2817             : 
    2818          12 :   AddOptionalDefs(MIB);
    2819          12 :   updateValueMap(I, ResultReg);
    2820          12 :   return true;
    2821             : }
    2822             : 
    2823             : // TODO: SoftFP support.
    2824        3028 : bool ARMFastISel::fastSelectInstruction(const Instruction *I) {
    2825        3028 :   switch (I->getOpcode()) {
    2826         322 :     case Instruction::Load:
    2827         322 :       return SelectLoad(I);
    2828         593 :     case Instruction::Store:
    2829         593 :       return SelectStore(I);
    2830          79 :     case Instruction::Br:
    2831          79 :       return SelectBranch(I);
    2832           4 :     case Instruction::IndirectBr:
    2833           4 :       return SelectIndirectBr(I);
    2834          26 :     case Instruction::ICmp:
    2835             :     case Instruction::FCmp:
    2836          26 :       return SelectCmp(I);
    2837           1 :     case Instruction::FPExt:
    2838           1 :       return SelectFPExt(I);
    2839           1 :     case Instruction::FPTrunc:
    2840           1 :       return SelectFPTrunc(I);
    2841          19 :     case Instruction::SIToFP:
    2842          19 :       return SelectIToFP(I, /*isSigned*/ true);
    2843          18 :     case Instruction::UIToFP:
    2844          18 :       return SelectIToFP(I, /*isSigned*/ false);
    2845           6 :     case Instruction::FPToSI:
    2846           6 :       return SelectFPToI(I, /*isSigned*/ true);
    2847           7 :     case Instruction::FPToUI:
    2848           7 :       return SelectFPToI(I, /*isSigned*/ false);
    2849          22 :     case Instruction::Add:
    2850          22 :       return SelectBinaryIntOp(I, ISD::ADD);
    2851           6 :     case Instruction::Or:
    2852           6 :       return SelectBinaryIntOp(I, ISD::OR);
    2853           9 :     case Instruction::Sub:
    2854           9 :       return SelectBinaryIntOp(I, ISD::SUB);
    2855           2 :     case Instruction::FAdd:
    2856           2 :       return SelectBinaryFPOp(I, ISD::FADD);
    2857           0 :     case Instruction::FSub:
    2858           0 :       return SelectBinaryFPOp(I, ISD::FSUB);
    2859           0 :     case Instruction::FMul:
    2860           0 :       return SelectBinaryFPOp(I, ISD::FMUL);
    2861           4 :     case Instruction::SDiv:
    2862           4 :       return SelectDiv(I, /*isSigned*/ true);
    2863          10 :     case Instruction::UDiv:
    2864          10 :       return SelectDiv(I, /*isSigned*/ false);
    2865          31 :     case Instruction::SRem:
    2866          31 :       return SelectRem(I, /*isSigned*/ true);
    2867           5 :     case Instruction::URem:
    2868           5 :       return SelectRem(I, /*isSigned*/ false);
    2869         680 :     case Instruction::Call:
    2870          73 :       if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
    2871          73 :         return SelectIntrinsicCall(*II);
    2872         607 :       return SelectCall(I);
    2873          24 :     case Instruction::Select:
    2874          24 :       return SelectSelect(I);
    2875         889 :     case Instruction::Ret:
    2876         889 :       return SelectRet(I);
    2877          22 :     case Instruction::Trunc:
    2878          22 :       return SelectTrunc(I);
    2879         136 :     case Instruction::ZExt:
    2880             :     case Instruction::SExt:
    2881         136 :       return SelectIntExt(I);
    2882           4 :     case Instruction::Shl:
    2883           4 :       return SelectShift(I, ARM_AM::lsl);
    2884           4 :     case Instruction::LShr:
    2885           4 :       return SelectShift(I, ARM_AM::lsr);
    2886           4 :     case Instruction::AShr:
    2887           4 :       return SelectShift(I, ARM_AM::asr);
    2888             :     default: break;
    2889             :   }
    2890             :   return false;
    2891             : }
    2892             : 
    2893             : namespace {
    2894             : 
    2895             : // This table describes sign- and zero-extend instructions which can be
    2896             : // folded into a preceding load. All of these extends have an immediate
    2897             : // (sometimes a mask and sometimes a shift) that's applied after
    2898             : // extension.
    2899             : const struct FoldableLoadExtendsStruct {
    2900             :   uint16_t Opc[2];  // ARM, Thumb.
    2901             :   uint8_t ExpectedImm;
    2902             :   uint8_t isZExt     : 1;
    2903             :   uint8_t ExpectedVT : 7;
    2904             : } FoldableLoadExtends[] = {
    2905             :   { { ARM::SXTH,  ARM::t2SXTH  },   0, 0, MVT::i16 },
    2906             :   { { ARM::UXTH,  ARM::t2UXTH  },   0, 1, MVT::i16 },
    2907             :   { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8  },
    2908             :   { { ARM::SXTB,  ARM::t2SXTB  },   0, 0, MVT::i8  },
    2909             :   { { ARM::UXTB,  ARM::t2UXTB  },   0, 1, MVT::i8  }
    2910             : };
    2911             : 
    2912             : } // end anonymous namespace
    2913             : 
    2914             : /// \brief The specified machine instr operand is a vreg, and that
    2915             : /// vreg is being provided by the specified load instruction.  If possible,
    2916             : /// try to fold the load as an operand to the instruction, returning true if
    2917             : /// successful.
    2918         201 : bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
    2919             :                                       const LoadInst *LI) {
    2920             :   // Verify we have a legal type before going any further.
    2921         201 :   MVT VT;
    2922         201 :   if (!isLoadTypeLegal(LI->getType(), VT))
    2923             :     return false;
    2924             : 
    2925             :   // Combine load followed by zero- or sign-extend.
    2926             :   // ldrb r1, [r0]       ldrb r1, [r0]
    2927             :   // uxtb r2, r1     =>
    2928             :   // mov  r3, r2         mov  r3, r1
    2929         339 :   if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm())
    2930             :     return false;
    2931         107 :   const uint64_t Imm = MI->getOperand(2).getImm();
    2932             : 
    2933         107 :   bool Found = false;
    2934             :   bool isZExt;
    2935         642 :   for (const FoldableLoadExtendsStruct &FLE : FoldableLoadExtends) {
    2936         586 :     if (FLE.Opc[isThumb2] == MI->getOpcode() &&
    2937         586 :         (uint64_t)FLE.ExpectedImm == Imm &&
    2938         102 :         MVT((MVT::SimpleValueType)FLE.ExpectedVT) == VT) {
    2939          51 :       Found = true;
    2940          51 :       isZExt = FLE.isZExt;
    2941             :     }
    2942             :   }
    2943         107 :   if (!Found) return false;
    2944             : 
    2945             :   // See if we can handle this address.
    2946          51 :   Address Addr;
    2947         102 :   if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
    2948             : 
    2949          51 :   unsigned ResultReg = MI->getOperand(0).getReg();
    2950         102 :   if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
    2951             :     return false;
    2952          51 :   MI->eraseFromParent();
    2953          51 :   return true;
    2954             : }
    2955             : 
    2956           5 : unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
    2957             :                                      unsigned Align, MVT VT) {
    2958           5 :   bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
    2959             : 
    2960           5 :   LLVMContext *Context = &MF->getFunction()->getContext();
    2961          10 :   unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
    2962           5 :   unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
    2963           5 :   ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(
    2964             :       GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj,
    2965             :       UseGOT_PREL ? ARMCP::GOT_PREL : ARMCP::no_modifier,
    2966           5 :       /*AddCurrentAddress=*/UseGOT_PREL);
    2967             : 
    2968             :   unsigned ConstAlign =
    2969           5 :       MF->getDataLayout().getPrefTypeAlignment(Type::getInt32PtrTy(*Context));
    2970           5 :   unsigned Idx = MF->getConstantPool()->getConstantPoolIndex(CPV, ConstAlign);
    2971             : 
    2972           5 :   unsigned TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
    2973           5 :   unsigned Opc = isThumb2 ? ARM::t2LDRpci : ARM::LDRcp;
    2974             :   MachineInstrBuilder MIB =
    2975          15 :       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), TempReg)
    2976           5 :           .addConstantPoolIndex(Idx);
    2977           5 :   if (Opc == ARM::LDRcp)
    2978             :     MIB.addImm(0);
    2979          15 :   MIB.add(predOps(ARMCC::AL));
    2980             : 
    2981             :   // Fix the address by adding pc.
    2982           5 :   unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
    2983           5 :   Opc = Subtarget->isThumb() ? ARM::tPICADD : UseGOT_PREL ? ARM::PICLDR
    2984             :                                                           : ARM::PICADD;
    2985          10 :   DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0);
    2986          15 :   MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
    2987           5 :             .addReg(TempReg)
    2988          10 :             .addImm(ARMPCLabelIndex);
    2989           5 :   if (!Subtarget->isThumb())
    2990           9 :     MIB.add(predOps(ARMCC::AL));
    2991             : 
    2992           5 :   if (UseGOT_PREL && Subtarget->isThumb()) {
    2993           2 :     unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
    2994           4 :     MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    2995           4 :                   TII.get(ARM::t2LDRi12), NewDestReg)
    2996           2 :               .addReg(DestReg)
    2997           2 :               .addImm(0);
    2998           2 :     DestReg = NewDestReg;
    2999           2 :     AddOptionalDefs(MIB);
    3000             :   }
    3001           5 :   return DestReg;
    3002             : }
    3003             : 
    3004         899 : bool ARMFastISel::fastLowerArguments() {
    3005         899 :   if (!FuncInfo.CanLowerReturn)
    3006             :     return false;
    3007             : 
    3008         899 :   const Function *F = FuncInfo.Fn;
    3009         899 :   if (F->isVarArg())
    3010             :     return false;
    3011             : 
    3012         898 :   CallingConv::ID CC = F->getCallingConv();
    3013         898 :   switch (CC) {
    3014             :   default:
    3015             :     return false;
    3016             :   case CallingConv::Fast:
    3017             :   case CallingConv::C:
    3018             :   case CallingConv::ARM_AAPCS_VFP:
    3019             :   case CallingConv::ARM_AAPCS:
    3020             :   case CallingConv::ARM_APCS:
    3021             :   case CallingConv::Swift:
    3022             :     break;
    3023             :   }
    3024             : 
    3025             :   // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
    3026             :   // which are passed in r0 - r3.
    3027        1499 :   for (const Argument &Arg : F->args()) {
    3028         822 :     if (Arg.getArgNo() >= 4)
    3029         211 :       return false;
    3030             : 
    3031        1630 :     if (Arg.hasAttribute(Attribute::InReg) ||
    3032        1625 :         Arg.hasAttribute(Attribute::StructRet) ||
    3033        1610 :         Arg.hasAttribute(Attribute::SwiftSelf) ||
    3034        2408 :         Arg.hasAttribute(Attribute::SwiftError) ||
    3035         793 :         Arg.hasAttribute(Attribute::ByVal))
    3036             :       return false;
    3037             : 
    3038         793 :     Type *ArgTy = Arg.getType();
    3039        2374 :     if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
    3040             :       return false;
    3041             : 
    3042         783 :     EVT ArgVT = TLI.getValueType(DL, ArgTy);
    3043         783 :     if (!ArgVT.isSimple()) return false;
    3044         783 :     switch (ArgVT.getSimpleVT().SimpleTy) {
    3045             :     case MVT::i8:
    3046             :     case MVT::i16:
    3047             :     case MVT::i32:
    3048             :       break;
    3049             :     default:
    3050             :       return false;
    3051             :     }
    3052             :   }
    3053             : 
    3054             :   static const MCPhysReg GPRArgRegs[] = {
    3055             :     ARM::R0, ARM::R1, ARM::R2, ARM::R3
    3056             :   };
    3057             : 
    3058         677 :   const TargetRegisterClass *RC = &ARM::rGPRRegClass;
    3059        1216 :   for (const Argument &Arg : F->args()) {
    3060         539 :     unsigned ArgNo = Arg.getArgNo();
    3061         539 :     unsigned SrcReg = GPRArgRegs[ArgNo];
    3062         539 :     unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
    3063             :     // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
    3064             :     // Without this, EmitLiveInCopies may eliminate the livein if its only
    3065             :     // use is a bitcast (which isn't turned into an instruction).
    3066         539 :     unsigned ResultReg = createResultReg(RC);
    3067        1078 :     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
    3068         539 :             TII.get(TargetOpcode::COPY),
    3069        1617 :             ResultReg).addReg(DstReg, getKillRegState(true));
    3070         539 :     updateValueMap(&Arg, ResultReg);
    3071             :   }
    3072             : 
    3073             :   return true;
    3074             : }
    3075             : 
    3076             : namespace llvm {
    3077             : 
    3078        1131 :   FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
    3079             :                                 const TargetLibraryInfo *libInfo) {
    3080        1131 :     if (funcInfo.MF->getSubtarget<ARMSubtarget>().useFastISel())
    3081         901 :       return new ARMFastISel(funcInfo, libInfo);
    3082             : 
    3083             :     return nullptr;
    3084             :   }
    3085             : 
    3086             : } // end namespace llvm

Generated by: LCOV version 1.13