LCOV - code coverage report
Current view: top level - lib/Target/ARM - ARMISelDAGToDAG.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 1677 1811 92.6 %
Date: 2018-07-13 00:08:38 Functions: 67 69 97.1 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file defines an instruction selector for the ARM target.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "ARM.h"
      15             : #include "ARMBaseInstrInfo.h"
      16             : #include "ARMTargetMachine.h"
      17             : #include "MCTargetDesc/ARMAddressingModes.h"
      18             : #include "Utils/ARMBaseInfo.h"
      19             : #include "llvm/ADT/StringSwitch.h"
      20             : #include "llvm/CodeGen/MachineFrameInfo.h"
      21             : #include "llvm/CodeGen/MachineFunction.h"
      22             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      23             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      24             : #include "llvm/CodeGen/SelectionDAG.h"
      25             : #include "llvm/CodeGen/SelectionDAGISel.h"
      26             : #include "llvm/CodeGen/TargetLowering.h"
      27             : #include "llvm/IR/CallingConv.h"
      28             : #include "llvm/IR/Constants.h"
      29             : #include "llvm/IR/DerivedTypes.h"
      30             : #include "llvm/IR/Function.h"
      31             : #include "llvm/IR/Intrinsics.h"
      32             : #include "llvm/IR/LLVMContext.h"
      33             : #include "llvm/Support/CommandLine.h"
      34             : #include "llvm/Support/Debug.h"
      35             : #include "llvm/Support/ErrorHandling.h"
      36             : #include "llvm/Target/TargetOptions.h"
      37             : 
      38             : using namespace llvm;
      39             : 
      40             : #define DEBUG_TYPE "arm-isel"
      41             : 
      42             : static cl::opt<bool>
      43       99743 : DisableShifterOp("disable-shifter-op", cl::Hidden,
      44       99743 :   cl::desc("Disable isel of shifter-op"),
      45      299229 :   cl::init(false));
      46             : 
      47             : //===--------------------------------------------------------------------===//
      48             : /// ARMDAGToDAGISel - ARM specific code to select ARM machine
      49             : /// instructions for SelectionDAG operations.
      50             : ///
      51             : namespace {
      52             : 
      53        2682 : class ARMDAGToDAGISel : public SelectionDAGISel {
      54             :   /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
      55             :   /// make the right decision when generating code for different targets.
      56             :   const ARMSubtarget *Subtarget;
      57             : 
      58             : public:
      59             :   explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOpt::Level OptLevel)
      60        2709 :       : SelectionDAGISel(tm, OptLevel) {}
      61             : 
      62       13591 :   bool runOnMachineFunction(MachineFunction &MF) override {
      63             :     // Reset the subtarget each time through.
      64       13591 :     Subtarget = &MF.getSubtarget<ARMSubtarget>();
      65       13591 :     SelectionDAGISel::runOnMachineFunction(MF);
      66       13564 :     return true;
      67             :   }
      68             : 
      69           0 :   StringRef getPassName() const override { return "ARM Instruction Selection"; }
      70             : 
      71             :   void PreprocessISelDAG() override;
      72             : 
      73             :   /// getI32Imm - Return a target constant of type i32 with the specified
      74             :   /// value.
      75             :   inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) {
      76             :     return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
      77             :   }
      78             : 
      79             :   void Select(SDNode *N) override;
      80             : 
      81             :   bool hasNoVMLxHazardUse(SDNode *N) const;
      82             :   bool isShifterOpProfitable(const SDValue &Shift,
      83             :                              ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
      84             :   bool SelectRegShifterOperand(SDValue N, SDValue &A,
      85             :                                SDValue &B, SDValue &C,
      86             :                                bool CheckProfitability = true);
      87             :   bool SelectImmShifterOperand(SDValue N, SDValue &A,
      88             :                                SDValue &B, bool CheckProfitability = true);
      89             :   bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
      90             :                                     SDValue &B, SDValue &C) {
      91             :     // Don't apply the profitability check
      92         394 :     return SelectRegShifterOperand(N, A, B, C, false);
      93             :   }
      94             :   bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
      95             :                                     SDValue &B) {
      96             :     // Don't apply the profitability check
      97        5859 :     return SelectImmShifterOperand(N, A, B, false);
      98             :   }
      99             : 
     100             :   bool SelectAddLikeOr(SDNode *Parent, SDValue N, SDValue &Out);
     101             : 
     102             :   bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
     103             :   bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
     104             : 
     105        1340 :   bool SelectCMOVPred(SDValue N, SDValue &Pred, SDValue &Reg) {
     106             :     const ConstantSDNode *CN = cast<ConstantSDNode>(N);
     107        5360 :     Pred = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(N), MVT::i32);
     108        2680 :     Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
     109        1340 :     return true;
     110             :   }
     111             : 
     112             :   bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
     113             :                              SDValue &Offset, SDValue &Opc);
     114             :   bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
     115             :                              SDValue &Offset, SDValue &Opc);
     116             :   bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
     117             :                              SDValue &Offset, SDValue &Opc);
     118             :   bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
     119             :   bool SelectAddrMode3(SDValue N, SDValue &Base,
     120             :                        SDValue &Offset, SDValue &Opc);
     121             :   bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
     122             :                              SDValue &Offset, SDValue &Opc);
     123             :   bool IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset,
     124             :                          int Lwb, int Upb, bool FP16);
     125             :   bool SelectAddrMode5(SDValue N, SDValue &Base, SDValue &Offset);
     126             :   bool SelectAddrMode5FP16(SDValue N, SDValue &Base, SDValue &Offset);
     127             :   bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
     128             :   bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
     129             : 
     130             :   bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
     131             : 
     132             :   // Thumb Addressing Modes:
     133             :   bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
     134             :   bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
     135             :                                 SDValue &OffImm);
     136             :   bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
     137             :                                  SDValue &OffImm);
     138             :   bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
     139             :                                  SDValue &OffImm);
     140             :   bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
     141             :                                  SDValue &OffImm);
     142             :   bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
     143             : 
     144             :   // Thumb 2 Addressing Modes:
     145             :   bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
     146             :   bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
     147             :                             SDValue &OffImm);
     148             :   bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
     149             :                                  SDValue &OffImm);
     150             :   bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
     151             :                              SDValue &OffReg, SDValue &ShImm);
     152             :   bool SelectT2AddrModeExclusive(SDValue N, SDValue &Base, SDValue &OffImm);
     153             : 
     154             :   inline bool is_so_imm(unsigned Imm) const {
     155             :     return ARM_AM::getSOImmVal(Imm) != -1;
     156             :   }
     157             : 
     158             :   inline bool is_so_imm_not(unsigned Imm) const {
     159             :     return ARM_AM::getSOImmVal(~Imm) != -1;
     160             :   }
     161             : 
     162             :   inline bool is_t2_so_imm(unsigned Imm) const {
     163         336 :     return ARM_AM::getT2SOImmVal(Imm) != -1;
     164             :   }
     165             : 
     166             :   inline bool is_t2_so_imm_not(unsigned Imm) const {
     167         184 :     return ARM_AM::getT2SOImmVal(~Imm) != -1;
     168             :   }
     169             : 
     170             :   // Include the pieces autogenerated from the target description.
     171             : #include "ARMGenDAGISel.inc"
     172             : 
     173             : private:
     174             :   void transferMemOperands(SDNode *Src, SDNode *Dst);
     175             : 
     176             :   /// Indexed (pre/post inc/dec) load matching code for ARM.
     177             :   bool tryARMIndexedLoad(SDNode *N);
     178             :   bool tryT1IndexedLoad(SDNode *N);
     179             :   bool tryT2IndexedLoad(SDNode *N);
     180             : 
     181             :   /// SelectVLD - Select NEON load intrinsics.  NumVecs should be
     182             :   /// 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
     183             :   /// loads of D registers and even subregs and odd subregs of Q registers.
     184             :   /// For NumVecs <= 2, QOpcodes1 is not used.
     185             :   void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
     186             :                  const uint16_t *DOpcodes, const uint16_t *QOpcodes0,
     187             :                  const uint16_t *QOpcodes1);
     188             : 
     189             :   /// SelectVST - Select NEON store intrinsics.  NumVecs should
     190             :   /// be 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
     191             :   /// stores of D registers and even subregs and odd subregs of Q registers.
     192             :   /// For NumVecs <= 2, QOpcodes1 is not used.
     193             :   void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
     194             :                  const uint16_t *DOpcodes, const uint16_t *QOpcodes0,
     195             :                  const uint16_t *QOpcodes1);
     196             : 
     197             :   /// SelectVLDSTLane - Select NEON load/store lane intrinsics.  NumVecs should
     198             :   /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
     199             :   /// load/store of D registers and Q registers.
     200             :   void SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating,
     201             :                        unsigned NumVecs, const uint16_t *DOpcodes,
     202             :                        const uint16_t *QOpcodes);
     203             : 
     204             :   /// SelectVLDDup - Select NEON load-duplicate intrinsics.  NumVecs
     205             :   /// should be 1, 2, 3 or 4.  The opcode array specifies the instructions used
     206             :   /// for loading D registers.
     207             :   void SelectVLDDup(SDNode *N, bool IsIntrinsic, bool isUpdating,
     208             :                     unsigned NumVecs, const uint16_t *DOpcodes,
     209             :                     const uint16_t *QOpcodes0 = nullptr,
     210             :                     const uint16_t *QOpcodes1 = nullptr);
     211             : 
     212             :   /// Try to select SBFX/UBFX instructions for ARM.
     213             :   bool tryV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
     214             : 
     215             :   // Select special operations if node forms integer ABS pattern
     216             :   bool tryABSOp(SDNode *N);
     217             : 
     218             :   bool tryReadRegister(SDNode *N);
     219             :   bool tryWriteRegister(SDNode *N);
     220             : 
     221             :   bool tryInlineAsm(SDNode *N);
     222             : 
     223             :   void SelectCMPZ(SDNode *N, bool &SwitchEQNEToPLMI);
     224             : 
     225             :   void SelectCMP_SWAP(SDNode *N);
     226             : 
     227             :   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
     228             :   /// inline asm expressions.
     229             :   bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
     230             :                                     std::vector<SDValue> &OutOps) override;
     231             : 
     232             :   // Form pairs of consecutive R, S, D, or Q registers.
     233             :   SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
     234             :   SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
     235             :   SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
     236             :   SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
     237             : 
     238             :   // Form sequences of 4 consecutive S, D, or Q registers.
     239             :   SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
     240             :   SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
     241             :   SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
     242             : 
     243             :   // Get the alignment operand for a NEON VLD or VST instruction.
     244             :   SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
     245             :                         bool is64BitVector);
     246             : 
     247             :   /// Returns the number of instructions required to materialize the given
     248             :   /// constant in a register, or 3 if a literal pool load is needed.
     249             :   unsigned ConstantMaterializationCost(unsigned Val) const;
     250             : 
     251             :   /// Checks if N is a multiplication by a constant where we can extract out a
     252             :   /// power of two from the constant so that it can be used in a shift, but only
     253             :   /// if it simplifies the materialization of the constant. Returns true if it
     254             :   /// is, and assigns to PowerOfTwo the power of two that should be extracted
     255             :   /// out and to NewMulConst the new constant to be multiplied by.
     256             :   bool canExtractShiftFromMul(const SDValue &N, unsigned MaxShift,
     257             :                               unsigned &PowerOfTwo, SDValue &NewMulConst) const;
     258             : 
     259             :   /// Replace N with M in CurDAG, in a way that also ensures that M gets
     260             :   /// selected when N would have been selected.
     261             :   void replaceDAGValue(const SDValue &N, SDValue M);
     262             : };
     263             : }
     264             : 
     265             : /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
     266             : /// operand. If so Imm will receive the 32-bit value.
     267             : static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
     268         872 :   if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
     269        1436 :     Imm = cast<ConstantSDNode>(N)->getZExtValue();
     270             :     return true;
     271             :   }
     272             :   return false;
     273             : }
     274             : 
     275             : // isInt32Immediate - This method tests to see if a constant operand.
     276             : // If so Imm will receive the 32 bit value.
     277             : static bool isInt32Immediate(SDValue N, unsigned &Imm) {
     278             :   return isInt32Immediate(N.getNode(), Imm);
     279             : }
     280             : 
     281             : // isOpcWithIntImmediate - This method tests to see if the node is a specific
     282             : // opcode and that it has a immediate integer right operand.
     283             : // If so Imm will receive the 32 bit value.
     284             : static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
     285       13743 :   return N->getOpcode() == Opc &&
     286         848 :          isInt32Immediate(N->getOperand(1).getNode(), Imm);
     287             : }
     288             : 
     289             : /// Check whether a particular node is a constant value representable as
     290             : /// (N * Scale) where (N in [\p RangeMin, \p RangeMax).
     291             : ///
     292             : /// \param ScaledConstant [out] - On success, the pre-scaled constant value.
     293             : static bool isScaledConstantInRange(SDValue Node, int Scale,
     294             :                                     int RangeMin, int RangeMax,
     295             :                                     int &ScaledConstant) {
     296             :   assert(Scale > 0 && "Invalid scale!");
     297             : 
     298             :   // Check that this is a constant.
     299             :   const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
     300             :   if (!C)
     301             :     return false;
     302             : 
     303        8604 :   ScaledConstant = (int) C->getZExtValue();
     304        1081 :   if ((ScaledConstant % Scale) != 0)
     305             :     return false;
     306             : 
     307        1077 :   ScaledConstant /= Scale;
     308        4298 :   return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
     309             : }
     310             : 
     311       17707 : void ARMDAGToDAGISel::PreprocessISelDAG() {
     312       17707 :   if (!Subtarget->hasV6T2Ops())
     313             :     return;
     314             : 
     315       11361 :   bool isThumb2 = Subtarget->isThumb();
     316       11361 :   for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
     317      218768 :        E = CurDAG->allnodes_end(); I != E; ) {
     318             :     SDNode *N = &*I++; // Preincrement iterator to avoid invalidation issues.
     319             : 
     320      207407 :     if (N->getOpcode() != ISD::ADD)
     321      408977 :       continue;
     322             : 
     323             :     // Look for (add X1, (and (srl X2, c1), c2)) where c2 is constant with
     324             :     // leading zeros, followed by consecutive set bits, followed by 1 or 2
     325             :     // trailing zeros, e.g. 1020.
     326             :     // Transform the expression to
     327             :     // (add X1, (shl (and (srl X2, c1), (c2>>tz)), tz)) where tz is the number
     328             :     // of trailing zeros of c2. The left shift would be folded as an shifter
     329             :     // operand of 'add' and the 'and' and 'srl' would become a bits extraction
     330             :     // node (UBFX).
     331             : 
     332        5834 :     SDValue N0 = N->getOperand(0);
     333        5834 :     SDValue N1 = N->getOperand(1);
     334             :     unsigned And_imm = 0;
     335        5834 :     if (!isOpcWithIntImmediate(N1.getNode(), ISD::AND, And_imm)) {
     336             :       if (isOpcWithIntImmediate(N0.getNode(), ISD::AND, And_imm))
     337             :         std::swap(N0, N1);
     338             :     }
     339        5834 :     if (!And_imm)
     340        5749 :       continue;
     341             : 
     342             :     // Check if the AND mask is an immediate of the form: 000.....1111111100
     343          85 :     unsigned TZ = countTrailingZeros(And_imm);
     344          85 :     if (TZ != 1 && TZ != 2)
     345             :       // Be conservative here. Shifter operands aren't always free. e.g. On
     346             :       // Swift, left shifter operand of 1 / 2 for free but others are not.
     347             :       // e.g.
     348             :       //  ubfx   r3, r1, #16, #8
     349             :       //  ldr.w  r3, [r0, r3, lsl #2]
     350             :       // vs.
     351             :       //  mov.w  r9, #1020
     352             :       //  and.w  r2, r9, r1, lsr #14
     353             :       //  ldr    r2, [r0, r2]
     354          75 :       continue;
     355          10 :     And_imm >>= TZ;
     356          10 :     if (And_imm & (And_imm + 1))
     357           0 :       continue;
     358             : 
     359             :     // Look for (and (srl X, c1), c2).
     360          10 :     SDValue Srl = N1.getOperand(0);
     361             :     unsigned Srl_imm = 0;
     362          17 :     if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
     363             :         (Srl_imm <= 2))
     364           7 :       continue;
     365             : 
     366             :     // Make sure first operand is not a shifter operand which would prevent
     367             :     // folding of the left shift.
     368           3 :     SDValue CPTmp0;
     369           3 :     SDValue CPTmp1;
     370           3 :     SDValue CPTmp2;
     371           3 :     if (isThumb2) {
     372           0 :       if (SelectImmShifterOperand(N0, CPTmp0, CPTmp1))
     373           0 :         continue;
     374             :     } else {
     375           6 :       if (SelectImmShifterOperand(N0, CPTmp0, CPTmp1) ||
     376           3 :           SelectRegShifterOperand(N0, CPTmp0, CPTmp1, CPTmp2))
     377           0 :         continue;
     378             :     }
     379             : 
     380             :     // Now make the transformation.
     381           9 :     Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
     382             :                           Srl.getOperand(0),
     383           6 :                           CurDAG->getConstant(Srl_imm + TZ, SDLoc(Srl),
     384           9 :                                               MVT::i32));
     385           9 :     N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
     386             :                          Srl,
     387           9 :                          CurDAG->getConstant(And_imm, SDLoc(Srl), MVT::i32));
     388           9 :     N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
     389           9 :                          N1, CurDAG->getConstant(TZ, SDLoc(Srl), MVT::i32));
     390           3 :     CurDAG->UpdateNodeOperands(N, N0, N1);
     391             :   }
     392             : }
     393             : 
     394             : /// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
     395             : /// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
     396             : /// least on current ARM implementations) which should be avoidded.
     397         491 : bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
     398         491 :   if (OptLevel == CodeGenOpt::None)
     399             :     return true;
     400             : 
     401         475 :   if (!Subtarget->hasVMLxHazards())
     402             :     return true;
     403             : 
     404             :   if (!N->hasOneUse())
     405             :     return false;
     406             : 
     407             :   SDNode *Use = *N->use_begin();
     408         338 :   if (Use->getOpcode() == ISD::CopyToReg)
     409             :     return true;
     410         159 :   if (Use->isMachineOpcode()) {
     411             :     const ARMBaseInstrInfo *TII = static_cast<const ARMBaseInstrInfo *>(
     412         318 :         CurDAG->getSubtarget().getInstrInfo());
     413             : 
     414         318 :     const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
     415         318 :     if (MCID.mayStore())
     416             :       return true;
     417         145 :     unsigned Opcode = MCID.getOpcode();
     418         145 :     if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
     419             :       return true;
     420             :     // vmlx feeding into another vmlx. We actually want to unfold
     421             :     // the use later in the MLxExpansion pass. e.g.
     422             :     // vmla
     423             :     // vmla (stall 8 cycles)
     424             :     //
     425             :     // vmul (5 cycles)
     426             :     // vadd (5 cycles)
     427             :     // vmla
     428             :     // This adds up to about 18 - 19 cycles.
     429             :     //
     430             :     // vmla
     431             :     // vmul (stall 4 cycles)
     432             :     // vadd adds up to about 14 cycles.
     433          72 :     return TII->isFpMLxInstruction(Opcode);
     434             :   }
     435             : 
     436             :   return false;
     437             : }
     438             : 
     439         142 : bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
     440             :                                             ARM_AM::ShiftOpc ShOpcVal,
     441             :                                             unsigned ShAmt) {
     442         270 :   if (!Subtarget->isLikeA9() && !Subtarget->isSwift())
     443             :     return true;
     444          28 :   if (Shift.hasOneUse())
     445             :     return true;
     446             :   // R << 2 is free.
     447           3 :   return ShOpcVal == ARM_AM::lsl &&
     448           2 :          (ShAmt == 2 || (Subtarget->isSwift() && ShAmt == 1));
     449             : }
     450             : 
     451        6214 : unsigned ARMDAGToDAGISel::ConstantMaterializationCost(unsigned Val) const {
     452        6214 :   if (Subtarget->isThumb()) {
     453        3509 :     if (Val <= 255) return 1;                               // MOV
     454        1426 :     if (Subtarget->hasV6T2Ops() &&
     455         656 :         (Val <= 0xffff || ARM_AM::getT2SOImmValSplatVal(Val) != -1))
     456             :       return 1; // MOVW
     457        1009 :     if (Val <= 510) return 2;                               // MOV + ADDi8
     458         964 :     if (~Val <= 255) return 2;                              // MOV + MVN
     459         882 :     if (ARM_AM::isThumbImmShiftedVal(Val)) return 2;        // MOV + LSL
     460             :   } else {
     461        2705 :     if (ARM_AM::getSOImmVal(Val) != -1) return 1;           // MOV
     462         682 :     if (ARM_AM::getSOImmVal(~Val) != -1) return 1;          // MVN
     463         575 :     if (Subtarget->hasV6T2Ops() && Val <= 0xffff) return 1; // MOVW
     464         510 :     if (ARM_AM::isSOImmTwoPartVal(Val)) return 2;           // two instrs
     465             :   }
     466        1051 :   if (Subtarget->useMovt(*MF)) return 2; // MOVW + MOVT
     467             :   return 3; // Literal pool load
     468             : }
     469             : 
     470         188 : bool ARMDAGToDAGISel::canExtractShiftFromMul(const SDValue &N,
     471             :                                              unsigned MaxShift,
     472             :                                              unsigned &PowerOfTwo,
     473             :                                              SDValue &NewMulConst) const {
     474             :   assert(N.getOpcode() == ISD::MUL);
     475             :   assert(MaxShift > 0);
     476             : 
     477             :   // If the multiply is used in more than one place then changing the constant
     478             :   // will make other uses incorrect, so don't.
     479         376 :   if (!N.hasOneUse()) return false;
     480             :   // Check if the multiply is by a constant
     481         153 :   ConstantSDNode *MulConst = dyn_cast<ConstantSDNode>(N.getOperand(1));
     482             :   if (!MulConst) return false;
     483             :   // If the constant is used in more than one place then modifying it will mean
     484             :   // we need to materialize two constants instead of one, which is a bad idea.
     485             :   if (!MulConst->hasOneUse()) return false;
     486         120 :   unsigned MulConstVal = MulConst->getZExtValue();
     487          60 :   if (MulConstVal == 0) return false;
     488             : 
     489             :   // Find the largest power of 2 that MulConstVal is a multiple of
     490          60 :   PowerOfTwo = MaxShift;
     491        1427 :   while ((MulConstVal % (1 << PowerOfTwo)) != 0) {
     492        1377 :     --PowerOfTwo;
     493        1377 :     if (PowerOfTwo == 0) return false;
     494             :   }
     495             : 
     496             :   // Only optimise if the new cost is better
     497          50 :   unsigned NewMulConstVal = MulConstVal / (1 << PowerOfTwo);
     498         150 :   NewMulConst = CurDAG->getConstant(NewMulConstVal, SDLoc(N), MVT::i32);
     499          50 :   unsigned OldCost = ConstantMaterializationCost(MulConstVal);
     500          50 :   unsigned NewCost = ConstantMaterializationCost(NewMulConstVal);
     501          50 :   return NewCost < OldCost;
     502             : }
     503             : 
     504          33 : void ARMDAGToDAGISel::replaceDAGValue(const SDValue &N, SDValue M) {
     505          33 :   CurDAG->RepositionNode(N.getNode()->getIterator(), M.getNode());
     506             :   ReplaceUses(N, M);
     507          33 : }
     508             : 
     509       14364 : bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
     510             :                                               SDValue &BaseReg,
     511             :                                               SDValue &Opc,
     512             :                                               bool CheckProfitability) {
     513       14364 :   if (DisableShifterOp)
     514             :     return false;
     515             : 
     516             :   // If N is a multiply-by-constant and it's profitable to extract a shift and
     517             :   // use it in a shifted operand do so.
     518       28728 :   if (N.getOpcode() == ISD::MUL) {
     519         160 :     unsigned PowerOfTwo = 0;
     520         160 :     SDValue NewMulConst;
     521         160 :     if (canExtractShiftFromMul(N, 31, PowerOfTwo, NewMulConst)) {
     522          36 :       HandleSDNode Handle(N);
     523             :       SDLoc Loc(N);
     524          36 :       replaceDAGValue(N.getOperand(1), NewMulConst);
     525          18 :       BaseReg = Handle.getValue();
     526          36 :       Opc = CurDAG->getTargetConstant(
     527          36 :           ARM_AM::getSORegOpc(ARM_AM::lsl, PowerOfTwo), Loc, MVT::i32);
     528             :       return true;
     529             :     }
     530             :   }
     531             : 
     532       14346 :   ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
     533             : 
     534             :   // Don't match base register only case. That is matched to a separate
     535             :   // lower complexity pattern with explicit register operand.
     536        1137 :   if (ShOpcVal == ARM_AM::no_shift) return false;
     537             : 
     538        1137 :   BaseReg = N.getOperand(0);
     539             :   unsigned ShImmVal = 0;
     540             :   ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
     541             :   if (!RHS) return false;
     542        2242 :   ShImmVal = RHS->getZExtValue() & 31;
     543        2242 :   Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
     544        2242 :                                   SDLoc(N), MVT::i32);
     545        1121 :   return true;
     546             : }
     547             : 
     548        9216 : bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
     549             :                                               SDValue &BaseReg,
     550             :                                               SDValue &ShReg,
     551             :                                               SDValue &Opc,
     552             :                                               bool CheckProfitability) {
     553        9216 :   if (DisableShifterOp)
     554             :     return false;
     555             : 
     556        9216 :   ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
     557             : 
     558             :   // Don't match base register only case. That is matched to a separate
     559             :   // lower complexity pattern with explicit register operand.
     560         968 :   if (ShOpcVal == ARM_AM::no_shift) return false;
     561             : 
     562         968 :   BaseReg = N.getOperand(0);
     563             :   unsigned ShImmVal = 0;
     564             :   ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
     565             :   if (RHS) return false;
     566             : 
     567          36 :   ShReg = N.getOperand(1);
     568          36 :   if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
     569             :     return false;
     570          72 :   Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
     571          72 :                                   SDLoc(N), MVT::i32);
     572          36 :   return true;
     573             : }
     574             : 
     575             : // Determine whether an ISD::OR's operands are suitable to turn the operation
     576             : // into an addition, which often has more compact encodings.
     577             : bool ARMDAGToDAGISel::SelectAddLikeOr(SDNode *Parent, SDValue N, SDValue &Out) {
     578             :   assert(Parent->getOpcode() == ISD::OR && "unexpected parent");
     579         493 :   Out = N;
     580         986 :   return CurDAG->haveNoCommonBitsSet(N, Parent->getOperand(1));
     581             : }
     582             : 
     583             : 
     584        6186 : bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
     585             :                                           SDValue &Base,
     586             :                                           SDValue &OffImm) {
     587             :   // Match simple R + imm12 operands.
     588             : 
     589             :   // Base only.
     590        9501 :   if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
     591        3315 :       !CurDAG->isBaseWithConstantOffset(N)) {
     592        3151 :     if (N.getOpcode() == ISD::FrameIndex) {
     593             :       // Match frame index.
     594        1638 :       int FI = cast<FrameIndexSDNode>(N)->getIndex();
     595        3276 :       Base = CurDAG->getTargetFrameIndex(
     596        1638 :           FI, TLI->getPointerTy(CurDAG->getDataLayout()));
     597        4914 :       OffImm  = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
     598             :       return true;
     599             :     }
     600             : 
     601         390 :     if (N.getOpcode() == ARMISD::Wrapper &&
     602         647 :         N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
     603        1770 :         N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
     604             :         N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
     605         251 :       Base = N.getOperand(0);
     606             :     } else
     607        1262 :       Base = N;
     608        4539 :     OffImm  = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
     609             :     return true;
     610             :   }
     611             : 
     612             :   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
     613        6070 :     int RHSC = (int)RHS->getSExtValue();
     614        3035 :     if (N.getOpcode() == ISD::SUB)
     615           0 :       RHSC = -RHSC;
     616             : 
     617        3035 :     if (RHSC > -0x1000 && RHSC < 0x1000) { // 12 bits
     618        3035 :       Base   = N.getOperand(0);
     619        6070 :       if (Base.getOpcode() == ISD::FrameIndex) {
     620        1354 :         int FI = cast<FrameIndexSDNode>(Base)->getIndex();
     621        2708 :         Base = CurDAG->getTargetFrameIndex(
     622        1354 :             FI, TLI->getPointerTy(CurDAG->getDataLayout()));
     623             :       }
     624       12140 :       OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32);
     625             :       return true;
     626             :     }
     627             :   }
     628             : 
     629             :   // Base only.
     630           0 :   Base = N;
     631           0 :   OffImm  = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
     632             :   return true;
     633             : }
     634             : 
     635             : 
     636             : 
     637        6340 : bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
     638             :                                       SDValue &Opc) {
     639        6340 :   if (N.getOpcode() == ISD::MUL &&
     640           0 :       ((!Subtarget->isLikeA9() && !Subtarget->isSwift()) || N.hasOneUse())) {
     641             :     if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
     642             :       // X * [3,5,9] -> X + X * [2,4,8] etc.
     643           0 :       int RHSC = (int)RHS->getZExtValue();
     644           0 :       if (RHSC & 1) {
     645           0 :         RHSC = RHSC & ~1;
     646             :         ARM_AM::AddrOpc AddSub = ARM_AM::add;
     647           0 :         if (RHSC < 0) {
     648             :           AddSub = ARM_AM::sub;
     649           0 :           RHSC = - RHSC;
     650             :         }
     651           0 :         if (isPowerOf2_32(RHSC)) {
     652             :           unsigned ShAmt = Log2_32(RHSC);
     653           0 :           Base = Offset = N.getOperand(0);
     654           0 :           Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
     655             :                                                             ARM_AM::lsl),
     656           0 :                                           SDLoc(N), MVT::i32);
     657           0 :           return true;
     658             :         }
     659             :       }
     660             :     }
     661             :   }
     662             : 
     663        9667 :   if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
     664             :       // ISD::OR that is equivalent to an ISD::ADD.
     665        3327 :       !CurDAG->isBaseWithConstantOffset(N))
     666             :     return false;
     667             : 
     668             :   // Leave simple R +/- imm12 operands for LDRi12
     669        3177 :   if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
     670             :     int RHSC;
     671        3175 :     if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
     672             :                                 -0x1000+1, 0x1000, RHSC)) // 12 bits.
     673             :       return false;
     674             :   }
     675             : 
     676             :   // Otherwise this is R +/- [possibly shifted] R.
     677         142 :   ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
     678             :   ARM_AM::ShiftOpc ShOpcVal =
     679         142 :     ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
     680             :   unsigned ShAmt = 0;
     681             : 
     682         142 :   Base   = N.getOperand(0);
     683         142 :   Offset = N.getOperand(1);
     684             : 
     685         142 :   if (ShOpcVal != ARM_AM::no_shift) {
     686             :     // Check to see if the RHS of the shift is a constant, if not, we can't fold
     687             :     // it.
     688             :     if (ConstantSDNode *Sh =
     689          69 :            dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
     690         138 :       ShAmt = Sh->getZExtValue();
     691          69 :       if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
     692         138 :         Offset = N.getOperand(1).getOperand(0);
     693             :       else {
     694             :         ShAmt = 0;
     695             :         ShOpcVal = ARM_AM::no_shift;
     696             :       }
     697             :     } else {
     698             :       ShOpcVal = ARM_AM::no_shift;
     699             :     }
     700             :   }
     701             : 
     702             :   // Try matching (R shl C) + (R).
     703         142 :   if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
     704         193 :       !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
     705          60 :         N.getOperand(0).hasOneUse())) {
     706           5 :     ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
     707           0 :     if (ShOpcVal != ARM_AM::no_shift) {
     708             :       // Check to see if the RHS of the shift is a constant, if not, we can't
     709             :       // fold it.
     710             :       if (ConstantSDNode *Sh =
     711             :           dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
     712           0 :         ShAmt = Sh->getZExtValue();
     713           0 :         if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
     714           0 :           Offset = N.getOperand(0).getOperand(0);
     715           0 :           Base = N.getOperand(1);
     716             :         } else {
     717             :           ShAmt = 0;
     718             :           ShOpcVal = ARM_AM::no_shift;
     719             :         }
     720             :       } else {
     721             :         ShOpcVal = ARM_AM::no_shift;
     722             :       }
     723             :     }
     724             :   }
     725             : 
     726             :   // If Offset is a multiply-by-constant and it's profitable to extract a shift
     727             :   // and use it in a shifted operand do so.
     728         301 :   if (Offset.getOpcode() == ISD::MUL && N.hasOneUse()) {
     729          17 :     unsigned PowerOfTwo = 0;
     730          17 :     SDValue NewMulConst;
     731          17 :     if (canExtractShiftFromMul(Offset, 31, PowerOfTwo, NewMulConst)) {
     732          22 :       HandleSDNode Handle(Offset);
     733          22 :       replaceDAGValue(Offset.getOperand(1), NewMulConst);
     734          11 :       Offset = Handle.getValue();
     735          11 :       ShAmt = PowerOfTwo;
     736             :       ShOpcVal = ARM_AM::lsl;
     737             :     }
     738             :   }
     739             : 
     740         284 :   Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
     741         284 :                                   SDLoc(N), MVT::i32);
     742         142 :   return true;
     743             : }
     744             : 
     745          23 : bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
     746             :                                             SDValue &Offset, SDValue &Opc) {
     747          23 :   unsigned Opcode = Op->getOpcode();
     748             :   ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
     749          23 :     ? cast<LoadSDNode>(Op)->getAddressingMode()
     750             :     : cast<StoreSDNode>(Op)->getAddressingMode();
     751          23 :   ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
     752          23 :     ? ARM_AM::add : ARM_AM::sub;
     753             :   int Val;
     754          23 :   if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
     755             :     return false;
     756             : 
     757          17 :   Offset = N;
     758             :   ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
     759             :   unsigned ShAmt = 0;
     760           5 :   if (ShOpcVal != ARM_AM::no_shift) {
     761             :     // Check to see if the RHS of the shift is a constant, if not, we can't fold
     762             :     // it.
     763             :     if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
     764          10 :       ShAmt = Sh->getZExtValue();
     765           5 :       if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
     766           6 :         Offset = N.getOperand(0);
     767             :       else {
     768             :         ShAmt = 0;
     769             :         ShOpcVal = ARM_AM::no_shift;
     770             :       }
     771             :     } else {
     772             :       ShOpcVal = ARM_AM::no_shift;
     773             :     }
     774             :   }
     775             : 
     776          34 :   Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
     777          34 :                                   SDLoc(N), MVT::i32);
     778          17 :   return true;
     779             : }
     780             : 
     781          18 : bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
     782             :                                             SDValue &Offset, SDValue &Opc) {
     783          18 :   unsigned Opcode = Op->getOpcode();
     784             :   ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
     785          18 :     ? cast<LoadSDNode>(Op)->getAddressingMode()
     786             :     : cast<StoreSDNode>(Op)->getAddressingMode();
     787          18 :   ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
     788          18 :     ? ARM_AM::add : ARM_AM::sub;
     789             :   int Val;
     790          18 :   if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
     791           9 :     if (AddSub == ARM_AM::sub) Val *= -1;
     792          18 :     Offset = CurDAG->getRegister(0, MVT::i32);
     793          36 :     Opc = CurDAG->getTargetConstant(Val, SDLoc(Op), MVT::i32);
     794             :     return true;
     795             :   }
     796             : 
     797             :   return false;
     798             : }
     799             : 
     800             : 
     801          34 : bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
     802             :                                             SDValue &Offset, SDValue &Opc) {
     803          34 :   unsigned Opcode = Op->getOpcode();
     804             :   ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
     805          34 :     ? cast<LoadSDNode>(Op)->getAddressingMode()
     806             :     : cast<StoreSDNode>(Op)->getAddressingMode();
     807          34 :   ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
     808          34 :     ? ARM_AM::add : ARM_AM::sub;
     809             :   int Val;
     810          34 :   if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
     811          54 :     Offset = CurDAG->getRegister(0, MVT::i32);
     812          81 :     Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
     813             :                                                       ARM_AM::no_shift),
     814          54 :                                     SDLoc(Op), MVT::i32);
     815             :     return true;
     816             :   }
     817             : 
     818             :   return false;
     819             : }
     820             : 
     821             : bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
     822         422 :   Base = N;
     823             :   return true;
     824             : }
     825             : 
     826         577 : bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
     827             :                                       SDValue &Base, SDValue &Offset,
     828             :                                       SDValue &Opc) {
     829         577 :   if (N.getOpcode() == ISD::SUB) {
     830             :     // X - C  is canonicalize to X + -C, no need to handle it here.
     831           0 :     Base = N.getOperand(0);
     832           0 :     Offset = N.getOperand(1);
     833           0 :     Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0), SDLoc(N),
     834             :                                     MVT::i32);
     835             :     return true;
     836             :   }
     837             : 
     838         577 :   if (!CurDAG->isBaseWithConstantOffset(N)) {
     839         503 :     Base = N;
     840         503 :     if (N.getOpcode() == ISD::FrameIndex) {
     841          48 :       int FI = cast<FrameIndexSDNode>(N)->getIndex();
     842          96 :       Base = CurDAG->getTargetFrameIndex(
     843          48 :           FI, TLI->getPointerTy(CurDAG->getDataLayout()));
     844             :     }
     845        1006 :     Offset = CurDAG->getRegister(0, MVT::i32);
     846        1509 :     Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), SDLoc(N),
     847             :                                     MVT::i32);
     848             :     return true;
     849             :   }
     850             : 
     851             :   // If the RHS is +/- imm8, fold into addr mode.
     852             :   int RHSC;
     853          74 :   if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
     854             :                               -256 + 1, 256, RHSC)) { // 8 bits.
     855          74 :     Base = N.getOperand(0);
     856         148 :     if (Base.getOpcode() == ISD::FrameIndex) {
     857           9 :       int FI = cast<FrameIndexSDNode>(Base)->getIndex();
     858          18 :       Base = CurDAG->getTargetFrameIndex(
     859           9 :           FI, TLI->getPointerTy(CurDAG->getDataLayout()));
     860             :     }
     861         148 :     Offset = CurDAG->getRegister(0, MVT::i32);
     862             : 
     863             :     ARM_AM::AddrOpc AddSub = ARM_AM::add;
     864          74 :     if (RHSC < 0) {
     865             :       AddSub = ARM_AM::sub;
     866           0 :       RHSC = -RHSC;
     867             :     }
     868         222 :     Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC), SDLoc(N),
     869          74 :                                     MVT::i32);
     870             :     return true;
     871             :   }
     872             : 
     873           0 :   Base = N.getOperand(0);
     874           0 :   Offset = N.getOperand(1);
     875           0 :   Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), SDLoc(N),
     876             :                                   MVT::i32);
     877             :   return true;
     878             : }
     879             : 
     880          14 : bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
     881             :                                             SDValue &Offset, SDValue &Opc) {
     882          14 :   unsigned Opcode = Op->getOpcode();
     883             :   ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
     884          14 :     ? cast<LoadSDNode>(Op)->getAddressingMode()
     885             :     : cast<StoreSDNode>(Op)->getAddressingMode();
     886          14 :   ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
     887          14 :     ? ARM_AM::add : ARM_AM::sub;
     888             :   int Val;
     889          14 :   if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
     890          28 :     Offset = CurDAG->getRegister(0, MVT::i32);
     891          42 :     Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), SDLoc(Op),
     892          14 :                                     MVT::i32);
     893             :     return true;
     894             :   }
     895             : 
     896           0 :   Offset = N;
     897           0 :   Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), SDLoc(Op),
     898           0 :                                   MVT::i32);
     899             :   return true;
     900             : }
     901             : 
     902        3653 : bool ARMDAGToDAGISel::IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset,
     903             :                                         int Lwb, int Upb, bool FP16) {
     904        3653 :   if (!CurDAG->isBaseWithConstantOffset(N)) {
     905        3410 :     Base = N;
     906        3410 :     if (N.getOpcode() == ISD::FrameIndex) {
     907         363 :       int FI = cast<FrameIndexSDNode>(N)->getIndex();
     908         726 :       Base = CurDAG->getTargetFrameIndex(
     909         363 :           FI, TLI->getPointerTy(CurDAG->getDataLayout()));
     910        1077 :     } else if (N.getOpcode() == ARMISD::Wrapper &&
     911        2065 :                N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
     912        4035 :                N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
     913             :                N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
     914         988 :       Base = N.getOperand(0);
     915             :     }
     916        6820 :     Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
     917        3410 :                                        SDLoc(N), MVT::i32);
     918        3410 :     return true;
     919             :   }
     920             : 
     921             :   // If the RHS is +/- imm8, fold into addr mode.
     922             :   int RHSC;
     923         243 :   const int Scale = FP16 ? 2 : 4;
     924             : 
     925         243 :   if (isScaledConstantInRange(N.getOperand(1), Scale, Lwb, Upb, RHSC)) {
     926         243 :     Base = N.getOperand(0);
     927         486 :     if (Base.getOpcode() == ISD::FrameIndex) {
     928           2 :       int FI = cast<FrameIndexSDNode>(Base)->getIndex();
     929           4 :       Base = CurDAG->getTargetFrameIndex(
     930           2 :           FI, TLI->getPointerTy(CurDAG->getDataLayout()));
     931             :     }
     932             : 
     933             :     ARM_AM::AddrOpc AddSub = ARM_AM::add;
     934         243 :     if (RHSC < 0) {
     935             :       AddSub = ARM_AM::sub;
     936           2 :       RHSC = -RHSC;
     937             :     }
     938             : 
     939         243 :     if (FP16)
     940           0 :       Offset = CurDAG->getTargetConstant(ARM_AM::getAM5FP16Opc(AddSub, RHSC),
     941           0 :                                          SDLoc(N), MVT::i32);
     942             :     else
     943         486 :       Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
     944         486 :                                          SDLoc(N), MVT::i32);
     945             : 
     946             :     return true;
     947             :   }
     948             : 
     949           0 :   Base = N;
     950             : 
     951           0 :   if (FP16)
     952           0 :     Offset = CurDAG->getTargetConstant(ARM_AM::getAM5FP16Opc(ARM_AM::add, 0),
     953           0 :                                        SDLoc(N), MVT::i32);
     954             :   else
     955           0 :     Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
     956           0 :                                        SDLoc(N), MVT::i32);
     957             : 
     958             :   return true;
     959             : }
     960             : 
     961             : bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
     962             :                                       SDValue &Base, SDValue &Offset) {
     963             :   int Lwb = -256 + 1;
     964             :   int Upb = 256;
     965        3167 :   return IsAddressingMode5(N, Base, Offset, Lwb, Upb, /*FP16=*/ false);
     966             : }
     967             : 
     968             : bool ARMDAGToDAGISel::SelectAddrMode5FP16(SDValue N,
     969             :                                           SDValue &Base, SDValue &Offset) {
     970             :   int Lwb = -512 + 1;
     971             :   int Upb = 512;
     972         486 :   return IsAddressingMode5(N, Base, Offset, Lwb, Upb, /*FP16=*/ true);
     973             : }
     974             : 
     975        3968 : bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
     976             :                                       SDValue &Align) {
     977        3968 :   Addr = N;
     978             : 
     979             :   unsigned Alignment = 0;
     980             : 
     981             :   MemSDNode *MemN = cast<MemSDNode>(Parent);
     982             : 
     983         715 :   if (isa<LSBaseSDNode>(MemN) ||
     984         577 :       ((MemN->getOpcode() == ARMISD::VST1_UPD ||
     985         250 :         MemN->getOpcode() == ARMISD::VLD1_UPD) &&
     986         500 :        MemN->getConstantOperandVal(MemN->getNumOperands() - 1) == 1)) {
     987             :     // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
     988             :     // The maximum alignment is equal to the memory size being referenced.
     989        3500 :     unsigned MMOAlign = MemN->getAlignment();
     990        3500 :     unsigned MemSize = MemN->getMemoryVT().getSizeInBits() / 8;
     991        3500 :     if (MMOAlign >= MemSize && MemSize > 1)
     992             :       Alignment = MemSize;
     993             :   } else {
     994             :     // All other uses of addrmode6 are for intrinsics.  For now just record
     995             :     // the raw alignment value; it will be refined later based on the legal
     996             :     // alignment operands for the intrinsic.
     997         468 :     Alignment = MemN->getAlignment();
     998             :   }
     999             : 
    1000       15872 :   Align = CurDAG->getTargetConstant(Alignment, SDLoc(N), MVT::i32);
    1001        3968 :   return true;
    1002             : }
    1003             : 
    1004           4 : bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
    1005             :                                             SDValue &Offset) {
    1006             :   LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
    1007             :   ISD::MemIndexedMode AM = LdSt->getAddressingMode();
    1008           4 :   if (AM != ISD::POST_INC)
    1009             :     return false;
    1010           4 :   Offset = N;
    1011             :   if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
    1012           8 :     if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
    1013           6 :       Offset = CurDAG->getRegister(0, MVT::i32);
    1014             :   }
    1015             :   return true;
    1016             : }
    1017             : 
    1018        7055 : bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
    1019             :                                        SDValue &Offset, SDValue &Label) {
    1020        7067 :   if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
    1021          12 :     Offset = N.getOperand(0);
    1022          12 :     SDValue N1 = N.getOperand(1);
    1023          24 :     Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
    1024          24 :                                       SDLoc(N), MVT::i32);
    1025             :     return true;
    1026             :   }
    1027             : 
    1028             :   return false;
    1029             : }
    1030             : 
    1031             : 
    1032             : //===----------------------------------------------------------------------===//
    1033             : //                         Thumb Addressing Modes
    1034             : //===----------------------------------------------------------------------===//
    1035             : 
    1036         276 : bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
    1037             :                                             SDValue &Base, SDValue &Offset){
    1038         276 :   if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
    1039             :     ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
    1040           4 :     if (!NC || !NC->isNullValue())
    1041             :       return false;
    1042             : 
    1043           2 :     Base = Offset = N;
    1044             :     return true;
    1045             :   }
    1046             : 
    1047         253 :   Base = N.getOperand(0);
    1048         253 :   Offset = N.getOperand(1);
    1049             :   return true;
    1050             : }
    1051             : 
    1052             : bool
    1053        1137 : ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
    1054             :                                           SDValue &Base, SDValue &OffImm) {
    1055        1137 :   if (!CurDAG->isBaseWithConstantOffset(N)) {
    1056         808 :     if (N.getOpcode() == ISD::ADD) {
    1057             :       return false; // We want to select register offset instead
    1058          22 :     } else if (N.getOpcode() == ARMISD::Wrapper &&
    1059          32 :         N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
    1060          10 :         N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
    1061         643 :         N.getOperand(0).getOpcode() != ISD::TargetConstantPool &&
    1062             :         N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
    1063           0 :       Base = N.getOperand(0);
    1064             :     } else {
    1065         643 :       Base = N;
    1066             :     }
    1067             : 
    1068        1929 :     OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
    1069             :     return true;
    1070             :   }
    1071             : 
    1072             :   // If the RHS is + imm5 * scale, fold into addr mode.
    1073             :   int RHSC;
    1074         658 :   if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
    1075         254 :     Base = N.getOperand(0);
    1076        1016 :     OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32);
    1077             :     return true;
    1078             :   }
    1079             : 
    1080             :   // Offset is too large, so use register offset instead.
    1081             :   return false;
    1082             : }
    1083             : 
    1084             : bool
    1085             : ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
    1086             :                                            SDValue &OffImm) {
    1087         917 :   return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
    1088             : }
    1089             : 
    1090             : bool
    1091             : ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
    1092             :                                            SDValue &OffImm) {
    1093         112 :   return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
    1094             : }
    1095             : 
    1096             : bool
    1097             : ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
    1098             :                                            SDValue &OffImm) {
    1099         108 :   return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
    1100             : }
    1101             : 
    1102        1823 : bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
    1103             :                                             SDValue &Base, SDValue &OffImm) {
    1104        1823 :   if (N.getOpcode() == ISD::FrameIndex) {
    1105         372 :     int FI = cast<FrameIndexSDNode>(N)->getIndex();
    1106             :     // Only multiples of 4 are allowed for the offset, so the frame object
    1107             :     // alignment must be at least 4.
    1108         372 :     MachineFrameInfo &MFI = MF->getFrameInfo();
    1109         372 :     if (MFI.getObjectAlignment(FI) < 4)
    1110             :       MFI.setObjectAlignment(FI, 4);
    1111         744 :     Base = CurDAG->getTargetFrameIndex(
    1112         372 :         FI, TLI->getPointerTy(CurDAG->getDataLayout()));
    1113        1116 :     OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
    1114             :     return true;
    1115             :   }
    1116             : 
    1117        1451 :   if (!CurDAG->isBaseWithConstantOffset(N))
    1118             :     return false;
    1119             : 
    1120             :   RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
    1121         794 :   if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
    1122           0 :       (LHSR && LHSR->getReg() == ARM::SP)) {
    1123             :     // If the RHS is + imm8 * scale, fold into addr mode.
    1124             :     int RHSC;
    1125         509 :     if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
    1126         509 :       Base = N.getOperand(0);
    1127         509 :       if (Base.getOpcode() == ISD::FrameIndex) {
    1128         509 :         int FI = cast<FrameIndexSDNode>(Base)->getIndex();
    1129             :         // For LHS+RHS to result in an offset that's a multiple of 4 the object
    1130             :         // indexed by the LHS must be 4-byte aligned.
    1131         509 :         MachineFrameInfo &MFI = MF->getFrameInfo();
    1132         509 :         if (MFI.getObjectAlignment(FI) < 4)
    1133             :           MFI.setObjectAlignment(FI, 4);
    1134        1018 :         Base = CurDAG->getTargetFrameIndex(
    1135         509 :             FI, TLI->getPointerTy(CurDAG->getDataLayout()));
    1136             :       }
    1137        2036 :       OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32);
    1138             :       return true;
    1139             :     }
    1140             :   }
    1141             : 
    1142             :   return false;
    1143             : }
    1144             : 
    1145             : 
    1146             : //===----------------------------------------------------------------------===//
    1147             : //                        Thumb 2 Addressing Modes
    1148             : //===----------------------------------------------------------------------===//
    1149             : 
    1150             : 
    1151        4320 : bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
    1152             :                                             SDValue &Base, SDValue &OffImm) {
    1153             :   // Match simple R + imm12 operands.
    1154             : 
    1155             :   // Base only.
    1156        6837 :   if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
    1157        2517 :       !CurDAG->isBaseWithConstantOffset(N)) {
    1158        2460 :     if (N.getOpcode() == ISD::FrameIndex) {
    1159             :       // Match frame index.
    1160         983 :       int FI = cast<FrameIndexSDNode>(N)->getIndex();
    1161        1966 :       Base = CurDAG->getTargetFrameIndex(
    1162         983 :           FI, TLI->getPointerTy(CurDAG->getDataLayout()));
    1163        2949 :       OffImm  = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
    1164         983 :       return true;
    1165             :     }
    1166             : 
    1167         218 :     if (N.getOpcode() == ARMISD::Wrapper &&
    1168         290 :         N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
    1169        1542 :         N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
    1170             :         N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
    1171          59 :       Base = N.getOperand(0);
    1172          59 :       if (Base.getOpcode() == ISD::TargetConstantPool)
    1173             :         return false;  // We want to select t2LDRpci instead.
    1174             :     } else
    1175        1418 :       Base = N;
    1176        4254 :     OffImm  = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
    1177        1418 :     return true;
    1178             :   }
    1179             : 
    1180             :   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
    1181        1860 :     if (SelectT2AddrModeImm8(N, Base, OffImm))
    1182             :       // Let t2LDRi8 handle (R - imm8).
    1183             :       return false;
    1184             : 
    1185        3670 :     int RHSC = (int)RHS->getZExtValue();
    1186        1835 :     if (N.getOpcode() == ISD::SUB)
    1187           0 :       RHSC = -RHSC;
    1188             : 
    1189        1835 :     if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
    1190        1835 :       Base   = N.getOperand(0);
    1191        3670 :       if (Base.getOpcode() == ISD::FrameIndex) {
    1192         803 :         int FI = cast<FrameIndexSDNode>(Base)->getIndex();
    1193        1606 :         Base = CurDAG->getTargetFrameIndex(
    1194         803 :             FI, TLI->getPointerTy(CurDAG->getDataLayout()));
    1195             :       }
    1196        7340 :       OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32);
    1197        1835 :       return true;
    1198             :     }
    1199             :   }
    1200             : 
    1201             :   // Base only.
    1202           0 :   Base = N;
    1203           0 :   OffImm  = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
    1204           0 :   return true;
    1205             : }
    1206             : 
    1207        1944 : bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
    1208             :                                            SDValue &Base, SDValue &OffImm) {
    1209             :   // Match simple R - imm8 operands.
    1210        2060 :   if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
    1211         116 :       !CurDAG->isBaseWithConstantOffset(N))
    1212             :     return false;
    1213             : 
    1214             :   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
    1215        3770 :     int RHSC = (int)RHS->getSExtValue();
    1216        1885 :     if (N.getOpcode() == ISD::SUB)
    1217           0 :       RHSC = -RHSC;
    1218             : 
    1219        1885 :     if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
    1220          50 :       Base = N.getOperand(0);
    1221         100 :       if (Base.getOpcode() == ISD::FrameIndex) {
    1222           0 :         int FI = cast<FrameIndexSDNode>(Base)->getIndex();
    1223           0 :         Base = CurDAG->getTargetFrameIndex(
    1224           0 :             FI, TLI->getPointerTy(CurDAG->getDataLayout()));
    1225             :       }
    1226         200 :       OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32);
    1227             :       return true;
    1228             :     }
    1229             :   }
    1230             : 
    1231             :   return false;
    1232             : }
    1233             : 
    1234          49 : bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
    1235             :                                                  SDValue &OffImm){
    1236          49 :   unsigned Opcode = Op->getOpcode();
    1237             :   ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
    1238          49 :     ? cast<LoadSDNode>(Op)->getAddressingMode()
    1239             :     : cast<StoreSDNode>(Op)->getAddressingMode();
    1240             :   int RHSC;
    1241             :   if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
    1242          98 :     OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
    1243         188 :       ? CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32)
    1244         114 :       : CurDAG->getTargetConstant(-RHSC, SDLoc(N), MVT::i32);
    1245             :     return true;
    1246             :   }
    1247             : 
    1248             :   return false;
    1249             : }
    1250             : 
    1251        4473 : bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
    1252             :                                             SDValue &Base,
    1253             :                                             SDValue &OffReg, SDValue &ShImm) {
    1254             :   // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
    1255        4473 :   if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
    1256             :     return false;
    1257             : 
    1258             :   // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
    1259             :   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
    1260        1875 :     int RHSC = (int)RHS->getZExtValue();
    1261        1875 :     if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
    1262             :       return false;
    1263          40 :     else if (RHSC < 0 && RHSC >= -255) // 8 bits
    1264             :       return false;
    1265             :   }
    1266             : 
    1267             :   // Look for (R + R) or (R + (R << [1,2,3])).
    1268             :   unsigned ShAmt = 0;
    1269         153 :   Base   = N.getOperand(0);
    1270         153 :   OffReg = N.getOperand(1);
    1271             : 
    1272             :   // Swap if it is ((R << c) + R).
    1273         153 :   ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
    1274          53 :   if (ShOpcVal != ARM_AM::lsl) {
    1275         107 :     ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
    1276           0 :     if (ShOpcVal == ARM_AM::lsl)
    1277             :       std::swap(Base, OffReg);
    1278             :   }
    1279             : 
    1280         153 :   if (ShOpcVal == ARM_AM::lsl) {
    1281             :     // Check to see if the RHS of the shift is a constant, if not, we can't fold
    1282             :     // it.
    1283          46 :     if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
    1284          92 :       ShAmt = Sh->getZExtValue();
    1285          46 :       if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
    1286          92 :         OffReg = OffReg.getOperand(0);
    1287             :       else {
    1288             :         ShAmt = 0;
    1289             :       }
    1290             :     }
    1291             :   }
    1292             : 
    1293             :   // If OffReg is a multiply-by-constant and it's profitable to extract a shift
    1294             :   // and use it in a shifted operand do so.
    1295         318 :   if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) {
    1296          11 :     unsigned PowerOfTwo = 0;
    1297          11 :     SDValue NewMulConst;
    1298          11 :     if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) {
    1299           8 :       HandleSDNode Handle(OffReg);
    1300           8 :       replaceDAGValue(OffReg.getOperand(1), NewMulConst);
    1301           4 :       OffReg = Handle.getValue();
    1302           4 :       ShAmt = PowerOfTwo;
    1303             :     }
    1304             :   }
    1305             : 
    1306         612 :   ShImm = CurDAG->getTargetConstant(ShAmt, SDLoc(N), MVT::i32);
    1307             : 
    1308         153 :   return true;
    1309             : }
    1310             : 
    1311          79 : bool ARMDAGToDAGISel::SelectT2AddrModeExclusive(SDValue N, SDValue &Base,
    1312             :                                                 SDValue &OffImm) {
    1313             :   // This *must* succeed since it's used for the irreplaceable ldrex and strex
    1314             :   // instructions.
    1315          79 :   Base = N;
    1316         237 :   OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
    1317             : 
    1318          79 :   if (N.getOpcode() != ISD::ADD || !CurDAG->isBaseWithConstantOffset(N))
    1319             :     return true;
    1320             : 
    1321             :   ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
    1322             :   if (!RHS)
    1323             :     return true;
    1324             : 
    1325          12 :   uint32_t RHSC = (int)RHS->getZExtValue();
    1326           6 :   if (RHSC > 1020 || RHSC % 4 != 0)
    1327             :     return true;
    1328             : 
    1329           2 :   Base = N.getOperand(0);
    1330           4 :   if (Base.getOpcode() == ISD::FrameIndex) {
    1331           0 :     int FI = cast<FrameIndexSDNode>(Base)->getIndex();
    1332           0 :     Base = CurDAG->getTargetFrameIndex(
    1333           0 :         FI, TLI->getPointerTy(CurDAG->getDataLayout()));
    1334             :   }
    1335             : 
    1336           8 :   OffImm = CurDAG->getTargetConstant(RHSC/4, SDLoc(N), MVT::i32);
    1337             :   return true;
    1338             : }
    1339             : 
    1340             : //===--------------------------------------------------------------------===//
    1341             : 
    1342             : /// getAL - Returns a ARMCC::AL immediate node.
    1343        3778 : static inline SDValue getAL(SelectionDAG *CurDAG, const SDLoc &dl) {
    1344        3778 :   return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, dl, MVT::i32);
    1345             : }
    1346             : 
    1347             : void ARMDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
    1348          69 :   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
    1349          69 :   MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
    1350          69 :   cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
    1351             : }
    1352             : 
    1353        7354 : bool ARMDAGToDAGISel::tryARMIndexedLoad(SDNode *N) {
    1354             :   LoadSDNode *LD = cast<LoadSDNode>(N);
    1355             :   ISD::MemIndexedMode AM = LD->getAddressingMode();
    1356        7354 :   if (AM == ISD::UNINDEXED)
    1357             :     return false;
    1358             : 
    1359             :   EVT LoadedVT = LD->getMemoryVT();
    1360          43 :   SDValue Offset, AMOpc;
    1361          43 :   bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
    1362             :   unsigned Opcode = 0;
    1363             :   bool Match = false;
    1364          38 :   if (LoadedVT == MVT::i32 && isPre &&
    1365          11 :       SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
    1366             :     Opcode = ARM::LDR_PRE_IMM;
    1367             :     Match = true;
    1368          41 :   } else if (LoadedVT == MVT::i32 && !isPre &&
    1369          16 :       SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
    1370             :     Opcode = ARM::LDR_POST_IMM;
    1371             :     Match = true;
    1372          14 :   } else if (LoadedVT == MVT::i32 &&
    1373          14 :       SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
    1374          14 :     Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
    1375             :     Match = true;
    1376             : 
    1377           4 :   } else if (LoadedVT == MVT::i16 &&
    1378           4 :              SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
    1379             :     Match = true;
    1380             :     Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
    1381           4 :       ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
    1382             :       : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
    1383             :   } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
    1384          12 :     if (LD->getExtensionType() == ISD::SEXTLOAD) {
    1385           5 :       if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
    1386             :         Match = true;
    1387           5 :         Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
    1388             :       }
    1389             :     } else {
    1390          14 :       if (isPre &&
    1391           7 :           SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
    1392             :         Match = true;
    1393             :         Opcode = ARM::LDRB_PRE_IMM;
    1394           0 :       } else if (!isPre &&
    1395           0 :                   SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
    1396             :         Match = true;
    1397             :         Opcode = ARM::LDRB_POST_IMM;
    1398           0 :       } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
    1399             :         Match = true;
    1400           0 :         Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
    1401             :       }
    1402             :     }
    1403             :   }
    1404             : 
    1405             :   if (Match) {
    1406          43 :     if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
    1407           9 :       SDValue Chain = LD->getChain();
    1408           9 :       SDValue Base = LD->getBasePtr();
    1409          18 :       SDValue Ops[]= { Base, AMOpc, getAL(CurDAG, SDLoc(N)),
    1410          36 :                        CurDAG->getRegister(0, MVT::i32), Chain };
    1411          18 :       SDNode *New = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
    1412           9 :                                            MVT::Other, Ops);
    1413           9 :       transferMemOperands(N, New);
    1414           9 :       ReplaceNode(N, New);
    1415             :       return true;
    1416             :     } else {
    1417          34 :       SDValue Chain = LD->getChain();
    1418          34 :       SDValue Base = LD->getBasePtr();
    1419          68 :       SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG, SDLoc(N)),
    1420         136 :                        CurDAG->getRegister(0, MVT::i32), Chain };
    1421          68 :       SDNode *New = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
    1422          34 :                                            MVT::Other, Ops);
    1423          34 :       transferMemOperands(N, New);
    1424          34 :       ReplaceNode(N, New);
    1425             :       return true;
    1426             :     }
    1427             :   }
    1428             : 
    1429             :   return false;
    1430             : }
    1431             : 
    1432        1656 : bool ARMDAGToDAGISel::tryT1IndexedLoad(SDNode *N) {
    1433             :   LoadSDNode *LD = cast<LoadSDNode>(N);
    1434             :   EVT LoadedVT = LD->getMemoryVT();
    1435             :   ISD::MemIndexedMode AM = LD->getAddressingMode();
    1436        1659 :   if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD ||
    1437             :       LoadedVT.getSimpleVT().SimpleTy != MVT::i32)
    1438             :     return false;
    1439             : 
    1440             :   auto *COffs = dyn_cast<ConstantSDNode>(LD->getOffset());
    1441           6 :   if (!COffs || COffs->getZExtValue() != 4)
    1442             :     return false;
    1443             : 
    1444             :   // A T1 post-indexed load is just a single register LDM: LDM r0!, {r1}.
    1445             :   // The encoding of LDM is not how the rest of ISel expects a post-inc load to
    1446             :   // look however, so we use a pseudo here and switch it for a tLDMIA_UPD after
    1447             :   // ISel.
    1448           3 :   SDValue Chain = LD->getChain();
    1449           3 :   SDValue Base = LD->getBasePtr();
    1450           6 :   SDValue Ops[]= { Base, getAL(CurDAG, SDLoc(N)),
    1451          12 :                    CurDAG->getRegister(0, MVT::i32), Chain };
    1452           6 :   SDNode *New = CurDAG->getMachineNode(ARM::tLDR_postidx, SDLoc(N), MVT::i32,
    1453           3 :                                        MVT::i32, MVT::Other, Ops);
    1454           3 :   transferMemOperands(N, New);
    1455           3 :   ReplaceNode(N, New);
    1456           3 :   return true;
    1457             : }
    1458             : 
    1459        3921 : bool ARMDAGToDAGISel::tryT2IndexedLoad(SDNode *N) {
    1460             :   LoadSDNode *LD = cast<LoadSDNode>(N);
    1461             :   ISD::MemIndexedMode AM = LD->getAddressingMode();
    1462        3921 :   if (AM == ISD::UNINDEXED)
    1463             :     return false;
    1464             : 
    1465             :   EVT LoadedVT = LD->getMemoryVT();
    1466             :   bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
    1467          23 :   SDValue Offset;
    1468          23 :   bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
    1469             :   unsigned Opcode = 0;
    1470             :   bool Match = false;
    1471          23 :   if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
    1472          23 :     switch (LoadedVT.getSimpleVT().SimpleTy) {
    1473          16 :     case MVT::i32:
    1474          16 :       Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
    1475             :       break;
    1476           0 :     case MVT::i16:
    1477           0 :       if (isSExtLd)
    1478           0 :         Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
    1479             :       else
    1480           0 :         Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
    1481             :       break;
    1482           7 :     case MVT::i8:
    1483             :     case MVT::i1:
    1484           7 :       if (isSExtLd)
    1485           2 :         Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
    1486             :       else
    1487           5 :         Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
    1488             :       break;
    1489             :     default:
    1490             :       return false;
    1491             :     }
    1492             :     Match = true;
    1493             :   }
    1494             : 
    1495             :   if (Match) {
    1496          23 :     SDValue Chain = LD->getChain();
    1497          23 :     SDValue Base = LD->getBasePtr();
    1498          46 :     SDValue Ops[]= { Base, Offset, getAL(CurDAG, SDLoc(N)),
    1499          92 :                      CurDAG->getRegister(0, MVT::i32), Chain };
    1500          46 :     SDNode *New = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
    1501          23 :                                          MVT::Other, Ops);
    1502          23 :     transferMemOperands(N, New);
    1503          23 :     ReplaceNode(N, New);
    1504             :     return true;
    1505             :   }
    1506             : 
    1507             :   return false;
    1508             : }
    1509             : 
    1510             : /// Form a GPRPair pseudo register from a pair of GPR regs.
    1511         109 : SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
    1512         109 :   SDLoc dl(V0.getNode());
    1513             :   SDValue RegClass =
    1514         109 :     CurDAG->getTargetConstant(ARM::GPRPairRegClassID, dl, MVT::i32);
    1515         109 :   SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32);
    1516         109 :   SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32);
    1517         109 :   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
    1518         327 :   return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
    1519             : }
    1520             : 
    1521             : /// Form a D register from a pair of S registers.
    1522          38 : SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
    1523          38 :   SDLoc dl(V0.getNode());
    1524             :   SDValue RegClass =
    1525          38 :     CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, dl, MVT::i32);
    1526          38 :   SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32);
    1527          38 :   SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32);
    1528          38 :   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
    1529         114 :   return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
    1530             : }
    1531             : 
    1532             : /// Form a quad register from a pair of D registers.
    1533         356 : SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
    1534         356 :   SDLoc dl(V0.getNode());
    1535         356 :   SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl,
    1536             :                                                MVT::i32);
    1537         356 :   SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32);
    1538         356 :   SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32);
    1539         356 :   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
    1540        1068 :   return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
    1541             : }
    1542             : 
    1543             : /// Form 4 consecutive D registers from a pair of Q registers.
    1544          30 : SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
    1545          30 :   SDLoc dl(V0.getNode());
    1546          30 :   SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl,
    1547             :                                                MVT::i32);
    1548          30 :   SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32);
    1549          30 :   SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32);
    1550          30 :   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
    1551          90 :   return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
    1552             : }
    1553             : 
    1554             : /// Form 4 consecutive S registers.
    1555          53 : SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
    1556             :                                    SDValue V2, SDValue V3) {
    1557          53 :   SDLoc dl(V0.getNode());
    1558             :   SDValue RegClass =
    1559          53 :     CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, dl, MVT::i32);
    1560          53 :   SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32);
    1561          53 :   SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32);
    1562          53 :   SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, dl, MVT::i32);
    1563          53 :   SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, dl, MVT::i32);
    1564             :   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
    1565          53 :                                     V2, SubReg2, V3, SubReg3 };
    1566         159 :   return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
    1567             : }
    1568             : 
    1569             : /// Form 4 consecutive D registers.
    1570          67 : SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
    1571             :                                    SDValue V2, SDValue V3) {
    1572          67 :   SDLoc dl(V0.getNode());
    1573          67 :   SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl,
    1574             :                                                MVT::i32);
    1575          67 :   SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32);
    1576          67 :   SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32);
    1577          67 :   SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, dl, MVT::i32);
    1578          67 :   SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, dl, MVT::i32);
    1579             :   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
    1580          67 :                                     V2, SubReg2, V3, SubReg3 };
    1581         201 :   return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
    1582             : }
    1583             : 
    1584             : /// Form 4 consecutive Q registers.
    1585          50 : SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
    1586             :                                    SDValue V2, SDValue V3) {
    1587          50 :   SDLoc dl(V0.getNode());
    1588          50 :   SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl,
    1589             :                                                MVT::i32);
    1590          50 :   SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32);
    1591          50 :   SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32);
    1592          50 :   SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, dl, MVT::i32);
    1593          50 :   SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, dl, MVT::i32);
    1594             :   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
    1595          50 :                                     V2, SubReg2, V3, SubReg3 };
    1596         150 :   return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
    1597             : }
    1598             : 
    1599             : /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
    1600             : /// of a NEON VLD or VST instruction.  The supported values depend on the
    1601             : /// number of registers being loaded.
    1602         558 : SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, const SDLoc &dl,
    1603             :                                        unsigned NumVecs, bool is64BitVector) {
    1604             :   unsigned NumRegs = NumVecs;
    1605         558 :   if (!is64BitVector && NumVecs < 3)
    1606         299 :     NumRegs *= 2;
    1607             : 
    1608        1116 :   unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
    1609         558 :   if (Alignment >= 32 && NumRegs == 4)
    1610             :     Alignment = 32;
    1611         524 :   else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
    1612             :     Alignment = 16;
    1613         437 :   else if (Alignment >= 8)
    1614             :     Alignment = 8;
    1615             :   else
    1616             :     Alignment = 0;
    1617             : 
    1618        1116 :   return CurDAG->getTargetConstant(Alignment, dl, MVT::i32);
    1619             : }
    1620             : 
    1621             : static bool isVLDfixed(unsigned Opc)
    1622             : {
    1623             :   switch (Opc) {
    1624             :   default: return false;
    1625             :   case ARM::VLD1d8wb_fixed : return true;
    1626             :   case ARM::VLD1d16wb_fixed : return true;
    1627             :   case ARM::VLD1d64Qwb_fixed : return true;
    1628             :   case ARM::VLD1d32wb_fixed : return true;
    1629             :   case ARM::VLD1d64wb_fixed : return true;
    1630             :   case ARM::VLD1d64TPseudoWB_fixed : return true;
    1631             :   case ARM::VLD1d64QPseudoWB_fixed : return true;
    1632             :   case ARM::VLD1q8wb_fixed : return true;
    1633             :   case ARM::VLD1q16wb_fixed : return true;
    1634             :   case ARM::VLD1q32wb_fixed : return true;
    1635             :   case ARM::VLD1q64wb_fixed : return true;
    1636             :   case ARM::VLD1DUPd8wb_fixed : return true;
    1637             :   case ARM::VLD1DUPd16wb_fixed : return true;
    1638             :   case ARM::VLD1DUPd32wb_fixed : return true;
    1639             :   case ARM::VLD1DUPq8wb_fixed : return true;
    1640             :   case ARM::VLD1DUPq16wb_fixed : return true;
    1641             :   case ARM::VLD1DUPq32wb_fixed : return true;
    1642             :   case ARM::VLD2d8wb_fixed : return true;
    1643             :   case ARM::VLD2d16wb_fixed : return true;
    1644             :   case ARM::VLD2d32wb_fixed : return true;
    1645             :   case ARM::VLD2q8PseudoWB_fixed : return true;
    1646             :   case ARM::VLD2q16PseudoWB_fixed : return true;
    1647             :   case ARM::VLD2q32PseudoWB_fixed : return true;
    1648             :   case ARM::VLD2DUPd8wb_fixed : return true;
    1649             :   case ARM::VLD2DUPd16wb_fixed : return true;
    1650             :   case ARM::VLD2DUPd32wb_fixed : return true;
    1651             :   }
    1652             : }
    1653             : 
    1654             : static bool isVSTfixed(unsigned Opc)
    1655             : {
    1656             :   switch (Opc) {
    1657             :   default: return false;
    1658             :   case ARM::VST1d8wb_fixed : return true;
    1659             :   case ARM::VST1d16wb_fixed : return true;
    1660             :   case ARM::VST1d32wb_fixed : return true;
    1661             :   case ARM::VST1d64wb_fixed : return true;
    1662             :   case ARM::VST1q8wb_fixed : return true;
    1663             :   case ARM::VST1q16wb_fixed : return true;
    1664             :   case ARM::VST1q32wb_fixed : return true;
    1665             :   case ARM::VST1q64wb_fixed : return true;
    1666             :   case ARM::VST1d64TPseudoWB_fixed : return true;
    1667             :   case ARM::VST1d64QPseudoWB_fixed : return true;
    1668             :   case ARM::VST2d8wb_fixed : return true;
    1669             :   case ARM::VST2d16wb_fixed : return true;
    1670             :   case ARM::VST2d32wb_fixed : return true;
    1671             :   case ARM::VST2q8PseudoWB_fixed : return true;
    1672             :   case ARM::VST2q16PseudoWB_fixed : return true;
    1673             :   case ARM::VST2q32PseudoWB_fixed : return true;
    1674             :   }
    1675             : }
    1676             : 
    1677             : // Get the register stride update opcode of a VLD/VST instruction that
    1678             : // is otherwise equivalent to the given fixed stride updating instruction.
    1679         139 : static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
    1680             :   assert((isVLDfixed(Opc) || isVSTfixed(Opc))
    1681             :     && "Incorrect fixed stride updating instruction.");
    1682         139 :   switch (Opc) {
    1683             :   default: break;
    1684             :   case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
    1685           0 :   case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
    1686           2 :   case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
    1687           8 :   case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
    1688          21 :   case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
    1689           0 :   case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
    1690           9 :   case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
    1691           6 :   case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
    1692           0 :   case ARM::VLD1d64Twb_fixed: return ARM::VLD1d64Twb_register;
    1693           0 :   case ARM::VLD1d64Qwb_fixed: return ARM::VLD1d64Qwb_register;
    1694           2 :   case ARM::VLD1d64TPseudoWB_fixed: return ARM::VLD1d64TPseudoWB_register;
    1695           1 :   case ARM::VLD1d64QPseudoWB_fixed: return ARM::VLD1d64QPseudoWB_register;
    1696           1 :   case ARM::VLD1DUPd8wb_fixed : return ARM::VLD1DUPd8wb_register;
    1697           0 :   case ARM::VLD1DUPd16wb_fixed : return ARM::VLD1DUPd16wb_register;
    1698           0 :   case ARM::VLD1DUPd32wb_fixed : return ARM::VLD1DUPd32wb_register;
    1699           1 :   case ARM::VLD1DUPq8wb_fixed : return ARM::VLD1DUPq8wb_register;
    1700           0 :   case ARM::VLD1DUPq16wb_fixed : return ARM::VLD1DUPq16wb_register;
    1701           0 :   case ARM::VLD1DUPq32wb_fixed : return ARM::VLD1DUPq32wb_register;
    1702             : 
    1703          10 :   case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
    1704           4 :   case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
    1705          10 :   case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
    1706           4 :   case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
    1707          14 :   case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
    1708           5 :   case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
    1709           9 :   case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
    1710          13 :   case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
    1711           1 :   case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
    1712           1 :   case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
    1713             : 
    1714           0 :   case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register;
    1715           0 :   case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register;
    1716           0 :   case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register;
    1717           1 :   case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
    1718           0 :   case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
    1719           0 :   case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
    1720             : 
    1721           1 :   case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register;
    1722           0 :   case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register;
    1723           0 :   case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register;
    1724           0 :   case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
    1725           0 :   case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
    1726           0 :   case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
    1727             : 
    1728           1 :   case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register;
    1729           1 :   case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register;
    1730           0 :   case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register;
    1731             :   }
    1732           0 :   return Opc; // If not one we handle, return it unchanged.
    1733             : }
    1734             : 
    1735             : /// Returns true if the given increment is a Constant known to be equal to the
    1736             : /// access size performed by a NEON load/store. This means the "[rN]!" form can
    1737             : /// be used.
    1738         300 : static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) {
    1739             :   auto C = dyn_cast<ConstantSDNode>(Inc);
    1740         516 :   return C && C->getZExtValue() == VecTy.getSizeInBits() / 8 * NumVecs;
    1741             : }
    1742             : 
    1743         288 : void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
    1744             :                                 const uint16_t *DOpcodes,
    1745             :                                 const uint16_t *QOpcodes0,
    1746             :                                 const uint16_t *QOpcodes1) {
    1747             :   assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
    1748             :   SDLoc dl(N);
    1749             : 
    1750         288 :   SDValue MemAddr, Align;
    1751             :   bool IsIntrinsic = !isUpdating;  // By coincidence, all supported updating
    1752             :                                    // nodes are not intrinsics.
    1753         288 :   unsigned AddrOpIdx = IsIntrinsic ? 2 : 1;
    1754         576 :   if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
    1755             :     return;
    1756             : 
    1757         288 :   SDValue Chain = N->getOperand(0);
    1758         576 :   EVT VT = N->getValueType(0);
    1759         288 :   bool is64BitVector = VT.is64BitVector();
    1760         288 :   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);
    1761             : 
    1762             :   unsigned OpcodeIndex;
    1763         288 :   switch (VT.getSimpleVT().SimpleTy) {
    1764           0 :   default: llvm_unreachable("unhandled vld type");
    1765             :     // Double-register operations:
    1766             :   case MVT::v8i8:  OpcodeIndex = 0; break;
    1767          13 :   case MVT::v4i16: OpcodeIndex = 1; break;
    1768          25 :   case MVT::v2f32:
    1769          25 :   case MVT::v2i32: OpcodeIndex = 2; break;
    1770          23 :   case MVT::v1i64: OpcodeIndex = 3; break;
    1771             :     // Quad-register operations:
    1772             :   case MVT::v16i8: OpcodeIndex = 0; break;
    1773          20 :   case MVT::v8i16: OpcodeIndex = 1; break;
    1774          85 :   case MVT::v4f32:
    1775          85 :   case MVT::v4i32: OpcodeIndex = 2; break;
    1776          28 :   case MVT::v2f64:
    1777          28 :   case MVT::v2i64: OpcodeIndex = 3; break;
    1778             :   }
    1779             : 
    1780         288 :   EVT ResTy;
    1781         288 :   if (NumVecs == 1)
    1782         180 :     ResTy = VT;
    1783             :   else {
    1784         108 :     unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
    1785         108 :     if (!is64BitVector)
    1786          48 :       ResTyElts *= 2;
    1787         108 :     ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
    1788             :   }
    1789             :   std::vector<EVT> ResTys;
    1790         288 :   ResTys.push_back(ResTy);
    1791         288 :   if (isUpdating)
    1792         132 :     ResTys.push_back(MVT::i32);
    1793         288 :   ResTys.push_back(MVT::Other);
    1794             : 
    1795         288 :   SDValue Pred = getAL(CurDAG, dl);
    1796         576 :   SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
    1797             :   SDNode *VLd;
    1798             :   SmallVector<SDValue, 7> Ops;
    1799             : 
    1800             :   // Double registers and VLD1/VLD2 quad registers are directly supported.
    1801         288 :   if (is64BitVector || NumVecs <= 2) {
    1802         416 :     unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
    1803         156 :                     QOpcodes0[OpcodeIndex]);
    1804         260 :     Ops.push_back(MemAddr);
    1805         260 :     Ops.push_back(Align);
    1806         260 :     if (isUpdating) {
    1807         256 :       SDValue Inc = N->getOperand(AddrOpIdx + 1);
    1808         128 :       bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);
    1809         128 :       if (!IsImmUpdate) {
    1810             :         // We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so
    1811             :         // check for the opcode rather than the number of vector elements.
    1812          63 :         if (isVLDfixed(Opc))
    1813          63 :           Opc = getVLDSTRegisterUpdateOpcode(Opc);
    1814          66 :         Ops.push_back(Inc);
    1815             :       // VLD1/VLD2 fixed increment does not need Reg0 so only include it in
    1816             :       // the operands if not such an opcode.
    1817          62 :       } else if (!isVLDfixed(Opc))
    1818           0 :         Ops.push_back(Reg0);
    1819             :     }
    1820         260 :     Ops.push_back(Pred);
    1821         260 :     Ops.push_back(Reg0);
    1822         260 :     Ops.push_back(Chain);
    1823         520 :     VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
    1824             : 
    1825             :   } else {
    1826             :     // Otherwise, quad registers are loaded with two separate instructions,
    1827             :     // where one loads the even registers and the other loads the odd registers.
    1828          56 :     EVT AddrTy = MemAddr.getValueType();
    1829             : 
    1830             :     // Load the even subregs.  This is always an updating load, so that it
    1831             :     // provides the address to the second load for the odd subregs.
    1832             :     SDValue ImplDef =
    1833          28 :       SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
    1834          28 :     const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
    1835          84 :     SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
    1836          28 :                                           ResTy, AddrTy, MVT::Other, OpsA);
    1837          28 :     Chain = SDValue(VLdA, 2);
    1838             : 
    1839             :     // Load the odd subregs.
    1840          28 :     Ops.push_back(SDValue(VLdA, 1));
    1841          28 :     Ops.push_back(Align);
    1842          28 :     if (isUpdating) {
    1843             :       SDValue Inc = N->getOperand(AddrOpIdx + 1);
    1844             :       assert(isa<ConstantSDNode>(Inc.getNode()) &&
    1845             :              "only constant post-increment update allowed for VLD3/4");
    1846             :       (void)Inc;
    1847           4 :       Ops.push_back(Reg0);
    1848             :     }
    1849          28 :     Ops.push_back(SDValue(VLdA, 0));
    1850          28 :     Ops.push_back(Pred);
    1851          28 :     Ops.push_back(Reg0);
    1852          28 :     Ops.push_back(Chain);
    1853          56 :     VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops);
    1854             :   }
    1855             : 
    1856             :   // Transfer memoperands.
    1857         288 :   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
    1858         288 :   MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
    1859         288 :   cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
    1860             : 
    1861         288 :   if (NumVecs == 1) {
    1862         180 :     ReplaceNode(N, VLd);
    1863             :     return;
    1864             :   }
    1865             : 
    1866             :   // Extract out the subregisters.
    1867             :   SDValue SuperReg = SDValue(VLd, 0);
    1868             :   static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 &&
    1869             :                     ARM::qsub_3 == ARM::qsub_0 + 3,
    1870             :                 "Unexpected subreg numbering");
    1871         108 :   unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
    1872         740 :   for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
    1873         316 :     ReplaceUses(SDValue(N, Vec),
    1874         316 :                 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
    1875         108 :   ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
    1876         108 :   if (isUpdating)
    1877          20 :     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
    1878         108 :   CurDAG->RemoveDeadNode(N);
    1879             : }
    1880             : 
    1881         270 : void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
    1882             :                                 const uint16_t *DOpcodes,
    1883             :                                 const uint16_t *QOpcodes0,
    1884             :                                 const uint16_t *QOpcodes1) {
    1885             :   assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
    1886             :   SDLoc dl(N);
    1887             : 
    1888         270 :   SDValue MemAddr, Align;
    1889             :   bool IsIntrinsic = !isUpdating;  // By coincidence, all supported updating
    1890             :                                    // nodes are not intrinsics.
    1891         270 :   unsigned AddrOpIdx = IsIntrinsic ? 2 : 1;
    1892             :   unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
    1893         540 :   if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
    1894             :     return;
    1895             : 
    1896         270 :   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
    1897         270 :   MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
    1898             : 
    1899         270 :   SDValue Chain = N->getOperand(0);
    1900         540 :   EVT VT = N->getOperand(Vec0Idx).getValueType();
    1901         270 :   bool is64BitVector = VT.is64BitVector();
    1902         270 :   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);
    1903             : 
    1904             :   unsigned OpcodeIndex;
    1905         270 :   switch (VT.getSimpleVT().SimpleTy) {
    1906           0 :   default: llvm_unreachable("unhandled vst type");
    1907             :     // Double-register operations:
    1908             :   case MVT::v8i8:  OpcodeIndex = 0; break;
    1909          13 :   case MVT::v4f16:
    1910          13 :   case MVT::v4i16: OpcodeIndex = 1; break;
    1911          31 :   case MVT::v2f32:
    1912          31 :   case MVT::v2i32: OpcodeIndex = 2; break;
    1913          17 :   case MVT::v1i64: OpcodeIndex = 3; break;
    1914             :     // Quad-register operations:
    1915             :   case MVT::v16i8: OpcodeIndex = 0; break;
    1916          31 :   case MVT::v8f16:
    1917          31 :   case MVT::v8i16: OpcodeIndex = 1; break;
    1918          73 :   case MVT::v4f32:
    1919          73 :   case MVT::v4i32: OpcodeIndex = 2; break;
    1920          27 :   case MVT::v2f64:
    1921          27 :   case MVT::v2i64: OpcodeIndex = 3; break;
    1922             :   }
    1923             : 
    1924             :   std::vector<EVT> ResTys;
    1925         270 :   if (isUpdating)
    1926         151 :     ResTys.push_back(MVT::i32);
    1927         270 :   ResTys.push_back(MVT::Other);
    1928             : 
    1929         270 :   SDValue Pred = getAL(CurDAG, dl);
    1930         540 :   SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
    1931             :   SmallVector<SDValue, 7> Ops;
    1932             : 
    1933             :   // Double registers and VST1/VST2 quad registers are directly supported.
    1934         270 :   if (is64BitVector || NumVecs <= 2) {
    1935         244 :     SDValue SrcReg;
    1936         244 :     if (NumVecs == 1) {
    1937         175 :       SrcReg = N->getOperand(Vec0Idx);
    1938          69 :     } else if (is64BitVector) {
    1939             :       // Form a REG_SEQUENCE to force register allocation.
    1940          50 :       SDValue V0 = N->getOperand(Vec0Idx + 0);
    1941          50 :       SDValue V1 = N->getOperand(Vec0Idx + 1);
    1942          50 :       if (NumVecs == 2)
    1943          14 :         SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
    1944             :       else {
    1945          36 :         SDValue V2 = N->getOperand(Vec0Idx + 2);
    1946             :         // If it's a vst3, form a quad D-register and leave the last part as
    1947             :         // an undef.
    1948             :         SDValue V3 = (NumVecs == 3)
    1949          22 :           ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
    1950          50 :           : N->getOperand(Vec0Idx + 3);
    1951          36 :         SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
    1952             :       }
    1953             :     } else {
    1954             :       // Form a QQ register.
    1955          19 :       SDValue Q0 = N->getOperand(Vec0Idx);
    1956          19 :       SDValue Q1 = N->getOperand(Vec0Idx + 1);
    1957          19 :       SrcReg = SDValue(createQRegPairNode(MVT::v4i64, Q0, Q1), 0);
    1958             :     }
    1959             : 
    1960         387 :     unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
    1961         143 :                     QOpcodes0[OpcodeIndex]);
    1962         244 :     Ops.push_back(MemAddr);
    1963         244 :     Ops.push_back(Align);
    1964         244 :     if (isUpdating) {
    1965         298 :       SDValue Inc = N->getOperand(AddrOpIdx + 1);
    1966         149 :       bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);
    1967         149 :       if (!IsImmUpdate) {
    1968             :         // We use a VST1 for v1i64 even if the pseudo says VST2/3/4, so
    1969             :         // check for the opcode rather than the number of vector elements.
    1970          72 :         if (isVSTfixed(Opc))
    1971          72 :           Opc = getVLDSTRegisterUpdateOpcode(Opc);
    1972          73 :         Ops.push_back(Inc);
    1973             :       }
    1974             :       // VST1/VST2 fixed increment does not need Reg0 so only include it in
    1975             :       // the operands if not such an opcode.
    1976          75 :       else if (!isVSTfixed(Opc))
    1977           1 :         Ops.push_back(Reg0);
    1978             :     }
    1979         244 :     Ops.push_back(SrcReg);
    1980         244 :     Ops.push_back(Pred);
    1981         244 :     Ops.push_back(Reg0);
    1982         244 :     Ops.push_back(Chain);
    1983         488 :     SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
    1984             : 
    1985             :     // Transfer memoperands.
    1986         244 :     cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
    1987             : 
    1988         244 :     ReplaceNode(N, VSt);
    1989             :     return;
    1990             :   }
    1991             : 
    1992             :   // Otherwise, quad registers are stored with two separate instructions,
    1993             :   // where one stores the even registers and the other stores the odd registers.
    1994             : 
    1995             :   // Form the QQQQ REG_SEQUENCE.
    1996          26 :   SDValue V0 = N->getOperand(Vec0Idx + 0);
    1997          26 :   SDValue V1 = N->getOperand(Vec0Idx + 1);
    1998          26 :   SDValue V2 = N->getOperand(Vec0Idx + 2);
    1999             :   SDValue V3 = (NumVecs == 3)
    2000           9 :     ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
    2001          43 :     : N->getOperand(Vec0Idx + 3);
    2002          52 :   SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
    2003             : 
    2004             :   // Store the even D registers.  This is always an updating store, so that it
    2005             :   // provides the address to the second store for the odd subregs.
    2006          26 :   const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
    2007         104 :   SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
    2008             :                                         MemAddr.getValueType(),
    2009          26 :                                         MVT::Other, OpsA);
    2010          26 :   cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
    2011          26 :   Chain = SDValue(VStA, 1);
    2012             : 
    2013             :   // Store the odd D registers.
    2014          26 :   Ops.push_back(SDValue(VStA, 0));
    2015          26 :   Ops.push_back(Align);
    2016          26 :   if (isUpdating) {
    2017             :     SDValue Inc = N->getOperand(AddrOpIdx + 1);
    2018             :     assert(isa<ConstantSDNode>(Inc.getNode()) &&
    2019             :            "only constant post-increment update allowed for VST3/4");
    2020             :     (void)Inc;
    2021           2 :     Ops.push_back(Reg0);
    2022             :   }
    2023          26 :   Ops.push_back(RegSeq);
    2024          26 :   Ops.push_back(Pred);
    2025          26 :   Ops.push_back(Reg0);
    2026          26 :   Ops.push_back(Chain);
    2027          78 :   SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
    2028          26 :                                         Ops);
    2029             :   cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
    2030          26 :   ReplaceNode(N, VStB);
    2031             : }
    2032             : 
    2033          87 : void ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating,
    2034             :                                       unsigned NumVecs,
    2035             :                                       const uint16_t *DOpcodes,
    2036             :                                       const uint16_t *QOpcodes) {
    2037             :   assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
    2038             :   SDLoc dl(N);
    2039             : 
    2040          87 :   SDValue MemAddr, Align;
    2041             :   bool IsIntrinsic = !isUpdating;  // By coincidence, all supported updating
    2042             :                                    // nodes are not intrinsics.
    2043          87 :   unsigned AddrOpIdx = IsIntrinsic ? 2 : 1;
    2044             :   unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
    2045         174 :   if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
    2046             :     return;
    2047             : 
    2048          87 :   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
    2049          87 :   MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
    2050             : 
    2051          87 :   SDValue Chain = N->getOperand(0);
    2052             :   unsigned Lane =
    2053         174 :     cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
    2054         174 :   EVT VT = N->getOperand(Vec0Idx).getValueType();
    2055          87 :   bool is64BitVector = VT.is64BitVector();
    2056             : 
    2057             :   unsigned Alignment = 0;
    2058          87 :   if (NumVecs != 3) {
    2059         116 :     Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
    2060          58 :     unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;
    2061          58 :     if (Alignment > NumBytes)
    2062             :       Alignment = NumBytes;
    2063          58 :     if (Alignment < 8 && Alignment < NumBytes)
    2064             :       Alignment = 0;
    2065             :     // Alignment must be a power of two; make sure of that.
    2066          58 :     Alignment = (Alignment & -Alignment);
    2067          58 :     if (Alignment == 1)
    2068             :       Alignment = 0;
    2069             :   }
    2070         174 :   Align = CurDAG->getTargetConstant(Alignment, dl, MVT::i32);
    2071             : 
    2072             :   unsigned OpcodeIndex;
    2073          87 :   switch (VT.getSimpleVT().SimpleTy) {
    2074           0 :   default: llvm_unreachable("unhandled vld/vst lane type");
    2075             :     // Double-register operations:
    2076             :   case MVT::v8i8:  OpcodeIndex = 0; break;
    2077          10 :   case MVT::v4i16: OpcodeIndex = 1; break;
    2078          28 :   case MVT::v2f32:
    2079          28 :   case MVT::v2i32: OpcodeIndex = 2; break;
    2080             :     // Quad-register operations:
    2081             :   case MVT::v8i16: OpcodeIndex = 0; break;
    2082          19 :   case MVT::v4f32:
    2083          19 :   case MVT::v4i32: OpcodeIndex = 1; break;
    2084             :   }
    2085             : 
    2086             :   std::vector<EVT> ResTys;
    2087          87 :   if (IsLoad) {
    2088          60 :     unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
    2089          60 :     if (!is64BitVector)
    2090          25 :       ResTyElts *= 2;
    2091         120 :     ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
    2092          60 :                                       MVT::i64, ResTyElts));
    2093             :   }
    2094          87 :   if (isUpdating)
    2095          11 :     ResTys.push_back(MVT::i32);
    2096          87 :   ResTys.push_back(MVT::Other);
    2097             : 
    2098          87 :   SDValue Pred = getAL(CurDAG, dl);
    2099         174 :   SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
    2100             : 
    2101             :   SmallVector<SDValue, 8> Ops;
    2102          87 :   Ops.push_back(MemAddr);
    2103          87 :   Ops.push_back(Align);
    2104          87 :   if (isUpdating) {
    2105          22 :     SDValue Inc = N->getOperand(AddrOpIdx + 1);
    2106             :     bool IsImmUpdate =
    2107          11 :         isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);
    2108          11 :     Ops.push_back(IsImmUpdate ? Reg0 : Inc);
    2109             :   }
    2110             : 
    2111          87 :   SDValue SuperReg;
    2112          87 :   SDValue V0 = N->getOperand(Vec0Idx + 0);
    2113          87 :   SDValue V1 = N->getOperand(Vec0Idx + 1);
    2114          87 :   if (NumVecs == 2) {
    2115          32 :     if (is64BitVector)
    2116          21 :       SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
    2117             :     else
    2118          11 :       SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
    2119             :   } else {
    2120          55 :     SDValue V2 = N->getOperand(Vec0Idx + 2);
    2121             :     SDValue V3 = (NumVecs == 3)
    2122          29 :       ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
    2123          81 :       : N->getOperand(Vec0Idx + 3);
    2124          55 :     if (is64BitVector)
    2125          31 :       SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
    2126             :     else
    2127          24 :       SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
    2128             :   }
    2129          87 :   Ops.push_back(SuperReg);
    2130         174 :   Ops.push_back(getI32Imm(Lane, dl));
    2131          87 :   Ops.push_back(Pred);
    2132          87 :   Ops.push_back(Reg0);
    2133          87 :   Ops.push_back(Chain);
    2134             : 
    2135         122 :   unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
    2136          35 :                                   QOpcodes[OpcodeIndex]);
    2137         174 :   SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
    2138          87 :   cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
    2139          87 :   if (!IsLoad) {
    2140          27 :     ReplaceNode(N, VLdLn);
    2141             :     return;
    2142             :   }
    2143             : 
    2144             :   // Extract the subregisters.
    2145          60 :   SuperReg = SDValue(VLdLn, 0);
    2146             :   static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 &&
    2147             :                     ARM::qsub_3 == ARM::qsub_0 + 3,
    2148             :                 "Unexpected subreg numbering");
    2149          60 :   unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
    2150         408 :   for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
    2151         174 :     ReplaceUses(SDValue(N, Vec),
    2152         174 :                 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
    2153          60 :   ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
    2154          60 :   if (isUpdating)
    2155           8 :     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
    2156          60 :   CurDAG->RemoveDeadNode(N);
    2157             : }
    2158             : 
    2159          70 : void ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool IsIntrinsic,
    2160             :                                    bool isUpdating, unsigned NumVecs,
    2161             :                                    const uint16_t *DOpcodes,
    2162             :                                    const uint16_t *QOpcodes0,
    2163             :                                    const uint16_t *QOpcodes1) {
    2164             :   assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
    2165             :   SDLoc dl(N);
    2166             : 
    2167          70 :   SDValue MemAddr, Align;
    2168          70 :   unsigned AddrOpIdx = IsIntrinsic ? 2 : 1;
    2169         140 :   if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
    2170             :     return;
    2171             : 
    2172          70 :   SDValue Chain = N->getOperand(0);
    2173         140 :   EVT VT = N->getValueType(0);
    2174          70 :   bool is64BitVector = VT.is64BitVector();
    2175             : 
    2176             :   unsigned Alignment = 0;
    2177          70 :   if (NumVecs != 3) {
    2178         120 :     Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
    2179          60 :     unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;
    2180          60 :     if (Alignment > NumBytes)
    2181             :       Alignment = NumBytes;
    2182          60 :     if (Alignment < 8 && Alignment < NumBytes)
    2183             :       Alignment = 0;
    2184             :     // Alignment must be a power of two; make sure of that.
    2185          60 :     Alignment = (Alignment & -Alignment);
    2186          60 :     if (Alignment == 1)
    2187             :       Alignment = 0;
    2188             :   }
    2189         140 :   Align = CurDAG->getTargetConstant(Alignment, dl, MVT::i32);
    2190             : 
    2191             :   unsigned OpcodeIndex;
    2192          70 :   switch (VT.getSimpleVT().SimpleTy) {
    2193           0 :   default: llvm_unreachable("unhandled vld-dup type");
    2194             :   case MVT::v8i8:
    2195             :   case MVT::v16i8: OpcodeIndex = 0; break;
    2196          20 :   case MVT::v4i16:
    2197          20 :   case MVT::v8i16: OpcodeIndex = 1; break;
    2198          25 :   case MVT::v2f32:
    2199             :   case MVT::v2i32:
    2200             :   case MVT::v4f32:
    2201          25 :   case MVT::v4i32: OpcodeIndex = 2; break;
    2202           3 :   case MVT::v1f64:
    2203           3 :   case MVT::v1i64: OpcodeIndex = 3; break;
    2204             :   }
    2205             : 
    2206          70 :   unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
    2207          70 :   if (!is64BitVector)
    2208          21 :     ResTyElts *= 2;
    2209          70 :   EVT ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
    2210             : 
    2211             :   std::vector<EVT> ResTys;
    2212          70 :   ResTys.push_back(ResTy);
    2213          70 :   if (isUpdating)
    2214          12 :     ResTys.push_back(MVT::i32);
    2215          70 :   ResTys.push_back(MVT::Other);
    2216             : 
    2217          70 :   SDValue Pred = getAL(CurDAG, dl);
    2218         140 :   SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
    2219             : 
    2220             :   SDNode *VLdDup;
    2221          70 :   if (is64BitVector || NumVecs == 1) {
    2222             :     SmallVector<SDValue, 6> Ops;
    2223          61 :     Ops.push_back(MemAddr);
    2224          61 :     Ops.push_back(Align);
    2225          73 :     unsigned Opc = is64BitVector ? DOpcodes[OpcodeIndex] :
    2226          12 :                                    QOpcodes0[OpcodeIndex];
    2227          61 :     if (isUpdating) {
    2228             :       // fixed-stride update instructions don't have an explicit writeback
    2229             :       // operand. It's implicit in the opcode itself.
    2230          12 :       SDValue Inc = N->getOperand(2);
    2231             :       bool IsImmUpdate =
    2232          12 :           isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);
    2233          12 :       if (NumVecs <= 2 && !IsImmUpdate)
    2234           4 :         Opc = getVLDSTRegisterUpdateOpcode(Opc);
    2235          12 :       if (!IsImmUpdate)
    2236           5 :         Ops.push_back(Inc);
    2237             :       // FIXME: VLD3 and VLD4 haven't been updated to that form yet.
    2238           7 :       else if (NumVecs > 2)
    2239           1 :         Ops.push_back(Reg0);
    2240             :     }
    2241          61 :     Ops.push_back(Pred);
    2242          61 :     Ops.push_back(Reg0);
    2243          61 :     Ops.push_back(Chain);
    2244         122 :     VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
    2245           9 :   } else if (NumVecs == 2) {
    2246           3 :     const SDValue OpsA[] = { MemAddr, Align, Pred, Reg0, Chain };
    2247           9 :     SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex],
    2248           3 :                                           dl, ResTys, OpsA);
    2249             : 
    2250           3 :     Chain = SDValue(VLdA, 1);
    2251           3 :     const SDValue OpsB[] = { MemAddr, Align, Pred, Reg0, Chain };
    2252           6 :     VLdDup = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, OpsB);
    2253             :   } else {
    2254             :     SDValue ImplDef =
    2255           6 :       SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
    2256           6 :     const SDValue OpsA[] = { MemAddr, Align, ImplDef, Pred, Reg0, Chain };
    2257          18 :     SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex],
    2258           6 :                                           dl, ResTys, OpsA);
    2259             : 
    2260             :     SDValue SuperReg = SDValue(VLdA, 0);
    2261           6 :     Chain = SDValue(VLdA, 1);
    2262           6 :     const SDValue OpsB[] = { MemAddr, Align, SuperReg, Pred, Reg0, Chain };
    2263          12 :     VLdDup = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, OpsB);
    2264             :   }
    2265             : 
    2266             :   // Transfer memoperands.
    2267          70 :   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
    2268          70 :   MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
    2269          70 :   cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
    2270             : 
    2271             :   // Extract the subregisters.
    2272          70 :   if (NumVecs == 1) {
    2273          34 :     ReplaceUses(SDValue(N, 0), SDValue(VLdDup, 0));
    2274             :   } else {
    2275             :     SDValue SuperReg = SDValue(VLdDup, 0);
    2276             :     static_assert(ARM::dsub_7 == ARM::dsub_0 + 7, "Unexpected subreg numbering");
    2277          36 :     unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
    2278         240 :     for (unsigned Vec = 0; Vec != NumVecs; ++Vec) {
    2279         102 :       ReplaceUses(SDValue(N, Vec),
    2280         102 :                   CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
    2281             :     }
    2282             :   }
    2283          70 :   ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
    2284          70 :   if (isUpdating)
    2285          12 :     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
    2286          70 :   CurDAG->RemoveDeadNode(N);
    2287             : }
    2288             : 
    2289        2333 : bool ARMDAGToDAGISel::tryV6T2BitfieldExtractOp(SDNode *N, bool isSigned) {
    2290        2333 :   if (!Subtarget->hasV6T2Ops())
    2291             :     return false;
    2292             : 
    2293             :   unsigned Opc = isSigned
    2294        2041 :     ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
    2295         931 :     : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
    2296             :   SDLoc dl(N);
    2297             : 
    2298             :   // For unsigned extracts, check for a shift right and mask
    2299             :   unsigned And_imm = 0;
    2300        2220 :   if (N->getOpcode() == ISD::AND) {
    2301             :     if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
    2302             : 
    2303             :       // The immediate is a mask of the low bits iff imm & (imm+1) == 0
    2304         511 :       if (And_imm & (And_imm + 1))
    2305             :         return false;
    2306             : 
    2307             :       unsigned Srl_imm = 0;
    2308         355 :       if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
    2309             :                                 Srl_imm)) {
    2310             :         assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
    2311             : 
    2312             :         // Note: The width operand is encoded as width-1.
    2313          55 :         unsigned Width = countTrailingOnes(And_imm) - 1;
    2314             :         unsigned LSB = Srl_imm;
    2315             : 
    2316         110 :         SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
    2317             : 
    2318         110 :         if ((LSB + Width + 1) == N->getValueType(0).getSizeInBits()) {
    2319             :           // It's cheaper to use a right shift to extract the top bits.
    2320           1 :           if (Subtarget->isThumb()) {
    2321           0 :             Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri;
    2322           0 :             SDValue Ops[] = { N->getOperand(0).getOperand(0),
    2323           0 :                               CurDAG->getTargetConstant(LSB, dl, MVT::i32),
    2324           0 :                               getAL(CurDAG, dl), Reg0, Reg0 };
    2325           0 :             CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
    2326             :             return true;
    2327             :           }
    2328             : 
    2329             :           // ARM models shift instructions as MOVsi with shifter operand.
    2330             :           ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL);
    2331             :           SDValue ShOpc =
    2332           1 :             CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, LSB), dl,
    2333           1 :                                       MVT::i32);
    2334           1 :           SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
    2335           1 :                             getAL(CurDAG, dl), Reg0, Reg0 };
    2336           2 :           CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops);
    2337           1 :           return true;
    2338             :         }
    2339             : 
    2340             :         assert(LSB + Width + 1 <= 32 && "Shouldn't create an invalid ubfx");
    2341          54 :         SDValue Ops[] = { N->getOperand(0).getOperand(0),
    2342          54 :                           CurDAG->getTargetConstant(LSB, dl, MVT::i32),
    2343          54 :                           CurDAG->getTargetConstant(Width, dl, MVT::i32),
    2344         162 :                           getAL(CurDAG, dl), Reg0 };
    2345         108 :         CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
    2346          54 :         return true;
    2347             :       }
    2348             :     }
    2349             :     return false;
    2350             :   }
    2351             : 
    2352             :   // Otherwise, we're looking for a shift of a shift
    2353             :   unsigned Shl_imm = 0;
    2354         445 :   if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
    2355             :     assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
    2356             :     unsigned Srl_imm = 0;
    2357          12 :     if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
    2358             :       assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
    2359             :       // Note: The width operand is encoded as width-1.
    2360          12 :       unsigned Width = 32 - Srl_imm - 1;
    2361          12 :       int LSB = Srl_imm - Shl_imm;
    2362          12 :       if (LSB < 0)
    2363             :         return false;
    2364          22 :       SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
    2365             :       assert(LSB + Width + 1 <= 32 && "Shouldn't create an invalid ubfx");
    2366          11 :       SDValue Ops[] = { N->getOperand(0).getOperand(0),
    2367          11 :                         CurDAG->getTargetConstant(LSB, dl, MVT::i32),
    2368          11 :                         CurDAG->getTargetConstant(Width, dl, MVT::i32),
    2369          33 :                         getAL(CurDAG, dl), Reg0 };
    2370          22 :       CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
    2371          11 :       return true;
    2372             :     }
    2373             :   }
    2374             : 
    2375             :   // Or we are looking for a shift of an and, with a mask operand
    2376             :   if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, And_imm) &&
    2377             :       isShiftedMask_32(And_imm)) {
    2378             :     unsigned Srl_imm = 0;
    2379          12 :     unsigned LSB = countTrailingZeros(And_imm);
    2380             :     // Shift must be the same as the ands lsb
    2381          24 :     if (isInt32Immediate(N->getOperand(1), Srl_imm) && Srl_imm == LSB) {
    2382             :       assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
    2383           5 :       unsigned MSB = 31 - countLeadingZeros(And_imm);
    2384             :       // Note: The width operand is encoded as width-1.
    2385           5 :       unsigned Width = MSB - LSB;
    2386          10 :       SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
    2387             :       assert(Srl_imm + Width + 1 <= 32 && "Shouldn't create an invalid ubfx");
    2388           5 :       SDValue Ops[] = { N->getOperand(0).getOperand(0),
    2389           5 :                         CurDAG->getTargetConstant(Srl_imm, dl, MVT::i32),
    2390           5 :                         CurDAG->getTargetConstant(Width, dl, MVT::i32),
    2391          15 :                         getAL(CurDAG, dl), Reg0 };
    2392          10 :       CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
    2393             :       return true;
    2394             :     }
    2395             :   }
    2396             : 
    2397         428 :   if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
    2398         125 :     unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
    2399             :     unsigned LSB = 0;
    2400         237 :     if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL, LSB) &&
    2401             :         !isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRA, LSB))
    2402             :       return false;
    2403             : 
    2404          13 :     if (LSB + Width > 32)
    2405             :       return false;
    2406             : 
    2407          26 :     SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
    2408             :     assert(LSB + Width <= 32 && "Shouldn't create an invalid ubfx");
    2409          13 :     SDValue Ops[] = { N->getOperand(0).getOperand(0),
    2410          13 :                       CurDAG->getTargetConstant(LSB, dl, MVT::i32),
    2411          13 :                       CurDAG->getTargetConstant(Width - 1, dl, MVT::i32),
    2412          39 :                       getAL(CurDAG, dl), Reg0 };
    2413          26 :     CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
    2414          13 :     return true;
    2415             :   }
    2416             : 
    2417             :   return false;
    2418             : }
    2419             : 
    2420             : /// Target-specific DAG combining for ISD::XOR.
    2421             : /// Target-independent combining lowers SELECT_CC nodes of the form
    2422             : /// select_cc setg[ge] X,  0,  X, -X
    2423             : /// select_cc setgt    X, -1,  X, -X
    2424             : /// select_cc setl[te] X,  0, -X,  X
    2425             : /// select_cc setlt    X,  1, -X,  X
    2426             : /// which represent Integer ABS into:
    2427             : /// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
    2428             : /// ARM instruction selection detects the latter and matches it to
    2429             : /// ARM::ABS or ARM::t2ABS machine node.
    2430         454 : bool ARMDAGToDAGISel::tryABSOp(SDNode *N){
    2431         454 :   SDValue XORSrc0 = N->getOperand(0);
    2432         454 :   SDValue XORSrc1 = N->getOperand(1);
    2433         908 :   EVT VT = N->getValueType(0);
    2434             : 
    2435         454 :   if (Subtarget->isThumb1Only())
    2436             :     return false;
    2437             : 
    2438         323 :   if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
    2439             :     return false;
    2440             : 
    2441           8 :   SDValue ADDSrc0 = XORSrc0.getOperand(0);
    2442           8 :   SDValue ADDSrc1 = XORSrc0.getOperand(1);
    2443           8 :   SDValue SRASrc0 = XORSrc1.getOperand(0);
    2444           8 :   SDValue SRASrc1 = XORSrc1.getOperand(1);
    2445             :   ConstantSDNode *SRAConstant =  dyn_cast<ConstantSDNode>(SRASrc1);
    2446           8 :   EVT XType = SRASrc0.getValueType();
    2447           8 :   unsigned Size = XType.getSizeInBits() - 1;
    2448             : 
    2449           8 :   if (ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 &&
    2450          24 :       XType.isInteger() && SRAConstant != nullptr &&
    2451           8 :       Size == SRAConstant->getZExtValue()) {
    2452             :     unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
    2453           8 :     CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
    2454             :     return true;
    2455             :   }
    2456             : 
    2457             :   return false;
    2458             : }
    2459             : 
    2460             : /// We've got special pseudo-instructions for these
    2461           6 : void ARMDAGToDAGISel::SelectCMP_SWAP(SDNode *N) {
    2462             :   unsigned Opcode;
    2463             :   EVT MemTy = cast<MemSDNode>(N)->getMemoryVT();
    2464             :   if (MemTy == MVT::i8)
    2465             :     Opcode = ARM::CMP_SWAP_8;
    2466             :   else if (MemTy == MVT::i16)
    2467             :     Opcode = ARM::CMP_SWAP_16;
    2468             :   else if (MemTy == MVT::i32)
    2469             :     Opcode = ARM::CMP_SWAP_32;
    2470             :   else
    2471           0 :     llvm_unreachable("Unknown AtomicCmpSwap type");
    2472             : 
    2473           6 :   SDValue Ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3),
    2474           6 :                    N->getOperand(0)};
    2475          18 :   SDNode *CmpSwap = CurDAG->getMachineNode(
    2476           6 :       Opcode, SDLoc(N),
    2477           6 :       CurDAG->getVTList(MVT::i32, MVT::i32, MVT::Other), Ops);
    2478             : 
    2479           6 :   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
    2480           6 :   MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
    2481           6 :   cast<MachineSDNode>(CmpSwap)->setMemRefs(MemOp, MemOp + 1);
    2482             : 
    2483           6 :   ReplaceUses(SDValue(N, 0), SDValue(CmpSwap, 0));
    2484           6 :   ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 2));
    2485           6 :   CurDAG->RemoveDeadNode(N);
    2486           6 : }
    2487             : 
    2488             : static Optional<std::pair<unsigned, unsigned>>
    2489          86 : getContiguousRangeOfSetBits(const APInt &A) {
    2490          86 :   unsigned FirstOne = A.getBitWidth() - A.countLeadingZeros() - 1;
    2491          86 :   unsigned LastOne = A.countTrailingZeros();
    2492          86 :   if (A.countPopulation() != (FirstOne - LastOne + 1))
    2493             :     return Optional<std::pair<unsigned,unsigned>>();
    2494             :   return std::make_pair(FirstOne, LastOne);
    2495             : }
    2496             : 
    2497        1958 : void ARMDAGToDAGISel::SelectCMPZ(SDNode *N, bool &SwitchEQNEToPLMI) {
    2498             :   assert(N->getOpcode() == ARMISD::CMPZ);
    2499        1958 :   SwitchEQNEToPLMI = false;
    2500             : 
    2501        1958 :   if (!Subtarget->isThumb())
    2502             :     // FIXME: Work out whether it is profitable to do this in A32 mode - LSL and
    2503             :     // LSR don't exist as standalone instructions - they need the barrel shifter.
    2504        1880 :     return;
    2505             : 
    2506             :   // select (cmpz (and X, C), #0) -> (LSLS X) or (LSRS X) or (LSRS (LSLS X))
    2507        1143 :   SDValue And = N->getOperand(0);
    2508             :   if (!And->hasOneUse())
    2509             :     return;
    2510             : 
    2511         580 :   SDValue Zero = N->getOperand(1);
    2512        1479 :   if (!isa<ConstantSDNode>(Zero) || !cast<ConstantSDNode>(Zero)->isNullValue() ||
    2513         415 :       And->getOpcode() != ISD::AND)
    2514             :     return;
    2515          93 :   SDValue X = And.getOperand(0);
    2516             :   auto C = dyn_cast<ConstantSDNode>(And.getOperand(1));
    2517             : 
    2518             :   if (!C)
    2519             :     return;
    2520         172 :   auto Range = getContiguousRangeOfSetBits(C->getAPIntValue());
    2521          86 :   if (!Range)
    2522             :     return;
    2523             : 
    2524             :   // There are several ways to lower this:
    2525             :   SDNode *NewN;
    2526             :   SDLoc dl(N);
    2527             : 
    2528          78 :   auto EmitShift = [&](unsigned Opc, SDValue Src, unsigned Imm) -> SDNode* {
    2529         390 :     if (Subtarget->isThumb2()) {
    2530          53 :       Opc = (Opc == ARM::tLSLri) ? ARM::t2LSLri : ARM::t2LSRri;
    2531         234 :       SDValue Ops[] = { Src, CurDAG->getTargetConstant(Imm, dl, MVT::i32),
    2532         159 :                         getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
    2533         318 :                         CurDAG->getRegister(0, MVT::i32) };
    2534         106 :       return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops);
    2535             :     } else {
    2536          50 :       SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), Src,
    2537          50 :                        CurDAG->getTargetConstant(Imm, dl, MVT::i32),
    2538         150 :                        getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32)};
    2539          50 :       return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops);
    2540             :     }
    2541          78 :   };
    2542             :   
    2543          78 :   if (Range->second == 0) {
    2544             :     //  1. Mask includes the LSB -> Simply shift the top N bits off
    2545          59 :     NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);
    2546          59 :     ReplaceNode(And.getNode(), NewN);
    2547          19 :   } else if (Range->first == 31) {
    2548             :     //  2. Mask includes the MSB -> Simply shift the bottom N bits off
    2549           2 :     NewN = EmitShift(ARM::tLSRri, X, Range->second);
    2550           2 :     ReplaceNode(And.getNode(), NewN);
    2551          17 :   } else if (Range->first == Range->second) {
    2552             :     //  3. Only one bit is set. We can shift this into the sign bit and use a
    2553             :     //     PL/MI comparison.
    2554          15 :     NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);
    2555          15 :     ReplaceNode(And.getNode(), NewN);
    2556             : 
    2557          15 :     SwitchEQNEToPLMI = true;
    2558           2 :   } else if (!Subtarget->hasV6T2Ops()) {
    2559             :     //  4. Do a double shift to clear bottom and top bits, but only in
    2560             :     //     thumb-1 mode as in thumb-2 we can use UBFX.
    2561           1 :     NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);
    2562           2 :     NewN = EmitShift(ARM::tLSRri, SDValue(NewN, 0),
    2563           1 :                      Range->second + (31 - Range->first));
    2564           1 :     ReplaceNode(And.getNode(), NewN);
    2565             :   }
    2566             : 
    2567             : }
    2568             : 
    2569      287122 : void ARMDAGToDAGISel::Select(SDNode *N) {
    2570             :   SDLoc dl(N);
    2571             : 
    2572      287122 :   if (N->isMachineOpcode()) {
    2573             :     N->setNodeId(-1);
    2574             :     return;   // Already selected.
    2575             :   }
    2576             : 
    2577      287035 :   switch (N->getOpcode()) {
    2578             :   default: break;
    2579         135 :   case ISD::WRITE_REGISTER:
    2580         135 :     if (tryWriteRegister(N))
    2581             :       return;
    2582             :     break;
    2583          95 :   case ISD::READ_REGISTER:
    2584          95 :     if (tryReadRegister(N))
    2585             :       return;
    2586             :     break;
    2587        3483 :   case ISD::INLINEASM:
    2588        3483 :     if (tryInlineAsm(N))
    2589             :       return;
    2590             :     break;
    2591         454 :   case ISD::XOR:
    2592             :     // Select special operations if XOR node forms integer ABS pattern
    2593         454 :     if (tryABSOp(N))
    2594             :       return;
    2595             :     // Other cases are autogenerated.
    2596             :     break;
    2597             :   case ISD::Constant: {
    2598       11288 :     unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
    2599             :     // If we can't materialize the constant we need to use a literal pool
    2600        5644 :     if (ConstantMaterializationCost(Val) > 2) {
    2601         345 :       SDValue CPIdx = CurDAG->getTargetConstantPool(
    2602         345 :           ConstantInt::get(Type::getInt32Ty(*CurDAG->getContext()), Val),
    2603         345 :           TLI->getPointerTy(CurDAG->getDataLayout()));
    2604             : 
    2605             :       SDNode *ResNode;
    2606         345 :       if (Subtarget->isThumb()) {
    2607             :         SDValue Ops[] = {
    2608             :           CPIdx,
    2609         211 :           getAL(CurDAG, dl),
    2610         422 :           CurDAG->getRegister(0, MVT::i32),
    2611         211 :           CurDAG->getEntryNode()
    2612         844 :         };
    2613         211 :         ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
    2614             :                                          Ops);
    2615             :       } else {
    2616             :         SDValue Ops[] = {
    2617             :           CPIdx,
    2618         134 :           CurDAG->getTargetConstant(0, dl, MVT::i32),
    2619         134 :           getAL(CurDAG, dl),
    2620         268 :           CurDAG->getRegister(0, MVT::i32),
    2621         134 :           CurDAG->getEntryNode()
    2622         670 :         };
    2623         134 :         ResNode = CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
    2624             :                                          Ops);
    2625             :       }
    2626             :       // Annotate the Node with memory operand information so that MachineInstr
    2627             :       // queries work properly. This e.g. gives the register allocation the
    2628             :       // required information for rematerialization.
    2629         345 :       MachineFunction& MF = CurDAG->getMachineFunction();
    2630         345 :       MachineSDNode::mmo_iterator MemOp = MF.allocateMemRefsArray(1);
    2631         345 :       MemOp[0] = MF.getMachineMemOperand(
    2632             :           MachinePointerInfo::getConstantPool(MF),
    2633             :           MachineMemOperand::MOLoad, 4, 4);
    2634             : 
    2635         345 :       cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp+1);
    2636             :         
    2637         345 :       ReplaceNode(N, ResNode);
    2638             :       return;
    2639             :     }
    2640             : 
    2641             :     // Other cases are autogenerated.
    2642             :     break;
    2643             :   }
    2644             :   case ISD::FrameIndex: {
    2645             :     // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
    2646        2070 :     int FI = cast<FrameIndexSDNode>(N)->getIndex();
    2647        2070 :     SDValue TFI = CurDAG->getTargetFrameIndex(
    2648        4140 :         FI, TLI->getPointerTy(CurDAG->getDataLayout()));
    2649        2070 :     if (Subtarget->isThumb1Only()) {
    2650             :       // Set the alignment of the frame object to 4, to avoid having to generate
    2651             :       // more than one ADD
    2652         284 :       MachineFrameInfo &MFI = MF->getFrameInfo();
    2653         284 :       if (MFI.getObjectAlignment(FI) < 4)
    2654             :         MFI.setObjectAlignment(FI, 4);
    2655         568 :       CurDAG->SelectNodeTo(N, ARM::tADDframe, MVT::i32, TFI,
    2656             :                            CurDAG->getTargetConstant(0, dl, MVT::i32));
    2657         284 :       return;
    2658             :     } else {
    2659        2457 :       unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
    2660             :                       ARM::t2ADDri : ARM::ADDri);
    2661        1786 :       SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, dl, MVT::i32),
    2662        5358 :                         getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
    2663       10716 :                         CurDAG->getRegister(0, MVT::i32) };
    2664        3572 :       CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
    2665             :       return;
    2666             :     }
    2667             :   }
    2668         450 :   case ISD::SRL:
    2669         450 :     if (tryV6T2BitfieldExtractOp(N, false))
    2670             :       return;
    2671             :     break;
    2672         445 :   case ISD::SIGN_EXTEND_INREG:
    2673             :   case ISD::SRA:
    2674         445 :     if (tryV6T2BitfieldExtractOp(N, true))
    2675             :       return;
    2676             :     break;
    2677         319 :   case ISD::MUL:
    2678         319 :     if (Subtarget->isThumb1Only())
    2679             :       break;
    2680         272 :     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
    2681         146 :       unsigned RHSV = C->getZExtValue();
    2682          73 :       if (!RHSV) break;
    2683          73 :       if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
    2684             :         unsigned ShImm = Log2_32(RHSV-1);
    2685             :         if (ShImm >= 32)
    2686             :           break;
    2687           0 :         SDValue V = N->getOperand(0);
    2688             :         ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
    2689           0 :         SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, dl, MVT::i32);
    2690           0 :         SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
    2691           0 :         if (Subtarget->isThumb()) {
    2692           0 :           SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
    2693           0 :           CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops);
    2694             :           return;
    2695             :         } else {
    2696           0 :           SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
    2697           0 :                             Reg0 };
    2698           0 :           CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops);
    2699             :           return;
    2700             :         }
    2701             :       }
    2702          73 :       if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
    2703             :         unsigned ShImm = Log2_32(RHSV+1);
    2704             :         if (ShImm >= 32)
    2705             :           break;
    2706           0 :         SDValue V = N->getOperand(0);
    2707             :         ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
    2708           0 :         SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, dl, MVT::i32);
    2709           0 :         SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
    2710           0 :         if (Subtarget->isThumb()) {
    2711           0 :           SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
    2712           0 :           CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops);
    2713             :           return;
    2714             :         } else {
    2715           0 :           SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
    2716           0 :                             Reg0 };
    2717           0 :           CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops);
    2718             :           return;
    2719             :         }
    2720             :       }
    2721             :     }
    2722             :     break;
    2723        1438 :   case ISD::AND: {
    2724             :     // Check for unsigned bitfield extract
    2725        1438 :     if (tryV6T2BitfieldExtractOp(N, false))
    2726          80 :       return;
    2727             : 
    2728             :     // If an immediate is used in an AND node, it is possible that the immediate
    2729             :     // can be more optimally materialized when negated. If this is the case we
    2730             :     // can negate the immediate and use a BIC instead.
    2731        1383 :     auto *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1));
    2732         741 :     if (N1C && N1C->hasOneUse() && Subtarget->isThumb()) {
    2733         828 :       uint32_t Imm = (uint32_t) N1C->getZExtValue();
    2734             : 
    2735             :       // In Thumb2 mode, an AND can take a 12-bit immediate. If this
    2736             :       // immediate can be negated and fit in the immediate operand of
    2737             :       // a t2BIC, don't do any manual transform here as this can be
    2738             :       // handled by the generic ISel machinery.
    2739             :       bool PreferImmediateEncoding =
    2740         934 :         Subtarget->hasThumb2() && (is_t2_so_imm(Imm) || is_t2_so_imm_not(Imm));
    2741         235 :       if (!PreferImmediateEncoding &&
    2742         235 :           ConstantMaterializationCost(Imm) >
    2743         235 :               ConstantMaterializationCost(~Imm)) {
    2744             :         // The current immediate costs more to materialize than a negated
    2745             :         // immediate, so negate the immediate and use a BIC.
    2746             :         SDValue NewImm =
    2747          69 :           CurDAG->getConstant(~N1C->getZExtValue(), dl, MVT::i32);
    2748             :         // If the new constant didn't exist before, reposition it in the topological
    2749             :         // ordering so it is just before N. Otherwise, don't touch its location.
    2750          23 :         if (NewImm->getNodeId() == -1)
    2751          13 :           CurDAG->RepositionNode(N->getIterator(), NewImm.getNode());
    2752             : 
    2753          23 :         if (!Subtarget->hasThumb2()) {
    2754          32 :           SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32),
    2755          32 :                            N->getOperand(0), NewImm, getAL(CurDAG, dl),
    2756          64 :                            CurDAG->getRegister(0, MVT::i32)};
    2757          32 :           ReplaceNode(N, CurDAG->getMachineNode(ARM::tBIC, dl, MVT::i32, Ops));
    2758             :           return;
    2759             :         } else {
    2760          14 :           SDValue Ops[] = {N->getOperand(0), NewImm, getAL(CurDAG, dl),
    2761          14 :                            CurDAG->getRegister(0, MVT::i32),
    2762          35 :                            CurDAG->getRegister(0, MVT::i32)};
    2763           7 :           ReplaceNode(N,
    2764          21 :                       CurDAG->getMachineNode(ARM::t2BICrr, dl, MVT::i32, Ops));
    2765             :           return;
    2766             :         }
    2767             :       }
    2768             :     }
    2769             : 
    2770             :     // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
    2771             :     // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
    2772             :     // are entirely contributed by c2 and lower 16-bits are entirely contributed
    2773             :     // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
    2774             :     // Select it to: "movt x, ((c1 & 0xffff) >> 16)
    2775        2720 :     EVT VT = N->getValueType(0);
    2776             :     if (VT != MVT::i32)
    2777             :       break;
    2778        1974 :     unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
    2779        2200 :       ? ARM::t2MOVTi16
    2780         894 :       : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
    2781             :     if (!Opc)
    2782             :       break;
    2783         558 :     SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
    2784             :     N1C = dyn_cast<ConstantSDNode>(N1);
    2785             :     if (!N1C)
    2786             :       break;
    2787         449 :     if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
    2788           9 :       SDValue N2 = N0.getOperand(1);
    2789             :       ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
    2790             :       if (!N2C)
    2791             :         break;
    2792           4 :       unsigned N1CVal = N1C->getZExtValue();
    2793           4 :       unsigned N2CVal = N2C->getZExtValue();
    2794           4 :       if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
    2795           4 :           (N1CVal & 0xffffU) == 0xffffU &&
    2796           2 :           (N2CVal & 0xffffU) == 0x0U) {
    2797           2 :         SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
    2798           2 :                                                   dl, MVT::i32);
    2799             :         SDValue Ops[] = { N0.getOperand(0), Imm16,
    2800           4 :                           getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32) };
    2801           4 :         ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, Ops));
    2802             :         return;
    2803             :       }
    2804             :     }
    2805             : 
    2806             :     break;
    2807             :   }
    2808          12 :   case ARMISD::UMAAL: {
    2809          12 :     unsigned Opc = Subtarget->isThumb() ? ARM::t2UMAAL : ARM::UMAAL;
    2810          12 :     SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
    2811             :                       N->getOperand(2), N->getOperand(3),
    2812          12 :                       getAL(CurDAG, dl),
    2813          36 :                       CurDAG->getRegister(0, MVT::i32) };
    2814          24 :     ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, MVT::i32, Ops));
    2815             :     return;
    2816             :   }
    2817          31 :   case ARMISD::UMLAL:{
    2818          31 :     if (Subtarget->isThumb()) {
    2819          15 :       SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
    2820          15 :                         N->getOperand(3), getAL(CurDAG, dl),
    2821          45 :                         CurDAG->getRegister(0, MVT::i32)};
    2822          15 :       ReplaceNode(
    2823          45 :           N, CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops));
    2824             :       return;
    2825             :     }else{
    2826          16 :       SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
    2827          16 :                         N->getOperand(3), getAL(CurDAG, dl),
    2828          32 :                         CurDAG->getRegister(0, MVT::i32),
    2829          80 :                         CurDAG->getRegister(0, MVT::i32) };
    2830          32 :       ReplaceNode(N, CurDAG->getMachineNode(
    2831          16 :                          Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl,
    2832             :                          MVT::i32, MVT::i32, Ops));
    2833             :       return;
    2834             :     }
    2835             :   }
    2836          37 :   case ARMISD::SMLAL:{
    2837          37 :     if (Subtarget->isThumb()) {
    2838          22 :       SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
    2839          22 :                         N->getOperand(3), getAL(CurDAG, dl),
    2840          66 :                         CurDAG->getRegister(0, MVT::i32)};
    2841          22 :       ReplaceNode(
    2842          66 :           N, CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops));
    2843             :       return;
    2844             :     }else{
    2845          15 :       SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
    2846          15 :                         N->getOperand(3), getAL(CurDAG, dl),
    2847          30 :                         CurDAG->getRegister(0, MVT::i32),
    2848          75 :                         CurDAG->getRegister(0, MVT::i32) };
    2849          30 :       ReplaceNode(N, CurDAG->getMachineNode(
    2850          15 :                          Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl,
    2851             :                          MVT::i32, MVT::i32, Ops));
    2852             :       return;
    2853             :     }
    2854             :   }
    2855         149 :   case ARMISD::SUBE: {
    2856         149 :     if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
    2857             :       break;
    2858             :     // Look for a pattern to match SMMLS
    2859             :     // (sube a, (smul_loHi a, b), (subc 0, (smul_LOhi(a, b))))
    2860          94 :     if (N->getOperand(1).getOpcode() != ISD::SMUL_LOHI ||
    2861          94 :         N->getOperand(2).getOpcode() != ARMISD::SUBC ||
    2862             :         !SDValue(N, 1).use_empty())
    2863             :       break;
    2864             : 
    2865           7 :     if (Subtarget->isThumb())
    2866             :       assert(Subtarget->hasThumb2() &&
    2867             :              "This pattern should not be generated for Thumb");
    2868             : 
    2869           7 :     SDValue SmulLoHi = N->getOperand(1);
    2870           7 :     SDValue Subc = N->getOperand(2);
    2871             :     auto *Zero = dyn_cast<ConstantSDNode>(Subc.getOperand(0));
    2872             : 
    2873          14 :     if (!Zero || Zero->getZExtValue() != 0 ||
    2874             :         Subc.getOperand(1) != SmulLoHi.getValue(0) ||
    2875             :         N->getOperand(1) != SmulLoHi.getValue(1) ||
    2876             :         N->getOperand(2) != Subc.getValue(1))
    2877             :       break;
    2878             : 
    2879             :     unsigned Opc = Subtarget->isThumb2() ? ARM::t2SMMLS : ARM::SMMLS;
    2880             :     SDValue Ops[] = { SmulLoHi.getOperand(0), SmulLoHi.getOperand(1),
    2881           7 :                       N->getOperand(0), getAL(CurDAG, dl),
    2882          21 :                       CurDAG->getRegister(0, MVT::i32) };
    2883          14 :     ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops));
    2884           7 :     return;
    2885             :   }
    2886       12931 :   case ISD::LOAD: {
    2887       12931 :     if (Subtarget->isThumb() && Subtarget->hasThumb2()) {
    2888        3921 :       if (tryT2IndexedLoad(N))
    2889             :         return;
    2890        9010 :     } else if (Subtarget->isThumb()) {
    2891        1656 :       if (tryT1IndexedLoad(N))
    2892             :         return;
    2893        7354 :     } else if (tryARMIndexedLoad(N))
    2894             :       return;
    2895             :     // Other cases are autogenerated.
    2896             :     break;
    2897             :   }
    2898        1841 :   case ARMISD::BRCOND: {
    2899             :     // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
    2900             :     // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
    2901             :     // Pattern complexity = 6  cost = 1  size = 0
    2902             : 
    2903             :     // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
    2904             :     // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
    2905             :     // Pattern complexity = 6  cost = 1  size = 0
    2906             : 
    2907             :     // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
    2908             :     // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
    2909             :     // Pattern complexity = 6  cost = 1  size = 0
    2910             : 
    2911        2964 :     unsigned Opc = Subtarget->isThumb() ?
    2912        1123 :       ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
    2913        1841 :     SDValue Chain = N->getOperand(0);
    2914        1841 :     SDValue N1 = N->getOperand(1);
    2915        1841 :     SDValue N2 = N->getOperand(2);
    2916        1841 :     SDValue N3 = N->getOperand(3);
    2917        1841 :     SDValue InFlag = N->getOperand(4);
    2918             :     assert(N1.getOpcode() == ISD::BasicBlock);
    2919             :     assert(N2.getOpcode() == ISD::Constant);
    2920             :     assert(N3.getOpcode() == ISD::Register);
    2921             : 
    2922        3682 :     unsigned CC = (unsigned) cast<ConstantSDNode>(N2)->getZExtValue();
    2923             :     
    2924        1841 :     if (InFlag.getOpcode() == ARMISD::CMPZ) {
    2925             :       bool SwitchEQNEToPLMI;
    2926        1503 :       SelectCMPZ(InFlag.getNode(), SwitchEQNEToPLMI);
    2927        1503 :       InFlag = N->getOperand(4);
    2928             : 
    2929        1503 :       if (SwitchEQNEToPLMI) {
    2930          11 :         switch ((ARMCC::CondCodes)CC) {
    2931           0 :         default: llvm_unreachable("CMPZ must be either NE or EQ!");
    2932             :         case ARMCC::NE:
    2933             :           CC = (unsigned)ARMCC::MI;
    2934             :           break;
    2935           9 :         case ARMCC::EQ:
    2936             :           CC = (unsigned)ARMCC::PL;
    2937           9 :           break;
    2938             :         }
    2939             :       }
    2940             :     }
    2941             : 
    2942        1841 :     SDValue Tmp2 = CurDAG->getTargetConstant(CC, dl, MVT::i32);
    2943        1841 :     SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
    2944        3682 :     SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
    2945        1841 :                                              MVT::Glue, Ops);
    2946             :     Chain = SDValue(ResNode, 0);
    2947        1841 :     if (N->getNumValues() == 2) {
    2948             :       InFlag = SDValue(ResNode, 1);
    2949          53 :       ReplaceUses(SDValue(N, 1), InFlag);
    2950             :     }
    2951        1841 :     ReplaceUses(SDValue(N, 0),
    2952             :                 SDValue(Chain.getNode(), Chain.getResNo()));
    2953        1841 :     CurDAG->RemoveDeadNode(N);
    2954             :     return;
    2955             :   }
    2956             : 
    2957        1958 :   case ARMISD::CMPZ: {
    2958             :     // select (CMPZ X, #-C) -> (CMPZ (ADDS X, #C), #0)
    2959             :     //   This allows us to avoid materializing the expensive negative constant.
    2960             :     //   The CMPZ #0 is useless and will be peepholed away but we need to keep it
    2961             :     //   for its glue output.
    2962        1958 :     SDValue X = N->getOperand(0);
    2963        1958 :     auto *C = dyn_cast<ConstantSDNode>(N->getOperand(1).getNode());
    2964        3610 :     if (C && C->getSExtValue() < 0 && Subtarget->isThumb()) {
    2965          26 :       int64_t Addend = -C->getSExtValue();
    2966             : 
    2967             :       SDNode *Add = nullptr;
    2968             :       // ADDS can be better than CMN if the immediate fits in a
    2969             :       // 16-bit ADDS, which means either [0,256) for tADDi8 or [0,8) for tADDi3.
    2970             :       // Outside that range we can just use a CMN which is 32-bit but has a
    2971             :       // 12-bit immediate range.
    2972          26 :       if (Addend < 1<<8) {
    2973             :         if (Subtarget->isThumb2()) {
    2974          20 :           SDValue Ops[] = { X, CurDAG->getTargetConstant(Addend, dl, MVT::i32),
    2975          60 :                             getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
    2976         120 :                             CurDAG->getRegister(0, MVT::i32) };
    2977          40 :           Add = CurDAG->getMachineNode(ARM::t2ADDri, dl, MVT::i32, Ops);
    2978             :         } else {
    2979           2 :           unsigned Opc = (Addend < 1<<3) ? ARM::tADDi3 : ARM::tADDi8;
    2980           4 :           SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), X,
    2981           2 :                            CurDAG->getTargetConstant(Addend, dl, MVT::i32),
    2982           8 :                            getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32)};
    2983           4 :           Add = CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops);
    2984             :         }
    2985             :       }
    2986          22 :       if (Add) {
    2987          44 :         SDValue Ops2[] = {SDValue(Add, 0), CurDAG->getConstant(0, dl, MVT::i32)};
    2988          44 :         CurDAG->MorphNodeTo(N, ARMISD::CMPZ, CurDAG->getVTList(MVT::Glue), Ops2);
    2989             :       }
    2990             :     }
    2991             :     // Other cases are autogenerated.
    2992             :     break;
    2993             :   }
    2994             : 
    2995        1520 :   case ARMISD::CMOV: {
    2996        1520 :     SDValue InFlag = N->getOperand(4);
    2997             : 
    2998        1520 :     if (InFlag.getOpcode() == ARMISD::CMPZ) {
    2999             :       bool SwitchEQNEToPLMI;
    3000         455 :       SelectCMPZ(InFlag.getNode(), SwitchEQNEToPLMI);
    3001             : 
    3002         455 :       if (SwitchEQNEToPLMI) {
    3003           4 :         SDValue ARMcc = N->getOperand(2);
    3004             :         ARMCC::CondCodes CC =
    3005           4 :           (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
    3006             : 
    3007           4 :         switch (CC) {
    3008           0 :         default: llvm_unreachable("CMPZ must be either NE or EQ!");
    3009             :         case ARMCC::NE:
    3010             :           CC = ARMCC::MI;
    3011             :           break;
    3012           4 :         case ARMCC::EQ:
    3013             :           CC = ARMCC::PL;
    3014           4 :           break;
    3015             :         }
    3016           8 :         SDValue NewARMcc = CurDAG->getConstant((unsigned)CC, dl, MVT::i32);
    3017           4 :         SDValue Ops[] = {N->getOperand(0), N->getOperand(1), NewARMcc,
    3018           4 :                          N->getOperand(3), N->getOperand(4)};
    3019          12 :         CurDAG->MorphNodeTo(N, ARMISD::CMOV, N->getVTList(), Ops);
    3020             :       }
    3021             : 
    3022             :     }
    3023             :     // Other cases are autogenerated.
    3024             :     break;
    3025             :   }
    3026             :     
    3027          26 :   case ARMISD::VZIP: {
    3028             :     unsigned Opc = 0;
    3029          52 :     EVT VT = N->getValueType(0);
    3030          26 :     switch (VT.getSimpleVT().SimpleTy) {
    3031             :     default: return;
    3032             :     case MVT::v8i8:  Opc = ARM::VZIPd8; break;
    3033           7 :     case MVT::v4i16: Opc = ARM::VZIPd16; break;
    3034           0 :     case MVT::v2f32:
    3035             :     // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
    3036           0 :     case MVT::v2i32: Opc = ARM::VTRNd32; break;
    3037           4 :     case MVT::v16i8: Opc = ARM::VZIPq8; break;
    3038           2 :     case MVT::v8i16: Opc = ARM::VZIPq16; break;
    3039           8 :     case MVT::v4f32:
    3040           8 :     case MVT::v4i32: Opc = ARM::VZIPq32; break;
    3041             :     }
    3042          26 :     SDValue Pred = getAL(CurDAG, dl);
    3043          52 :     SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
    3044          26 :     SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
    3045          52 :     ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
    3046          26 :     return;
    3047             :   }
    3048          54 :   case ARMISD::VUZP: {
    3049             :     unsigned Opc = 0;
    3050         108 :     EVT VT = N->getValueType(0);
    3051          54 :     switch (VT.getSimpleVT().SimpleTy) {
    3052             :     default: return;
    3053             :     case MVT::v8i8:  Opc = ARM::VUZPd8; break;
    3054          15 :     case MVT::v4i16: Opc = ARM::VUZPd16; break;
    3055           0 :     case MVT::v2f32:
    3056             :     // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
    3057           0 :     case MVT::v2i32: Opc = ARM::VTRNd32; break;
    3058           4 :     case MVT::v16i8: Opc = ARM::VUZPq8; break;
    3059           7 :     case MVT::v8i16: Opc = ARM::VUZPq16; break;
    3060           8 :     case MVT::v4f32:
    3061           8 :     case MVT::v4i32: Opc = ARM::VUZPq32; break;
    3062             :     }
    3063          54 :     SDValue Pred = getAL(CurDAG, dl);
    3064         108 :     SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
    3065          54 :     SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
    3066         108 :     ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
    3067          54 :     return;
    3068             :   }
    3069          31 :   case ARMISD::VTRN: {
    3070             :     unsigned Opc = 0;
    3071          62 :     EVT VT = N->getValueType(0);
    3072          31 :     switch (VT.getSimpleVT().SimpleTy) {
    3073             :     default: return;
    3074             :     case MVT::v8i8:  Opc = ARM::VTRNd8; break;
    3075           7 :     case MVT::v4i16: Opc = ARM::VTRNd16; break;
    3076           5 :     case MVT::v2f32:
    3077           5 :     case MVT::v2i32: Opc = ARM::VTRNd32; break;
    3078           2 :     case MVT::v16i8: Opc = ARM::VTRNq8; break;
    3079           6 :     case MVT::v8i16: Opc = ARM::VTRNq16; break;
    3080           5 :     case MVT::v4f32:
    3081           5 :     case MVT::v4i32: Opc = ARM::VTRNq32; break;
    3082             :     }
    3083          31 :     SDValue Pred = getAL(CurDAG, dl);
    3084          62 :     SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
    3085          31 :     SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
    3086          62 :     ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
    3087          31 :     return;
    3088             :   }
    3089         412 :   case ARMISD::BUILD_VECTOR: {
    3090         824 :     EVT VecVT = N->getValueType(0);
    3091         412 :     EVT EltVT = VecVT.getVectorElementType();
    3092         412 :     unsigned NumElts = VecVT.getVectorNumElements();
    3093             :     if (EltVT == MVT::f64) {
    3094             :       assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
    3095         321 :       ReplaceNode(
    3096         321 :           N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)));
    3097         321 :       return;
    3098             :     }
    3099             :     assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
    3100          91 :     if (NumElts == 2) {
    3101          38 :       ReplaceNode(
    3102          38 :           N, createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)));
    3103          38 :       return;
    3104             :     }
    3105             :     assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
    3106          53 :     ReplaceNode(N,
    3107             :                 createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
    3108          53 :                                     N->getOperand(2), N->getOperand(3)));
    3109          53 :     return;
    3110             :   }
    3111             : 
    3112          28 :   case ARMISD::VLD1DUP: {
    3113             :     static const uint16_t DOpcodes[] = { ARM::VLD1DUPd8, ARM::VLD1DUPd16,
    3114             :                                          ARM::VLD1DUPd32 };
    3115             :     static const uint16_t QOpcodes[] = { ARM::VLD1DUPq8, ARM::VLD1DUPq16,
    3116             :                                          ARM::VLD1DUPq32 };
    3117          28 :     SelectVLDDup(N, /* IsIntrinsic= */ false, false, 1, DOpcodes, QOpcodes);
    3118          28 :     return;
    3119             :   }
    3120             : 
    3121           4 :   case ARMISD::VLD2DUP: {
    3122             :     static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
    3123             :                                         ARM::VLD2DUPd32 };
    3124           4 :     SelectVLDDup(N, /* IsIntrinsic= */ false, false, 2, Opcodes);
    3125           4 :     return;
    3126             :   }
    3127             : 
    3128           1 :   case ARMISD::VLD3DUP: {
    3129             :     static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo,
    3130             :                                         ARM::VLD3DUPd16Pseudo,
    3131             :                                         ARM::VLD3DUPd32Pseudo };
    3132           1 :     SelectVLDDup(N, /* IsIntrinsic= */ false, false, 3, Opcodes);
    3133           1 :     return;
    3134             :   }
    3135             : 
    3136           1 :   case ARMISD::VLD4DUP: {
    3137             :     static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo,
    3138             :                                         ARM::VLD4DUPd16Pseudo,
    3139             :                                         ARM::VLD4DUPd32Pseudo };
    3140           1 :     SelectVLDDup(N, /* IsIntrinsic= */ false, false, 4, Opcodes);
    3141           1 :     return;
    3142             :   }
    3143             : 
    3144           6 :   case ARMISD::VLD1DUP_UPD: {
    3145             :     static const uint16_t DOpcodes[] = { ARM::VLD1DUPd8wb_fixed,
    3146             :                                          ARM::VLD1DUPd16wb_fixed,
    3147             :                                          ARM::VLD1DUPd32wb_fixed };
    3148             :     static const uint16_t QOpcodes[] = { ARM::VLD1DUPq8wb_fixed,
    3149             :                                          ARM::VLD1DUPq16wb_fixed,
    3150             :                                          ARM::VLD1DUPq32wb_fixed };
    3151           6 :     SelectVLDDup(N, /* IsIntrinsic= */ false, true, 1, DOpcodes, QOpcodes);
    3152           6 :     return;
    3153             :   }
    3154             : 
    3155           4 :   case ARMISD::VLD2DUP_UPD: {
    3156             :     static const uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed,
    3157             :                                         ARM::VLD2DUPd16wb_fixed,
    3158             :                                         ARM::VLD2DUPd32wb_fixed };
    3159           4 :     SelectVLDDup(N, /* IsIntrinsic= */ false, true, 2, Opcodes);
    3160           4 :     return;
    3161             :   }
    3162             : 
    3163           1 :   case ARMISD::VLD3DUP_UPD: {
    3164             :     static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD,
    3165             :                                         ARM::VLD3DUPd16Pseudo_UPD,
    3166             :                                         ARM::VLD3DUPd32Pseudo_UPD };
    3167           1 :     SelectVLDDup(N, /* IsIntrinsic= */ false, true, 3, Opcodes);
    3168           1 :     return;
    3169             :   }
    3170             : 
    3171           1 :   case ARMISD::VLD4DUP_UPD: {
    3172             :     static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD,
    3173             :                                         ARM::VLD4DUPd16Pseudo_UPD,
    3174             :                                         ARM::VLD4DUPd32Pseudo_UPD };
    3175           1 :     SelectVLDDup(N, /* IsIntrinsic= */ false, true, 4, Opcodes);
    3176           1 :     return;
    3177             :   }
    3178             : 
    3179         112 :   case ARMISD::VLD1_UPD: {
    3180             :     static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed,
    3181             :                                          ARM::VLD1d16wb_fixed,
    3182             :                                          ARM::VLD1d32wb_fixed,
    3183             :                                          ARM::VLD1d64wb_fixed };
    3184             :     static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed,
    3185             :                                          ARM::VLD1q16wb_fixed,
    3186             :                                          ARM::VLD1q32wb_fixed,
    3187             :                                          ARM::VLD1q64wb_fixed };
    3188         112 :     SelectVLD(N, true, 1, DOpcodes, QOpcodes, nullptr);
    3189         112 :     return;
    3190             :   }
    3191             : 
    3192           7 :   case ARMISD::VLD2_UPD: {
    3193             :     static const uint16_t DOpcodes[] = { ARM::VLD2d8wb_fixed,
    3194             :                                          ARM::VLD2d16wb_fixed,
    3195             :                                          ARM::VLD2d32wb_fixed,
    3196             :                                          ARM::VLD1q64wb_fixed};
    3197             :     static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
    3198             :                                          ARM::VLD2q16PseudoWB_fixed,
    3199             :                                          ARM::VLD2q32PseudoWB_fixed };
    3200           7 :     SelectVLD(N, true, 2, DOpcodes, QOpcodes, nullptr);
    3201           7 :     return;
    3202             :   }
    3203             : 
    3204           9 :   case ARMISD::VLD3_UPD: {
    3205             :     static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD,
    3206             :                                          ARM::VLD3d16Pseudo_UPD,
    3207             :                                          ARM::VLD3d32Pseudo_UPD,
    3208             :                                          ARM::VLD1d64TPseudoWB_fixed};
    3209             :     static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
    3210             :                                           ARM::VLD3q16Pseudo_UPD,
    3211             :                                           ARM::VLD3q32Pseudo_UPD };
    3212             :     static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
    3213             :                                           ARM::VLD3q16oddPseudo_UPD,
    3214             :                                           ARM::VLD3q32oddPseudo_UPD };
    3215           9 :     SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
    3216           9 :     return;
    3217             :   }
    3218             : 
    3219           4 :   case ARMISD::VLD4_UPD: {
    3220             :     static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD,
    3221             :                                          ARM::VLD4d16Pseudo_UPD,
    3222             :                                          ARM::VLD4d32Pseudo_UPD,
    3223             :                                          ARM::VLD1d64QPseudoWB_fixed};
    3224             :     static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
    3225             :                                           ARM::VLD4q16Pseudo_UPD,
    3226             :                                           ARM::VLD4q32Pseudo_UPD };
    3227             :     static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
    3228             :                                           ARM::VLD4q16oddPseudo_UPD,
    3229             :                                           ARM::VLD4q32oddPseudo_UPD };
    3230           4 :     SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
    3231           4 :     return;
    3232             :   }
    3233             : 
    3234           4 :   case ARMISD::VLD2LN_UPD: {
    3235             :     static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD,
    3236             :                                          ARM::VLD2LNd16Pseudo_UPD,
    3237             :                                          ARM::VLD2LNd32Pseudo_UPD };
    3238             :     static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
    3239             :                                          ARM::VLD2LNq32Pseudo_UPD };
    3240           4 :     SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
    3241           4 :     return;
    3242             :   }
    3243             : 
    3244           2 :   case ARMISD::VLD3LN_UPD: {
    3245             :     static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD,
    3246             :                                          ARM::VLD3LNd16Pseudo_UPD,
    3247             :                                          ARM::VLD3LNd32Pseudo_UPD };
    3248             :     static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
    3249             :                                          ARM::VLD3LNq32Pseudo_UPD };
    3250           2 :     SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
    3251           2 :     return;
    3252             :   }
    3253             : 
    3254           2 :   case ARMISD::VLD4LN_UPD: {
    3255             :     static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD,
    3256             :                                          ARM::VLD4LNd16Pseudo_UPD,
    3257             :                                          ARM::VLD4LNd32Pseudo_UPD };
    3258             :     static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
    3259             :                                          ARM::VLD4LNq32Pseudo_UPD };
    3260           2 :     SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
    3261           2 :     return;
    3262             :   }
    3263             : 
    3264         138 :   case ARMISD::VST1_UPD: {
    3265             :     static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed,
    3266             :                                          ARM::VST1d16wb_fixed,
    3267             :                                          ARM::VST1d32wb_fixed,
    3268             :                                          ARM::VST1d64wb_fixed };
    3269             :     static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed,
    3270             :                                          ARM::VST1q16wb_fixed,
    3271             :                                          ARM::VST1q32wb_fixed,
    3272             :                                          ARM::VST1q64wb_fixed };
    3273         138 :     SelectVST(N, true, 1, DOpcodes, QOpcodes, nullptr);
    3274         138 :     return;
    3275             :   }
    3276             : 
    3277           5 :   case ARMISD::VST2_UPD: {
    3278             :     static const uint16_t DOpcodes[] = { ARM::VST2d8wb_fixed,
    3279             :                                          ARM::VST2d16wb_fixed,
    3280             :                                          ARM::VST2d32wb_fixed,
    3281             :                                          ARM::VST1q64wb_fixed};
    3282             :     static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
    3283             :                                          ARM::VST2q16PseudoWB_fixed,
    3284             :                                          ARM::VST2q32PseudoWB_fixed };
    3285           5 :     SelectVST(N, true, 2, DOpcodes, QOpcodes, nullptr);
    3286           5 :     return;
    3287             :   }
    3288             : 
    3289           4 :   case ARMISD::VST3_UPD: {
    3290             :     static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD,
    3291             :                                          ARM::VST3d16Pseudo_UPD,
    3292             :                                          ARM::VST3d32Pseudo_UPD,
    3293             :                                          ARM::VST1d64TPseudoWB_fixed};
    3294             :     static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
    3295             :                                           ARM::VST3q16Pseudo_UPD,
    3296             :                                           ARM::VST3q32Pseudo_UPD };
    3297             :     static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
    3298             :                                           ARM::VST3q16oddPseudo_UPD,
    3299             :                                           ARM::VST3q32oddPseudo_UPD };
    3300           4 :     SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
    3301           4 :     return;
    3302             :   }
    3303             : 
    3304           4 :   case ARMISD::VST4_UPD: {
    3305             :     static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo_UPD,
    3306             :                                          ARM::VST4d16Pseudo_UPD,
    3307             :                                          ARM::VST4d32Pseudo_UPD,
    3308             :                                          ARM::VST1d64QPseudoWB_fixed};
    3309             :     static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
    3310             :                                           ARM::VST4q16Pseudo_UPD,
    3311             :                                           ARM::VST4q32Pseudo_UPD };
    3312             :     static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
    3313             :                                           ARM::VST4q16oddPseudo_UPD,
    3314             :                                           ARM::VST4q32oddPseudo_UPD };
    3315           4 :     SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
    3316           4 :     return;
    3317             :   }
    3318             : 
    3319           1 :   case ARMISD::VST2LN_UPD: {
    3320             :     static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD,
    3321             :                                          ARM::VST2LNd16Pseudo_UPD,
    3322             :                                          ARM::VST2LNd32Pseudo_UPD };
    3323             :     static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
    3324             :                                          ARM::VST2LNq32Pseudo_UPD };
    3325           1 :     SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
    3326           1 :     return;
    3327             :   }
    3328             : 
    3329           1 :   case ARMISD::VST3LN_UPD: {
    3330             :     static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD,
    3331             :                                          ARM::VST3LNd16Pseudo_UPD,
    3332             :                                          ARM::VST3LNd32Pseudo_UPD };
    3333             :     static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
    3334             :                                          ARM::VST3LNq32Pseudo_UPD };
    3335           1 :     SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
    3336           1 :     return;
    3337             :   }
    3338             : 
    3339           1 :   case ARMISD::VST4LN_UPD: {
    3340             :     static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD,
    3341             :                                          ARM::VST4LNd16Pseudo_UPD,
    3342             :                                          ARM::VST4LNd32Pseudo_UPD };
    3343             :     static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
    3344             :                                          ARM::VST4LNq32Pseudo_UPD };
    3345           1 :     SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
    3346           1 :     return;
    3347             :   }
    3348             : 
    3349        1608 :   case ISD::INTRINSIC_VOID:
    3350             :   case ISD::INTRINSIC_W_CHAIN: {
    3351        4824 :     unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
    3352        1608 :     switch (IntNo) {
    3353             :     default:
    3354             :       break;
    3355             : 
    3356             :     case Intrinsic::arm_mrrc:
    3357             :     case Intrinsic::arm_mrrc2: {
    3358             :       SDLoc dl(N);
    3359           4 :       SDValue Chain = N->getOperand(0);
    3360             :       unsigned Opc;
    3361             : 
    3362           4 :       if (Subtarget->isThumb())
    3363           2 :         Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::t2MRRC : ARM::t2MRRC2);
    3364             :       else
    3365           2 :         Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::MRRC : ARM::MRRC2);
    3366             : 
    3367             :       SmallVector<SDValue, 5> Ops;
    3368          12 :       Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(), dl)); /* coproc */
    3369          16 :       Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(3))->getZExtValue(), dl)); /* opc */
    3370          16 :       Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(4))->getZExtValue(), dl)); /* CRm */
    3371             : 
    3372             :       // The mrrc2 instruction in ARM doesn't allow predicates, the top 4 bits of the encoded
    3373             :       // instruction will always be '1111' but it is possible in assembly language to specify
    3374             :       // AL as a predicate to mrrc2 but it doesn't make any difference to the encoded instruction.
    3375           4 :       if (Opc != ARM::MRRC2) {
    3376           3 :         Ops.push_back(getAL(CurDAG, dl));
    3377           6 :         Ops.push_back(CurDAG->getRegister(0, MVT::i32));
    3378             :       }
    3379             : 
    3380           4 :       Ops.push_back(Chain);
    3381             : 
    3382             :       // Writes to two registers.
    3383           4 :       const EVT RetType[] = {MVT::i32, MVT::i32, MVT::Other};
    3384             : 
    3385           8 :       ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, RetType, Ops));
    3386             :       return;
    3387             :     }
    3388             :     case Intrinsic::arm_ldaexd:
    3389             :     case Intrinsic::arm_ldrexd: {
    3390             :       SDLoc dl(N);
    3391         127 :       SDValue Chain = N->getOperand(0);
    3392         127 :       SDValue MemAddr = N->getOperand(2);
    3393         127 :       bool isThumb = Subtarget->isThumb() && Subtarget->hasV8MBaselineOps();
    3394             : 
    3395             :       bool IsAcquire = IntNo == Intrinsic::arm_ldaexd;
    3396          69 :       unsigned NewOpc = isThumb ? (IsAcquire ? ARM::t2LDAEXD : ARM::t2LDREXD)
    3397             :                                 : (IsAcquire ? ARM::LDAEXD : ARM::LDREXD);
    3398             : 
    3399             :       // arm_ldrexd returns a i64 value in {i32, i32}
    3400             :       std::vector<EVT> ResTys;
    3401         127 :       if (isThumb) {
    3402          58 :         ResTys.push_back(MVT::i32);
    3403          58 :         ResTys.push_back(MVT::i32);
    3404             :       } else
    3405          69 :         ResTys.push_back(MVT::Untyped);
    3406         127 :       ResTys.push_back(MVT::Other);
    3407             : 
    3408             :       // Place arguments in the right order.
    3409         127 :       SDValue Ops[] = {MemAddr, getAL(CurDAG, dl),
    3410         381 :                        CurDAG->getRegister(0, MVT::i32), Chain};
    3411         254 :       SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
    3412             :       // Transfer memoperands.
    3413         127 :       MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
    3414         127 :       MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
    3415         127 :       cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
    3416             : 
    3417             :       // Remap uses.
    3418         127 :       SDValue OutChain = isThumb ? SDValue(Ld, 2) : SDValue(Ld, 1);
    3419         127 :       if (!SDValue(N, 0).use_empty()) {
    3420             :         SDValue Result;
    3421         109 :         if (isThumb)
    3422             :           Result = SDValue(Ld, 0);
    3423             :         else {
    3424             :           SDValue SubRegIdx =
    3425         112 :             CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32);
    3426         112 :           SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
    3427          56 :               dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
    3428             :           Result = SDValue(ResNode,0);
    3429             :         }
    3430         109 :         ReplaceUses(SDValue(N, 0), Result);
    3431             :       }
    3432         127 :       if (!SDValue(N, 1).use_empty()) {
    3433             :         SDValue Result;
    3434         108 :         if (isThumb)
    3435             :           Result = SDValue(Ld, 1);
    3436             :         else {
    3437             :           SDValue SubRegIdx =
    3438         110 :             CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32);
    3439         110 :           SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
    3440          55 :               dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
    3441             :           Result = SDValue(ResNode,0);
    3442             :         }
    3443         108 :         ReplaceUses(SDValue(N, 1), Result);
    3444             :       }
    3445         127 :       ReplaceUses(SDValue(N, 2), OutChain);
    3446         127 :       CurDAG->RemoveDeadNode(N);
    3447             :       return;
    3448             :     }
    3449             :     case Intrinsic::arm_stlexd:
    3450             :     case Intrinsic::arm_strexd: {
    3451             :       SDLoc dl(N);
    3452         109 :       SDValue Chain = N->getOperand(0);
    3453         109 :       SDValue Val0 = N->getOperand(2);
    3454         109 :       SDValue Val1 = N->getOperand(3);
    3455         109 :       SDValue MemAddr = N->getOperand(4);
    3456             : 
    3457             :       // Store exclusive double return a i32 value which is the return status
    3458             :       // of the issued store.
    3459         109 :       const EVT ResTys[] = {MVT::i32, MVT::Other};
    3460             : 
    3461         109 :       bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
    3462             :       // Place arguments in the right order.
    3463             :       SmallVector<SDValue, 7> Ops;
    3464         109 :       if (isThumb) {
    3465          51 :         Ops.push_back(Val0);
    3466          51 :         Ops.push_back(Val1);
    3467             :       } else
    3468             :         // arm_strexd uses GPRPair.
    3469         116 :         Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
    3470         109 :       Ops.push_back(MemAddr);
    3471         109 :       Ops.push_back(getAL(CurDAG, dl));
    3472         218 :       Ops.push_back(CurDAG->getRegister(0, MVT::i32));
    3473         109 :       Ops.push_back(Chain);
    3474             : 
    3475             :       bool IsRelease = IntNo == Intrinsic::arm_stlexd;
    3476         109 :       unsigned NewOpc = isThumb ? (IsRelease ? ARM::t2STLEXD : ARM::t2STREXD)
    3477             :                                 : (IsRelease ? ARM::STLEXD : ARM::STREXD);
    3478             : 
    3479         218 :       SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
    3480             :       // Transfer memoperands.
    3481         109 :       MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
    3482         109 :       MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
    3483         109 :       cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
    3484             : 
    3485         109 :       ReplaceNode(N, St);
    3486             :       return;
    3487             :     }
    3488             : 
    3489          68 :     case Intrinsic::arm_neon_vld1: {
    3490             :       static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
    3491             :                                            ARM::VLD1d32, ARM::VLD1d64 };
    3492             :       static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
    3493             :                                            ARM::VLD1q32, ARM::VLD1q64};
    3494          68 :       SelectVLD(N, false, 1, DOpcodes, QOpcodes, nullptr);
    3495          68 :       return;
    3496             :     }
    3497             : 
    3498           8 :     case Intrinsic::arm_neon_vld1x2: {
    3499             :       static const uint16_t DOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
    3500             :                                            ARM::VLD1q32, ARM::VLD1q64 };
    3501             :       static const uint16_t QOpcodes[] = { ARM::VLD1d8QPseudo,
    3502             :                                            ARM::VLD1d16QPseudo,
    3503             :                                            ARM::VLD1d32QPseudo,
    3504             :                                            ARM::VLD1d64QPseudo };
    3505           8 :       SelectVLD(N, false, 2, DOpcodes, QOpcodes, nullptr);
    3506           8 :       return;
    3507             :     }
    3508             : 
    3509           8 :     case Intrinsic::arm_neon_vld1x3: {
    3510             :       static const uint16_t DOpcodes[] = { ARM::VLD1d8TPseudo,
    3511             :                                            ARM::VLD1d16TPseudo,
    3512             :                                            ARM::VLD1d32TPseudo,
    3513             :                                            ARM::VLD1d64TPseudo };
    3514             :       static const uint16_t QOpcodes0[] = { ARM::VLD1q8LowTPseudo_UPD,
    3515             :                                             ARM::VLD1q16LowTPseudo_UPD,
    3516             :                                             ARM::VLD1q32LowTPseudo_UPD,
    3517             :                                             ARM::VLD1q64LowTPseudo_UPD };
    3518             :       static const uint16_t QOpcodes1[] = { ARM::VLD1q8HighTPseudo,
    3519             :                                             ARM::VLD1q16HighTPseudo,
    3520             :                                             ARM::VLD1q32HighTPseudo,
    3521             :                                             ARM::VLD1q64HighTPseudo };
    3522           8 :       SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
    3523           8 :       return;
    3524             :     }
    3525             : 
    3526           8 :     case Intrinsic::arm_neon_vld1x4: {
    3527             :       static const uint16_t DOpcodes[] = { ARM::VLD1d8QPseudo,
    3528             :                                            ARM::VLD1d16QPseudo,
    3529             :                                            ARM::VLD1d32QPseudo,
    3530             :                                            ARM::VLD1d64QPseudo };
    3531             :       static const uint16_t QOpcodes0[] = { ARM::VLD1q8LowQPseudo_UPD,
    3532             :                                             ARM::VLD1q16LowQPseudo_UPD,
    3533             :                                             ARM::VLD1q32LowQPseudo_UPD,
    3534             :                                             ARM::VLD1q64LowQPseudo_UPD };
    3535             :       static const uint16_t QOpcodes1[] = { ARM::VLD1q8HighQPseudo,
    3536             :                                             ARM::VLD1q16HighQPseudo,
    3537             :                                             ARM::VLD1q32HighQPseudo,
    3538             :                                             ARM::VLD1q64HighQPseudo };
    3539           8 :       SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
    3540           8 :       return;
    3541             :     }
    3542             : 
    3543          16 :     case Intrinsic::arm_neon_vld2: {
    3544             :       static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
    3545             :                                            ARM::VLD2d32, ARM::VLD1q64 };
    3546             :       static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
    3547             :                                            ARM::VLD2q32Pseudo };
    3548          16 :       SelectVLD(N, false, 2, DOpcodes, QOpcodes, nullptr);
    3549          16 :       return;
    3550             :     }
    3551             : 
    3552          37 :     case Intrinsic::arm_neon_vld3: {
    3553             :       static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo,
    3554             :                                            ARM::VLD3d16Pseudo,
    3555             :                                            ARM::VLD3d32Pseudo,
    3556             :                                            ARM::VLD1d64TPseudo };
    3557             :       static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
    3558             :                                             ARM::VLD3q16Pseudo_UPD,
    3559             :                                             ARM::VLD3q32Pseudo_UPD };
    3560             :       static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo,
    3561             :                                             ARM::VLD3q16oddPseudo,
    3562             :                                             ARM::VLD3q32oddPseudo };
    3563          37 :       SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
    3564          37 :       return;
    3565             :     }
    3566             : 
    3567          11 :     case Intrinsic::arm_neon_vld4: {
    3568             :       static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo,
    3569             :                                            ARM::VLD4d16Pseudo,
    3570             :                                            ARM::VLD4d32Pseudo,
    3571             :                                            ARM::VLD1d64QPseudo };
    3572             :       static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
    3573             :                                             ARM::VLD4q16Pseudo_UPD,
    3574             :                                             ARM::VLD4q32Pseudo_UPD };
    3575             :       static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo,
    3576             :                                             ARM::VLD4q16oddPseudo,
    3577             :                                             ARM::VLD4q32oddPseudo };
    3578          11 :       SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
    3579          11 :       return;
    3580             :     }
    3581             : 
    3582           8 :     case Intrinsic::arm_neon_vld2dup: {
    3583             :       static const uint16_t DOpcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
    3584             :                                            ARM::VLD2DUPd32, ARM::VLD1q64 };
    3585             :       static const uint16_t QOpcodes0[] = { ARM::VLD2DUPq8EvenPseudo,
    3586             :                                             ARM::VLD2DUPq16EvenPseudo,
    3587             :                                             ARM::VLD2DUPq32EvenPseudo };
    3588             :       static const uint16_t QOpcodes1[] = { ARM::VLD2DUPq8OddPseudo,
    3589             :                                             ARM::VLD2DUPq16OddPseudo,
    3590             :                                             ARM::VLD2DUPq32OddPseudo };
    3591           8 :       SelectVLDDup(N, /* IsIntrinsic= */ true, false, 2,
    3592             :                    DOpcodes, QOpcodes0, QOpcodes1);
    3593           8 :       return;
    3594             :     }
    3595             : 
    3596           8 :     case Intrinsic::arm_neon_vld3dup: {
    3597             :       static const uint16_t DOpcodes[] = { ARM::VLD3DUPd8Pseudo,
    3598             :                                            ARM::VLD3DUPd16Pseudo,
    3599             :                                            ARM::VLD3DUPd32Pseudo,
    3600             :                                            ARM::VLD1d64TPseudo };
    3601             :       static const uint16_t QOpcodes0[] = { ARM::VLD3DUPq8EvenPseudo,
    3602             :                                             ARM::VLD3DUPq16EvenPseudo,
    3603             :                                             ARM::VLD3DUPq32EvenPseudo };
    3604             :       static const uint16_t QOpcodes1[] = { ARM::VLD3DUPq8OddPseudo,
    3605             :                                             ARM::VLD3DUPq16OddPseudo,
    3606             :                                             ARM::VLD3DUPq32OddPseudo };
    3607           8 :       SelectVLDDup(N, /* IsIntrinsic= */ true, false, 3,
    3608             :                    DOpcodes, QOpcodes0, QOpcodes1);
    3609           8 :       return;
    3610             :     }
    3611             : 
    3612           8 :     case Intrinsic::arm_neon_vld4dup: {
    3613             :       static const uint16_t DOpcodes[] = { ARM::VLD4DUPd8Pseudo,
    3614             :                                            ARM::VLD4DUPd16Pseudo,
    3615             :                                            ARM::VLD4DUPd32Pseudo,
    3616             :                                            ARM::VLD1d64QPseudo };
    3617             :       static const uint16_t QOpcodes0[] = { ARM::VLD4DUPq8EvenPseudo,
    3618             :                                             ARM::VLD4DUPq16EvenPseudo,
    3619             :                                             ARM::VLD4DUPq32EvenPseudo };
    3620             :       static const uint16_t QOpcodes1[] = { ARM::VLD4DUPq8OddPseudo,
    3621             :                                             ARM::VLD4DUPq16OddPseudo,
    3622             :                                             ARM::VLD4DUPq32OddPseudo };
    3623           8 :       SelectVLDDup(N, /* IsIntrinsic= */ true, false, 4,
    3624             :                    DOpcodes, QOpcodes0, QOpcodes1);
    3625           8 :       return;
    3626             :     }
    3627             : 
    3628          19 :     case Intrinsic::arm_neon_vld2lane: {
    3629             :       static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo,
    3630             :                                            ARM::VLD2LNd16Pseudo,
    3631             :                                            ARM::VLD2LNd32Pseudo };
    3632             :       static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo,
    3633             :                                            ARM::VLD2LNq32Pseudo };
    3634          19 :       SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
    3635          19 :       return;
    3636             :     }
    3637             : 
    3638          18 :     case Intrinsic::arm_neon_vld3lane: {
    3639             :       static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo,
    3640             :                                            ARM::VLD3LNd16Pseudo,
    3641             :                                            ARM::VLD3LNd32Pseudo };
    3642             :       static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo,
    3643             :                                            ARM::VLD3LNq32Pseudo };
    3644          18 :       SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
    3645          18 :       return;
    3646             :     }
    3647             : 
    3648          15 :     case Intrinsic::arm_neon_vld4lane: {
    3649             :       static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo,
    3650             :                                            ARM::VLD4LNd16Pseudo,
    3651             :                                            ARM::VLD4LNd32Pseudo };
    3652             :       static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo,
    3653             :                                            ARM::VLD4LNq32Pseudo };
    3654          15 :       SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
    3655          15 :       return;
    3656             :     }
    3657             : 
    3658          37 :     case Intrinsic::arm_neon_vst1: {
    3659             :       static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
    3660             :                                            ARM::VST1d32, ARM::VST1d64 };
    3661             :       static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
    3662             :                                            ARM::VST1q32, ARM::VST1q64 };
    3663          37 :       SelectVST(N, false, 1, DOpcodes, QOpcodes, nullptr);
    3664          37 :       return;
    3665             :     }
    3666             : 
    3667           8 :     case Intrinsic::arm_neon_vst1x2: {
    3668             :       static const uint16_t DOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
    3669             :                                            ARM::VST1q32, ARM::VST1q64 };
    3670             :       static const uint16_t QOpcodes[] = { ARM::VST1d8QPseudo,
    3671             :                                            ARM::VST1d16QPseudo,
    3672             :                                            ARM::VST1d32QPseudo,
    3673             :                                            ARM::VST1d64QPseudo };
    3674           8 :       SelectVST(N, false, 2, DOpcodes, QOpcodes, nullptr);
    3675           8 :       return;
    3676             :     }
    3677             : 
    3678           8 :     case Intrinsic::arm_neon_vst1x3: {
    3679             :       static const uint16_t DOpcodes[] = { ARM::VST1d8TPseudo,
    3680             :                                            ARM::VST1d16TPseudo,
    3681             :                                            ARM::VST1d32TPseudo,
    3682             :                                            ARM::VST1d64TPseudo };
    3683             :       static const uint16_t QOpcodes0[] = { ARM::VST1q8LowTPseudo_UPD,
    3684             :                                             ARM::VST1q16LowTPseudo_UPD,
    3685             :                                             ARM::VST1q32LowTPseudo_UPD,
    3686             :                                             ARM::VST1q64LowTPseudo_UPD };
    3687             :       static const uint16_t QOpcodes1[] = { ARM::VST1q8HighTPseudo,
    3688             :                                             ARM::VST1q16HighTPseudo,
    3689             :                                             ARM::VST1q32HighTPseudo,
    3690             :                                             ARM::VST1q64HighTPseudo };
    3691           8 :       SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
    3692           8 :       return;
    3693             :     }
    3694             : 
    3695           8 :     case Intrinsic::arm_neon_vst1x4: {
    3696             :       static const uint16_t DOpcodes[] = { ARM::VST1d8QPseudo,
    3697             :                                            ARM::VST1d16QPseudo,
    3698             :                                            ARM::VST1d32QPseudo,
    3699             :                                            ARM::VST1d64QPseudo };
    3700             :       static const uint16_t QOpcodes0[] = { ARM::VST1q8LowQPseudo_UPD,
    3701             :                                             ARM::VST1q16LowQPseudo_UPD,
    3702             :                                             ARM::VST1q32LowQPseudo_UPD,
    3703             :                                             ARM::VST1q64LowQPseudo_UPD };
    3704             :       static const uint16_t QOpcodes1[] = { ARM::VST1q8HighQPseudo,
    3705             :                                             ARM::VST1q16HighQPseudo,
    3706             :                                             ARM::VST1q32HighQPseudo,
    3707             :                                             ARM::VST1q64HighQPseudo };
    3708           8 :       SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
    3709           8 :       return;
    3710             :     }
    3711             : 
    3712          20 :     case Intrinsic::arm_neon_vst2: {
    3713             :       static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
    3714             :                                            ARM::VST2d32, ARM::VST1q64 };
    3715             :       static const uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
    3716             :                                            ARM::VST2q32Pseudo };
    3717          20 :       SelectVST(N, false, 2, DOpcodes, QOpcodes, nullptr);
    3718          20 :       return;
    3719             :     }
    3720             : 
    3721          19 :     case Intrinsic::arm_neon_vst3: {
    3722             :       static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo,
    3723             :                                            ARM::VST3d16Pseudo,
    3724             :                                            ARM::VST3d32Pseudo,
    3725             :                                            ARM::VST1d64TPseudo };
    3726             :       static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
    3727             :                                             ARM::VST3q16Pseudo_UPD,
    3728             :                                             ARM::VST3q32Pseudo_UPD };
    3729             :       static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo,
    3730             :                                             ARM::VST3q16oddPseudo,
    3731             :                                             ARM::VST3q32oddPseudo };
    3732          19 :       SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
    3733          19 :       return;
    3734             :     }
    3735             : 
    3736          19 :     case Intrinsic::arm_neon_vst4: {
    3737             :       static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo,
    3738             :                                            ARM::VST4d16Pseudo,
    3739             :                                            ARM::VST4d32Pseudo,
    3740             :                                            ARM::VST1d64QPseudo };
    3741             :       static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
    3742             :                                             ARM::VST4q16Pseudo_UPD,
    3743             :                                             ARM::VST4q32Pseudo_UPD };
    3744             :       static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo,
    3745             :                                             ARM::VST4q16oddPseudo,
    3746             :                                             ARM::VST4q32oddPseudo };
    3747          19 :       SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
    3748          19 :       return;
    3749             :     }
    3750             : 
    3751           8 :     case Intrinsic::arm_neon_vst2lane: {
    3752             :       static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo,
    3753             :                                            ARM::VST2LNd16Pseudo,
    3754             :                                            ARM::VST2LNd32Pseudo };
    3755             :       static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo,
    3756             :                                            ARM::VST2LNq32Pseudo };
    3757           8 :       SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
    3758           8 :       return;
    3759             :     }
    3760             : 
    3761           8 :     case Intrinsic::arm_neon_vst3lane: {
    3762             :       static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo,
    3763             :                                            ARM::VST3LNd16Pseudo,
    3764             :                                            ARM::VST3LNd32Pseudo };
    3765             :       static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo,
    3766             :                                            ARM::VST3LNq32Pseudo };
    3767           8 :       SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
    3768           8 :       return;
    3769             :     }
    3770             : 
    3771           8 :     case Intrinsic::arm_neon_vst4lane: {
    3772             :       static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo,
    3773             :                                            ARM::VST4LNd16Pseudo,
    3774             :                                            ARM::VST4LNd32Pseudo };
    3775             :       static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo,
    3776             :                                            ARM::VST4LNq32Pseudo };
    3777           8 :       SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
    3778           8 :       return;
    3779             :     }
    3780             :     }
    3781             :     break;
    3782             :   }
    3783             : 
    3784           6 :   case ISD::ATOMIC_CMP_SWAP:
    3785           6 :     SelectCMP_SWAP(N);
    3786           6 :     return;
    3787             :   }
    3788             : 
    3789             :   SelectCode(N);
    3790             : }
    3791             : 
    3792             : // Inspect a register string of the form
    3793             : // cp<coprocessor>:<opc1>:c<CRn>:c<CRm>:<opc2> (32bit) or
    3794             : // cp<coprocessor>:<opc1>:c<CRm> (64bit) inspect the fields of the string
    3795             : // and obtain the integer operands from them, adding these operands to the
    3796             : // provided vector.
    3797         230 : static void getIntOperandsFromRegisterString(StringRef RegString,
    3798             :                                              SelectionDAG *CurDAG,
    3799             :                                              const SDLoc &DL,
    3800             :                                              std::vector<SDValue> &Ops) {
    3801             :   SmallVector<StringRef, 5> Fields;
    3802         230 :   RegString.split(Fields, ':');
    3803             : 
    3804         230 :   if (Fields.size() > 1) {
    3805             :     bool AllIntFields = true;
    3806             : 
    3807          72 :     for (StringRef Field : Fields) {
    3808             :       // Need to trim out leading 'cp' characters and get the integer field.
    3809             :       unsigned IntField;
    3810          64 :       AllIntFields &= !Field.trim("CPcp").getAsInteger(10, IntField);
    3811          96 :       Ops.push_back(CurDAG->getTargetConstant(IntField, DL, MVT::i32));
    3812             :     }
    3813             : 
    3814             :     assert(AllIntFields &&
    3815             :             "Unexpected non-integer value in special register string.");
    3816             :   }
    3817         230 : }
    3818             : 
    3819             : // Maps a Banked Register string to its mask value. The mask value returned is
    3820             : // for use in the MRSbanked / MSRbanked instruction nodes as the Banked Register
    3821             : // mask operand, which expresses which register is to be used, e.g. r8, and in
    3822             : // which mode it is to be used, e.g. usr. Returns -1 to signify that the string
    3823             : // was invalid.
    3824         222 : static inline int getBankedRegisterMask(StringRef RegString) {
    3825         666 :   auto TheReg = ARMBankedReg::lookupBankedRegByName(RegString.lower());
    3826         222 :   if (!TheReg)
    3827             :      return -1;
    3828           0 :   return TheReg->Encoding;
    3829             : }
    3830             : 
    3831             : // The flags here are common to those allowed for apsr in the A class cores and
    3832             : // those allowed for the special registers in the M class cores. Returns a
    3833             : // value representing which flags were present, -1 if invalid.
    3834          12 : static inline int getMClassFlagsMask(StringRef Flags) {
    3835          12 :   return StringSwitch<int>(Flags)
    3836             :           .Case("", 0x2) // no flags means nzcvq for psr registers, and 0x2 is
    3837             :                          // correct when flags are not permitted
    3838             :           .Case("g", 0x1)
    3839             :           .Case("nzcvq", 0x2)
    3840             :           .Case("nzcvqg", 0x3)
    3841          12 :           .Default(-1);
    3842             : }
    3843             : 
    3844             : // Maps MClass special registers string to its value for use in the
    3845             : // t2MRS_M/t2MSR_M instruction nodes as the SYSm value operand.
    3846             : // Returns -1 to signify that the string was invalid.
    3847         182 : static int getMClassRegisterMask(StringRef Reg, const ARMSubtarget *Subtarget) {
    3848         182 :   auto TheReg = ARMSysReg::lookupMClassSysRegByName(Reg);
    3849             :   const FeatureBitset &FeatureBits = Subtarget->getFeatureBits();
    3850         363 :   if (!TheReg || !TheReg->hasRequiredFeatures(FeatureBits))
    3851             :     return -1;
    3852         178 :   return (int)(TheReg->Encoding & 0xFFF); // SYSm value
    3853             : }
    3854             : 
    3855          24 : static int getARClassRegisterMask(StringRef Reg, StringRef Flags) {
    3856             :   // The mask operand contains the special register (R Bit) in bit 4, whether
    3857             :   // the register is spsr (R bit is 1) or one of cpsr/apsr (R bit is 0), and
    3858             :   // bits 3-0 contains the fields to be accessed in the special register, set by
    3859             :   // the flags provided with the register.
    3860             :   int Mask = 0;
    3861             :   if (Reg == "apsr") {
    3862             :     // The flags permitted for apsr are the same flags that are allowed in
    3863             :     // M class registers. We get the flag value and then shift the flags into
    3864             :     // the correct place to combine with the mask.
    3865          12 :     Mask = getMClassFlagsMask(Flags);
    3866          12 :     if (Mask == -1)
    3867             :       return -1;
    3868          12 :     return Mask << 2;
    3869             :   }
    3870             : 
    3871             :   if (Reg != "cpsr" && Reg != "spsr") {
    3872             :     return -1;
    3873             :   }
    3874             : 
    3875             :   // This is the same as if the flags were "fc"
    3876          10 :   if (Flags.empty() || Flags == "all")
    3877             :     return Mask | 0x9;
    3878             : 
    3879             :   // Inspect the supplied flags string and set the bits in the mask for
    3880             :   // the relevant and valid flags allowed for cpsr and spsr.
    3881          42 :   for (char Flag : Flags) {
    3882             :     int FlagVal;
    3883          16 :     switch (Flag) {
    3884             :       case 'c':
    3885             :         FlagVal = 0x1;
    3886             :         break;
    3887             :       case 'x':
    3888             :         FlagVal = 0x2;
    3889             :         break;
    3890             :       case 's':
    3891             :         FlagVal = 0x4;
    3892             :         break;
    3893             :       case 'f':
    3894             :         FlagVal = 0x8;
    3895             :         break;
    3896             :       default:
    3897             :         FlagVal = 0;
    3898             :     }
    3899             : 
    3900             :     // This avoids allowing strings where the same flag bit appears twice.
    3901          16 :     if (!FlagVal || (Mask & FlagVal))
    3902             :       return -1;
    3903          16 :     Mask |= FlagVal;
    3904             :   }
    3905             : 
    3906             :   // If the register is spsr then we need to set the R bit.
    3907             :   if (Reg == "spsr")
    3908           5 :     Mask |= 0x10;
    3909             : 
    3910             :   return Mask;
    3911             : }
    3912             : 
    3913             : // Lower the read_register intrinsic to ARM specific DAG nodes
    3914             : // using the supplied metadata string to select the instruction node to use
    3915             : // and the registers/masks to construct as operands for the node.
    3916          95 : bool ARMDAGToDAGISel::tryReadRegister(SDNode *N){
    3917          95 :   const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(N->getOperand(1));
    3918          95 :   const MDString *RegString = dyn_cast<MDString>(MD->getMD()->getOperand(0));
    3919          95 :   bool IsThumb2 = Subtarget->isThumb2();
    3920             :   SDLoc DL(N);
    3921             : 
    3922             :   std::vector<SDValue> Ops;
    3923          95 :   getIntOperandsFromRegisterString(RegString->getString(), CurDAG, DL, Ops);
    3924             : 
    3925          95 :   if (!Ops.empty()) {
    3926             :     // If the special register string was constructed of fields (as defined
    3927             :     // in the ACLE) then need to lower to MRC node (32 bit) or
    3928             :     // MRRC node(64 bit), we can make the distinction based on the number of
    3929             :     // operands we have.
    3930             :     unsigned Opcode;
    3931             :     SmallVector<EVT, 3> ResTypes;
    3932           4 :     if (Ops.size() == 5){
    3933           2 :       Opcode = IsThumb2 ? ARM::t2MRC : ARM::MRC;
    3934             :       ResTypes.append({ MVT::i32, MVT::Other });
    3935             :     } else {
    3936             :       assert(Ops.size() == 3 &&
    3937             :               "Invalid number of fields in special register string.");
    3938           2 :       Opcode = IsThumb2 ? ARM::t2MRRC : ARM::MRRC;
    3939             :       ResTypes.append({ MVT::i32, MVT::i32, MVT::Other });
    3940             :     }
    3941             : 
    3942           8 :     Ops.push_back(getAL(CurDAG, DL));
    3943          12 :     Ops.push_back(CurDAG->getRegister(0, MVT::i32));
    3944           8 :     Ops.push_back(N->getOperand(0));
    3945           8 :     ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, ResTypes, Ops));
    3946             :     return true;
    3947             :   }
    3948             : 
    3949          91 :   std::string SpecialReg = RegString->getString().lower();
    3950             : 
    3951          91 :   int BankedReg = getBankedRegisterMask(SpecialReg);
    3952          91 :   if (BankedReg != -1) {
    3953           0 :     Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32),
    3954           0 :             getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
    3955           0 :             N->getOperand(0) };
    3956           0 :     ReplaceNode(
    3957           0 :         N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSbanked : ARM::MRSbanked,
    3958             :                                   DL, MVT::i32, MVT::Other, Ops));
    3959           0 :     return true;
    3960             :   }
    3961             : 
    3962             :   // The VFP registers are read by creating SelectionDAG nodes with opcodes
    3963             :   // corresponding to the register that is being read from. So we switch on the
    3964             :   // string to find which opcode we need to use.
    3965          91 :   unsigned Opcode = StringSwitch<unsigned>(SpecialReg)
    3966             :                     .Case("fpscr", ARM::VMRS)
    3967             :                     .Case("fpexc", ARM::VMRS_FPEXC)
    3968             :                     .Case("fpsid", ARM::VMRS_FPSID)
    3969             :                     .Case("mvfr0", ARM::VMRS_MVFR0)
    3970             :                     .Case("mvfr1", ARM::VMRS_MVFR1)
    3971             :                     .Case("mvfr2", ARM::VMRS_MVFR2)
    3972             :                     .Case("fpinst", ARM::VMRS_FPINST)
    3973             :                     .Case("fpinst2", ARM::VMRS_FPINST2)
    3974             :                     .Default(0);
    3975             : 
    3976             :   // If an opcode was found then we can lower the read to a VFP instruction.
    3977           2 :   if (Opcode) {
    3978           2 :     if (!Subtarget->hasVFP2())
    3979             :       return false;
    3980           2 :     if (Opcode == ARM::VMRS_MVFR2 && !Subtarget->hasFPARMv8())
    3981             :       return false;
    3982             : 
    3983           8 :     Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
    3984           2 :             N->getOperand(0) };
    3985           2 :     ReplaceNode(N,
    3986           6 :                 CurDAG->getMachineNode(Opcode, DL, MVT::i32, MVT::Other, Ops));
    3987           2 :     return true;
    3988             :   }
    3989             : 
    3990             :   // If the target is M Class then need to validate that the register string
    3991             :   // is an acceptable value, so check that a mask can be constructed from the
    3992             :   // string.
    3993          89 :   if (Subtarget->isMClass()) {
    3994          77 :     int SYSmValue = getMClassRegisterMask(SpecialReg, Subtarget);
    3995          77 :     if (SYSmValue == -1)
    3996             :       return false;
    3997             : 
    3998          74 :     SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32),
    3999         222 :                       getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
    4000         296 :                       N->getOperand(0) };
    4001          74 :     ReplaceNode(
    4002         222 :         N, CurDAG->getMachineNode(ARM::t2MRS_M, DL, MVT::i32, MVT::Other, Ops));
    4003          74 :     return true;
    4004             :   }
    4005             : 
    4006             :   // Here we know the target is not M Class so we need to check if it is one
    4007             :   // of the remaining possible values which are apsr, cpsr or spsr.
    4008          22 :   if (SpecialReg == "apsr" || SpecialReg == "cpsr") {
    4009          16 :     Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
    4010           4 :             N->getOperand(0) };
    4011           8 :     ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRS_AR : ARM::MRS,
    4012             :                                           DL, MVT::i32, MVT::Other, Ops));
    4013           4 :     return true;
    4014             :   }
    4015             : 
    4016           8 :   if (SpecialReg == "spsr") {
    4017           4 :     Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
    4018           1 :             N->getOperand(0) };
    4019           1 :     ReplaceNode(
    4020           3 :         N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSsys_AR : ARM::MRSsys, DL,
    4021             :                                   MVT::i32, MVT::Other, Ops));
    4022           1 :     return true;
    4023             :   }
    4024             : 
    4025             :   return false;
    4026             : }
    4027             : 
    4028             : // Lower the write_register intrinsic to ARM specific DAG nodes
    4029             : // using the supplied metadata string to select the instruction node to use
    4030             : // and the registers/masks to use in the nodes
    4031         135 : bool ARMDAGToDAGISel::tryWriteRegister(SDNode *N){
    4032         135 :   const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(N->getOperand(1));
    4033         135 :   const MDString *RegString = dyn_cast<MDString>(MD->getMD()->getOperand(0));
    4034         135 :   bool IsThumb2 = Subtarget->isThumb2();
    4035             :   SDLoc DL(N);
    4036             : 
    4037             :   std::vector<SDValue> Ops;
    4038         135 :   getIntOperandsFromRegisterString(RegString->getString(), CurDAG, DL, Ops);
    4039             : 
    4040         135 :   if (!Ops.empty()) {
    4041             :     // If the special register string was constructed of fields (as defined
    4042             :     // in the ACLE) then need to lower to MCR node (32 bit) or
    4043             :     // MCRR node(64 bit), we can make the distinction based on the number of
    4044             :     // operands we have.
    4045             :     unsigned Opcode;
    4046           4 :     if (Ops.size() == 5) {
    4047           2 :       Opcode = IsThumb2 ? ARM::t2MCR : ARM::MCR;
    4048           4 :       Ops.insert(Ops.begin()+2, N->getOperand(2));
    4049             :     } else {
    4050             :       assert(Ops.size() == 3 &&
    4051             :               "Invalid number of fields in special register string.");
    4052           2 :       Opcode = IsThumb2 ? ARM::t2MCRR : ARM::MCRR;
    4053           2 :       SDValue WriteValue[] = { N->getOperand(2), N->getOperand(3) };
    4054             :       Ops.insert(Ops.begin()+2, WriteValue, WriteValue+2);
    4055             :     }
    4056             : 
    4057           8 :     Ops.push_back(getAL(CurDAG, DL));
    4058          12 :     Ops.push_back(CurDAG->getRegister(0, MVT::i32));
    4059           8 :     Ops.push_back(N->getOperand(0));
    4060             : 
    4061           8 :     ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops));
    4062           4 :     return true;
    4063             :   }
    4064             : 
    4065         131 :   std::string SpecialReg = RegString->getString().lower();
    4066         131 :   int BankedReg = getBankedRegisterMask(SpecialReg);
    4067         131 :   if (BankedReg != -1) {
    4068           0 :     Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32), N->getOperand(2),
    4069           0 :             getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
    4070           0 :             N->getOperand(0) };
    4071           0 :     ReplaceNode(
    4072           0 :         N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSRbanked : ARM::MSRbanked,
    4073             :                                   DL, MVT::Other, Ops));
    4074           0 :     return true;
    4075             :   }
    4076             : 
    4077             :   // The VFP registers are written to by creating SelectionDAG nodes with
    4078             :   // opcodes corresponding to the register that is being written. So we switch
    4079             :   // on the string to find which opcode we need to use.
    4080         131 :   unsigned Opcode = StringSwitch<unsigned>(SpecialReg)
    4081             :                     .Case("fpscr", ARM::VMSR)
    4082             :                     .Case("fpexc", ARM::VMSR_FPEXC)
    4083             :                     .Case("fpsid", ARM::VMSR_FPSID)
    4084             :                     .Case("fpinst", ARM::VMSR_FPINST)
    4085             :                     .Case("fpinst2", ARM::VMSR_FPINST2)
    4086             :                     .Default(0);
    4087             : 
    4088           2 :   if (Opcode) {
    4089           2 :     if (!Subtarget->hasVFP2())
    4090             :       return false;
    4091           8 :     Ops = { N->getOperand(2), getAL(CurDAG, DL),
    4092           6 :             CurDAG->getRegister(0, MVT::i32), N->getOperand(0) };
    4093           4 :     ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops));
    4094           2 :     return true;
    4095             :   }
    4096             : 
    4097             :   std::pair<StringRef, StringRef> Fields;
    4098         129 :   Fields = StringRef(SpecialReg).rsplit('_');
    4099             :   std::string Reg = Fields.first.str();
    4100         129 :   StringRef Flags = Fields.second;
    4101             : 
    4102             :   // If the target was M Class then need to validate the special register value
    4103             :   // and retrieve the mask for use in the instruction node.
    4104         129 :   if (Subtarget->isMClass()) {
    4105         105 :     int SYSmValue = getMClassRegisterMask(SpecialReg, Subtarget);
    4106         105 :     if (SYSmValue == -1)
    4107             :       return false;
    4108             : 
    4109         104 :     SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32),
    4110         208 :                       N->getOperand(2), getAL(CurDAG, DL),
    4111         416 :                       CurDAG->getRegister(0, MVT::i32), N->getOperand(0) };
    4112         208 :     ReplaceNode(N, CurDAG->getMachineNode(ARM::t2MSR_M, DL, MVT::Other, Ops));
    4113         104 :     return true;
    4114             :   }
    4115             : 
    4116             :   // We then check to see if a valid mask can be constructed for one of the
    4117             :   // register string values permitted for the A and R class cores. These values
    4118             :   // are apsr, spsr and cpsr; these are also valid on older cores.
    4119          24 :   int Mask = getARClassRegisterMask(Reg, Flags);
    4120          24 :   if (Mask != -1) {
    4121         132 :     Ops = { CurDAG->getTargetConstant(Mask, DL, MVT::i32), N->getOperand(2),
    4122          66 :             getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
    4123          22 :             N->getOperand(0) };
    4124          44 :     ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSR_AR : ARM::MSR,
    4125             :                                           DL, MVT::Other, Ops));
    4126          22 :     return true;
    4127             :   }
    4128             : 
    4129             :   return false;
    4130             : }
    4131             : 
    4132        3483 : bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
    4133             :   std::vector<SDValue> AsmNodeOperands;
    4134             :   unsigned Flag, Kind;
    4135             :   bool Changed = false;
    4136        3483 :   unsigned NumOps = N->getNumOperands();
    4137             : 
    4138             :   // Normally, i64 data is bounded to two arbitrary GRPs for "%r" constraint.
    4139             :   // However, some instrstions (e.g. ldrexd/strexd in ARM mode) require
    4140             :   // (even/even+1) GPRs and use %n and %Hn to refer to the individual regs
    4141             :   // respectively. Since there is no constraint to explicitly specify a
    4142             :   // reg pair, we use GPRPair reg class for "%r" for 64-bit data. For Thumb,
    4143             :   // the 64-bit data may be referred by H, Q, R modifiers, so we still pack
    4144             :   // them into a GPRPair.
    4145             : 
    4146             :   SDLoc dl(N);
    4147         126 :   SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1)
    4148         126 :                                    : SDValue(nullptr,0);
    4149             : 
    4150             :   SmallVector<bool, 8> OpChanged;
    4151             :   // Glue node will be appended late.
    4152       22504 :   for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
    4153       44756 :     SDValue op = N->getOperand(i);
    4154       22378 :     AsmNodeOperands.push_back(op);
    4155             : 
    4156       22378 :     if (i < InlineAsm::Op_FirstOperand)
    4157       36215 :       continue;
    4158             : 
    4159       12589 :     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
    4160        8606 :       Flag = C->getZExtValue();
    4161             :       Kind = InlineAsm::getKind(Flag);
    4162             :     }
    4163             :     else
    4164        4143 :       continue;
    4165             : 
    4166             :     // Immediate operands to inline asm in the SelectionDAG are modeled with
    4167             :     // two operands. The first is a constant of value InlineAsm::Kind_Imm, and
    4168             :     // the second is a constant with the value of the immediate. If we get here
    4169             :     // and we have a Kind_Imm, skip the next operand, and continue.
    4170        4303 :     if (Kind == InlineAsm::Kind_Imm) {
    4171          80 :       SDValue op = N->getOperand(++i);
    4172          40 :       AsmNodeOperands.push_back(op);
    4173          40 :       continue;
    4174             :     }
    4175             : 
    4176             :     unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
    4177        4263 :     if (NumRegs)
    4178        4263 :       OpChanged.push_back(false);
    4179             : 
    4180             :     unsigned DefIdx = 0;
    4181             :     bool IsTiedToChangedOp = false;
    4182             :     // If it's a use that is tied with a previous def, it has no
    4183             :     // reg class constraint.
    4184        4263 :     if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
    4185          14 :       IsTiedToChangedOp = OpChanged[DefIdx];
    4186             : 
    4187             :     // Memory operands to inline asm in the SelectionDAG are modeled with two
    4188             :     // operands: a constant of value InlineAsm::Kind_Mem followed by the input
    4189             :     // operand. If we get here and we have a Kind_Mem, skip the next operand (so
    4190             :     // it doesn't get misinterpreted), and continue. We do this here because
    4191             :     // it's important to update the OpChanged array correctly before moving on.
    4192        4263 :     if (Kind == InlineAsm::Kind_Mem) {
    4193          50 :       SDValue op = N->getOperand(++i);
    4194          25 :       AsmNodeOperands.push_back(op);
    4195          25 :       continue;
    4196             :     }
    4197             : 
    4198        4238 :     if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
    4199        4238 :         && Kind != InlineAsm::Kind_RegDefEarlyClobber)
    4200        3829 :       continue;
    4201             : 
    4202             :     unsigned RC;
    4203             :     bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
    4204         723 :     if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID))
    4205         286 :         || NumRegs != 2)
    4206         314 :       continue;
    4207             : 
    4208             :     assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
    4209         190 :     SDValue V0 = N->getOperand(i+1);
    4210         190 :     SDValue V1 = N->getOperand(i+2);
    4211          95 :     unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
    4212          95 :     unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
    4213          95 :     SDValue PairedReg;
    4214          95 :     MachineRegisterInfo &MRI = MF->getRegInfo();
    4215             : 
    4216          95 :     if (Kind == InlineAsm::Kind_RegDef ||
    4217             :         Kind == InlineAsm::Kind_RegDefEarlyClobber) {
    4218             :       // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
    4219             :       // the original GPRs.
    4220             : 
    4221          44 :       unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
    4222          88 :       PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
    4223             :       SDValue Chain = SDValue(N,0);
    4224             : 
    4225             :       SDNode *GU = N->getGluedUser();
    4226          44 :       SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::Untyped,
    4227          44 :                                                Chain.getValue(1));
    4228             : 
    4229             :       // Extract values from a GPRPair reg and copy to the original GPR reg.
    4230          44 :       SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
    4231          44 :                                                     RegCopy);
    4232          44 :       SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
    4233          44 :                                                     RegCopy);
    4234          44 :       SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
    4235          44 :                                         RegCopy.getValue(1));
    4236          44 :       SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
    4237             : 
    4238             :       // Update the original glue user.
    4239          88 :       std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
    4240          88 :       Ops.push_back(T1.getValue(1));
    4241          88 :       CurDAG->UpdateNodeOperands(GU, Ops);
    4242             :     }
    4243             :     else {
    4244             :       // For Kind  == InlineAsm::Kind_RegUse, we first copy two GPRs into a
    4245             :       // GPRPair and then pass the GPRPair to the inline asm.
    4246          51 :       SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
    4247             : 
    4248             :       // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
    4249          51 :       SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
    4250          51 :                                           Chain.getValue(1));
    4251          51 :       SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
    4252         102 :                                           T0.getValue(1));
    4253         102 :       SDValue Pair = SDValue(createGPRPairNode(MVT::Untyped, T0, T1), 0);
    4254             : 
    4255             :       // Copy REG_SEQ into a GPRPair-typed VR and replace the original two
    4256             :       // i32 VRs of inline asm with it.
    4257          51 :       unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
    4258         102 :       PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
    4259          51 :       Chain = CurDAG->getCopyToReg(T1, dl, GPVR, Pair, T1.getValue(1));
    4260             : 
    4261          51 :       AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
    4262          51 :       Glue = Chain.getValue(1);
    4263             :     }
    4264             : 
    4265             :     Changed = true;
    4266             : 
    4267          95 :     if(PairedReg.getNode()) {
    4268         190 :       OpChanged[OpChanged.size() -1 ] = true;
    4269             :       Flag = InlineAsm::getFlagWord(Kind, 1 /* RegNum*/);
    4270          95 :       if (IsTiedToChangedOp)
    4271             :         Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
    4272             :       else
    4273             :         Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID);
    4274             :       // Replace the current flag.
    4275         380 :       AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(
    4276          95 :           Flag, dl, MVT::i32);
    4277             :       // Add the new register node and skip the original two GPRs.
    4278          95 :       AsmNodeOperands.push_back(PairedReg);
    4279             :       // Skip the next two GPRs.
    4280             :       i += 2;
    4281             :     }
    4282             :   }
    4283             : 
    4284        3483 :   if (Glue.getNode())
    4285         126 :     AsmNodeOperands.push_back(Glue);
    4286        3483 :   if (!Changed)
    4287             :     return false;
    4288             : 
    4289          98 :   SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
    4290         147 :       CurDAG->getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
    4291             :   New->setNodeId(-1);
    4292          49 :   ReplaceNode(N, New.getNode());
    4293          49 :   return true;
    4294             : }
    4295             : 
    4296             : 
    4297          18 : bool ARMDAGToDAGISel::
    4298             : SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
    4299             :                              std::vector<SDValue> &OutOps) {
    4300             :   switch(ConstraintID) {
    4301           0 :   default:
    4302           0 :     llvm_unreachable("Unexpected asm memory constraint");
    4303          18 :   case InlineAsm::Constraint_i:
    4304             :     // FIXME: It seems strange that 'i' is needed here since it's supposed to
    4305             :     //        be an immediate and not a memory constraint.
    4306             :     LLVM_FALLTHROUGH;
    4307             :   case InlineAsm::Constraint_m:
    4308             :   case InlineAsm::Constraint_o:
    4309             :   case InlineAsm::Constraint_Q:
    4310             :   case InlineAsm::Constraint_Um:
    4311             :   case InlineAsm::Constraint_Un:
    4312             :   case InlineAsm::Constraint_Uq:
    4313             :   case InlineAsm::Constraint_Us:
    4314             :   case InlineAsm::Constraint_Ut:
    4315             :   case InlineAsm::Constraint_Uv:
    4316             :   case InlineAsm::Constraint_Uy:
    4317             :     // Require the address to be in a register.  That is safe for all ARM
    4318             :     // variants and it is hard to do anything much smarter without knowing
    4319             :     // how the operand is used.
    4320          18 :     OutOps.push_back(Op);
    4321             :     return false;
    4322             :   }
    4323             :   return true;
    4324             : }
    4325             : 
    4326             : /// createARMISelDag - This pass converts a legalized DAG into a
    4327             : /// ARM-specific DAG, ready for instruction scheduling.
    4328             : ///
    4329        2709 : FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
    4330             :                                      CodeGenOpt::Level OptLevel) {
    4331        5418 :   return new ARMDAGToDAGISel(TM, OptLevel);
    4332      299229 : }

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